19-1155; Rev 5; 8/10
KIT
ATION
EVALU
E
L
B
AVAILA
+2.7V, Low-Power,
12-Bit Serial ADCs in 8-Pin SO
________________________________Features
The MAX1240/MAX1241 low-power, 12-bit analog-todigital converters (ADCs) are available in 8-pin packages. The MAX1240 operates with a single +2.7V to
+3.6V supply, and the MAX1241 operates with a single
+2.7V to +5.25V supply. Both devices feature a 7.5µs
successive-approximation ADC, a fast track/hold
(1.5µs), an on-chip clock, and a high-speed, 3-wire serial interface.
Power consumption is only 37mW (VDD = 3V) at the
73ksps maximum sampling speed. A 2µA shutdown
mode reduces power at slower throughput rates.
The MAX1240 has an internal 2.5V reference, while the
MAX1241 requires an external reference. The MAX1241
accepts signals from 0V to VREF, and the reference
input range includes the positive supply rail. An external clock accesses data from the 3-wire interface,
which connects directly to standard microcontroller I/O
ports. The interface is compatible with SPI™, QSPI™,
and MICROWIRE™.
Excellent AC characteristics and very low power combined with ease of use and small package size make
these converters ideal for remote-sensor and dataacquisition applications, or for other circuits with
demanding power consumption and space requirements. The MAX1240/MAX1241 are available in 8-pin
PDIP and SO packages.
♦ Single-Supply Operation:
+2.7V to +3.6V (MAX1240)
+2.7V to +5.25V (MAX1241)
♦ 12-Bit Resolution
♦ Internal 2.5V Reference (MAX1240)
♦ Small Footprint: 8-Pin PDIP/SO Packages
♦ Low Power: 3.7µW (73ksps, MAX1240)
3mW (73ksps, MAX1241)
66µW (1ksps, MAX1241)
5µW (power-down mode)
♦ Internal Track/Hold
♦ SPI/QSPI/MICROWIRE 3-Wire Serial Interface
♦ Internal Clock
Ordering Information
PART*
TEMP RANGE
Battery-Powered Systems
Portable Data Logging
Isolated Data Acquisition
INL
(LSB)
MAX1240ACPA+
0°C to +70°C
8 PDIP
±1/2
MAX1240BCPA+
0°C to +70°C
8 PDIP
±1
MAX1240CCPA+
0°C to +70°C
8 PDIP
±1
MAX1240ACSA+
0°C to +70°C
8 SO
±1/2
MAX1240BCSA+
0°C to +70°C
8 SO
±1
MAX1240CCSA+
0°C to +70°C
8 SO
±1
0°C to +70°C
Dice*
±1
-40°C to +85°C
8 SO
±1/2
MAX1240CC/D
MAX1240AESA/V+**
Applications
PINPACKAGE
MAX1240BESA/V+
-40°C to +85°C 8 SO
±1
Ordering Information continued at end of data sheet.
*Dice are specified at TA = +25°C, DC parameters only.
**Future product—contact factory for availability.
/V denotes an automotive qualified part.
+Denotes a lead(Pb)-free/RoHS-compliant package.
Process Control
Functional Diagram
Instrumentation
VDD
1
Pin Configuration
CS
SCLK
TOP VIEW
SHDN
VDD
1
AIN
2
SHDN 3
MAX1240
MAX1241
REF 4
8
SCLK
7
CS
6
DOUT
5
GND
AIN
REF
PDIP/SO
7
8
3
2
4
INT
CLOCK
CONTROL
LOGIC
T/H
OUTPUT
SHIFT
REGISTER
6
DOUT
12-BIT
SAR
2.5V REFERENCE
(MAX1240 ONLY)
MAX1240
MAX1241
5
GND
SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
MAX1240/MAX1241
__________________General Description
MAX1240/MAX1241
+2.7V, Low-Power,
12-Bit Serial ADCs in 8-Pin SO
ABSOLUTE MAXIMUM RATINGS
VDD to GND .............................................................-0.3V to +6V
AIN to GND................................................-0.3V to (VDD + 0.3V)
REF to GND ...............................................-0.3V to (VDD + 0.3V)
Digital Inputs to GND...............................................-0.3V to +6V
DOUT to GND............................................-0.3V to (VDD + 0.3V)
DOUT Current ..................................................................±25mA
Continuous Power Dissipation (TA = +70°C)
Plastic DIP (derate 9.09mW/°C above +70°C) ...........727mW
SO (derate 5.88mW/°C above +70°C)........................471mW
CERDIP (derate 8.00mW/°C above +70°C)................640mW
Operating Temperature Ranges
MAX1240_C_A/MAX1241_C_A .........................0°C to +70°C
MAX1240_E_ A/MAX1241_E_ A .....................-40°C to +85°C
MAX1240_MJA/MAX1241_MJA ...................-55°C to +125°C
Storage Temperature Range............................-60°C to +150°C
Lead Temperature (soldering, 10s) ................................+300°C
Soldering Temperature (reflow)
PDIP, SO .....................................................................+260°C
CDIP ...........................................................................+250°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = +2.7V to +3.6V (MAX1240); VDD = +2.7V to +5.25V (MAX1241); 73ksps, fSCLK = 2.1MHz (50% duty cycle); MAX1240—4.7µF
capacitor at REF pin, MAX1241—external reference; VREF = 2.500V applied to REF pin; TA = TMIN to TMAX; unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC ACCURACY (Note 1)
Resolution
12
Relative Accuracy (Note 2)
INL
Differential Nonlinearity
DNL
Bits
MAX124_A
±0.5
MAX124_B/C
±1.0
No missing codes over temperature
±1
MAX124_A
±0.5
±3.0
MAX124_B/C
±0.5
±4.0
Gain Error (Note 3)
±0.5
±4.0
Gain Temperature Coefficient
±0.25
Offset Error
LSB
LSB
LSB
LSB
ppm/°C
DYNAMIC SPECIFICATIONS (10kHz sine-wave input, 0V to 2.500Vp-p, 73ksps, fSCLK = 2.1MHz)
Signal-to-Noise Plus
Distortion Ratio
SINAD
Total Harmonic Distortion
THD
Spurious-Free Dynamic Range
SFDR
Small-Signal Bandwidth
MAX124_A/B
70
MAX124_C
Up to the 5th harmonic
MAX124_A/B
dB
71.5
MAX124_A/B
-80
MAX124_C
-88
80
dB
dB
MAX124_C
88
-3dB rolloff
2.25
MHz
1.0
MHz
Full-Power Bandwidth
CONVERSION RATE
Conversion Time
tCONV
Track/Hold Acquisition Time
tACQ
Throughput Rate
Aperture Delay
5.5
7.5
fSCLK = 2.1MHz
tAPR
Figure 8
Aperture Jitter
µs
1.5
µs
73
ksps
30
ns
3.6V (MAX1241)
3.0
V
VIL
VHYST
SCLK, CS Input Leakage
IIN
VIN = 0V or VDD
SCLK, CS Input Capacitance
CIN
(Note 5)
SHDN Input High Voltage
VSH
SHDN Input Low Voltage
VSL
SHDN Input Current
±0.01
VSM
SHDN Voltage, Unconnected
VFLT
SHDN Max Allowed Leakage,
Mid Input
V
±1
µA
15
pF
V
VDD - 0.4
V
VSHDN = 0V or VDD
SHDN Input Mid Voltage
0.8
0.2
1.1
SHDN = unconnected
0.4
V
±4.0
µA
VDD - 1.1
V
VDD/2
SHDN = unconnected
V
±100
nA
DIGITAL OUTPUT: DOUT
Output Voltage Low
VOL
Output Voltage High
VOH
Three-State Leakage Current
Three-State Output Capacitance
IL
COUT
ISINK = 5mA
0.4
ISINK = 16mA
0.8
ISOURCE = 0.5mA
CS = VDD
CS = VDD (Note 5)
VDD - 0.5
V
V
±0.01
±10
µA
15
pF
_______________________________________________________________________________________
3
MAX1240/MAX1241
ELECTRICAL CHARACTERISTICS (continued)
MAX1240/MAX1241
+2.7V, Low-Power,
12-Bit Serial ADCs in 8-Pin SO
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +2.7V to +3.6V (MAX1240); VDD = +2.7V to +5.25V (MAX1241); 73ksps, fSCLK = 2.1MHz (50% duty cycle); MAX1240—4.7µF
capacitor at REF pin, MAX1241—external reference; VREF = 2.500V applied to REF pin; TA = TMIN to TMAX; unless otherwise noted.)
PARAMETERS
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER REQUIREMENTS
Supply Voltage
VDD
MAX1240
2.7
3.6
MAX1241
2.7
5.25
MAX1240A/B
MAX1240C
Operating
mode
Supply Current
MAX1241A/B
IDD
MAX1241C
Power-down, digital inputs
at 0V or VDD
Supply Rejection
PSR
VDD = 3.6V
VDD = 3.6V
1.4
2.0
1.4
3.5
VDD = 3.6V
0.9
1.5
VDD = 5.25V
1.6
2.5
VDD = 3.6V
0.9
2.8
VDD = 5.25V
1.6
3.8
VDD = 3.6V
1.9
10
VDD = 5.25V
3.5
15
(Note 5)
±0.3
V
mA
µA
mV
TIMING CHARACTERISTICS (Figure 8)
(VDD = +2.7V to +3.6V (MAX1240); VDD = +2.7V to +5.25V (MAX1241); TA = TMIN to TMAX, unless otherwise noted.)
PARAMETERS
Acquisition Time
SYMBOL
tACQ
CONDITIONS
CS = VDD (Note 6)
MIN
TYP
MAX
1.5
UNITS
µs
MAX124_ _C/E
20
200
MAX124_ _M
20
240
SCLK Fall to Output Data Valid
tDO
Figure 1,
CLOAD = 50pF
CS Fall to Output Enable
tDV
Figure 1, CLOAD = 50pF
240
ns
CS Rise to Output Disable
tTR
Figure 2, CLOAD = 50pF
240
ns
2.1
MHz
ns
SCLK Clock Frequency
fSCLK
0
SCLK Pulse Width High
tCH
200
ns
SCLK Pulse Width Low
tCL
200
ns
SCLK Low to CS Fall Setup Time
tCS0
50
ns
DOUT Rise to SCLK Rise (Note 5)
tSTR
0
ns
CS Pulse Width
tCS
240
ns
Note 1: Tested at VDD = +2.7V.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and
offset have been calibrated.
Note 3: MAX1240—internal reference, offset nulled; MAX1241—external reference (VREF = +2.500V), offset nulled.
Note 4: External load should not change during conversion for specified accuracy.
Note 5: Guaranteed by design. Not subject to production testing.
Note 6: Measured as [VFS(2.7V) - VFS(VDD(MAX)].
Note 7: To guarantee acquisition time, tACQ is the maximum time the device takes to acquire the signal, and is also the minimum
time needed for the signal to be acquired.
4
_______________________________________________________________________________________
+2.7V, Low-Power,
12-Bit Serial ADCs in 8-Pin SO
MAX1240/MAX1241
+2.7V
6k
DOUT
DOUT
6k
CLOAD = 50pF
CLOAD = 50pF
DGND
DGND
a) High-Z to VOH and VOL to VOH
b) High-Z to VOL and VOH to VOL
Figure 1. Load Circuits for DOUT Enable Time
+2.7V
6k
DOUT
DOUT
6k
CLOAD = 50pF
CLOAD = 50pF
DGND
DGND
a) VOH to High-Z
b) VOLto High-Z
Figure 2. Load Circuits for DOUT Disable Time
__________________________________________Typical Operating Characteristics
(VDD = 3.0V, VREF = 2.5V, fSCLK = 2.1MHz, CL = 20pF, TA = +25°C, unless otherwise noted.)
OPERATING SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.2
1.0
MAX1241
0.8
0.6
0.4
1.0
MAX1241
0.8
2
3
4
SUPPLY VOLTAGE (V)
5
6
0.7
0.6
0.5
0.4
0.3
0.2
0.9
0
MAX1241-03
0.8
1.1
0.2
0.9
OFFSET ERROR (LSB)
SUPPLY CURRENT (mA)
MAX1240
1.4
MAX1240
1.2
1.0
MAX1241-A/NEW
RL = ∞
CODE = 101010100000
1.6
1.3
MAX1241-D
OPERATING SUPPLY CURRENT (mA)
2.0
1.8
OFFSET ERROR
vs. SUPPLY VOLTAGE
SUPPLY CURRENT vs. TEMPERATURE
RLOAD = ∞
CODE = 10101010000
-60
-20
20
0.1
0
60
TEMPERATURE (°C)
100
140
2.25
2.75
3.25
3.75
4.25
4.75
5.25
SUPPLY VOLTAGE (V)
_______________________________________________________________________________________
5
____________________________Typical Operating Characteristics (continued)
(VDD = 3.0V, VREF = 2.5V, fSCLK = 2.1MHz, CL = 20pF, TA = +25°C, unless otherwise noted.)
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
2.0
1.5
1.0
0.5
4.0
3.5
3.0
2.5
2.0
1.5
3.25
3.75
4.25
4.75
-20
20
60
100
TEMPERATURE (°C)
GAIN ERROR
vs. SUPPLY VOLTAGE
GAIN ERROR
vs. TEMPERATURE
-55
140
-30
-5
20
45
70
95
120 145
MAX1240
INTERNAL REFERENCE VOLTAGE
vs. SUPPLY VOLTAGE
2.5020
MAX1241-08
0.8
MAX1241-07
0.7
0.3
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
0.8
0.4
0
-60
5.25
0.5
0.1
0
2.75
0.6
0.2
1.0
0.5
0
2.25
VDD = 2.7V
0.7
2.5015
0.6
0.5
0.4
0.3
2.5010
0.5
VREF (V)
GAIN ERROR (LSB)
0.6
GAIN ERROR (LSB)
VDD = 2.7V
0.7
MAX1241-0X
2.5
4.5
OFFSET ERROR (LSB)
3.0
OFFSET ERROR vs. TEMPERATURE
0.8
MAX1241-B
3.5
5.0
SHUTDOWN SUPPLY CURRENT (μA)
MAX1241-C/NEW
SHUTDOWN SUPPLY CURRENT (μA)
4.0
MAX1241-06
SHUTDOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
0.4
0.3
0.2
0.2
0.1
0.1
2.5005
2.5000
2.4995
2.75
3.25
3.75
4.25
4.75
-55
5.25
-30
-5
20
45
70
95
120 145
2.75
3.25
3.75
4.25
4.75
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
VDD (V)
MAX1240
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
INTEGRAL NONLINEARITY
vs. SUPPLY VOLTAGE
INTEGRAL NONLINEARITY
vs. TEMPERATURE
1.0
VDD = 3.6V
2.499
VDD = 2.7V
1.0
0.8
INL (LSB)
VDD = 2.7V
2.498
2.497
0.8
INL (LSB)
2.500
1.2
0.6
MAX1240
0.4
2.496
5.25
MAX1241-10/NEW
1.2
MAX1241-0Y
2.501
MAX1241-09/NEW
2.25
0.6
0.4
MAX1240
0.2
2.495
0.2
MAX1241
MAX1241
0
2.494
-60
-20
20
60
TEMPERATURE (°C)
6
2.4990
2.25
0
0
VREF (V)
MAX1240/MAX1241
+2.7V, Low-Power,
12-Bit Serial ADCs in 8-Pin SO
100
140
2.25
2.75
3.25
3.75
4.25
SUPPLY VOLTAGE (V)
4.75
5.25
0
-60 -40 -20 0
20 40 60 80 100 120 140
TEMPERATURE (°C)
_______________________________________________________________________________________
+2.7V, Low-Power,
12-Bit Serial ADCs in 8-Pin SO
INTEGRAL NONLINEARITY
vs. CODE
FFT PLOT
0.4
MAX1241-TOC12A
20
MAX1241-11A/NEW
0.6
fAIN = 10kHz, 2.5VP-P
fSAMPLE = 73ksps
0
-20
AMPLITUDE (dB)
INL (LSB)
0.2
0
-0.2
-40
-60
-80
-100
-0.4
-120
-140
-0.6
0
1024
2048
CODE
3072
4096
0
18.75
37.50
FREQUENCY (kHz)
_______________________________________________________________________Pin Description
PIN
NAME
FUNCTION
1
VDD
Positive Supply Voltage: 2.7V to 3.6V, (MAX1240); 2.7V to 5.25V (MAX1241)
2
AIN
Sampling Analog Input, 0V to VREF range
3
SHDN
Three-Level Shutdown Input. Pulling SHDN low shuts the MAX1240/MAX1241 down to 15µA (max)
supply current. Both the MAX1240 and MAX1241 are fully operational with either SHDN high or
unconnected. For the MAX1240, pulling SHDN high enables the internal reference, and letting SHDN
open disables the internal reference and allows for the use of an external reference.
4
REF
Reference Voltage for Analog-to-Digital Conversion. Internal 2.5V reference output for MAX1240;
bypass with 4.7µF capacitor. External reference voltage input for MAX1241, or for MAX1240 with the
internal reference disabled. Bypass REF with a minimum of 0.1µF when using an external reference.
5
GND
Analog and Digital Ground
6
DOUT
Serial Data Output. Data changes state at SCLK’s falling edge. DOUT is high impedance when CS is
high.
7
CS
8
SCLK
Active-Low Chip Select initiates conversions on the falling edge. When CS is high, DOUT is high
impedance.
Serial Clock Input. SCLK clocks data out at rates up to 2.1MHz.
_______________________________________________________________________________________
7
MAX1240/MAX1241
____________________________Typical Operating Characteristics (continued)
(VDD = 3.0V, REF = 2.5V, fSCLK = 2.1MHz, CL = 20pF, TA = +25°C, unless otherwise noted.)
MAX1240/MAX1241
+2.7V, Low-Power,
12-Bit Serial ADCs in 8-Pin SO
+2.7V to +3.6V*
* VDD,MAX = +5.25V (MAX1241)
** 4.7μF (MAX1240)
0.1μF (MAX1241)
4.7μF
0.1μF
1
ANALOG INPUT
0V TO VREF
2
SHUTDOWN
INPUT
3
REFERENCE
INPUT
(MAX1241 ONLY)
4
VDD
SCLK
AIN MAX1240 CS
MAX1241
SHDN
REF
DOUT
GND
8
7
AIN
SERIAL
INTERFACE
COMPARATOR
TRACK INPUT CHOLD
HOLD
ZERO
- +
16pF
CSWITCH
6
9k
RIN
HOLD
TRACK
5
C**
AT THE SAMPLING INSTANT,
THE INPUT SWITCHES FROM
AIN TO GND.
GND
Figure 4. Equivalent Input Circuit
Figure 3. Operational Diagram
_______________Detailed Description
Converter Operation
The MAX1240/MAX1241 use an input track/hold (T/H)
and successive-approximation register (SAR) circuitry
to convert an analog input signal to a digital 12-bit output. No external-hold capacitor is needed for the T/H.
Figure 3 shows the MAX1240/MAX1241 in its simplest
configuration. The MAX1240/MAX1241 convert input
signals in the 0V to VREF range in 9µs, including T/H
acquisition time. The MAX1240’s internal reference is
trimmed to 2.5V, while the MAX1241 requires an external
reference. Both devices accept voltages from 1.0V to
VDD. The serial interface requires only three digital lines
(SCLK, CS, and DOUT) and provides an easy interface
to microprocessors (µPs).
The MAX1240/MAX1241 have two modes: normal and
shutdown. Pulling SHDN low shuts the device down and
reduces supply current below 10µA (VDD ≤ 3.6V), while
pulling SHDN high or leaving it open puts the device
into operational mode. Pulling CS low initiates a conversion. The conversion result is available at DOUT in
unipolar serial format. The serial data stream consists
of a high bit, signaling the end of conversion (EOC), followed by the data bits (MSB first).
Analog Input
Figure 4 illustrates the sampling architecture of the analog-to-digital converter’s (ADC’s) comparator. The fullscale input voltage is set by the voltage at REF.
Track/Hold
In track mode, the analog signal is acquired and stored
in the internal hold capacitor. In hold mode, the T/H
switch opens and maintains a constant input to the
ADC’s SAR section.
8
12-BIT CAPACITIVE DAC
REF
During acquisition, the analog input (AIN) charges
capacitor CHOLD. Bringing CS low ends the acquisition
interval. At this instant, the T/H switches the input side
of CHOLD to GND. The retained charge on CHOLD represents a sample of the input, unbalancing node ZERO at
the comparator’s input.
In hold mode, the capacitive digital-to-analog converter
(DAC) adjusts during the remainder of the conversion
cycle to restore node ZERO to 0V within the limits of 12bit resolution. This action is equivalent to transferring a
charge from CHOLD to the binary-weighted capacitive
DAC, which in turn forms a digital representation of the
analog input signal. At the conversion’s end, the input
side of C HOLD switches back to AIN, and C HOLD
charges to the input signal again.
The time required for the T/H to acquire an input signal
is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens and more time must be
allowed between conversions. The acquisition time
(tACQ) is the maximum time the device takes to acquire
the signal, and is also the minimum time needed for the
signal to be acquired. Acquisition time is calculated by:
tACQ = 9(RS + RIN) x 16pF
where RIN = 9kΩ, RS = the input signal’s source impedance, and tACQ is never less than 1.5µs. Source impedances below 1kΩ do not significantly affect the ADC’s
AC performance.
Higher source impedances can be used if a 0.01µF
capacitor is connected to the analog input. Note that
the input capacitor forms an RC filter with the input
source impedance, limiting the ADC’s input signal
bandwidth.
_______________________________________________________________________________________
+2.7V, Low-Power,
12-Bit Serial ADCs in 8-Pin SO
Analog Input Protection
Internal protection diodes, which clamp the analog
input to VDD and GND, allow the input to swing from
GND - 0.3V to VDD + 0.3V without damage. However,
for accurate conversions near full scale, the input must
not exceed VDD by more than 50mV, or be lower than
GND by 50mV.
If the analog input exceeds 50mV beyond the supplies, limit the input current to 2mA.
Internal Reference (MAX1240)
The MAX1240 has an on-chip voltage reference
trimmed to 2.5V. The internal reference output is connected to REF and also drives the internal capacitive
DAC. The output can be used as a reference voltage
source for other components and can source up to
400µA. Bypass REF with a 4.7µF capacitor. Larger
capacitors increase wake-up time when exiting shutdown (see the section Using SHDN to Reduce Supply
Current). The internal reference is enabled by pulling the
SHDN pin high. Letting SHDN open disables the internal
reference, which allows the use of an external reference,
as described in the External Reference section.
External Reference
The MAX1240/MAX1241 operate with an external reference at the REF pin. To use the MAX1240 with an
external reference, disable the internal reference by letting SHDN open. Stay within the +1.0V to VDD voltage
range to achieve specified accuracy. The minimum
input impedance is 18kΩ for DC currents. During conversion, the external reference must be able to deliver
up to 250µA of DC load current and have an output
impedance of 10Ω or less. The recommended minimum value for the bypass capacitor is 0.1µF. If the reference has higher output impedance or is noisy,
bypass it close to the REF pin with a 4.7µF capacitor.
____________________Serial Interface
Initialization after Power-Up and
Starting a Conversion
When power is first applied, and if SHDN is not pulled
low, it takes the fully discharged 4.7µF reference
bypass capacitor up to 20ms to provide adequate
charge for specified accuracy. With an external reference, the internal reset time is 10µs after the power
supplies have stabilized. No conversions should be
performed during these times.
To start a conversion, pull CS low. At CS’s falling edge,
the T/H enters its hold mode and a conversion is initiated. After an internally timed conversion period, the end
of conversion is signaled by DOUT pulling high. Data
can then be shifted out serially with the external clock.
COMPLETE CONVERSION SEQUENCE
CS
tWAKE
SHDN
DOUT
CONVERSION 0
POWERED UP
CONVERSION 1
POWERED DOWN
POWERED UP
Figure 5. Shutdown Sequence
_______________________________________________________________________________________
9
MAX1240/MAX1241
Input Bandwidth
The ADCs’ input tracking circuitry has a 2.25MHz smallsignal bandwidth, so it is possible to digitize highspeed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. To avoid aliasing of
unwanted high-frequency signals into the frequency
band of interest, anti-alias filtering is recommended.
Using SHDN to Reduce Supply Current
VDD = VREF = 3.0V
RLOAD = ∞, CLOAD = 50pF
CODE = 010101010000
1
SUPPLY CURRNET (mA)
MAX1241 FIG. 06a
10
Power consumption can be reduced significantly by
shutting down the MAX1240/MAX1241 between conversions. Figure 6 shows a plot of average supply current versus conversion rate. Because the MAX1241
uses an external reference voltage (assumed to be present continuously), it “wakes up” from shutdown more
quickly (in 4µs) and therefore provides lower average
supply currents. The wake-up time (tWAKE) is the time
from when SHDN is deasserted to the time when a conversion may be initiated (Figure 5). For the MAX1240,
this time depends on the time in shutdown (Figure 7)
because the external 4.7µF reference bypass capacitor
loses charge slowly during shutdown.
0.1
MAX1240
0.01
MAX1241
0.001
0.1
1
10
100
1k
10k
100k
CONVERSION RATE (Hz)
External Clock
Figure 6. Average Supply Current vs. Conversion Rate
The actual conversion does not require the external
clock. This allows the conversion result to be read back
at the µP’s convenience at any clock rate from up to
2.1MHz. The clock duty cycle is unrestricted if each
clock phase is at least 200ns. Do not run the clock
while a conversion is in progress.
MAX1240/41-07a
1.0
0.8
POWER-UP DELAY (ms)
MAX1240/MAX1241
+2.7V, Low-Power,
12-Bit Serial ADCs in 8-Pin SO
Timing and Control
Conversion-start and data-read operations are controlled
by the CS and SCLK digital inputs. The timing diagrams
of Figures 8 and 9 outline serial-interface operation.
A CS falling edge initiates a conversion sequence: the
T/H stage holds the input voltage, the ADC begins to
convert, and DOUT changes from high impedance to
logic low. SCLK must be kept low during the conversion. An internal register stores the data when the conversion is in progress.
0.6
0.4
0.2
0.0
0.001
0.01
0.1
1
10
TIME IN SHUTDOWN (sec)
Figure 7. Typical Reference Power-Up Delay vs. Time in
Shutdown
CS
1
4
8
12
16
SCLK
DOUT
B11 B10 B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
EOC
INTERFACE IDLE
CONVERSION
IN PROGRESS
TRACK/HOLD
TRACK
STATE
HOLD
7.5μs (tCONV)
CYCLE TIME
EOC
CLOCK OUT SERIAL DATA
TRAILING
ZEROS
IDLE
TRACK
0μs
12.5 × 0.476μs = 5.95μs
HOLD
0μs
0.24μs
TOTAL = 13.7μs
Figure 8. Interface Timing Sequence
10
______________________________________________________________________________________
(tCS)
+2.7V, Low-Power,
12-Bit Serial ADCs in 8-Pin SO
…
tCS0
SCLK
tDO
tCONV
tDV
…
DOUT
tAPR
INTERNAL
T/H
tCH
…
tCL
B2
tTR
B1
B0
tSTR
(TRACK/ACQUIRE)
…
(HOLD)
(TRACK/ACQUIRE)
Figure 9. Detailed Serial-Interface Timing
End of conversion (EOC) is signaled by DOUT going
high. DOUT’s rising edge can be used as a framing
signal. SCLK shifts the data out of this register any time
after the conversion is complete. DOUT transitions on
SCLK’s falling edge. The next falling clock edge produces the MSB of the conversion at DOUT, followed by
the remaining bits. Since there are 12 data bits and one
leading high bit, at least 13 falling clock edges are
needed to shift out these bits. Extra clock pulses occurring after the conversion result has been clocked out,
and prior to a rising edge of CS, produce trailing zeros
at DOUT and have no effect on converter operation.
Minimum cycle time is accomplished by using DOUT’s
rising edge as the EOC signal. Clock out the data with
12.5 clock cycles at full speed. Pull CS high after reading
OUTPUT CODE
11…111
FULL-SCALE
TRANSITION
11…110
11…101
FS = VREF - 1 LSB
1 LSB = VREF
4096
00…011
00…010
00…001
00…000
0
1
2
3
INPUT VOLTAGE (LSBs)
FS
FS - 3/2 LSB
Figure 10. Unipolar Transfer Function, Full Scale (FS) = VREF 1 LSB, Zero Scale (ZS) = GND
the conversion’s LSB. After the specified minimum time
(tCS), CS can be pulled low again to initiate the next
conversion.
Output Coding and Transfer Function
The data output from the MAX1240/MAX1241 is binary,
and Figure 10 depicts the nominal transfer function.
Code transitions occur halfway between successiveinteger LSB values. If VREF = +2.500V, then 1 LSB =
610µV or 2.500V/4096.
____________Applications Information
Connection to Standard Interfaces
The MAX1240/MAX1241 serial interface is fully compatible with SPI/QSPI and MICROWIRE standard serial
interfaces (Figure 11).
If a serial interface is available, set the CPU’s serial
interface in master mode so the CPU generates the serial clock. Choose a clock frequency up to 2.1MHz.
1) Use a general-purpose I/O line on the CPU to pull CS
low. Keep SCLK low.
2) Wait the for the maximum conversion time specified
before activating SCLK. Alternatively, look for a DOUT
rising edge to determine the end of conversion.
3) Activate SCLK for a minimum of 13 clock cycles. The
first falling clock edge produces the MSB of the
DOUT conversion. DOUT output data transitions on
SCLK’s falling edge and is available in MSB-first format. Observe the SCLK to DOUT valid timing characteristic. Data can be clocked into the µP on
SCLK’s rising edge.
4) Pull CS high at or after the 13th falling clock edge. If
CS remains low, trailing zeros are clocked out after
the LSB.
______________________________________________________________________________________
11
MAX1240/MAX1241
tCS
CS
MAX1240/MAX1241
+2.7V, Low-Power,
12-Bit Serial ADCs in 8-Pin SO
5) With CS = high, wait the minimum specified time, tCS,
before initiating a new conversion by pulling CS low.
If a conversion is aborted by pulling CS high before
the conversion’s end, wait for the minimum acquisition time, tACQ, before starting a new conversion.
CS must be held low until all data bits are clocked out.
Data can be output in two bytes or continuously, as
shown in Figure 8. The bytes contain the result of the
conversion padded with one leading 1, and trailing 0s.
I/O
CS
SCK
SCLK
MISO
DOUT
+3V
MAX1240
MAX1241
SS
a) SPI
SPI and MICROWIRE
When using SPI or MICROWIRE, set CPOL = 0 and
CPHA = 0. Conversion begins with a CS falling edge.
DOUT goes low, indicating a conversion in progress. Wait
until DOUT goes high or until the maximum specified
7.5µs conversion time elapses. Two consecutive 1-byte
reads are required to get the full 12 bits from the ADC.
DOUT output data transitions on SCLK’s falling edge and
is clocked into the µP on SCLK’s rising edge.
The first byte contains a leading 1, and seven bits of conversion result. The second byte contains the remaining
five bits and three trailing zeros. See Figure 11 for connections and Figure 12 for timing.
CS
Layout, Grounding, and Bypassing
For best performance, use printed circuit boards. Wirewrap boards are not recommended. Board layout should
ensure that digital and analog signal lines are separated
from each other. Do not run analog and digital (especially
clock) lines parallel to one another, or digital lines underneath the ADC package.
Figure 14 shows the recommended system ground connections. Establish a single-point analog ground (“star”
ground point) at GND, separate from the logic ground.
Connect all other analog grounds and DGND to this star
ground point for further noise reduction. No other digital
12
SCLK
MISO
DOUT
+3V
MAX1240
MAX1241
SS
b) QSPI
QSPI
Set CPOL = CPHA = 0. Unlike SPI, which requires two
1-byte reads to acquire the 12 bits of data from the ADC,
QSPI allows the minimum number of clock cycles necessary to clock in the data. The MAX1240/MAX1241
requires 13 clock cycles from the µP to clock out the 12
bits of data with no trailing zeros (Figure 13). The maximum clock frequency to ensure compatibility with QSPI is
2.097MHz.
CS
SCK
I/O
CS
SK
SCLK
SI
DOUT
MAX1240
MAX1241
c) MICROWIRE
Figure 11. Common Serial-Interface Connections to the
MAX1241
system ground should be connected to this single-point
analog ground. The ground return to the power supply for
this ground should be low impedance and as short as
possible for noise-free operation.
High-frequency noise in the VDD power supply may affect
the ADC’s high-speed comparator. Bypass this supply to
the single-point analog ground with 0.1µF and 4.7µF
bypass capacitors. Minimize capacitor lead lengths for
best supply-noise rejection. If the power supply is very
noisy, a 10Ω resistor can be connected as a lowpass filter
to attenuate supply noise (Figure 14).
______________________________________________________________________________________
+2.7V, Low-Power,
12-Bit Serial ADCs in 8-Pin SO
MAX1240/MAX1241
1ST BYTE READ
2ND BYTE READ
SCLK
CS
tCONV
D11
DOUT*
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
MSB
HIGH-Z
D0
LSB
EOC
*WHEN CS IS HIGH, DOUT = HIGH -Z
Figure 12. SPI/MICROWIRE Serial Interface Timing (CPOL = CPHA = 0)
SCLK
CS
tCONV
D11
MSB
DOUT*
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
LSB
HIGH-Z
EOC
*WHEN CS IS HIGH, DOUT = HIGH -Z
Figure 13. QSPI Serial Interface Timing (CPOL = CPHA = 0)
SUPPLIES
+3V
+3V
GND
+3V
DGND
R* = 10Ω
4.7μF
0.1μF
VDD
GND
MAX1240
MAX1241
DIGITAL
CIRCUITRY
*OPTIONAL
Figure 14. Power-Supply Grounding Condition
______________________________________________________________________________________
13
MAX1240/MAX1241
+2.7V, Low-Power,
12-Bit Serial ADCs in 8-Pin SO
__Ordering Information (continued)
PART
TEMP RANGE
PINPACKAGE
INL
(LSB)
MAX1240AEPA+ -40°C to +85°C
8 PDIP
±1/2
±1
MAX1240BEPA+ -40°C to +85°C
8 PDIP
MAX1240CEPA+ -40°C to +85°C
8 PDIP
±1
MAX1240AESA+ -40°C to +85°C
8 SO
±1/2
MAX1240BESA+ -40°C to +85°C
8 SO
±1
MAX1240CESA+ -40°C to +85°C
8 SO
±1
MAX1240AMJA+ -55°C to +125°C
8 CERDIP†
±1/2
MAX1240BMJA+ -55°C to +125°C
8 CERDIP†
±1
MAX1240CMJA+ -55°C to +125°C
CERDIP†
±1
MAX1241ACPA+
0°C to +70°C
8
8 PDIP
MAX1241BCPA+
0°C to +70°C
8 PDIP
MAX1241CCPA+
0°C to +70°C
8 PDIP
±1
MAX1241ACSA+
0°C to +70°C
8 SO
±1/2
MAX1241BCSA +
0°C to +70°C
8 SO
±1
MAX1241CCSA+
0°C to +70°C
8 SO
±1
MAX1241BC/D
0°C to +70°C
Dice*
±1
MAX1241AEPA+ -40°C to +85°C
8 PDIP
±1/2
±1/2
±1
MAX1241BEPA+ -40°C to +85°C
8 PDIP
±1
MAX1241CEPA+ -40°C to +85°C
8 PDIP
±1
MAX1241AESA+ -40°C to +85°C
8 SO
±1/2
MAX1241BESA+ -40°C to +85°C
8 SO
±1
MAX1241CESA+ -40°C to +85°C
8 SO
±1
MAX1241AMJA+ -55°C to +125°C
8
CERDIP†
±1/2
MAX1241BMJA+ -55°C to +125°C
8 CERDIP†
±1
MAX1241CMJA+ -55°C to +125°C
CERDIP†
Chip Information
PROCESS: BiCMOS
SUBSTRATE CONNECTED TO GND
Package Information
For the latest package outline information and land
patterns, go to www.maxim-ic.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates
RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the
package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
8 PDIP
P8+2
21-0043
—
8 SO
S8+5
21-0041
90-0096
8 CERDIP
J8+2
21-0045
—
±1
8
+Denotes lead(Pb)-free/RoHS-compliant package.
*Dice are specified at TA = +25°C, DC parameters only.
†Contact factory for availability and processing to MIL-STD-883.
14
______________________________________________________________________________________
2.7V, Low-Power,
12-Bit Serial ADCs in 8-Pin SO
REVISION
NUMBER
REVISION
DATE
3
3/10
4
6/10
Future product note removed from one part in the Ordering Information
1
5
8/10
Removed MAX1240BC/D and add MAX1240CC/D
1
DESCRIPTION
Added automotive grade to data sheet
PAGES
CHANGED
1, 2, 3, 7, 9, 14,
15, 16
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
15 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2010 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
MAX1240/MAX1241
Revision History
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