MAX12529ETK+

19-3927; Rev 1; 5/07 KIT ATION EVALU E L B A AVAIL Dual, 96Msps, 12-Bit, IF/Baseband ADC The MAX12529 is a dual, 96Msps, 12-bit analog-to-digital converter (ADC) featuring fully differential wideband track-and-hold (T/H) inputs, driving internal quantizers. The MAX12529 is optimized for low power, small size, and high dynamic performance in intermediate frequency (IF) and baseband sampling applications. This dual ADC operates from a single 3.3V supply, consuming only 980mW while delivering a typical 69.7dB signal-tonoise ratio (SNR) performance at a 175MHz input frequency. The T/H input stages accept single-ended or differential inputs up to 350MHz. In addition to low operating power, the MAX12529 features a 0.66mW powerdown mode to conserve power during idle periods. A flexible reference structure allows the MAX12529 to use the internal 2.048V bandgap reference or accept an externally applied reference and allows the reference to be shared between the two ADCs. The reference structure allows the full-scale analog input range to be adjusted from ±0.35V to ±1.15V. The MAX12529 provides a common-mode reference to simplify design and reduce external component count in differential analog input circuits. The MAX12529 supports either a single-ended or differential input clock. User-selectable divide-by-two (DIV2) and divide-by-four (DIV4) modes allow for design flexibility and help eliminate the negative effects of clock jitter. Wide variations in the clock duty cycle are compensated with the ADC’s internal duty-cycle equalizer (DCE). The MAX12529 features two parallel, 12-bit-wide, CMOS-compatible outputs. The digital output format is pin-selectable to be either two’s complement or Gray code. A separate power-supply input for the digital outputs accepts a 1.7V to 3.6V voltage for flexible interfacing with various logic levels. The MAX12529 is available in a 10mm x 10mm x 0.8mm, 68-pin thin QFN package with exposed paddle (EP), and is specified for the extended (-40°C to +85°C) temperature range. Features ♦ Direct IF Sampling Up to 350MHz ♦ Excellent Dynamic Performance 70.1dB/69.7dB SNR at fIN = 70MHz/175MHz 83.2dBc/78.9dBc SFDR at fIN = 70MHz/175MHz ♦ 3.3V Low-Power Operation 980mW (Differential Clock Mode) 952mW (Single-Ended Clock Mode) ♦ Fully Differential or Single-Ended Analog Input ♦ Adjustable Differential Analog Input Voltage ♦ 750MHz Input Bandwidth ♦ Internal, External, or Shared Reference ♦ Differential or Single-Ended Clock ♦ Accepts 25% to 75% Clock Duty Cycle ♦ User-Selectable DIV2 and DIV4 Clock Modes ♦ Power-Down Mode ♦ CMOS Outputs in Two’s Complement or Gray Code ♦ Out-of-Range and Data-Valid Indicators ♦ Compact, 68-Pin Thin QFN Package (10mm x 10mm x 0.8mm) ♦ Evaluation Kit Available (Order MAX12529EVKIT) Ordering Information TEMP RANGE MAX12529ETK-D -40°C to +85°C 68 Thin QFN-EP* T6800-4 MAX12529ETK+D -40°C to +85°C 68 Thin QFN-EP* T6800-4 Low-Power Data Acquisition PIN-PACKAGE *EP = Exposed paddle. +Denotes lead-free package. D = Dry pack. Selector Guide Applications IF and Baseband Communication Receivers Cellular, LMDS, Point-to-Point Microwave, MMDS, HFC, WLAN I/Q Receivers Medical Imaging Portable Instrumentation Digital Set-Top Boxes PKG CODE PART SAMPLING RATE (Msps) RESOLUTION (Bits) MAX12559 96 14 MAX12558 80 14 MAX12557 65 14 MAX12529 96 12 MAX12528 80 12 MAX12527 65 12 PART Pin Configuration appears at end of data sheet. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com. 1 MAX12529 General Description MAX12529 Dual, 96Msps, 12-Bit, IF/Baseband ADC ABSOLUTE MAXIMUM RATINGS VDD to GND ................................................................-0.3V to +3.6V OVDD to GND............-0.3V to the lower of (VDD + 0.3V) and +3.6V INAP, INAN to GND....-0.3V to the lower of (VDD + 0.3V) and +3.6V INBP, INBN to GND....-0.3V to the lower of (VDD + 0.3V) and +3.6V CLKP, CLKN to GND ........................-0.3V to the lower of (VDD + 0.3V) and +3.6V REFIN, REFOUT to GND ..................-0.3V to the lower of (VDD + 0.3V) and +3.6V REFAP, REFAN, COMA to GND ......-0.3V to the lower of (VDD + 0.3V) and +3.6V REFBP, REFBN, COMB to GND ......-0.3V to the lower of (VDD + 0.3V) and +3.6V DIFFCLK/SECLK, G/T, PD, SHREF, DIV2, DIV4 to GND .........-0.3V to the lower of (VDD + 0.3V) and +3.6V D0A–D11A, D0B–D11B, DAV, DORA, DORB to GND..............................-0.3V to (OVDD + 0.3V) Continuous Power Dissipation (TA = +70°C) 68-Pin Thin QFN 10mm x 10mm x 0.8mm (derate 70mW/°C above +70°C) ....................................4000mW Thermal Resistance θjc........................................................0.4°C/W Operating Temperature Range................................-40°C to +85°C Junction Temperature ...........................................................+150°C Storage Temperature Range .................................-65°C to +150°C Lead Temperature (soldering, 10s)......................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), CL ≈ 10pF at digital outputs, AIN = -1dBFS (differential), DIFFCLK/SECLK = OVDD, PD = GND, SHREF = GND, DIV2 = GND, DIV4 = GND, G/T = GND, fCLK = 96MHz (50% duty cycle), TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DC ACCURACY Resolution 12 Bits Integral Nonlinearity INL fIN = 3MHz ±0.65 ±3.4 LSB Differential Nonlinearity DNL fIN = 3MHz, no missing codes over temperature ±0.4 ±0.8 LSB ±0.04 ±0.7 %FSR ±0.4 ±4.7 %FSR Offset Error Gain Error External reference, VREFIN = 2.048V ANALOG INPUTS (INAP, INAN, INBP, INBN) Differential Input Voltage Range VDIFF Differential or single-ended inputs ±1.024 Common-Mode Input Voltage Analog Input Resistance RIN CPAR Each input, Figure 3 Fixed capacitance to ground, each input, Figure 3 V VDD / 2 V 2.3 kΩ 2 pF Analog Input Capacitance CSAMPLE Switched capacitance, each input, Figure 3 4.5 CONVERSION RATE Maximum Clock Frequency fCLK 96 MHz Minimum Clock Frequency 5 Data Latency fIN = 3MHz Signal-to-Noise Ratio SNR Clock Cycles 70.9 72.2 dBFS 68.6 70.8 fIN = 48MHz 70.6 fIN = 70MHz 70.1 fIN = 175MHz 2 8 Figure 5 DYNAMIC CHARACTERISTICS (VIN = -1dBFS) Small-Signal Noise Floor SSNF Input at -35dBFS MHz 67.4 69.7 _______________________________________________________________________________________ dB Dual, 96Msps, 12-Bit, IF/Baseband ADC (VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), CL ≈ 10pF at digital outputs, AIN = -1dBFS (differential), DIFFCLK/SECLK = OVDD, PD = GND, SHREF = GND, DIV2 = GND, DIV4 = GND, G/T = GND, fCLK = 96MHz (50% duty cycle), TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS fIN = 3MHz Signal-to-Noise Plus Distortion Spurious-Free Dynamic Range SINAD SFDR Second Harmonic THD HD2 Third Harmonic HD3 3rd-Order Intermodulation Distortion Full-Power Bandwidth IM3 FPBW Aperture Delay tAD Aperture Jitter tAJ Output Noise nOUT 67.2 TYP 69.9 fIN = 70MHz 69.7 fIN = 175MHz 64.9 fIN = 3MHz 71.9 UNITS dB 69.1 84.5 fIN = 48MHz 81.7 fIN = 70MHz 83.2 68.8 MAX 70.5 fIN = 48MHz fIN = 175MHz Total Harmonic Distortion MIN dBc 78.9 fIN = 3MHz -82.1 fIN = 48MHz -78.7 fIN = 70MHz -80.2 fIN = 175MHz -77.9 fIN = 3MHz -85.7 fIN = 48MHz -82.4 fIN = 70MHz -86.3 fIN = 175MHz -78.9 fIN = 3MHz -89.6 fIN = 48MHz -86.9 fIN = 70MHz -84 fIN = 175MHz -88.6 -70 dBc -66.7 dBc dBc fIN1 = 69MHz at AIN1 = -7dBFS, fIN2 = 72MHz at AIN2 = -7dBFS -82 fIN1 = 173MHz at AIN1 = -7dBFS, fIN2 = 177MHz at AIN2 = -7dBFS -87 Input at -0.2dBFS, -3dB rolloff 750 MHz Figure 5 1.2 ns < 0.1 psRMS 0.44 LSBRMS INAP = INAN = COMA, INBP = INBN = COMB dBc _______________________________________________________________________________________ 3 MAX12529 ELECTRICAL CHARACTERISTICS (continued) MAX12529 Dual, 96Msps, 12-Bit, IF/Baseband ADC ELECTRICAL CHARACTERISTICS (continued) (VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), CL ≈ 10pF at digital outputs, AIN = -1dBFS (differential), DIFFCLK/SECLK = OVDD, PD = GND, SHREF = GND, DIV2 = GND, DIV4 = GND, G/T = GND, fCLK = 96MHz (50% duty cycle), TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL Overdrive Recovery Time CONDITIONS MIN TYP ±10% beyond full scale 1 fINA or fINB = 70MHz at -1dBFS 92 fINA or fINB = 175MHz at -1dBFS 85 MAX UNITS Clock cycle INTERCHANNEL CHARACTERISTICS Crosstalk Rejection Gain Matching ±0.02 Offset Matching ±0.05 dB ±0.12 dB %FSR INTERNAL REFERENCE (REFOUT) REFOUT Output Voltage VREFOUT REFOUT Load Regulation REFOUT Temperature Coefficient 2.000 -1mA < IREFOUT < +1mA TCREF REFOUT Short-Circuit Current 2.048 2.080 V 35 mV/mA 55 ppm/°C Short to VDD—sinking 0.24 Short to GND—sourcing 2.1 mA BUFFERED REFERENCE MODE (REFIN is driven by REFOUT or an external 2.048V single-ended reference source; VREFAP/VREFAN/VCOMA and VREFBP/VREFBN/VCOMB are generated internally) REFIN Input Voltage VREFIN 2.048 V REFIN Input Resistance RREFIN > 50 MΩ COM_ Output Voltage VCOMA VCOMB VCOM_ = VDD / 2 REF_P Output Voltage VREFAP VREFBP VREF_P = VDD / 2 + (VREFIN x 3/8) 2.418 V REF_N Output Voltage VREFAN VREFBN VREF_N = VDD / 2 - (VREFIN x 3/8) 0.882 V Differential Reference Voltage VREFA VREFB Differential Reference Temperature Coefficient TCREF VREFA = VREFAP - VREFAN VREFB = VREFBP - VREFBN 1.60 1.450 1.65 1.536 30 1.70 V 1.590 V ppm/°C UNBUFFERED EXTERNAL REFERENCE (REFIN = GND, VREFAP/VREFAN/VCOMA and VREFBP/VREFBN/VCOMB are applied externally, VCOMA = VCOMB = VDD / 2) REF_P Input Voltage VREFAP VREFBP VREF_P - VCOM +0.768 V REF_N Input Voltage VREFAN VREFBN VREF_N - VCOM -0.768 V COM_ Input Voltage VCOM VCOM_ = VDD / 2 1.65 V Differential Reference Voltage VREFA VREFB VREF_ = VREF_P - VREF_N = VREFIN x 3/4 1.536 V 4 _______________________________________________________________________________________ Dual, 96Msps, 12-Bit, IF/Baseband ADC (VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), CL ≈ 10pF at digital outputs, AIN = -1dBFS (differential), DIFFCLK/SECLK = OVDD, PD = GND, SHREF = GND, DIV2 = GND, DIV4 = GND, G/T = GND, fCLK = 96MHz (50% duty cycle), TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS REF_P Sink Current IREFAP IREFBP VREF_P = 2.418V 1.2 mA REF_N Source Current IREFAN IREFBN VREF_N = 0.882V 0.85 mA COM_ Sink Current ICOMA ICOMB VCOM_ = 1.65V 0.85 mA REF_P, REF_N Capacitance CREF_P, CREF_N 13 pF COM_ Capacitance CCOM_ 6 pF CLOCK INPUTS (CLKP, CLKN) Single-Ended Input High Threshold Single-Ended Input Low Threshold VIH DIFFCLK/SECLK = GND, CLKN = GND VIL DIFFCLK/SECLK = GND, CLKN = GND 0.8 x VDD V 0.2 x VDD V Minimum Differential Clock Input Voltage Swing DIFFCLK/SECLK = OVDD 0.2 VP-P Differential Input Common-Mode Voltage DIFFCLK/SECLK = OVDD VDD / 2 V CLK_ Input Resistance RCLK Each input, Figure 4 5 kΩ CLK_ Input Capacitance CCLK Each input 2 pF DIGITAL INPUTS (DIFFCLK/SECLK, G/T, PD, DIV2, DIV4) Input High Threshold VIH Input Low Threshold VIL V 0.2 x OVDD ±5 OVDD applied to input Input Leakage Current Digital Input Capacitance 0.8 x OVDD Input connected to ground ±5 CDIN 5 V µA pF DIGITAL OUTPUTS (D0A–D11A, D0B–D11B, DORA, DORB, DAV) Output-Voltage Low VOL D0A–D11A, D0B–D11B, DORA, DORB: ISINK = 200µA 0.2 DAV: ISINK = 600µA Output-Voltage High Tri-State Leakage Current (Note 2) VOH ILEAK V 0.2 D0A–D11A, D0B–D11B, DORA, DORB: ISOURCE = 200µA OVDD 0.2 DAV: ISOURCE = 600µA OVDD 0.2 V OVDD applied to input ±5 Input connected to ground ±5 µA _______________________________________________________________________________________ 5 MAX12529 ELECTRICAL CHARACTERISTICS (continued) MAX12529 Dual, 96Msps, 12-Bit, IF/Baseband ADC ELECTRICAL CHARACTERISTICS (continued) (VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), CL ≈ 10pF at digital outputs, AIN = -1dBFS (differential), DIFFCLK/SECLK = OVDD, PD = GND, SHREF = GND, DIV2 = GND, DIV4 = GND, G/T = GND, fCLK = 96MHz (50% duty cycle), TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS D0A–D11A, DORA, D0B–D11B and DORB Tri-State Output Capacitance (Note 2) COUT 3 pF DAV Tri-State Output Capacitance (Note 2) CDAV 6 pF POWER REQUIREMENTS Analog Supply Voltage Digital Output Supply Voltage Analog Supply Current Analog Power Dissipation Digital Output Supply Current 6 VDD OVDD IVDD PVDD IOVDD 3.15 3.30 3.60 V 1.70 2.0 VDD V Normal operating mode fIN = 175MHz, single-ended clock (DIFFCLK/SECLK = GND) 288.5 Normal operating mode fIN = 175MHz, differential clock (DIFFCLK/SECLK = OVDD) 297 Power-down mode (PD = OVDD) clock idle 0.2 Normal operating mode fIN = 175MHz, single-ended clock (DIFFCLK/SECLK = GND) 952 Normal operating mode fIN = 175MHz, differential clock (DIFFCLK/SECLK = OVDD) 980 Power-down mode (PD = OVDD) clock idle 0.66 Normal operating mode fIN = 175MHz, CL ≈ 10pF Power-down mode (PD = OVDD) clock idle mA 322 mW 1063 24 mA 0.001 _______________________________________________________________________________________ Dual, 96Msps, 12-Bit, IF/Baseband ADC (VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), CL ≈ 10pF at digital outputs, AIN = -1dBFS (differential), DIFFCLK/SECLK = OVDD, PD = GND, SHREF = GND, DIV2 = GND, DIV4 = GND, G/T = GND, fCLK = 96MHz (50% duty cycle), TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS TIMING CHARACTERISTICS (Figure 5) Clock Pulse-Width High tCH 5.1 ns Clock Pulse-Width Low tCL 5.1 ns Data-Valid Delay tDAV (Notes 3, 4) 3.15 Data Setup Time Before Rising Edge of DAV tSETUP (Notes 3, 4) 3.6 ns Data Hold Time After Rising Edge of DAV tHOLD (Notes 3, 4) 3.55 ns Data Setup Time Before Falling Edge of Clock tDATASETUP (Notes 3, 4) 2.25 ns Data Hold Time After Falling Edge of Clock tDATAHOLD (Notes 3, 4) 3.25 ns Wake-Up Time from Power-Down tWAKE 5.8 VREFIN = 2.048V 6.65 10 ns ms Specifications ≥ +25°C guaranteed by production test, < +25°C guaranteed by design and characterization. During power-down, D0A–D11A, D0B–D11B, DORA, DORB, and DAV are high impedance. Data outputs settle to VIH or VIL. Guaranteed by design and characterization. Note 1: Note 2: Note 3: Note 4: Typical Operating Characteristics (VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference mode), CL ≈ 5pF at digital outputs, AIN = -1dBFS (differential), DIFFCLK/SECLK = OVDD, PD = GND, G/T = GND, fCLK = 96MHz (50% duty cycle), TA = +25°C, unless otherwise noted.) -60 HD2 -80 HD3 -100 -40 -60 HD2 -80 HD3 -100 -120 5 10 15 20 25 30 35 40 45 ANALOG INPUT FREQUENCY (MHz) -20 -40 -60 HD3 fCLK = 96Msps fIN = 70.1001MHz AIN = -0.98dBFS SNR = 70.2dB SINAD = 69.8dB THD = -80.6dBc SFDR = 84.3dBc HD2 = -93.2dBc HD3 = -85.5dBc HD2 -80 -100 -120 0 MAX12529 toc02 MAX12529 toc01 fCLK = 96Msps fIN = 47.89893MHz AIN = -0.98dBFS SNR = 70.7dB SINAD = 69.6dB THD = -76.1dBc SFDR = 79.8dBc HD2 = -79.7dBc HD3 = -85.2dBc FFT PLOT (65,536-POINT DATA RECORD) 0 AMPLITUDE (dBFS) -40 -20 AMPLITUDE (dBFS) AMPLITUDE (dBFS) -20 fCLK = 96Msps fIN = 2.99919MHz AIN = -1.00dBFS SNR = 70.9dB SINAD = 70.5dB THD = -81.1dBc SFDR = 85dBc HD2 = -86.2dBc HD3 = -91.5dBc FFT PLOT (65,536-POINT DATA RECORD) 0 MAX12529 toc03 FFT PLOT (65,536-POINT DATA RECORD) 0 -120 0 5 10 15 20 25 30 35 40 45 ANALOG INPUT FREQUENCY (MHz) 0 5 10 15 20 25 30 35 40 45 ANALOG INPUT FREQUENCY (MHz) _______________________________________________________________________________________ 7 MAX12529 ELECTRICAL CHARACTERISTICS (continued) Typical Operating Characteristics (continued) (VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference mode), CL ≈ 5pF at digital outputs, AIN = -1dBFS (differential), DIFFCLK/SECLK = OVDD, PD = GND, G/T = GND, fCLK = 96MHz (50% duty cycle), TA = +25°C, unless otherwise noted.) -60 -80 -100 -60 2fIN2 - fIN1 -80 2fIN1 - fIN2 -20 10 15 20 25 30 35 40 45 -60 2fIN2 - fIN1 -80 2fIN1 - fIN2 -120 0 5 10 15 20 25 30 35 40 45 0 5 10 15 20 25 30 35 40 45 ANALOG INPUT FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz) INTEGRAL NONLINEARITY vs. DIGITAL OUTPUT CODE DIFFERENTIAL NONLINEARITY vs. DIGITAL OUTPUT CODE SNR, SINAD vs. ANALOG INPUT FREQUENCY (fCLK = 96MHz, AIN = -1dBFS) 0.75 0.50 0.50 DNL (LSB) 0.25 0.75 0 0.25 0 -0.25 -0.25 -0.50 -0.50 -0.75 -0.75 75 MAX12529 toc09 1.00 MAX12529 toc07 1.00 SNR 70 SNR, SINAD (dB) 5 -40 fCLK = 96Msps fIN1 = 172.50146MHz AIN1 = -6.97dBFS fIN2 = 177.50244MHz AIN2 = -7.01dBFS IM3 = -84.7dBc -100 -120 0 fIN1 fIN2 -100 -120 INL (LSB) -40 0 MAX12529 toc06 -20 fIN1 AMPLITUDE (dBFS) -40 fCLK = 96Msps fIN2 fIN1 = 68.50049MHz AIN1 = -7dBFS fIN2 = 71.50049MHz AIN2 = -7.04dBFS IM3 = -84.5dBc MAX12529 toc08 AMPLITUDE (dBFS) -20 0 AMPLITUDE (dBFS) fCLK = 96Msps fIN = 175.00049MHz AIN = -1.00dBFS SNR = 69.8dB SINAD = 69.3dB THD = -78.3dBc SFDR = 80.3dBc HD2 = -80.2dBc HD3 = -89.3dBc HD2 HD3 MAX12529 toc04 0 TWO-TONE IMD PLOT (65,536-POINT DATA RECORD) TWO-TONE IMD (65,536-POINT DATA RECORD) MAX12529 toc05 FFT PLOT (65,536-POINT DATA RECORD) SINAD 65 60 55 fIN = 2.99908MHz fIN = 2.99908MHz -1.00 512 1024 1536 2048 2560 3072 3584 4096 513 1025 1537 2049 2561 3073 3585 4096 DIGITAL OUTPUT CODE DIGITAL OUTPUT CODE -THD, SFDR vs. ANALOG INPUT FREQUENCY (fCLK = 96MHz, AIN = -1dBFS) SNR, SINAD vs. ANALOG INPUT AMPLITUDE (fCLK = 96MHz, fIN = 70MHz) SFDR SNR, SINAD (dB) 80 -THD 75 70 65 60 55 50 0 50 100 150 200 fIN (MHz) 250 300 350 75 70 65 60 55 50 45 40 35 30 25 20 15 10 0 50 100 150 200 250 300 350 fIN (MHz) -THD, SFDR vs. ANALOG INPUT AMPLITUDE (fCLK = 96MHz, fIN = 70MHz) MAX12529 toc11 85 MAX12529 toc10 90 8 50 0 SNR SINAD 90 85 80 75 70 65 60 55 50 45 40 35 30 25 MAX12529 toc12 0 -THD, SFDR (dBc) -1.00 -THD, SFDR (dBc) MAX12529 Dual, 96Msps, 12-Bit, IF/Baseband ADC SFDR -THD -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 AIN (dBFS) AIN (dBFS) _______________________________________________________________________________________ Dual, 96Msps, 12-Bit, IF/Baseband ADC SINAD -THD MAX12529 toc15 SFDR SNR 70 SINAD 65 60 55 DIV4 = 0VDD DIV2 = GND 50 20 30 40 50 60 70 80 90 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 AIN (dBFS) AIN (dBFS) fCLK (MHz) -THD, SFDR vs. CLOCK SPEED (fIN = 70MHz, AIN = -1dBFS) SNR, SINAD vs. CLOCK SPEED (fIN = 175MHz, AIN = -1dBFS) -THD, SFDR vs. CLOCK SPEED (fIN = 175MHz, AIN = -1dBFS) 70 SNR, SINAD (dB) 90 85 80 -THD 75 70 80 SINAD 65 60 DIV4 = 0VDD DIV2 = GND DIV4 = 0VDD DIV2 = GND 60 30 40 50 60 70 80 90 100 -THD 70 65 DIV4 = 0VDD DIV2 = GND 55 50 20 75 60 55 65 SFDR 85 100 MAX12529 toc18 SNR -THD, SFDR (dBc) SFDR 90 MAX12529 toc17 75 MAX12529 toc16 95 50 20 30 40 50 60 70 80 90 100 20 30 40 50 60 70 80 90 100 fCLK (MHz) fCLK (MHz) SNR, SINAD vs. ANALOG SUPPLY VOLTAGE (fCLK = 96MHz, fIN = 70MHz) -THD, SFDR vs. ANALOG SUPPLY VOLTAGE (fCLK = 96MHz, fIN = 70MHz) SNR, SINAD vs. ANALOG SUPPLY VOLTAGE (fCLK = 96MHz, fIN = 175MHz) 70 SINAD 68 66 SFDR 90 -THD, SFDR (dBc) SNR 80 -THD 70 60 3.2 3.3 3.4 VDD (V) 3.5 3.6 68 SINAD 66 62 40 3.1 SNR 70 64 50 64 72 SNR, SINAD (dB) 72 100 MAX12529 toc19 74 MAX12529 toc21 fCLK (MHz) MAX12529 toc20 -THD, SFDR (dBc) 75 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 100 SNR, SINAD (dB) 90 85 80 75 70 65 60 55 50 45 40 35 30 25 SNR, SINAD (dB) SNR MAX12529 toc14 MAX12529 toc13 75 70 65 60 55 50 45 40 35 30 25 20 15 10 SNR, SINAD vs. CLOCK SPEED (fIN = 70MHz, AIN = -1dBFS) -THD, SFDR vs. ANALOG INPUT AMPLITUDE (fCLK = 96MHz, fIN = 175MHz) -THD, SFDR (dBc) SNR, SINAD (dB) SNR, SINAD vs. ANALOG INPUT AMPLITUDE (fCLK = 96MHz, fIN = 175MHz) 60 3.1 3.2 3.3 3.4 VDD (V) 3.5 3.6 3.1 3.2 3.3 3.4 3.5 3.6 VDD (V) _______________________________________________________________________________________ 9 MAX12529 Typical Operating Characteristics (continued) (VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference mode), CL ≈ 5pF at digital outputs, AIN = -1dBFS (differential), DIFFCLK/SECLK = OVDD, PD = GND, G/T = GND, fCLK = 96MHz (50% duty cycle), TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference mode), CL ≈ 5pF at digital outputs, AIN = -1dBFS (differential), DIFFCLK/SECLK = OVDD, PD = GND, G/T = GND, fCLK = 96MHz (50% duty cycle), TA = +25°C, unless otherwise noted.) SNR, SINAD vs. DIGITAL SUPPLY VOLTAGE (fCLK = 96MHz, fIN = 70MHz) -THD 70 65 80 70 SINAD 68 75 -THD 70 65 60 66 60 55 55 64 50 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VDD (V) OVDD (V) OVDD (V) SNR, SINAD vs. DIGITAL SUPPLY VOLTAGE (fCLK = 96MHz, fIN = 175MHz) -THD, SFDR vs. DIGITAL SUPPLY VOLTAGE (fCLK = 96MHz, fIN = 175MHz) PDISS, IVDD (ANALOG) vs. ANALOG SUPPLY VOLTAGE (fCLK = 96MHz, fIN = 175MHz) SNR 70 65 3.6 90 MAX12529 toc25 75 3.5 SINAD 60 SFDR 85 80 75 -THD 70 65 55 PDISS (ANALOG) 1100 900 700 IVDD 500 300 60 55 50 1300 MAX12529 toc27 3.4 PDISS, IVDD (mW, mA) 3.3 MAX12529 toc26 3.2 -THD, SFDR (dBc) 3.1 SNR, SINAD (dB) SNR SFDR 85 -THD, SFDR (dBc) SNR, SINAD (dB) 75 72 90 MAX12529 toc23 SFDR 80 -THD, SFDR (dBc) 74 MAX12529 toc22 85 -THD, SFDR vs. DIGITAL SUPPLY VOLTAGE (fCLK = 96MHz, fIN = 70MHz) MAX12529 toc24 -THD, SFDR vs. ANALOG SUPPLY VOLTAGE (fCLK = 96MHz, fIN = 175MHz) 100 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 OVDD (V) OVDD (V) VDD (V) PDISS, IOVDD (DIGITAL) vs. DIGITAL SUPPLY VOLTAGE (fCLK = 96MHz, fIN = 175MHz) SNR, SINAD vs. CLOCK DUTY CYCLE (fIN = 70MHz, AIN = -1dBFS) -THD, SFDR vs. CLOCK DUTY CYCLE (fIN = 70MHz, AIN = -1dBFS) 3.4 3.5 3.6 MAX12529 toc30 85 40 IOVDD -THD, SFDR (dBc) 50 20 SINAD 65 60 55 SFDR 0 SINGLE-ENDED CLOCK DRIVE 50 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 3.5 3.7 OVDD (V) 80 75 -THD 70 65 10 10 3.3 90 MAX12529 toc29 70 3.2 3.1 PDISS (DIGITAL) 60 30 SNR SNR, SINAD (dB) 70 75 MAX12529 toc28 90 80 PDISS, IOVDD (mW, mA) MAX12529 Dual, 96Msps, 12-Bit, IF/Baseband ADC 25 30 35 40 45 50 55 60 CLOCK DUTY CYCLE (%) SINGLE-ENDED CLOCK DRIVE 60 65 70 25 30 35 40 45 50 55 60 CLOCK DUTY CYCLE (%) ______________________________________________________________________________________ 65 70 Dual, 96Msps, 12-Bit, IF/Baseband ADC SNR, SINAD vs. TEMPERATURE (fIN = 175MHz, AIN = -1dBFS) SFDR SNR, SINAD (dB) 68 SINAD 66 64 62 80 75 -THD 70 65 60 60 -40 -15 10 35 60 85 -40 -15 TEMPERATURE (°C) 10 35 60 85 TEMPERATURE (°C) GAIN ERROR vs. TEMPERATURE (VREFIN = 2.048V) OFFSET ERROR vs. TEMPERATURE 0.2 OFFSET ERROR (%FSR) 2 1 0 -1 MAX12529 toc34 0.3 MAX12529 toc33 3 GAIN ERROR (%FSR) MAX12529 toc32 85 -THD, SFDR (dBc) SNR 70 90 MAX12529 toc31 72 -THD, SFDR vs. TEMPERATURE (fIN = 175MHz, AIN = -1dBFS) 0.1 0 -0.1 -0.2 -2 -0.3 -3 -40 -15 10 35 TEMPERATURE (°C) 60 85 -40 -15 10 35 60 85 TEMPERATURE (°C) ______________________________________________________________________________________ 11 MAX12529 Typical Operating Characteristics (continued) (VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference mode), CL ≈ 5pF at digital outputs, AIN = -1dBFS (differential), DIFFCLK/SECLK = OVDD, PD = GND, G/T = GND, fCLK = 96MHz (50% duty cycle), TA = +25°C, unless otherwise noted.) MAX12529 Dual, 96Msps, 12-Bit, IF/Baseband ADC Pin Description PIN NAME 1, 4, 5, 9, 13, 14, 17 GND Converter Ground. Connect all ground pins and the exposed paddle (EP) together. 2 INAP Channel A Positive Analog Input 3 INAN Channel A Negative Analog Input 6 COMA Channel A Common-Mode Voltage I/O. Bypass COMA to GND with a 0.1µF capacitor. REFAP Channel A Positive Reference I/O. Channel A conversion range is ±2/3 x (VREFAP - VREFAN). Bypass REFAP with a 0.1µF capacitor to GND. Connect a 10µF and a 1µF bypass capacitor between REFAP and REFAN. Place the 1µF REFAP-to-REFAN capacitor as close to the device as possible on the same side of the PC board. REFAN Channel A Negative Reference I/O. Channel A conversion range is ±2/3 x (VREFAP - VREFAN). Bypass REFAN with a 0.1µF capacitor to GND. Connect a 10µF and a 1µF bypass capacitor between REFAP and REFAN. Place the 1µF REFAP-to-REFAN capacitor as close to the device as possible on the same side of the PC board. REFBN Channel B Negative Reference I/O. Channel B conversion range is ±2/3 x (VREFBP - VREFBN). Bypass REFBN with a 0.1µF capacitor to GND. Connect a 10µF and a 1µF bypass capacitor between REFBP and REFBN. Place the 1µF REFBP-to-REFBN capacitor as close to the device as possible on the same side of the PC board. 11 REFBP Channel B Positive Reference I/O. Channel B conversion range is ±2/3 x (VREFBP - VREFBN). Bypass REFBP with a 0.1µF capacitor to GND. Connect a 10µF and a 1µF bypass capacitor between REFBP and REFBN. Place the 1µF REFBP-to-REFBN capacitor as close to the device as possible on the same side of the PC board. 12 COMB 15 INBN 16 INBP 7 8 10 FUNCTION Channel B Common-Mode Voltage I/O. Bypass COMB to GND with a 0.1µF capacitor. Channel B Negative Analog Input Channel B Positive Analog Input 18 DIFFCLK/ SECLK 19 CLKN 20 CLKP 21 DIV2 Differential/Single-Ended Input Clock Drive. This input selects between single-ended or differential clock input drives. DIFFCLK/SECLK = GND: Selects single-ended clock input drive. DIFFCLK/SECLK = OVDD: Selects differential clock input drive. Negative Clock Input. In differential clock input mode (DIFFCLK/SECLK = OVDD), connect a differential clock signal between CLKP and CLKN. In single-ended clock mode (DIFFCLK/SECLK = GND), apply the clock signal to CLKP and connect CLKN to GND. Positive Clock Input. In differential clock input mode (DIFFCLK/SECLK = OVDD), connect a differential clock signal between CLKP and CLKN. In single-ended clock mode (DIFFCLK/SECLK = GND), apply the single-ended clock signal to CLKP and connect CLKN to GND. Divide-by-Two Clock-Divider Digital Control Input. See Table 2 for details. 22 DIV4 Divide-by-Four Clock-Divider Digital Control Input. See Table 2 for details. 23–26, 61, 62, 63 VDD Analog Power Input. Connect VDD to a 3.15V to 3.60V power supply. Bypass VDD to GND with a parallel capacitor combination of ≥ 10µF and 0.1µF. Connect all VDD pins to the same potential. 27, 43, 60 OVDD Output-Driver Power Input. Connect OVDD to a 1.7V to VDD power supply. Bypass OVDD to GND with a parallel capacitor combination of ≥ 10µF and 0.1µF. 28, 29, 45, 46 N.C. 12 No Connection ______________________________________________________________________________________ Dual, 96Msps, 12-Bit, IF/Baseband ADC PIN NAME FUNCTION 30 D0B Channel B CMOS Digital Output, Bit 0 (LSB) 31 D1B Channel B CMOS Digital Output, Bit 1 32 D2B Channel B CMOS Digital Output, Bit 2 33 D3B Channel B CMOS Digital Output, Bit 3 34 D4B Channel B CMOS Digital Output, Bit 4 35 D5B Channel B CMOS Digital Output, Bit 5 36 D6B Channel B CMOS Digital Output, Bit 6 37 D7B Channel B CMOS Digital Output, Bit 7 38 D8B Channel B CMOS Digital Output, Bit 8 39 D9B Channel B CMOS Digital Output, Bit 9 40 D10B Channel B CMOS Digital Output, Bit 10 41 D11B Channel B CMOS Digital Output, Bit 11 (MSB) 42 DORB Channel B Data Out-of-Range Indicator. The DORB digital output indicates when the channel B analog input voltage is out of range. DORB = 1: Digital outputs exceed full-scale range. DORB = 0: Digital outputs are within full-scale range. 44 DAV Data-Valid Digital Output. The rising edge of DAV indicates that data is present on the digital outputs. The MAX12529 evaluation kit utilizes DAV to latch data into any external back-end digital logic. 47 D0A Channel A CMOS Digital Output, Bit 0 (LSB) 48 D1A Channel A CMOS Digital Output, Bit 1 49 D2A Channel A CMOS Digital Output, Bit 2 50 D3A Channel A CMOS Digital Output, Bit 3 51 D4A Channel A CMOS Digital Output, Bit 4 52 D5A Channel A CMOS Digital Output, Bit 5 53 D6A Channel A CMOS Digital Output, Bit 6 54 D7A Channel A CMOS Digital Output, Bit 7 55 D8A Channel A CMOS Digital Output, Bit 8 56 D9A Channel A CMOS Digital Output, Bit 9 57 D10A Channel A CMOS Digital Output, Bit 10 58 D11A 59 DORA 64 G/T Channel A CMOS Digital Output, Bit 11 (MSB) Channel A Data Out-of-Range Indicator. The DORA digital output indicates when the channel A analog input voltage is out of range. DORA = 1: Digital outputs exceed full-scale range. DORA = 0: Digital outputs are within full-scale range. Output Format Select Digital Input. G/T = GND: Two’s-complement output format selected. G/T = OVDD: Gray-code output format selected. 65 PD Power-Down Digital Input. PD = GND: ADCs are fully operational. PD = OVDD: ADCs are powered down. ______________________________________________________________________________________ 13 MAX12529 Pin Description (continued) Dual, 96Msps, 12-Bit, IF/Baseband ADC MAX12529 Pin Description (continued) PIN NAME 66 SHREF 67 REFOUT 68 REFIN — EP FUNCTION Shared Reference Digital Input. SHREF = VDD: Shared reference enabled. SHREF = GND: Shared reference disabled. When sharing the reference, externally connect REFAP and REFBP together to ensure that VREFAP equals VREFBP. Similarly, when sharing the reference, externally connect REFAN to REFBN together to ensure that VREFAN = VREFBN. Internal Reference Voltage Output. The REFOUT output voltage is 2.048V and REFOUT can deliver 1mA. For internal reference operation, connect REFOUT directly to REFIN or use a resistive divider from REFOUT to set the voltage at REFIN. Bypass REFOUT to GND with a ≥ 0.1µF capacitor. For external reference operation, REFOUT is not required and must be bypassed to GND with a ≥ 0.1µF capacitor. Single-Ended Reference Analog Input. For internal reference and buffered external reference operation, apply a 0.7V to 2.3V DC reference voltage to REFIN. Bypass REFIN to GND with a 4.7µF capacitor. Within its specified operating voltage, REFIN has a > 50MΩ input impedance, and the differential reference voltage (VREF_P - VREF_N) is generated from REFIN. For unbuffered external reference operation, connect REFIN to GND. In this mode REF_P, REF_N, and COM_ are high-impedance inputs that accept the external reference voltages. Exposed Paddle. EP is internally connected to GND. Externally connect EP to GND to achieve specified dynamic performance. + MAX12529 Σ x2 − FLASH ADC DAC IN_P STAGE 1 STAGE 2 STAGE 9 IN_N STAGE 10 END OF PIPELINE DIGITAL ERROR CORRECTION D0_ THROUGH D11_ Figure 1. Pipeline Architecture—Stage Blocks Detailed Description The MAX12529 uses a 10-stage, fully differential, pipelined architecture (Figure 1) that allows for highspeed conversion while minimizing power consumption. Samples taken at the inputs move progressively through the pipeline stages every half clock cycle. From input to output the total latency is 8 clock cycles. 14 Each pipeline converter stage converts its input voltage to a digital output code. At every stage, except the last, the error between the input voltage and the digital output code is multiplied and passed along to the next pipeline stage. Digital error correction compensates for ADC comparator offsets in each pipeline stage and ensures no missing codes. Figure 2 shows the MAX12529 functional diagram. ______________________________________________________________________________________ Dual, 96Msps, 12-Bit, IF/Baseband ADC MAX12529 CLOCK INAP INAN REFAP COMA REFAN 12-BIT PIPELINE ADC CHANNEL A REFERENCE SYSTEM DIGITAL ERROR CORRECTION DATA FORMAT OUTPUT DRIVERS D0A TO D11A DORA MAX12529 G/T REFIN INTERNAL REFERENCE GENERATOR REFOUT DAV SHREF REFBP COMB REFBN INBP INBN OVDD CHANNEL B REFERENCE SYSTEM 12-BIT PIPELINE ADC DIGITAL ERROR CORRECTION DATA FORMAT OUTPUT DRIVERS D0B TO D11B DORB CLOCK VDD DIFFCLK/SECLK CLOCK CLKP CLKN DIV2 DIV4 CLOCK DIVIDER DUTY-CYCLE EQUALIZER POWER CONTROL AND BIAS CIRCUITS PD GND Figure 2. Functional Diagram ______________________________________________________________________________________ 15 MAX12529 Dual, 96Msps, 12-Bit, IF/Baseband ADC Table 1. Reference Modes BOND WIRE INDUCTANCE 1.5nH VDD VREFIN MAX12529 IN_P CPAR 2pF BOND WIRE INDUCTANCE 1.5nH *CSAMPLE 4.5pF VDD IN_N CPAR 2pF *CSAMPLE 4.5pF 0.7V to 2.3V SAMPLING CLOCK *THE EFFECTIVE RESISTANCE OF THE SWITCHED SAMPLING CAPACITORS IS: RIN = 1 fCLK x CSAMPLE Figure 3. Internal T/H Circuit Analog Inputs and Input Track-and-Hold (T/H) Amplifier Figure 3 displays a simplified functional diagram of the input T/H circuit. This input T/H circuit allows for high analog input frequencies of 175MHz and beyond and supports a VDD / 2 common-mode input voltage. The MAX12529 sampling clock controls the switchedcapacitor input T/H architecture (Figure 3) allowing the analog input signals to be stored as charge on the sampling capacitors. These switches are closed (track mode) when the sampling clock is high and open (hold mode) when the sampling clock is low (Figure 4). The analog input signal source must be able to provide the dynamic currents necessary to charge and discharge the sampling capacitors. To avoid signal degradation, these capacitors must be charged to one-half LSB accuracy within one-half of a clock cycle. The analog input of the MAX12529 supports differential or singleended input drive. For optimum performance with differential inputs, balance the input impedance of IN_P and IN_N and set the common-mode voltage to mid-supply (VDD / 2). The MAX12529 provides the optimum common-mode voltage of VDD / 2 through the COM output when operating in internal reference mode and buffered external reference mode. This COM output voltage can be used to bias the input network as shown in Figures 9, 10, and 11. Reference Output An internal bandgap reference is the basis for all the internal voltages and bias currents used in the 16 REFERENCE MODE Internal Reference Mode. REFIN is driven by REFOUT either through a 35% VREFOUT direct short or a resistive divider. to 100% VCOM_ = VDD / 2 VREFOUT VREF_P = VDD / 2 + 3/8 x VREFIN VREF_N = VDD / 2 - 3/8 x VREFIN < 0.5V Buffered External Reference Mode. An external 0.7V to 2.3V reference voltage is applied to REFIN. VCOM_ = VDD / 2 VREF_P = VDD / 2 + 3/8 x VREFIN VREF_N = VDD / 2 - 3/8 x VREFIN Unbuffered External Reference Mode. REF_P, REF_N, and COM_ are driven by external reference sources. The full-scale analog input range is ±(VREF_P - VREF_N) x 2/3. MAX12529. The power-down logic input (PD) enables and disables the reference circuit. REFOUT has approximately 17kΩ to GND when the MAX12529 is powered down. The reference circuit requires 10ms to power up and settle to its final value when power is applied to the MAX12529 or when PD transitions from high to low. The internal bandgap reference produces a buffered reference voltage of 2.048V ±1% at the REFOUT pin with a ±50ppm/°C temperature coefficient. Connect an external ≥ 0.1µF bypass capacitor from REFOUT to GND for stability. REFOUT sources up to 1mA and sinks up to 0.1mA for external circuits with a 35mV/mA load regulation. Short-circuit protection limits IREFOUT to a 2.1mA source current when shorted to GND and a 0.24mA sink current when shorted to VDD. Similar to REFOUT, REFIN should be bypassed with a 4.7µF capacitor to GND. Reference Configurations The MAX12529 full-scale analog input range is ±2/3 x VREF with a VDD / 2 ±0.5V common-mode input range. VREF is the voltage difference between REFAP (REFBP) and REFAN (REFBN). The MAX12529 provides three modes of reference operation. The voltage at REFIN (VREFIN) selects the reference operation mode (Table 1). Connect REFOUT to REFIN either with a direct short or through a resistive divider to enter internal reference mode. COM_, REF_P, and REF_N are low-impedance outputs with VCOM_ = VDD / 2, VREF_P = VDD / 2 + 3/8 x VREFIN, and VREF_N = VDD / 2 - 3/8 x VREFIN. Bypass REF_P, REF_N, and COM_ each with a 0.1µF capacitor to GND. Bypass REF_P to REF_N with a 10µF capacitor. ______________________________________________________________________________________ Dual, 96Msps, 12-Bit, IF/Baseband ADC Clock Duty-Cycle Equalizer The MAX12529 has an internal clock duty-cycle equalizer, which makes the converter insensitive to the duty cycle of the signal applied to CLKP and CLKN. The converters allow clock duty-cycle variations from 25% to 75% without negatively impacting the dynamic performance. The clock duty-cycle equalizer uses a delay-locked loop (DLL) to create internal timing signals that are duty-cycle independent. Due to this DLL, the MAX12529 requires approximately 100 clock cycles to acquire and lock to new clock frequencies. Clock Input and Clock Control Lines The MAX12529 accepts both differential and singleended clock inputs with a wide 25% to 75% input clock duty cycle. For single-ended clock input operation, connect DIFFCLK/SECLK and CLKN to GND. Apply an external single-ended clock signal to CLKP. To reduce clock jitter, the external single-ended clock must have sharp falling edges. For differential clock input operation, connect DIFFCLK/SECLK to OV DD . Apply an external differential clock signal to CLKP and CLKN. Consider the clock input as an analog input and route it away from any other analog inputs and digital signal lines. CLKP and CLKN enter high impedance when the MAX12529 is powered down (Figure 4). Low clock jitter is required for the specified SNR performance of the MAX12529. The analog inputs are sampled on the falling (rising) edge of CLKP (CLKN), requiring this edge to have the lowest possible jitter. Jitter limits the maximum SNR performance of any ADC according to the following relationship: ⎛ ⎞ 1 SNR = 20 × log ⎜ ⎟ 2 × π × f × t ⎝ IN J⎠ where fIN represents the analog input frequency and tJ is the total system clock jitter. Clock jitter is especially critical for undersampling applications. For instance, assuming that clock jitter is the only noise source, to obtain the specified 69.5dB of SNR with an input frequency of 175MHz, the system must have less than 0.31ps of clock jitter. However, in reality there are other noise sources such as thermal noise and quantization noise that contribute to the system noise requiring the clock jitter to be less than 0.2ps to obtain the specified 69.5dB of SNR at 175MHz. Clock-Divider Control Inputs (DIV2, DIV4) The MAX12529 features three different modes of sampling/clock operation (see Table 2). Pulling both control lines low, the clock-divider function is disabled and the converters sample at full clock speed. Pulling DIV4 low and DIV2 high enables the divide-by-two feature, which sets the sampling speed to one-half the selected clock frequency. In divide-by-four mode, the converter sampling speed is set to one-fourth the clock speed of the MAX12529. Divide-by-four mode is achieved by applying a high level to DIV4 and a low level to DIV2. The option to select either one-half or one-fourth of the clock speed for ______________________________________________________________________________________ 17 MAX12529 Bypass REFIN and REFOUT to GND with a 0.1µF capacitor. The REFIN input impedance is very large (> 50MΩ). When driving REFIN through a resistive divider, use resistances ≥ 10kΩ to avoid loading REFOUT. Buffered external reference mode is virtually identical to the internal reference mode except that the reference source is derived from an external reference and not the MAX12529’s internal bandgap reference. In buffered external reference mode, apply a stable reference voltage source between 0.7V to 2.3V at REFIN. Pins COM_, REF_P, and REF_N are low-impedance outputs with VCOM_ = VDD / 2, VREF_P = VDD / 2 + 3/8 x VREFIN, and VREF_N = VDD / 2 - 3/8 x VREFIN. Bypass REF_P, REF_N, and COM_ each with a 0.1µF capacitor to GND. Bypass REF_P to REF_N with a 10µF capacitor. Connect REFIN to GND to enter unbuffered external reference mode. Connecting REFIN to GND deactivates the on-chip reference buffers for COM_, REF_P, and REF_N. With their buffers deactivated, COM_, REF_P, and REF_N become high-impedance inputs and must be driven with separate, external reference sources. Drive VCOM_ to VDD / 2 ±5%, and drive REF_P and REF_N so VCOM_ = (VREF_P_ + VREF_N_) / 2. The analog input range is ±(V REF_P_ - V REF_N ) x 2/3. Bypass REF_P, REF_N, and COM_ each with a 0.1µF capacitor to GND. Bypass REF_P to REF_N with a 10µF capacitor. For all reference modes, bypass REFOUT with a 0.1µF and REFIN with a 4.7µF capacitor to GND. The MAX12529 also features a shared reference mode, in which the user can achieve better channel-to-channel matching. When sharing the reference (SHREF = VDD), externally connect REFAP and REFBP together to ensure that VREFAP = VREFBP. Similarly, when sharing the reference, externally connect REFAN to REFBN together to ensure that VREFAN = VREFBN. Connect SHREF to GND to disable the shared reference mode of the MAX12529. In this independent reference mode, a better channel-to-channel isolation is achieved. For detailed circuit suggestions and how to drive the ADC in buffered/unbuffered external reference mode, see the Applications Information section. MAX12529 Dual, 96Msps, 12-Bit, IF/Baseband ADC Table 2. Clock-Divider Control Inputs VDD S1H MAX12529 10kΩ DIV4 DIV2 0 0 Clock Divider Disabled fSAMPLE = fCLK 0 1 Divide-by-Two Clock Divider fSAMPLE = fCLK / 2 1 0 Divide-by-Four Clock Divider fSAMPLE = fCLK / 4 1 1 Not Allowed CLKP 10kΩ S2H DUTY-CYCLE EQUALIZER S1L 10kΩ cuitry can be latched with the rising edge of the conversion clock (CLKP - CLKN). CLKN Data-Valid Output DAV is a single-ended version of the input clock that is compensated to correct for any input clock duty-cycle variations. The MAX12529 output data changes on the falling edge of DAV, and DAV rises once the output data is valid. The falling edge of DAV is synchronized to have a 5.8ns delay from the falling edge of the input clock. Output data at D0A/B–D11A/B and DORA/B are valid from 3.6ns before the rising edge of DAV to 3.55ns after the rising edge of DAV. 10kΩ S2L GND SWITCHES S1_ AND S2_ ARE OPEN DURING POWER-DOWN MAKING CLKP AND CLKN HIGH IMPEDANCE. SWITCHES S2_ ARE OPEN IN SINGLE-ENDED CLOCK MODE. Figure 4. Simplified Clock Input Circuit sampling provides design flexibility, relaxes clock requirements, and can minimize clock jitter. DAV enters high impedance when the MAX12529 is powered down (PD = OV DD ). DAV enters its highimpedance state 10ns after the rising edge of PD and becomes active again 10ns after PD transitions low. DAV can sink and source 600µA and has three times the driving capabilities of D0A/B–D11A/B and DORA/B. DAV is typically used to latch the MAX12529 output data into an external digital back-end circuit. Keep the capacitive load on DAV as low as possible (< 15pF) to avoid large digital currents feeding back into the analog portion of the MAX12529, thereby degrading its dynamic performance. Buffering DAV externally isolates it from heavy System Timing Requirements Figure 5 shows the timing relationship between the clock, analog inputs, DAV indicator, DOR_ indicators, and the resulting output data. The analog input is sampled on the falling (rising) edge of CLKP (CLKN) and the resulting data appears at the digital outputs 8 clock cycles later. The DAV indicator is synchronized with the digital output and optimized for use in latching data into digital back-end circuitry. Alternatively, digital back-end cir- N+4 DIFFERENTIAL ANALOG INPUT (IN_P–IN_N) (VREF_P - VREF_N) x 2/3 N+5 N+3 N-3 N-2 N-1 N N+1 FUNCTION N+6 N +2 N+7 N+9 N+8 (VREF_N - VREF_P) x 2/3 tAD CLKN CLKP tDAV tCL tCH DAV tSETUP D0_–D13_ tHOLD N-3 N-2 N-1 N N+1 N+2 N+3 N+4 N+5 N+6 tDATAHOLD DOR 8.0 CLOCK-CYCLE DATA LATENCY tDATASETUP Figure 5. System Timing Diagram 18 ______________________________________________________________________________________ N+7 N+8 N+9 Dual, 96Msps, 12-Bit, IF/Baseband ADC Data Out-of-Range Indicator The DORA and DORB digital outputs indicate when the analog input voltage is out of range. When DOR_ is high, the analog input is out of range. When DOR_ is low, the analog input is within range. The valid differential input range is from (V REF_P - V REF_N ) x 2/3 to (V REF_N VREF_P) x 2/3. Signals outside of this valid differential range cause DOR_ to assert high as shown in Table 1. DOR is synchronized with DAV and transitions along with the output data D11_–D0_. There is an 8 clockcycle latency in the DOR function as is with the output data (Figure 5). DOR_ is high impedance when the MAX12529 is in power-down (PD = high). DOR_ enters a high-impedance state within 10ns after the rising edge of PD and becomes active 10ns after PD’s falling edge. Digital Output Data and Output Format Selection The MAX12529 provides two 12-bit, parallel, tri-state output buses. D0A/B–D11A/B and DORA/B update on the falling edge of DAV and are valid on the rising edge of DAV. The MAX12529 output data format is either Gray code or two’s complement depending on the logic input G/T. With G/T high, the output data format is Gray code. With G/T low, the output data format is set to two’s complement. See Figure 8 for a binary-to-Gray and Gray-tobinary code conversion example. The following equations, Table 3, Figure 6, and Figure 7 define the relationship between the digital output and the analog input. Gray Code (G/T = 1): VIN_P - VIN_N = 2/3 x (VREF_P - VREF_N) x 2 x (CODE10 - 2048) / 4096 Two’s Complement (G/T = 0): VIN_P - VIN_N = 2/3 x (VREF_P - VREF_N) x 2 x CODE10 / 4096 where CODE10 is the decimal equivalent of the digital output code as shown in Table 3. Table 3. Output Codes vs. Input Voltage GRAY-CODE OUTPUT CODE (G/T = 1) BINARY D11A–D0A D11B–D0B TWO’S-COMPLEMENT OUTPUT CODE (G/T = 0) DECIMAL HEXADECIMAL EQUIVALENT EQUIVALENT OF DOR OF D11A–D0A D11A–D0A D11B–D0B D11B–D0B (CODE10) BINARY D11A–D0A D11B–D0B DECIMAL VIN_P - VIN_N HEXADECIMAL EQUIVALENT VREF_P = 2.418V EQUIVALENT OF VREF_N = 0.882V DOR OF D11A–D0A D11A–D0A D11B–D0B D11B–D0B (CODE10) 1000 0000 0000 1 0x800 +4095 0111 1111 1111 1 0x7FF +2047 > +1.0235V (DATA OUT OF RANGE) 1000 0000 0000 0 0x800 +4095 0111 1111 1111 0 0x7FF +2047 +1.0235V 1000 0000 0001 0 0x801 +4094 0111 1111 1110 0 0x7FE +2046 +1.0230V 1100 0000 0011 0 0xC03 +2050 0000 0000 0010 0 0x002 +2 +0.0010V 1100 0000 0001 0 0xC01 +2049 0000 0000 0001 0 0x001 +1 +0.0005V 1100 0000 0000 0 0xC00 +2048 0000 0000 0000 0 0x000 0 +0.0000V 0100 0000 0000 0 0x400 +2047 1111 1111 1111 0 0xFFF -1 -0.0005V 0100 0000 0001 0 0x401 +2046 1111 1111 1110 0 0xFFE -2 -0.0010V 0000 0000 0001 0 0x001 +1 1000 0000 0001 0 0x801 -2047 -1.0235V 0000 0000 0000 0 0x000 0 1000 0000 0000 0 0x800 -2048 -1.0240V -2048 < -1.0240V (DATA OUT OF RANGE) 0000 0000 0000 1 0x000 0 1000 0000 0000 1 0x800 ______________________________________________________________________________________ 19 MAX12529 capacitive loads. Refer to the MAX12529 EV kit schematic for recommendations of how to drive the DAV signal through an external buffer. 1 LSB = 4/3 x (VREFP - VREFN) / 4096 2/3 x (VREFP - VREFN) 1 LSB = 4/3 x (VREFP - VREFN) / 4096 2/3 x (VREFP - VREFN) 2/3 x (VREFP - VREFN) 0x7FF 0x7FE 0x800 0x801 0x7FD 0x803 GRAY OUTPUT CODE (LSB) TWO'S-COMPLEMENT OUTPUT CODE (LSB) MAX12529 Dual, 96Msps, 12-Bit, IF/Baseband ADC 0x001 0x000 0xFFF 0xC01 0xC00 0xC00 0x803 0x802 0x002 0x003 0x801 0x800 0x001 0x000 -2047 -2045 -1 0 +1 +2045 +2047 DIFFERENTIAL INPUT VOLTAGE (LSB) 2/3 x (VREFP - VREFN) -2047 -2045 -1 0 +1 +2045 +2047 DIFFERENTIAL INPUT VOLTAGE (LSB) Figure 6. Two’s-Complement Transfer Function (G/T = 0) Figure 7. Gray-Code Transfer Function (G/T = 1) The digital outputs D0A/B–D11A/B are high impedance when the MAX12529 is in power-down (PD = 1) mode. D0A/B–D11A/B enter this state 10ns after the rising edge of PD and become active again 10ns after PD transitions low. Keep the capacitive load on the MAX12529 digital outputs D0A/B–D11A/B as low as possible (< 15pF) to avoid large digital currents feeding back into the analog portion of the MAX12529 and degrading its dynamic performance. Adding external digital buffers on the digital outputs helps isolate the MAX12529 from heavy capacitive loads. To improve the dynamic performance of the MAX12529, add 220Ω resistors in series with the digital outputs close to the MAX12529. Refer to the MAX12529 EV kit schematic for guidelines of how to drive the digital outputs through 220Ω series resistors and external digital output buffers. In power-down mode all internal circuits are off, the analog supply current reduces to less than 100µA, and the digital supply current reduces to less than 1µA. The following list shows the state of the analog inputs and digital outputs in power-down mode: Power-Down Input 6) CLKP and CLKN clock inputs enter a high-impedance state (Figure 4). The MAX12529 has two power modes that are controlled with a power-down digital input (PD). With PD low, the MAX12529 is in its normal operating mode. With PD high, the MAX12529 is in power-down mode. The power-down mode allows the MAX12529 to efficiently use power by transitioning to a low-power state when conversions are not required. Additionally, the MAX12529 parallel output bus goes high-impedance in power-down mode, allowing other devices on the bus to be accessed. 20 1) INAP/B and INAN/B analog inputs are disconnected from the internal input amplifier (Figure 3). 2) REFOUT has approximately 17kΩ to GND. 3) REFAP/B, COMA/B, and REFAN/B enter a highimpedance state with respect to VDD and GND, but there is an internal 4kΩ resistor between REFAP/B and COMA/B, as well as an internal 4kΩ resistor between REFAN/B and COMA/B. 4) D0A–D11A, D0B–D11B, DORA, and DORB enter a high-impedance state. 5) DAV enters a high-impedance state. The wake-up time from power-down mode is dominated by the time required to charge the capacitors at REF_P, REF_N, and COM. In internal reference mode and buffered external reference mode the wake-up time is typically 10ms. When operating in the unbuffered external reference mode the wake-up time is dependent on the external reference drivers. ______________________________________________________________________________________ Dual, 96Msps, 12-Bit, IF/Baseband ADC GRAY-TO-BINARY CODE CONVERSION 1) THE MOST SIGNIFICANT GRAY-CODE BIT IS THE SAME AS THE MOST SIGNIFICANT BINARY BIT. 1) THE MOST SIGNIFICANT BINARY BIT IS THE SAME AS THE MOST SIGNIFICANT GRAY-CODE BIT. D11 0 D7 1 1 1 0 D3 1 0 0 1 D0 1 0 0 0 BIT POSITION D11 BINARY 0 GRAY CODE 0 2) SUBSEQUENT GRAY-CODE BITS ARE FOUND ACCORDING TO THE FOLLOWING EQUATION: 0 0 1 D3 1 1 GRAYX = BINARYX + BINARYX + 1 BINARY10 = 0 + 1 GRAY10 = 1 BINARY10 = 1 D7 1 1 0 D3 1 0 1 0 BIT POSITION GRAY CODE BINARYX = BINARYX+1 + GRAYX BINARY10 = BINARY11 + GRAY10 1 D0 0 WHERE + IS THE EXCLUSIVE OR FUNCTION (SEE TRUTH TABLE BELOW) AND X IS THE BIT POSITION: GRAY10 = 1 + 0 + 1 BINARY GRAY10 = BINARY10 + BINARY11 D11 0 2) SUBSEQUENT BINARY BITS ARE FOUND ACCORDING TO THE FOLLOWING EQUATION: WHERE + IS THE EXCLUSIVE OR FUNCTION (SEE TRUTH TABLE BELOW) AND X IS THE BIT POSITION: 0 D7 1 MAX12529 BINARY-TO-GRAY CODE CONVERSION 0 1 D0 1 0 0 D11 BIT POSITION BINARY 0 GRAY CODE 0 D7 1 0 0 1 D3 1 1 0 1 D0 0 1 0 BIT POSITION GRAY CODE + 0 1 3) REPEAT STEP 2 UNTIL COMPLETE: BINARY 1 3) REPEAT STEP 2 UNTIL COMPLETE: GRAY9 = BINARY9 + BINARY10 BINARY9 = BINARY10 + GRAY9 GRAY9 = 1 + 1 BINARY9 = 1 + 0 GRAY9 = 0 BINARY9 = 1 D11 0 1 D7 + 1 1 0 D3 1 0 0 1 D0 1 0 0 BIT POSITION D11 BINARY 0 D7 1 0 0 1 D3 1 1 0 1 D0 0 1 0 BIT POSITION GRAY CODE + 0 1 0 GRAY CODE 0 4) THE FINAL GRAY-CODE CONVERSION IS: D11 D7 1 1 BINARY 4) THE FINAL BINARY CONVERSION IS: D3 D0 BIT POSITION D11 D7 D3 D0 BIT POSITION 0 1 1 1 0 1 0 0 1 1 0 0 BINARY 0 1 0 0 1 1 1 0 1 0 1 0 GRAY CODE 0 1 0 0 1 1 1 0 1 0 1 0 GRAY CODE 0 1 1 1 0 1 0 0 1 1 0 0 BINARY EXCLUSIVE OR TRUTH TABLE FIGURE 8 SHOWS THE GRAY-TO-BINARY AND BINARY-TO-GRAY CODE CONVERSION IN OFFSET BINARY FORMAT. THE OUTPUT FORMAT OF THE MAX12529 IS TWO'S-COMPLEMENT BINARY, HENCE EACH MSB OF THE TWO'S-COMPLEMENT OUTPUT CODE MUST BE INVERTED TO REFLECT TRUE OFFSET BINARY FORMAT. A B 0 0 1 1 0 1 0 1 Y = A + B 0 1 1 0 Figure 8. Binary-to-Gray and Gray-to-Binary Code Conversion ______________________________________________________________________________________ 21 MAX12529 Dual, 96Msps, 12-Bit, IF/Baseband ADC An RF transformer (Figure 9) provides an excellent solution to convert a single-ended input source signal to a fully differential signal, required by the MAX12529 for optimum performance. Connecting the center tap of the transformer to COM provides a VDD / 2 DC level shift to the input. Although a 1:1 transformer is shown, a step-up transformer can be selected to reduce the drive requirements. A reduced signal swing from the input driver, such as an op amp, can also improve the overall distortion. The configuration of Figure 9 is good for frequencies up to Nyquist (fCLK / 2). The circuit of Figure 10 converts a single-ended input signal to fully differential just as Figure 9. However, Figure 10 utilizes an additional transformer to improve the common-mode rejection allowing high-frequency signals beyond the Nyquist frequency. A set of 75Ω Applications Information Using Transformer Coupling In general, the MAX12529 provides better SFDR and THD with fully differential input signals than singleended input drive, especially for input frequencies above 125MHz. In differential input mode, even-order harmonics are lower as both inputs are balanced, and each of the ADC inputs only requires half the signal swing compared to single-ended input mode. IN_P 5.6pF 0.1μF 1 VIN 6 49.9Ω 0.5% 24.9Ω MAX12529 T1 N.C. 5 2 VIN COM_ N.C. 0.1μF 3 0.1μF 0Ω IN_P MAX4108 4 5.6pF MINI-CIRCUITS 49.9Ω 0.5% ADT1-1WT 24.9Ω 100Ω MAX12529 COM_ 0.1μF IN_N 100Ω 24.9Ω 5.6pF IN_N 5.6pF 24.9Ω Figure 9. Transformer-Coupled Input Drive for Input Frequencies Up to Nyquist Figure 11. Single-Ended, AC-Coupled Input Drive 0Ω* IN_P CIN 0.1μF 1 VIN N.C. 5 T1 6 2 3 4 MINI-CIRCUITS ADT1-1WT 1 75Ω 0.5% N.C. N.C. 75Ω 0.5% 5 T2 6 2 3 4 MINI-CIRCUITS ADT1-1WT RIN 110Ω 0.5% MAX12529 N.C. COM_ 110Ω 0.5% 0.1μF 0Ω* IN_N *0Ω RESISTORS CAN BE REPLACED WITH LOW-VALUE RESISTORS TO LIMIT THE INPUT BANDWIDTH. CIN RIN Figure 10. Transformer-Coupled Input Drive for Input Frequencies Beyond Nyquist 22 ______________________________________________________________________________________ Dual, 96Msps, 12-Bit, IF/Baseband ADC MAX12529 3.3V 0.1μF 2.2μF VDD REF_P REFIN 0.1μF 0.1μF 1 5 16.2kΩ 3 0.1μF 1 47Ω 300μF 6V 0.1μF REF_N MAX4230 4 10μF MAX12529 5 1μF MAX6029 (EUK21) 2.048V 0.1μF 2 2 COM_ REFOUT 1.47kΩ GND 0.1μF 0.1μF NOTE: ONE FRONT-END REFERENCE CIRCUIT IS CAPABLE OF SOURCING UP TO 15mA AND SINKING UP TO 30mA OF OUTPUT CURRENT. 3.3V 0.1μF 2.2μF VDD REF_P REFIN 0.1μF 10μF MAX12529 0.1μF REF_N 0.1μF COM_ REFOUT 0.1μF GND 0.1μF Figure 12. External Buffered (MAX4230) Reference Drive Using a MAX6029 Bandgap Reference and 110Ω termination resistors provide an equivalent 50Ω termination to the signal source. The second set of termination resistors connects to COM_ providing the correct input common-mode voltage. Two 0Ω resistors in series with the analog inputs allow high IF input frequencies. These 0Ω resistors can be replaced with lowvalue resistors to limit the input bandwidth. The input network in Figure 10 can be modified to enhance the frequency-range specific AC performance of the MAX12529 by simply replacing the input capaci- tance with a series network of resistor (RIN) and capacitor (CIN). Table 4 displays a selection of resistors and capacitors that are recommended to help improve the already excellent performance of this ADC for specific applications requiring only a certain range of input frequencies. Single-Ended AC-Coupled Input Signal Figure 11 shows an AC-coupled, single-ended input application. The MAX4108 provides high speed, high bandwidth, low noise, and low distortion to maintain the input signal integrity. ______________________________________________________________________________________________________ 23 MAX12529 Dual, 96Msps, 12-Bit, IF/Baseband ADC 3.3V 3V 0.1μF 0.1μF 1 2.2μF 5 MAX6029 (EUK30) 20kΩ 1% REF_P 20kΩ 1% 2 VDD REFOUT 0.1μF 10μF MAX12529 2.413V 1 4 REF_N 47Ω 0.1μF MAX4230 3 0.47μF 330μF 6V 10μF 6V 1.47kΩ 52.3kΩ 1% COM_ 0.1μF REFIN GND 1.647V 1 4 47Ω MAX4230 3 3.3V 330μF 6V 10μF 6V 52.3kΩ 1% 1.47kΩ 0.1μF 4 47Ω REF_P MAX4230 3 20kΩ 1% 2.2μF 0.880V 1 20kΩ 1% 0.1μF 0.1μF VDD REFOUT 0.1μF 10μF 6V 330μF 6V 10μF 0.1μF 0.1μF MAX12529 1.47kΩ REF_N 0.1μF 20kΩ 1% COM_ 0.1μF GND REFIN Figure 13. External Unbuffered Reference Driving Multiple ADCs Table 4. Component Selection to Enhance the Frequency-Range Specific AC Performance CIN COMPONENT VALUES (pF) RIN COMPONENT VALUES (Ω) 12 to 22 0 10MHz to 125MHz 12 50 > 125MHz 5.6 0 INPUT FREQUENCY RANGE < 10MHz 24 Buffered External Reference Drives Multiple ADCs The buffered external reference mode allows for more control over the MAX12529 reference voltage and allows multiple converters to use a common reference. The REFIN input impedance is > 50MΩ. Figure 12 shows the MAX6029 precision 2.048V bandgap reference used as a common reference for multiple converters. The 2.048V output of the MAX6029 passes through a single-pole 10Hz LP filter to the MAX4230. The MAX4250 buffers the 2.048V reference and provides additional 10Hz LP filtering before its output is applied to the REFIN input of the MAX12529. ______________________________________________________________________________________ Dual, 96Msps, 12-Bit, IF/Baseband ADC The unbuffered external reference mode allows for precise control over the MAX12529 reference and allows multiple converters to use a common reference. Connecting REFIN to GND disables the internal reference, allowing REF_P, REF_N, and COM_ to be driven directly by a set of external reference sources. Figure 13 uses a MAX6029 precision 3.000V bandgap reference as a common reference for multiple converters. A seven-component resistive divider chain follows the MAX6029 voltage reference. The 0.47µF capacitor along this chain creates a 10Hz LP filter. Three MAX4230 amplifiers buffer taps along this resistor chain providing 2.413V, 1.647V, and 0.880V to the MAX12529 REF_P, REF_N, and COM_ reference inputs. The feedback around the MAX4230 op amps provides additional 10Hz LP filtering. Reference voltages 2.413V and 0.880V set the full-scale analog input range for the converter to ±1.022V (±[VREF_P - VREF_N] x 2/3). Note that one single power supply for all active circuit components removes any concern regarding powersupply sequencing when powering up or down. Grounding, Bypassing, and Board Layout The MAX12529 requires high-speed board layout design techniques. Refer to the MAX12527/MAX12528/ MAX12529/MAX12557/MAX12558/MAX12559 EV kit data sheet for a board layout reference. Locate all bypass capacitors as close to the device as possible, preferably on the same side as the ADC, using surfacemount devices for minimum inductance. Bypass VDD to GND with a 220µF ceramic capacitor in parallel with at least one 10µF, one 4.7µF, and one 0.1µF ceramic capacitor. Bypass OVDD to GND with a 220µF ceramic capacitor in parallel with at least one 10µF, one 4.7µF, and one 0.1µF ceramic capacitor. High-frequency bypassing/decoupling capacitors should be located as close as possible to the converter supply pins. Multilayer boards with ample ground and power planes produce the highest level of signal integrity. All grounds and the exposed backside paddle of the MAX12529 package (package code: T6800-2) must be connected to the same ground plane. The MAX12529 relies on the exposed backside paddle connection for a low-inductance ground connection. Isolate the ground plane from any noisy digital system ground planes such as a DSP or output buffer ground. Route high-speed digital signal traces away from the sensitive analog traces. Keep all signal lines short and free of 90° turns. Ensure that the differential, analog input network layout is symmetric and that all parasitic components are balanced equally. Refer to the MAX12529 EV kit data sheet for an example of symmetric input layout. Parameter Definitions Integral Nonlinearity (INL) INL is the deviation of the values on an actual transfer function from a straight line. For the MAX12529, this straight line is between the endpoints of the transfer function, once offset and gain errors have been nullified. INL deviations are measured at every step of the transfer function and the worst-case deviation is reported in the Electrical Characteristics table. Differential Nonlinearity (DNL) DNL is the difference between an actual step width and the ideal value of 1 LSB. A DNL error specification of less than 1 LSB guarantees no missing codes and a monotonic transfer function. For the MAX12529, DNL deviations are measured at every step of the transfer function and the worst-case deviation is reported in the Electrical Characteristics table. Offset Error Offset error is a figure of merit that indicates how well the actual transfer function matches the ideal transfer function at a single point. Ideally, the midscale MAX12529 transition occurs at 0.5 LSB above midscale. The offset error is the amount of deviation between the measured midscale transition point and the ideal midscale transition point. Gain Error Gain error is a figure of merit that indicates how well the slope of the actual transfer function matches the slope of the ideal transfer function. The slope of the actual transfer function is measured between two data points: positive full scale and negative full scale. Ideally, the positive full-scale MAX12529 transition occurs at 1.5 LSBs below positive full scale, and the negative full-scale transition occurs at 0.5 LSB above negative full scale. The gain error is the difference of the measured transition points minus the difference of the ideal transition points. Small-Signal Noise Floor (SSNF) SSNF is the integrated noise and distortion power in the Nyquist band for small-signal inputs. The DC offset is excluded from this noise calculation. For this converter, a small signal is defined as a single tone with an amplitude of -35dBFS. This parameter captures the thermal and quantization noise characteristics of the data converter and can be used to help calculate the overall noise figure of a digital receiver signal path. ______________________________________________________________________________________ 25 MAX12529 Unbuffered External Reference Drives Multiple ADCs MAX12529 Dual, 96Msps, 12-Bit, IF/Baseband ADC Signal-to-Noise Ratio (SNR) For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC’s resolution (N bits): SNR[max] = 6.02 × N + 1.76 In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter, etc. SNR is computed by taking the ratio of the RMS signal to the RMS noise. RMS noise includes all spectral components to the Nyquist frequency excluding the fundamental, the first six harmonics (HD2 through HD7), and the DC offset. SNR = 20 x log (SIGNALRMS / NOISERMS) Signal-to-Noise Plus Distortion (SINAD) SINAD is computed by taking the ratio of the RMS signal to the RMS noise plus distortion. RMS noise plus distortion includes all spectral components to the Nyquist frequency excluding the fundamental and the DC offset. Total Harmonic Distortion (THD) THD is the ratio of the RMS sum of the first six harmonics of the input signal to the fundamental itself. This is expressed as: ⎛ V22 + V32 + V4 2 + V52 + V62 + V72 THD = 20 × log ⎜ ⎜ V1 ⎝ ⎞ ⎟ ⎟ ⎠ where V1 is the fundamental amplitude, and V2 through V7 are the amplitudes of the 2nd- through 7th-order harmonics (HD2 through HD7). Spurious-Free Dynamic Range (SFDR) SFDR is the ratio expressed in decibels of the RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next largest spurious component, excluding DC offset. 3rd-Order Intermodulation (IM3) IM3 is the power of the 3rd-order intermodulation product relative to the input power of either of the two input tones fIN1 and fIN2. The individual input tone power levels are set to -7dBFS for the MAX12529. The 3rd-order intermodulation products are 2 x fIN1 - fIN2 and 2 x fIN2 - fIN1. Aperture Jitter Figure 14 shows the aperture jitter (tAJ), which is the sample-to-sample variation in the aperture delay. 26 CLKN CLKP tAD ANALOG INPUT tAJ SAMPLED DATA T/H HOLD TRACK HOLD Figure 14. T/H Aperture Timing Aperture Delay Aperture delay (tAD) is the time defined between the rising edge of the sampling clock and the instant when an actual sample is taken (Figure 14). Full-Power Bandwidth A large -0.2dBFS analog input signal is applied to an ADC and the input frequency is swept up to the point where the amplitude of the digitized conversion result has decreased by -3dB. This point is defined as fullpower input bandwidth frequency. Output Noise (nOUT) The output noise (nOUT) parameter is similar to thermal plus quantization noise and is an indication of the converter’s overall noise performance. No fundamental input tone is used to test for nOUT. IN_P, IN_N, and COM_ are connected together and 1024k data points are collected. nOUT is computed by taking the RMS value of the collected data points after the mean is removed. Overdrive Recovery Time Overdrive recovery time is the time required for the ADC to recover from an input transient that exceeds the full-scale limits. The MAX12529 specifies overdrive recovery time using an input transient that exceeds the full-scale limits by ±10%. The MAX12529 requires one clock cycle to recover from an overdrive condition. Crosstalk Crosstalk is coupling onto one channel being driven by a (-1dBFS) signal when the adjacent interfering channel is driven by a full-scale signal. Measurement includes all spurs resulting from both direct coupling and mixing components. ______________________________________________________________________________________ Dual, 96Msps, 12-Bit, IF/Baseband ADC Offset Matching Like gain matching, offset matching is a figure of merit that indicates how well the offsets between the two channels are matched to each other. The same input signal is applied to both channels and the maximum deviation in offset is reported (typically in %FSR) as offset matching. 46 45 44 43 42 41 D6B D5B D7B D8B D9B D10B D11B OVDD DAV 50 49 48 47 N.C. 51 N.C. D0A D1A D3A D2A D4A TOP VIEW DORB Pin Configuration 40 39 38 37 36 35 D5A 52 34 D4B D6A 53 33 D3B D7A 54 32 D2B D8A 55 31 D1B D9A 56 30 D0B D10A 57 29 N.C. D11A 58 28 N.C. DORA 59 27 OVDD OVDD 60 26 VDD MAX12529 VDD 61 25 VDD VDD 62 24 VDD VDD 63 23 VDD G/T 64 22 DIV4 PD 65 21 DIV2 SHREF 66 20 CLKP EXPOSED PADDLE (GND) REFOUT 67 19 CLKN REFIN 68 9 10 11 12 13 14 15 16 17 GND INAN GND GND COMA REFAP REFAN GND REFBN GND 8 INBP 7 INBN 6 GND 5 GND 4 COMB 3 REFBP 2 INAP 18 DIFFCLK/SECLK 1 THIN QFN ______________________________________________________________________________________ 27 MAX12529 Gain Matching Gain matching is a figure of merit that indicates how well the gains between the two channels are matched to each other. The same input signal is applied to both channels and the maximum deviation in gain is reported (typically in dB) as gain matching. Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) 68L QFN THIN.EPS MAX12529 Dual, 96Msps, 12-Bit, IF/Baseband ADC PACKAGE OUTLINE 68L THIN QFN, 10x10x0.8mm 21-0142 28 ______________________________________________________________________________________ E 1 2 Dual, 96Msps, 12-Bit, IF/Baseband ADC PACKAGE OUTLINE 68L THIN QFN, 10x10x0.8mm 21-0142 E 2 2 Revision History Pages changed at Rev 1: 1–4, 7–11, 28, 29 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 29 © 2007 Maxim Integrated Products Boblet is a registered trademark of Maxim Integrated Products, Inc. MAX12529 Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)