MAX12553ETL+TG3U

19-3343; Rev 0; 8/04 KIT ATION EVALU LE B A IL A AV 14-Bit, 65Msps, 3.3V ADC Features ♦ Direct IF Sampling Up to 400MHz ♦ Excellent Dynamic Performance 74.0dB/71dB SNR at fIN = 3MHz/175MHz 90.6dBc/80.7dBc SFDR at fIN = 3MHz/175MHz ♦ Low Noise Floor: -76dBFS ♦ 3.3V Low-Power Operation 337mW (Single-Ended Clock Mode) 363mW (Differential Clock Mode) 150µW (Power-Down Mode) ♦ Fully Differential or Single-Ended Analog Input ♦ Adjustable Full-Scale Analog Input Range: ±0.35V to ±1.10V Applications IF and Baseband Communication Receivers Cellular, Point-to-Point Microwave, HFC, WLAN Ultrasound and Medical Imaging Portable Instrumentation ♦ Common-Mode Reference ♦ CMOS-Compatible Outputs in Two’s Complement or Gray Code ♦ Data-Valid Indicator Simplifies Digital Interface ♦ Data Out-of-Range Indicator ♦ Miniature, 40-Pin Thin QFN Package with Exposed Paddle ♦ Evaluation Kit Available (Order MAX12555EVKIT) Ordering Information PART TEMP RANGE PIN-PACKAGE PKG CODE MAX12553ETL -40°C to +85°C 40 Thin QFN (6mm x 6mm x 0.8mm) T4066-3 Pin-Compatible Versions PART SAMPLING RATE (Msps) RESOLUTION (BITS) TARGET APPLICATION MAX12553 65 14 IF/Baseband MAX1209 80 12 IF MAX1211 65 12 IF MAX1208 80 12 Baseband MAX1207 65 12 Baseband MAX1206 40 12 Baseband Low-Power Data Acquisition Pin Configuration appears at end of data sheet. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX12553 General Description The MAX12553 is a 3.3V, 14-bit, 65Msps analog-to-digital converter (ADC) featuring a fully differential wideband track-and-hold (T/H) input amplifier, driving a low-noise internal quantizer. The analog input stage accepts singleended or differential signals. The MAX12553 is optimized for low-power, small size, and high dynamic performance. Excellent dynamic performance is maintained from baseband to input frequencies of 175MHz and beyond, making the MAX12553 ideal for intermediatefrequency (IF) sampling applications. Powered from a single 3.15V to 3.60V supply, the MAX12553 consumes only 363mW while delivering a typical signal-to-noise (SNR) performance of 71dB at an input frequency of 175MHz. In addition to low operating power, the MAX12553 features a 150µW powerdown mode to conserve power during idle periods. A flexible reference structure allows the MAX12553 to use the internal 2.048V bandgap reference or accept an externally applied reference. The reference structure allows the full-scale analog input range to be adjusted from ±0.35V to ±1.10V. The MAX12553 provides a common-mode reference to simplify design and reduce external component count in differential analog input circuits. The MAX12553 supports both a single-ended and differential input clock drive. Wide variations in the clock duty cycle are compensated with the ADC’s internal duty-cycle equalizer (DCE). ADC conversion results are available through a 14-bit, parallel, CMOS-compatible output bus. The digital output format is pin selectable to be either two’s complement or Gray code. A data-valid indicator eliminates external components that are normally required for reliable digital interfacing. A separate digital power input accepts a wide 1.7V to 3.6V supply, allowing the MAX12553 to interface with various logic levels. The MAX12553 is available in a 6mm x 6mm x 0.8mm, 40-pin thin QFN package with exposed paddle (EP), and is specified for the extended industrial (-40°C to +85°C) temperature range. See the Pin-Compatible Versions table for a complete family of 14-bit and 12-bit high-speed ADCs. MAX12553 14-Bit, 65Msps, 3.3V ADC ABSOLUTE MAXIMUM RATINGS Continuous Power Dissipation (TA = +70°C) 40-Pin Thin QFN 6mm x 6mm x 0.8mm (derated 26.3mW/°C above +70°C)........................2105.3mW Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering 10s) ..................................+300°C VDD to GND ...........................................................-0.3V to +3.6V OVDD to GND........-0.3V to the lower of (VDD + 0.3V) and +3.6V INP, INN to GND ...-0.3V to the lower of (VDD + 0.3V) and +3.6V REFIN, REFOUT, REFP, REFN, COM to GND................-0.3V to the lower of (VDD + 0.3V) and +3.6V CLKP, CLKN, CLKTYP, G/T, DCE, PD to GND ........-0.3V to the lower of (VDD + 0.3V) and +3.6V D13–D0, DAV, DOR to GND....................-0.3V to (OVDD + 0.3V) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low, G/T = low, fCLK = 65MHz (50% duty cycle), TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DC ACCURACY (Note 2) Resolution Integral Nonlinearity Differential Nonlinearity 14 Bits INL fIN = 3MHz (Note 5) ±1.4 ±4.2 LSB DNL fIN = 3MHz, no missing codes over temperature (Note 3) ±0.5 ±1.0 LSB Offset Error VREFIN = 2.048V ±0.1 ±0.55 %FS Gain Error VREFIN = 2.048V ±0.5 ±4.9 %FS ANALOG INPUT (INP, INN) Differential Input Voltage Range VDIFF Differential or single-ended inputs Common-Mode Input Voltage Input Capacitance (Figure 3) CPAR CSAMPLE Fixed capacitance to ground ±1.024 V VDD/2 V 2 Switched capacitance pF 4.5 CONVERSION RATE Maximum Clock Frequency fCLK 65 MHz Minimum Clock Frequency 5 Data Latency Figure 6 MHz 8.5 Clock cycles -76.0 dBFS DYNAMIC CHARACTERISTICS (differential inputs, Note 2) Small-Signal Noise Floor SSNF Input at less than -35dBFS fIN = 3MHz at -0.5dBFS (Note 8) Signal-to-Noise Ratio Signal-to-Noise and Distortion SNR SINAD 74.0 fIN = 32.5MHz at -0.5dBFS 73.9 fIN = 70MHz at -0.5dBFS 73.4 fIN = 175MHz at -0.5dBFS (Notes 7, 8) 68.0 71.0 fIN = 3MHz at -0.5dBFS (Note 8) 69.2 73.9 fIN = 32.5MHz at -0.5dBFS 73.1 fIN = 70MHz at -0.5dBFS 73.1 fIN = 175MHz at -0.5dBFS (Notes 7, 8) 2 69.3 67.6 70.0 _______________________________________________________________________________________ dB dB 14-Bit, 65Msps, 3.3V ADC (VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low, G/T = low, fCLK = 65MHz (50% duty cycle), TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS fIN = 3MHz at -0.5dBFS Spurious-Free Dynamic Range SFDR THD HD2 Third Harmonic HD3 Intermodulation Distortion Third-Order Intermodulation Two-Tone Spurious-Free Dynamic Range IMD IM3 SFDRTT 79.8 90.6 84.0 fIN = 70MHz at -0.5dBFS 87.8 75.9 MAX UNITS dBc 80.7 fIN = 3MHz at -0.5dBFS -90.6 fIN = 32.5MHz at -0.5dBFS -81.0 fIN = 70MHz at -0.5dBFS -85.4 fIN = 175MHz at -0.5dBFS -78.9 fIN = 3MHz at -0.5dBFS Second Harmonic TYP fIN = 32.5MHz at -0.5dBFS fIN = 175MHz at -0.5dBFS (Note 7) Total Harmonic Distortion MIN -80.2 dBc -71.3 -99 fIN = 32.5MHz at -0.5dBFS -91 fIN = 70MHz at -0.5dBFS -92 fIN = 175MHz at -0.5dBFS -81 fIN = 3MHz at -0.5dBFS -94 fIN = 32.5MHz at -0.5dBFS -84 fIN = 70MHz at -0.5dBFS -88 fIN = 175MHz at -0.5dBFS -86 fIN1 = 68.5MHz at -7dBFS fIN2 = 71.5MHz at -7dBFS -87 fIN1 = 172.5MHz at -7dBFS fIN2 = 177.5MHz at -7dBFS -80 fIN1 = 68.5MHz at -7dBFS fIN2 = 71.5MHz at -7dBFS -91 fIN1 = 172.5MHz at -7dBFS fIN2 = 177.5MHz at -7dBFS -83 fIN1 = 68.5MHz at -7dBFS fIN2 = 71.5MHz at -7dBFS 90 fIN1 = 172.5MHz at -7dBFS fIN2 = 177.5MHz at -7dBFS 81 dBc dBc dBc dBc dBc Aperture Delay tAD Figure 4 1.2 ns Aperture Jitter tAJ Figure 4 50 MΩ UNBUFFERED EXTERNAL REFERENCE (REFIN = GND; VREFP, VREFN, and VCOM are applied externally) COM Input Voltage VDD/2 1.65 V REFP Input Voltage VCOM VREFP - VCOM 0.768 V REFN Input Voltage VREFN - VCOM -0.768 V 1.536 V 1 mA Differential Reference Input Voltage VREF VREF = VREFP - VREFN = VREFIN x 3/4 REFP Sink Current IREFP VREFP = 2.418V REFN Source Current IREFN VREFN = 0.882V COM Sink Current ICOM 0.7 mA 0.7 mA REFP, REFN Capacitance 13 pF COM Capacitance 6 pF CLOCK INPUTS (CLKP, CLKN) Single-Ended Input High Threshold VIH CLKTYP = GND, CLKN = GND Single-Ended Input Low Threshold VIL CLKTYP = GND, CLKN = GND 0.8 x VDD V 0.2 x VDD V Differential Input Voltage Swing CLKTYP = high 1.4 VP-P Differential Input Common-Mode Voltage CLKTYP = high VDD / 2 V 4 _______________________________________________________________________________________ 14-Bit, 65Msps, 3.3V ADC (VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low, G/T = low, fCLK = 65MHz (50% duty cycle), TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL Input Resistance RCLK Input Capacitance CCLK CONDITIONS MIN Figure 5 TYP MAX UNITS 5 kΩ 2 pF DIGITAL INPUTS (CLKTYP, G/T, PD) Input High Threshold VIH Input Low Threshold VIL Input Leakage Current Input Capacitance 0.8 x OVDD V 0.2 x OVDD VIH = OVDD ±5 VIL = 0 ±5 CDIN 5 V µA pF DIGITAL OUTPUTS (D13–D0, DAV, DOR) Output Voltage Low Output Voltage High VOL D13–D0, DOR, ISINK = 200µA 0.2 DAV, ISINK = 600µA 0.2 D13–D0, DOR, ISOURCE = 200µA OVDD 0.2 DAV, ISOURCE = 600µA OVDD 0.2 V V VOH Tri-State Leakage Current ILEAK (Note 4) ±5 µA D13–D0, DOR Tri-State Output Capacitance COUT (Note 4) 3 pF DAV Tri-State Output Capacitance CDAV (Note 4) 6 pF POWER REQUIREMENTS Analog Supply Voltage Digital Output Supply Voltage Analog Supply Current VDD 3.15 3.3 3.60 V OVDD 1.7 2.0 VDD + 0.3V V IVDD Normal operating mode, fIN = 175MHz at -0.5dBFS, CLKTYP = GND, single-ended clock 102 Normal operating mode, fIN = 175MHz at -0.5dBFS, CLKTYP = OVDD, differential clock 110 Power-down mode clock idle, PD = OVDD mA 123 0.045 _______________________________________________________________________________________ 5 MAX12553 ELECTRICAL CHARACTERISTICS (continued) MAX12553 14-Bit, 65Msps, 3.3V ADC ELECTRICAL CHARACTERISTICS (continued) (VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low, G/T = low, fCLK = 65MHz (50% duty cycle), TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER Analog Power Dissipation Digital Output Supply Current SYMBOL PDISS IOVDD CONDITIONS MIN TYP MAX UNITS Normal operating mode, fIN = 175MHz at -0.5dBFS, CLKTYP = GND, single-ended clock 337 Normal operating mode, fIN = 175MHz at -0.5dBFS, CLKTYP = OVDD, differential clock 363 Power-down mode clock idle, PD = OVDD 0.15 Normal operating mode, fIN = 175MHz at -0.5dBFS, OVDD = 2.0V, CL ≈ 5pF 8.2 mA Power-down mode clock idle, PD = OVDD 20 µA mW 406 TIMING CHARACTERISTICS (Figure 6) Clock Pulse-Width High tCH 7.7 ns Clock Pulse-Width Low tCL 7.7 ns 6.9 ns Data-Valid Delay tDAV CL = 5pF (Note 6) Data Setup Time Before Rising Edge of DAV tSETUP CL = 5pF (Notes 5, 6) 8.5 ns Data Hold Time After Rising Edge of DAV tHOLD CL = 5pF (Notes 5, 6) 6.3 ns Wake-Up Time from Power-Down tWAKE VREFIN = 2.048V 10 ms Specifications ≥+25°C guaranteed by production test; 50MΩ). When driving REFIN through a resistive divider, use resistances ≥10kΩ to avoid loading REFOUT. Buffered external reference mode is virtually identical to internal reference mode except that the reference source is derived from an external reference and not the MAX12553 REFOUT. In buffered external reference mode, apply a stable 0.7V to 2.2V source at REFIN. In this mode, COM, REFP, and REFN are low-impedance outputs with VCOM = VDD/2, VREFP = VDD/2 + VREFIN x 3/8, and VREFN = VDD/2 - VREFIN x 3/8. To operate the MAX12553 in unbuffered external reference mode, connect REFIN to GND. Connecting REFIN to GND deactivates the on-chip reference buffers for COM, REFP, and REFN. With the respective buffers deactivated, COM, REFP, and REFN become highimpedance inputs and must be driven through separate, external reference sources. Drive VCOM to VDD/2 ±5%, and drive REFP and REFN such that VCOM = (VREFP + VREFN)/2. The full-scale analog input range is ±(VREFP - VREFN) x 2/3. Table 1. Reference Modes VREFIN REFERENCE MODE 35% VREFOUT to 100% VREFOUT 0.7V to 2.2V