19-1319; Rev 3; 7/08
KIT
ATION
EVALU
E
L
B
A
AVAIL
2x4-Channel, Simultaneous-Sampling
14-Bit DAS
Features
The MAX125/MAX126 are high-speed, multichannel,
14-bit data-acquisition systems (DAS) with simultaneous
track/holds (T/Hs). These devices contain a 14-bit, 3µs,
successive-approximation analog-to-digital converter
(ADC), a +2.5V reference, a buffered reference input,
and a bank of four simultaneous-sampling T/H amplifiers that preserve the relative phase information of the
sampled inputs. The MAX125/MAX126 have two multiplexed inputs for each T/H, allowing a total of eight
inputs. In addition, the converter is overvoltage tolerant
to ±17V; a fault condition on any channel will not harm
the IC. Available input ranges are ±5V (MAX125) and
±2.5V (MAX126).
An on-board sequencer converts one to four channels
per CONVST pulse. In the default mode, one T/H output
(CH1A) is converted. An interrupt signal (INT) is provided
after the last conversion is complete. Convert two,
three, or four channels by reprogramming the
MAX125/MAX126 through the bidirectional parallel
interface. Once programmed, the MAX125/MAX126
continue to convert the specified number of channels
per CONVST pulse until they are reprogrammed. The
channels are converted sequentially, beginning with
CH1. The INT signal always follows the end of the last
conversion in a conversion sequence. The ADC converts each assigned channel in 3µs and stores the
result in an internal 14x4 RAM. Upon completion of the
conversions, data can be accessed by applying successive pulses to the RD pin. Four successive reads
access four data words sequentially.
The parallel interface’s data-access and bus-release
timing specifications are compatible with most popular
digital signal processors and 16-bit/32-bit microprocessors, so the MAX125/MAX126 conversion results can
be accessed without resorting to wait states.
♦ Four Simultaneous-Sampling T/H Amplifiers with
Two Multiplexed Inputs (eight single-ended inputs
total)
♦ 3µs Conversion Time per Channel
♦ Throughput: 250ksps (1 channel)
142ksps (2 channels)
100ksps (3 channels)
76ksps (4 channels)
♦ Input Range: ±5V (MAX125)
±2.5V (MAX126)
♦ Fault-Protected Input Multiplexer (±17V)
♦ ±5V Supplies
♦ Internal +2.5V or External Reference Operation
♦ Programmable On-Board Sequencer
♦ High-Speed Parallel DSP Interface
Ordering Information
PART
TEMP RANGE
MAX125CCAX
0°C to +70°C
PIN-PACKAGE
INL
(LSB)
36 SSOP
±4
MAX125CEAX
-40°C to +85°C
36 SSOP
±4
MAX126CCAX
0°C to +70°C
36 SSOP
±4
MAX126CEAX
-40°C to +85°C
36 SSOP
±4
Applications
Multiphase Motor Control
Power-Grid Synchronization
Power-Factor Monitoring
Digital Signal Processing
Vibration and Waveform Analysis
Typical Operating Circuit appears at end of data sheet.
Pin Configuration appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1
MAX125/MAX126
General Description
MAX125/MAX126
2x4-Channel, Simultaneous-Sampling
14-Bit DAS
ABSOLUTE MAXIMUM RATINGS
Continuous Power Dissipation (TA = +70°C)
SSOP (derate 11.8mW/°C above +70°C) ....................941mW
Operating Temperature Ranges
MAX125CCAX/MAX126CCAX ............................0°C to +70°C
MAX125CEAX/MAX126CEAX ..........................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10sec)................................300°C
AVDD to AGND ...........................................................-0.3V to 6V
AVSS to AGND ............................................................0.3V to -6V
DVDD to DGND ...........................................................-0.3V to 6V
AGND to DGND .......................................................-0.3V to 0.3V
CH_ _ to AGND....................................................................±17V
REFIN, REFOUT to AGND ..........................................-0.3V to 6V
Digital Inputs/Outputs to DGND ..............-0.3V to (DVDD + 0.3V)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AVDD = +5V ±5%, AVSS = -5V ±5%, DVDD = +5V ±5%, VREFIN = 2.5V, AGND = DGND = 0V, 4.7µF capacitor from REFOUT to
AGND, 0.1µF capacitor from REFIN to AGND, fCLK = 16MHz, external clock, 50% duty cycle, TA = TMIN to TMAX, unless otherwise
noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
±2
±4
LSB
DC ACCURACY (Note 1)
Resolution
Integral Nonlinearity
N
INL
All channels
14
(Note 2)
No Missing Codes
TA = +25°C
±5
TA = TMIN to TMAX
Bipolar Zero-Error Match
Between all channels
1.2
5
±5
TA = +25°C
Gain Error
±5
TA = TMIN to TMAX
Gain-Error Match
Between all channels
1.2
5
±5
DYNAMIC PERFORMANCE (fCLK = 16MHz, fIN = 10.06kHz (Notes 1, 3)
Single-channel mode,
MAX125
Signal-to-Noise Plus Distortion
SINAD
channel 1A, 250ksps (Note
MAX126
4)
Single-channel mode, channel 1A,
Total Harmonic Distortion
THD
250ksps (Notes 4, 5)
SFDR
Single-channel mode, channel 1A,
250ksps (Note 4)
Single-channel mode, channel 1A,
250ksps (Note 6)
72
75
70
72
-89
80
mV
mV
ppm/°C
±10
±15
Gain-Error Tempco
2
±15
±25
Zero-Code Tempco
Channel-to-Channel Isolation
Bits
13
Bipolar Zero Error
Spurious-Free Dynamic Range
Bits
mV
mV
ppm/°C
dB
-80
dB
90
dB
80
dB
_______________________________________________________________________________________
2x4-Channel, Simultaneous-Sampling
14-Bit DAS
(AVDD = +5V ±5%, AVSS = -5V ±5%, DVDD = +5V ±5%, VREFIN = 2.5V, AGND = DGND = 0V, 4.7µF capacitor from REFOUT to
AGND, 0.1µF capacitor from REFIN to AGND, fCLK = 16MHz, external clock, 50% duty cycle, TA = TMIN to TMAX, unless otherwise
noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ANALOG INPUT
Input Voltage Range
VIN
Input Current
IIN
Input Capacitance
CIN
MAX125
±5
MAX126
±2.5
MAX125, VIN = ±5V
MAX126, VIN = ±2.5V
(Note 7)
V
±667
µA
µA
16
pF
TRACK/HOLD
Acquisition Time
tACQ
1
Small-Signal Bandwidth
µs
8
Full-Power Bandwidth
Droop Rate
MHz
0.5
MHz
2
mV/ms
Aperture Delay
5
ns
Aperture Jitter
30
psRMS
Aperture-Delay Matching
500
ps
REFERENCE OUTPUT (Note 8)
Output Voltage
VREFOUT
TA = +25°C
2.475
2.500
2.525
V
External Load Regulation
0mA < ILOAD < 1mA
±1
%
REFOUT Tempco
(Note 9)
30
ppm/°C
External Capacitive
Bypass at REFIN
0.1
External Capacitive
Bypass at REFOUT
4.7
µF
22
µF
REFERENCE INPUT
Input Voltage Range
2.50 ±10%
Input Current
REFIN = 2.5V
Input Resistance
(Note 10)
Input Capacitance
(Note 7)
V
±10
10
µA
kΩ
10
pF
16
MHz
EXTERNAL CLOCK
External Clock Frequency
0.1
DIGITAL INPUTS (CONVST, RD, WR, CS, CLK, A0–A3) (Note 1)
Input High Voltage
VIH
Input Low Voltage
VIL
Input Current
IIN
Input Capacitance
CIN
2.4
V
0.8
CONVST, RD, WR, CS, CLK
±1
A0–A3
±10
(Note 7)
15
V
µA
pF
_______________________________________________________________________________________
3
MAX125/MAX126
ELECTRICAL CHARACTERISTICS (continued)
MAX125/MAX126
2x4-Channel, Simultaneous-Sampling
14-Bit DAS
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = +5V ±5%, AVSS = -5V ±5%, DVDD = +5V ±5%, VREFIN = 2.5V, AGND = DGND = 0V, 4.7µF capacitor from REFOUT to
AGND, 0.1µF capacitor from REFIN to AGND, fCLK = 16MHz, external clock, 50% duty cycle, TA = TMIN to TMAX, unless otherwise
noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL OUTPUTS (D0–D13, INT) (Note 1)
Output High Voltage
VOH
IOUT = 1mA
Output Low Voltage
VOL
IOUT = -1.6mA
4
0.4
V
V
Three-State Leakage Current
D0–D13
±10
µA
Three-State Output
Capacitance
(Note 7)
10
pF
POWER REQUIREMENTS
Positive Supply Voltage
AVDD
4.75
5
5.25
V
Negative Supply Voltage
AVSS
-5.25
-5
-4.75
V
Digital Supply Voltage
DVDD
4.75
5
5.25
V
Positive Supply Current
I(AVDD)
17
25
mA
Negative Supply Current
I(AVSS)
Digital Supply Current
I(DVDD)
-17
-13
3
Shutdown Positive Current
Shutdown Negative Current
Positive Supply Rejection
PSRR+
(Note 11)
Negative Supply Rejection
PSRR-
(Note 11)
4
5
mA
3
mA
-1
mA
Shutdown Digital Current
Power Dissipation
mA
(Note 12)
±1
165
_______________________________________________________________________________________
3
mA
±2
LSB
±2
LSB
250
mW
2x4-Channel, Simultaneous-Sampling
14-Bit DAS
(AVDD = +5V, AVSS = -5V, DVDD = +5V, AGND = DGND = 0V, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
tCW
30
ns
CS to WR Setup Time
tCWS
0
ns
CS to WR Hold Time
tCWH
0
ns
WR Low Pulse Width
tWR
30
ns
CS to CONVST Delay
tCSD
125
ns
Address Setup Time
tAS
30
ns
Address Hold Time
tAH
0
ns
CONVST Pulse Width
RD to INT Delay
tID
Delay Time Between Reads
tRD
40
ns
CS to RD Setup Time
tCRS
0
ns
CS to RD Hold Time
tCRH
0
ns
RD Low Pulse Width
tRD
30
Data-Access Time
tDA
25pF load (Note 13)
Bus-Relinquish Time
tDH
25pF load (Note 14)
Conversion Time
tCONV
Conversion Rate/Channel
25pF load
30
ns
5
30
ns
45
ns
Mode 1, 1 channel
3
Mode 2, 2 channel
6
Mode 3, 3 channel
9
Mode 4, 4 channel
12
Mode 1, 1 channel
250
Mode 2, 2 channel
142
Mode 3, 3 channel
100
Mode 4, 4 channel
Start-Up Time
Exiting shutdown
ns
µs
ksps
76
5
µs
Note 1: AVDD = +5V, AVSS = -5V, DVDD = +5V, VREFIN = 2.500V (external), VIN = ±5V (MAX125) or ±2.5V (MAX126).
Note 2: Relative accuracy is the analog value’s deviation at any code from its theoretical value after the full-scale range has been
calibrated.
Note 3: CLK synchronized with CONVST.
Note 4: fIN = 10.06kHz, VIN = ±5V (MAX125) or ±2.5V (MAX126).
Note 5: First five harmonics.
Note 6: All inputs except CH1A driven with ±5V (MAX125) or ±2.5V (MAX126) 10kHz signal; CH1A connected to AGND and digitized.
Note 7: Guaranteed by design. Not production tested.
Note 8: AVDD = +5V, AVSS = -5V, DVDD = +5V, VIN = 0V (all channels).
Note 9: Temperature drift is defined as the change in output voltage from +25°C to TMIN or TMAX. It is calculated as
TC = [∆REFOUT/REFOUT] / ∆T.
Note 10: See Figure 2.
Note 11: Defined as the change in positive full scale caused by a ±5% variation in the nominal supply voltage. Tested with one input
at full scale and all others at AGND. VREFIN = 2.5V (internal).
Note 12: Tested with VIN = AGND on all channels, VREFIN = 2.5V (internal).
Note 13: The data-access time is defined as the time required for an output to cross 0.8V or 2.0V. It is measured using the circuit of
Figure 1. The measured number is then extrapolated back to determine the value with a 25pF load.
Note 14: The bus-relinquish time is derived from the measured time taken for the data outputs to change 0.5V when loaded with the
circuit of Figure 1. The measured number is then extrapolated back to remove the effects of charging/discharging the 120pF
capacitor. Thus, the time given is the part’s true bus-relinquish time, independent of the external bus loading capacitance.
_______________________________________________________________________________________
5
MAX125/MAX126
TIMING CHARACTERISTICS (Figure 4)
MAX125/MAX126
2x4-Channel, Simultaneous-Sampling
14-Bit DAS
______________________________________________________________Pin Description
PIN
NAME
FUNCTION
1, 2
CH2B, CH2A
Channel 2 Multiplexed Inputs, single-ended
3, 4
CH1B, CH1A
Channel 1 Multiplexed Inputs, single-ended
5
AVDD
+5V ±5% Analog Supply Voltage
6
REFIN
External Reference Input/Internal Reference Output. Bypass with a 0.1µF capacitor to AGND.
7
REFOUT
8, 36
AGND
9–16
D13–D6
17
DVDD
+5V ±5% Digital Supply Voltage
18
DGND
Digital Ground
19, 20
D5, D4
Data Bits
21–24
D3/A3–D0/A0
25
CLK
26
CS
Chip-Select Input (active-low)
27
WR
Write Input (active-low)
28
RD
Read Input (active-low)
29
CONVST
30
INT
31
AVSS
32, 33
CH4A, CH4B
Channel 4 Multiplexed Inputs, single-ended
34, 35
CH3A, CH3B
Channel 3 Multiplexed Inputs, single-ended
Reference-Buffer Output. Bypass with a 4.7µF capacitor to AGND.
Analog Ground. Both pins must be tied to ground.
Data Bits. D13 = MSB.
Bidirectional Data Bits/Address Bits. D0/A0 = LSB.
Clock Input (duty cycle must be 30% to 70%).
Conversion-Start Input. Rising edge initiates sampling and conversion sequence.
Interrupt Output. Falling edge indicates the end of a conversion sequence.
-5V ±5% Analog Supply Voltage
_______________Detailed Description
The MAX125/MAX126 use a successive-approximation
conversion technique and four simultaneous-sampling
track/hold (T/H) amplifiers to convert analog signals into
14-bit digital outputs. Each T/H has two multiplexed
inputs, allowing a total of eight inputs. Each T/H output
is converted and stored in memory to be accessed
sequentially by the parallel interface with successive
read cycles. The MAX125/MAX126 internal microsequencer can be programmed to digitize one, two,
three, or four inputs sampled simultaneously from either
of the two banks of four inputs (see Figure 2).
The conversion timing and control sequences are
derived from a 16MHz external clock, the CONVST
6
1.6mA
TO OUTPUT
PIN
1.6V
120pF
1.0mA
Figure 1. Load Circuit for Access Time and Bus Relinquish Time
_______________________________________________________________________________________
2x4-Channel, Simultaneous-Sampling
14-Bit DAS
AGND
MAX125/MAX126
REFIN
REFOUT
BANDGAP REFERENCE
10k
CH1A
A
CH1B
CH2A
B
A
B
MUX
T/H
2.50V
MUX
T/H
VREF
CH2B
MUX
COMP
CH3A
A
B
MUX
T/H
CH3B
14-BIT
DAC
CH4A
A
CH4B
B
MUX
SAR
T/H
VREF
14x4
RAM
D0/A0 (LSB)
AVDD
D1/A1
AGND
THREE-STATE
OUTPUT
DRIVERS
AVSS
D3/A3
D13 (MSB)
CONTROL LOGIC
MAX125
MAX126
D2/A2
BUS INTERFACE
CLK
CONVST
INT
CS
RD
WR
DVDD
DGND
Figure 2. Functional Diagram
_______________________________________________________________________________________
7
MAX125/MAX126
2x4-Channel, Simultaneous-Sampling
14-Bit DAS
HOLD
BUFFER
C HOLD
7pF
HOLD
5k
CH_A
S1A
C IN
S2A
FROM MICROSEQUENCER
TRACK
TRACK
5k
S3A
MUX
S1B
5k
CH_B
C IN
S2B
5k
S3B
REFOUT
DAC
MAX125
MAX126
SAR
Figure 3. Equivalent Input Circuit
signal, and the programmed mode. The T/H amplifiers
hold the input voltages at the CONVST rising edge.
Additional CONVST pulses are ignored until the last
conversion for the sample is complete. The ADC converts each assigned channel in 3µs and stores the
result in an internal 4x14-bit memory.
At the end of the last conversion, INT goes low and the
T/H amplifiers begin to track the inputs again. The data
can be accessed by applying successive pulses to the
RD pin. Successive reads access data words sequentially. The memory is not random-access; data from
CH1 is always read first. After accessing all programmed channels, the address pointer selects CH1
again. Additional read pulses cycle through the data
words. CS can be held low during successive reads.
Input Bandwidth
The T/H’s input tracking circuitry has an 8MHz smallsignal bandwidth, so it is possible to digitize highspeed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. To avoid highfrequency signals being aliased into the frequency
band of interest, anti-alias filtering is recommended.
8
Analog Input Range and Input Protection
The MAX125’s input range is ±5V, and the MAX126’s
input range is ±2.5V. The input resistance for both parts
is 10kΩ. An input protection structure allows input voltages to ±17V without harming the IC. This protection is
also active in shutdown mode.
Track/Holds
The MAX125/MAX126 feature four simultaneous T/Hs.
Each T/H has two multiplexed inputs. A T-switch input
configuration provides excellent hold-mode isolation.
Allow 1µs acquisition time for 14-bit accuracy.
The T/H aperture delay is typically 10ns. The 500ps
aperture-delay mismatch between the T/Hs allows the
relative phase information of up to four different inputs
to be preserved. Figure 3 shows the equivalent input
circuit, illustrating the ADC’s sampling architecture.
Only one of four T/H stages with its two multiplexed
inputs (CH_A and CH_B) is shown. All switches are in
track configuration for channel A. An internal buffer
charges the hold capacitor to minimize the required
acquisition time between conversions. The analog input
appears as a 10kΩ resistor in parallel with a 16pF
capacitor.
_______________________________________________________________________________________
2x4-Channel, Simultaneous-Sampling
14-Bit DAS
MAX125/MAX126
tCW
CONVST
tCONV
INT
tACQ
tID
tCWH
tCSD
tCWS
CS
tCRS
tCRH
RD
tRD
t WR
t RD
WR
tDA
tDH
DATA
CH1
DATA IN
CH2
CH3
CH4
tAS
tAH
Figure 4. Timing Diagram
RD inputs and forces the interface into a high-Z state.
Figure 4 details the interface timing.
CS
Programming Modes
WR
A0
(LSB)
A1
A2
A3
Figure 5. Programming a Four-Channel Conversion, Input Mux A
Between conversions, the buffer input is connected to
channel 1 of the selected track/hold bank. When a
channel is not selected, switches S1, S2, and S3 are
placed in hold mode to improve channel-to-channel
isolation.
Digital Interface
Input data (A0–A3) and output data (D0–D13) are multiplexed on a three-state bidirectional interface. This parallel I/O can easily be interfaced with a microprocessor
(µP) or DSP. CS, WR, and RD control the write and read
operations. CS is the standard chip-select signal, which
enables the controller to address the MAX125/MAX126
as an I/O port. When CS is high, it disables the WR and
The MAX125/MAX126 have eight conversion modes
plus power-down, which are programmed through a
bidirectional parallel interface. At power-up, the devices
default to the mode Input Mux A/Single-Channel
Conversion. The user can select between two banks
(mux inputs A or mux inputs B) of four simultaneoussampled input channels, as illustrated in Figure 2. An
internal microsequencer can be programmed to convert
one, two, three, or four channels of the selected bank
per sample. For a single-channel conversion, CH1 is
digitized, and then INT goes low to indicate completion
of the conversion. For multichannel conversions, INT
goes low after the last channel has been digitized.
To input data into the MAX125/MAX126, pull CS low,
program the bidirectional pins A0–A3 (Table 1), and
pulse WR low. Data is latched into the devices on the
WR or CS rising edge. The ADC is now ready to convert.
Once programmed, the ADCs continue operating in the
same mode until they are reprogrammed or until power
is removed. Figure 5 shows an example of programming a four-channel conversion using Input Mux A.
Starting a Conversion
After programming the MAX125/MAX126 as outlined in
the Programming Modes section, pulse CONVST low to
initiate a conversion sequence. The analog inputs are
sampled at the CONVST rising edge. Do not start a
new conversion while the conversion is in progress.
Monitor the INT output. A falling edge indicates the end
of a conversion sequence.
_______________________________________________________________________________________
9
MAX125/MAX126
2x4-Channel, Simultaneous-Sampling
14-Bit DAS
Table 1. Modes of Operation
A3
A2
A1
A0
CONVERSION
TIME (µs)
0
0
0
0
3
Input Mux A/Single-Channel Conversion (default at power-up)
0
0
0
1
6
Input Mux A/Two-Channel Conversion
0
0
1
0
9
Input Mux A/Three-Channel Conversion
0
0
1
1
12
Input Mux A/Four-Channel Conversion
0
1
0
0
3
Input Mux B/Single-Channel Conversion
0
1
0
1
6
Input Mux B/Two-Channel Conversion
0
1
1
0
9
Input Mux B/Three-Channel Conversion
0
1
1
1
12
Input Mux B/Four-Channel Conversion
1
X
X
X
—
Power-Down
MODE
X = Don’t care
REFOUT
TO DAC
7
(2.5V)
4.7µF
AV = 1
address pointer is reset to CH_1. For multichannel conversions, up to four RD falling edges sequentially
access the data for channels 1 through 4. For n channels converted (1 < n ≤ 4), the address pointer is reset
to CH_1 after n RD pulses. Do not perform a read operation during conversion, as it will corrupt the conversion’s accuracy.
__________Applications Information
REFIN
MAX125
MAX126
6
(2.5V)
External Clock
0.1µF
10k
The MAX125/MAX126 require a TTL-compatible clock
up to 16MHz for proper operation. The clock duty
cycle’s range is between 30% and 70%.
Internal and External Reference
2.5V
Figure 6. Internal Reference
Reading a Conversion
Digitized data from up to four channels are stored in
memory to be read out through the parallel interface.
After receiving an INT signal, the user can access up to
four conversion results by performing up to four read
operations.
With CS low, the conversion result from CH_1 is
accessed, and INT is reset high on the first RD falling
edge. On the RD rising edge, the internal address
pointer is advanced. If a single conversion is programmed, only one RD pulse is required, and the
10
The MAX125/MAX126 can be used with an internal or
external reference voltage. An external reference can
be connected directly at REFIN. An internal buffer with
a gain of +1 provides 2.5V at REFOUT.
Internal Reference
The full-scale range with the internal reference is ±5V
for the MAX125 and ±2.5V for the MAX126. Bypass
REFIN with a 0.1µF capacitor to AGND and bypass the
REFOUT pin with a 4.7µF (min) capacitor to AGND
(Figure 6). The maximum value to compensate the reference buffer is 22µF. Larger values are acceptable if
low-ESR capacitors are used.
External Reference
For operation over a wide temperature range, an external 2.5V reference with tighter specifications improves
accuracy. The MAX6325 is an excellent choice
to match the MAX125/MAX126 accuracy over the
commercial and extended temperature ranges with a
______________________________________________________________________________________
2x4-Channel, Simultaneous-Sampling
14-Bit DAS
MAX125/MAX126
OUTPUT CODE
REFOUT
TO DAC
7
(2.5V)
011 . . . 111
011 . . . 110
4.7µF
000 . . . 010
AV = 1
000 . . . 001
REFIN
MAX125
MAX126
6
1LSB =
000 . . . 000
(2.5V)
OUT
4VREFOUT
16384
111 . . . 111
111 . . . 110
MAX6325
111 . . . 101
10k
100 . . . 001
100 . . . 000
2.5V
- FS
ZERO
+FS - 1LSB
INPUT VOLTAGE (LSB)
FS = 2 x VREFOUT (MAX125)
FS = VREFOUT (MAX126)
Figure 7. External Reference
Figure 8. Bipolar Transfer Function
1ppm/°C (max) temperature drift. Connect an external
reference at REFIN as shown in Figure 7. The minimum
impedance is 7kΩ for DC currents in both normal operation and shutdown. Bypass REFOUT with a 4.7µF lowESR capacitor.
buffer’s settling time and the bypass capacitor’s value
dominate the power-up delay. With the recommended
4.7µF at REFOUT, the power-up delay is typically 5µs.
Power-On Reset
When power is first applied, the internal power-on-reset
circuitry activates the MAX125/MAX126 with INT =
high, ready to convert. The default conversion mode is
Input Mux A/Single-Channel Conversion. See the
Programming Modes section if other configurations are
desired.
After the power supplies have been stabilized, the reset
time is 5µs; no conversions should be performed
during this phase. At power-up, data in memory is
undefined.
Software Power-Down
Software power-down is activated by setting bit A3 of
the control word high (Table 1). It is asserted after the
WR or CS rising edge, at which point the ADC immediately powers down to a low quiescent-current state.
AVDD drops to less than 1.5mA, and AVSS is reduced
to less than 1mA. The ADC blocks and reference buffer
are turned off, but the digital interface and the reference remain active for fast power-up recovery. Wake
up the MAX125/MAX126 by writing a control word
(A0–A3, Table 1). The bidirectional interface interprets
a logic zero at A3 as the start signal and powers up in
the mode selected by A0, A1, and A2. The reference
Transfer Function
The MAX125/MAX126 have bipolar input ranges. Figure 8 shows the bipolar/output transfer function. Code
transitions occur at successive-integer least significant
bit (LSB) values. Output coding is twos-complement
binary with 1LSB = 610µV for the MAX125 and
1LSB = 305µV for the MAX126.
Output Demultiplexer
An output demultiplexer circuit is useful for isolating
data from one channel in a four-channel conversion
sequence. Figure 9’s circuit uses the external 16MHz
clock and the INT signal to generate four RD pulses
and a latch clock to save data from the desired channel. CS must be low during the four RD pulses. The
channel is selected with the binary coding of two
switches. A 16-bit 16373 latch simplifies layout.
Motor-Control Applications
Vector motor control requires monitoring of the individual phase currents. In their most basic application, the
MAX125/MAX126 simultaneously sample two currents
(CH1A and CH2A, Figure 10) and preserve the necessary relative phase information. Only two of the three
phase currents have to be digitized, because the third
component can be mathematically derived with a coordinate transformation.
______________________________________________________________________________________
11
MAX125/MAX126
2x4-Channel, Simultaneous-Sampling
14-Bit DAS
VCC
VCC
HC161
1/2 HC74
PRE
D
CLR
ENP
ENT
Q
Q
RD
LOAD
HC688
CLR
VCC
INT
A
B
(LSB) 0
P0
1
C
2
D
3
RCO
P1
P2
P3
P4
P5
P6
P7
EXTERNAL
CLOCK
VCC
P=Q
Q0
Q1
LATCH
CLOCK
(TO 16373 LATCH)
Q2
Q3
10k
Q4
Q5
Q6
Q7
G
CH1
0
0
CH2
1
0
CH3
0
1
CH4
1
1
EXTERNAL
CLOCK
Figure 9. Output Demultiplexer Circuit
The circuit of Figure 10 shows a typical vector motorcontrol application using all available inputs of the
MAX125/MAX126. CH1A and CH2A are connected
to two isolated Hall-effect current sensors and are a
part of the current (torque) feedback loop. The
MAX125/MAX126 digitize the currents and deliver raw
data to the following DSP and controller stages, where
the vector processing takes place. Sensorless vector
control uses a computer model for the motor and an
algorithm to split each output current into its magnetizing (stator current) and torque-producing (rotor current)
components.
12
If a 2- to 3-phase conversion is not practical, three currents can be sampled simultaneously with the addition
of a third sensor (not shown). Optional voltage
(position) feedback can be derived by measuring two
phase voltages (CH3A, CH4A). Typically, an isolated
differential amplifier is used between the motor and the
MAX125/MAX126. Again, the third phase voltage can
be derived from the magnitude (phase voltage) and its
relative phase.
For optimum speed control and good load regulation
close to zero speed, additional velocity and position
feedback are derived from an encoder or resolver and
______________________________________________________________________________________
2x4-Channel, Simultaneous-Sampling
14-Bit DAS
MAX125/MAX126
MAIN DC
RESOLVER/
ENCODER
AC
AC
MOTOR
MOTOR
14
CH1
MAX125
MAX126
14 BIT ADC +
MICROSEQUENCER
B
AUX
A
SIMULTANEOUS T/H
DSP
BUFFER
A
CH2
B
MAIN DC
R/E
VOLTAGE/POSITION
FEEDBACK
POWER
STAGE
CONTROLLER
CURRENT/TORQUE
FEEDBACK
EXTERNAL
SETPOINTS
A
CH3
B
A
CH4
B
TEMP
VELOCITY
FEEDBACK
µC
Figure 10. Vector Motor Control
brought to the MAX125/MAX126 at CH4B. The additional channels can be used to evaluate slower analog
inputs, such as the main DC bus voltage (CH2B), temperature sensors (CH3B), or other analog inputs (AUX,
CH1B).
Power-Supply Bypassing
and Ground Management
For optimum system performance, use printed circuit
boards with separate analog and digital ground
planes. Wire-wrapped boards are not recommended.
Connect the two ground planes together at the lowimpedance power-supply source. Connect DGND and
AGND together at the IC. For the best ground connection, connect the DGND and AGND pins together and
connect that point to the system analog ground plane
to avoid interference from other digital noise sources. If
DGND is connected to the system digital ground, digital noise may get through to the ADC’s analog portion.
The AGND pins must be connected directly to a lowimpedance ground plane. Extra impedance between
the pins and the ground plane increases crosstalk and
degrades INL.
Bypass AVDD and AVSS with 0.1µF ceramic capacitors
to AGND. Mount them with short leads close to the
device. Ferrite beads may also be used to further isolate the analog and digital power supplies. Bypass
DVDD with a 0.1µF ceramic capacitor to DGND.
______________________________________________________________________________________
13
MAX125/MAX126
2x4-Channel, Simultaneous-Sampling
14-Bit DAS
__________________Pin Configuration
__________Typical Operating Circuit
TOP VIEW
CH2B 1
36 AGND
CH2A 2
35 CH3B
CH1B 3
34 CH3A
CH1A 4
33 CH4B
AVDD
32 CH4A
5
REFIN 6
MAX125
MAX126
REFOUT 7
AVSS
D0/A0
D1/A1
D2/A2
D3/A3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
REFIN
DVDD
+5V
D13 (MSB) 9
28 RD
D12 10
27 WR
D11 11
26 CS
D10 12
25 CLK
D9 13
24 D0/A0 (LSB)
D8 14
23 D1/A1
D7 15
22 D2/A2
D6 16
21 D3/A3
DVDD 17
20 D4
DGND 18
19 D5
AVDD
0.1µF
29 CONVST
AGND
0.1µF
-5V
0.1µF
REFOUT
14
DGND
4.7µF
CLK
CONVST INT
CS
RD
WR
16MHz
CONTROL INTERFACE
___________________Chip Information
SUBSTRATE CONNECTED TO AVSS
+5V
0.1µF
SSOP
TRANSISTOR COUNT: 4219
MAX125
MAX126
31 AVSS
30 INT
AGND 8
CH1A
CH1B
CH2A
CH2B
CH3A
CH3B
CH4A
CH4B
Package Information
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages.
PACKAGE TYPE
PACKAGE CODE
DOCUMENT NO.
36 SSOP
A36-4
21-0040
______________________________________________________________________________________
2x4-Channel, Simultaneous-Sampling
14-Bit DAS
REVISION
NUMBER
REVISION
DATE
2
6/07
Updated Ordering Information section
3
7/08
Added line to DC Accuracy section of EC table
DESCRIPTION
PAGES
CHANGED
1, 2, 15
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 15
© 2008 Maxim Integrated Products
is a registered trademark of Maxim Integrated Products, Inc.
MAX125/MAX126
Revision History
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