19-4813; Rev 0; 7/09
KIT
ATION
EVALU
E
L
B
AVAILA
1.62V to 3.6V, 8-Channel, High-Speed LLT
The MAX13055E–MAX13058E 8-channel, bidirectional
level translators provide the level shifting necessary for
100Mbps data transfer in multivoltage systems. The
MAX13055E–MAX13058E are ideal for level translation
in systems with 8 channels. Externally applied voltages,
VCC and VL, set the logic levels on either side of the
device. Logic-high signals presented on the VL side of
the device appear as a logic-high signal on the VCC
side of the device and vice versa.
The MAX13055E–MAX13058E operate at full speed
with external drivers that source as little as 4mA output
current or larger. Each input/output (I/O) channel is
pulled up to VCC or VL by an internal 40µA current
source, allowing the MAX13055E–MAX13058E to be
driven by either push-pull or open-drain drivers.
The MAX13055E–MAX13058E feature an enable (EN)
input to place the device into a low-power shutdown
mode when driven low. In addition, the MAX13055E–
MAX13058E feature an automatic shutdown mode that
disables the part when V CC is less than V L . Each
device has a different I/O VL_ and I/O VCC_ state during
shutdown mode (see the Ordering Information/Selector
Guide).
The MAX13055E–MAX13058E operate with VCC voltages
from +2.2V to +3.6V and VL voltages from +1.62V to
+3.2V, making them ideal for data transfer between lowvoltage ASIC/PLDs and higher voltage systems. The
MAX13055E–MAX13058E are available in 0.4mm pitch,
24-bump WLP and 28-pin TQFN (3.5mm x 5.5mm) packages. The MAX13055E–MAX13058E operate over the
extended -40°C to +85°C temperature range.
Features
♦ Compatible with 4mA Input Drivers or Larger
♦ 100Mbps Guaranteed Data Rate
♦ 8 Bidirectional Channels
♦ +1.62V ≤ VL ≤ +3.2V and +2.2V ≤ VCC ≤ +3.6V
Supply Voltage Range
♦ 24-Bump WLP (0.4mm Pitch) Lead-Free Package
♦ 28-Pin TQFN (3.5mm x 5.5mm) Lead-Free Package
♦ Extended ESD Protection on I/O VCC Lines
±15kV per Human Body Model
±15kV IEC 61000-4-2 Air Discharge
±8kV IEC 61000-4-2 Contact Discharge
Typical Operating Circuit
+3.3V
+1.8V
0.1μF
VL
+1.8V
SYSTEM
CONTROLLER
VCC
+3.3V
SYSTEM
MAX13055E–
MAX13058E
EN
I/O VL_
EN
DATA
I/O VCC_
8
GND
0.1μF
1μF
DATA
8
GND
GND
Applications
Low-Voltage ASIC Level
Translation
Portable Communication
Devices
Smart Card Readers
Cell Phones
Camera Modules
GPS
Portable POS Systems
Telecomm Equipment
Pin Configurations appear at end of data sheet.
Ordering Information/Selector Guide
I/O VL_ STATE
DURING SHUTDOWN
PART
I/O VCC_ STATE
DURING SHUTDOWN
TEMP RANGE
PIN-PACKAGE
24 WLP
28 TQFN-EP*
MAX13055EEWG+
Open Drain
Open Drain
-40°C to +85°C
MAX13055EETI+
Open Drain
Open Drain
-40°C to +85°C
Ordering Information/Selector Guide continued at end of data sheet.
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim's website at www.maxim-ic.com.
1
MAX13055E–MAX13058E
General Description
MAX13055E–MAX13058E
1.62V to 3.6V, 8-Channel, High-Speed LLT
ABSOLUTE MAXIMUM RATINGS
(Voltages referenced to GND.)
VCC, VL .............................................................................-0.3V to +4.0V
EN..........................................................................-0.3V to +4.0V
I/O VCC_ .....................................................-0.3V to (VCC + 0.3V)
I/O VL_ ...........................................................-0.3V to (VL + 0.3V)
Short-Circuit Duration
I/O to GND..................................................................Continuous
Continuous Power Dissipation (TA = +70°C)
28-Pin TQFN (derate 28.6mW/°C above +70°C) .......2286mW
Junction-to-Case Thermal Resistance (θJC) (Note 1)
28-Pin TQFN................................................................2.7°C/W
Junction-to-Ambient Thermal Resistance (θJA) (Note 1)
24-Bump WLP ..............................................................97°C/W
28-Pin TQFN.................................................................35°C/W
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = +2.2V to +3.6V, VL = +1.62V to +3.2V, EN = VL, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = +3.3V,
VL = +1.8V, and TA = +25°C.) (Notes 2, 3)
PARAMETER
VL Supply Range
VCC Supply Range
Supply Current from VCC
Supply Current from VL
VCC Shutdown Supply Current
VL Shutdown Mode Supply
Current
I/O Three-State Leakage Current
EN Input Leakage Current
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
VL
1.62
3.2
V
VCC
2.2
3.6
V
IQVCC
I/O VCC_ = VCC, I/O VL_ = VL
40
µA
IQVL
I/O VCC_ = VCC, I/O VL_ = VL
10
µA
µA
ISHDN-VCC
ISHDN-VL
ILEAK
0.1
2
TA = +25°C, EN = GND
0.1
1
TA = +25°C, EN = VL, VCC = 0V
0.1
4
TA = +25°C, EN = GND
0.1
2
µA
o
1
µA
VTH_H
VCC rising
0
0.1 x VL
0.8
V
VL - VCC Shutdown Threshold Low
VTH_L
VCC falling
0
0.12 x VL
0.8
V
RVCC_PD_SD MAX13056E/MAX13058E
10
16.5
23
kΩ
MAX13057E/MAX13058E
10
16.5
23
kΩ
IVL_PU_
I/O VL_ = GND, I/O VCC_ = GND
20
65
µA
IVCC_PU_
I/O VCC_ = GND, I/O VL_ = GND
20
65
µA
I/O VL_ Pulldown Resistance
During Shutdown
I/O VL_ Pullup Current
(Normal Mode)
I/O VCC_ Pullup Current
(Normal Mode)
I/O VL_ to I/O VCC_ DC Resistance
RVL_PD_SD
TA = +25 C
µA
VL - VCC Shutdown Threshold High
I/O VCC_ Pulldown Resistance
During Shutdown
ILEAK_EN
TA = +25°C, EN = GND
RIOVL_IOVCC
3
kΩ
Human Body Model
+2
kV
Human Body Model
+15
IEC 61000-4-2 Air-Gap Discharge, CVCC = 1µF
+15
IEC 61000-4-2 Contact Discharge, CVCC = 1µF
+8
ESD PROTECTION
All Ports
I/O VCC_ Only
2
_______________________________________________________________________________________
kV
1.62V to 3.6V, 8-Channel, High-Speed LLT
(VCC = +2.2V to +3.6V, VL = +1.62V to +3.2V, EN = VL, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = +3.3V,
VL = +1.8V, and TA = +25°C.) (Notes 2, 3)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
LOGIC LEVELS
I/O VL_ Input-Voltage High
VIHL
(Note 4)
I/O VL_ Input-Voltage Low
VILL
(Note 4)
I/O VCC_ Input-Voltage High
VIHC
(Note 4)
I/O VCC_ Input-Voltage Low
VILC
(Note 4)
EN Input-Voltage High
VIH
EN Input-Voltage Low
VIL
VL - 0.2
V
0.15
VCC 0.4
V
0.2
V
0.4
V
VL - 0.4
I/O VL_ Output-Voltage High
VOHL
I/O VL_ source current = 10µA
I/O VL_ Output-Voltage Low
VOLL
I/O VL_ sink current = 20µA, I/O VCC_ < 0.1V
I/O VCC_ Output-Voltage High
VOHC
I/O VCC_ source current = 10µA
I/O VCC_ Output-Voltage Low
VOLC
I/O VCC_ sink current = 20µA, I/O VL_ < 0.1V
V
V
V
4/5 VL
1/5 VL
4/5
VCC
V
V
1/5
V
RISE/FALL TIME ACCELERATOR STAGE
Accelerator Pulse Duration
On falling edge
On rising edge
3.5
ns
VL Output Accelerator Source
Impedance
VL = 1.62V
24
Ω
VCC Output Accelerator Source
Impedance
VCC = 2.2V
13
Ω
VL Output Accelerator Source
Impedance
VL = 3.2V
11
Ω
VCC Output Accelerator Source
Impedance
VCC = 3.6V
9
Ω
VL Output Accelerator Sink
Impedance
VL = 1.62V
14
Ω
VCC Output Accelerator Sink
Impedance
VCC = 2.2V
11
Ω
VL Output Accelerator Sink
Impedance
VL = 3.2V
10
Ω
VCC Output Accelerator Sink
Impedance
VCC = 3.6V
9
Ω
_______________________________________________________________________________________
3
MAX13055E–MAX13058E
ELECTRICAL CHARACTERISTICS (continued)
MAX13055E–MAX13058E
1.62V to 3.6V, 8-Channel, High-Speed LLT
TIMING CHARACTERISTICS
(+2.2V ≤ VCC ≤ 3.6V, +1.62V ≤ VL ≤ +3.2V; CI/OVL_ ≤ 15pF, CI/OVCC_ ≤ 10pF; RSOURCE < 150Ω, EN = VL, TA = -40°C to +85°C,
unless otherwise noted. Typical values are at VCC = +3.3V, VL = +1.8V, and TA = +25°C.) (Notes 2, 3)
MAX
UNITS
I/O VCC_ Rise Time
PARAMETER
tRVCC
Figure 2
2.5
ns
I/O VCC_ Fall Time
tFVCC
Figure 2
2.5
ns
I/O VL_ Rise Time
tRVL
Figure 1
2.5
ns
I/O VL_ Fall Time
tFVL
Figure 1
2.5
ns
Propagation Delay
(Driving I/O VL_)
tPVL-VCC
Figure 2
1
6.5
ns
Propagation Delay
(Driving I/O VCC_)
tPVCC-VL
Figure 1
1
6.5
ns
2
ns
Channel-to-Channel Skew
Propagation Delay from I/O VL_
to I/O VCC_ After EN
Propagation Delay from I/O VCC_
to I/O VL_ After EN
Maximum Data Rate
SYMBOL
CONDITIONS
MIN
TYP
tSKEW
tEN-VCC
Figure 3
5
µs
tEN-VL
Figure 3
5
µs
Push-pull operation
Open drain
100
1
Mbps
Note 2: All units are 100% production tested at TA = +25°C. Limits over the operating temperature range are guaranteed by design
and not production tested.
Note 3: VL must be less than or equal to VCC during normal operation. However, VL can be greater than VCC during startup and
shutdown conditions. It will not latch up.
Note 4: For input thresholds, see the rise/fall time accelerator circuit in Figure 4.
4
_______________________________________________________________________________________
1.62V to 3.6V, 8-Channel, High-Speed LLT
VL
tRVCC
VCC
90%
VCC
EN
VL
90%
I/O VL_
MAX13055E–MAX13058E
VL
tFVCC
50%
VCC
50%
50%
50%
I/O VCC_
I/O VL_
10%
I/O VCC_ 10%
50Ω
CIOVCC
tPLH
tPHL
tPVL-VCC = tPLH OR tPHL
Figure 1. Push-Pull Driving I/O VL_ Test Circuit and Timing
VL
EN
VL
tFVL
tRVL
VCC
I/O VCC_
VCC
MAX13055E–MAX13058E
VL
VCC
90%
50%
I/O VL_
50%
I/O VCC_
50Ω
50%
50%
10%
10%
I/O VL_
CIOVL_
tPLH
90%
tPHL
tPVCC-VL = tPLH OR tPHL
Figure 2. Push-Pull Driving I/O VCC_ Test Circuit and Timing
_______________________________________________________________________________________
5
MAX13055E–MAX13058E
Test Circuits/Timing Diagrams
MAX13055E–MAX13058E
1.62V to 3.6V, 8-Channel, High-Speed LLT
Test Circuits/Timing Diagrams (continued)
VL
VCC
VL
VCC
VL
MAX13055E–
MAX13058E VCC
V
I/O VCC_
EN
tEN-VCC
EN
RLOAD
0.5V
I/O VCC_
I/O VL_
CIOVCC_
150Ω
TIME
VL
VCC
VL
VCC
V
EN
RLOAD
VL
MAX13055E–
MAX13058E VCC
I/O VL_
tEN-VL
I/O VL_
EN
0.2V (VL < 2V)
0.5V (VL ≥ 2V)
I/O VCC_
CIOVL_
150Ω
TIME
Figure 3. Enable Test Circuit and Timing
6
_______________________________________________________________________________________
1.62V to 3.6V, 8-Channel, High-Speed LLT
380
VCC = 3.6V
340
6
4
VL = 1.8V
2.2
2.4
2.6
2.8
3.0
3.2
3.4
9
6
0
0
3.6
12
3
2
300
1.6
2.0
2.4
2.8
2.2
3.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC SUPPLY VOLTAGE (V)
VL SUPPLY VOLTAGE (V)
VCC SUPPLY VOLTAGE (V)
VCC SUPPLY CURRENT vs. VL SUPPLY
VOLTAGE (DRIVING ONE I/O VCC_)
SUPPLY CURRENT vs. TEMPERATURE
(DRIVING ONE I/O VCC_)
SUPPLY CURRENT vs. TEMPERATURE
(DRIVING ONE I/O VL_)
6
4
2
6
5
4
IVCC
IVL
3
2
2.0
2.4
2.8
VL SUPPLY VOLTAGE (V)
3.2
9
IVCC
8
7
6
5
4
3
IVL
1
0
1.6
10
2
1
0
11
MAX13055E toc06
8
7
SUPPLY CURRENT (mA)
VCC = 3.6V
SUPPLY CURRENT (mA)
MAX13055E toc04
10
VCC SUPPLY CURRENT (mA)
8
15
VCC SUPPLY CURRENT (FA)
420
MAX13055E toc02
460
10
MAX13055E toc05
VL SUPPLY CURRENT (FA)
VL = 1.8V
VL SUPPLY CURRENT (mA)
MAX13055E toc01
500
VCC SUPPLY CURRENT vs. VCC SUPPLY
VOLTAGE (DRIVING ONE I/O VL_)
VL SUPPLY CURRENT vs. VL SUPPLY
VOLTAGE (DRIVING ONE I/O VCC_)
MAX13055E toc03
VL SUPPLY CURRENT vs. VCC SUPPLY
VOLTAGE (DRIVING ONE I/O VL_)
-40
-15
10
35
TEMPERATURE (NC)
60
85
0
-40
-15
10
35
60
85
TEMPERATURE (NC)
_______________________________________________________________________________________
7
MAX13055E–MAX13058E
Typical Operating Characteristics
(VCC = +3.3V, VL = +1.8V, CI/OVCC_ = 10pF, CI/OVL_ = 15pF, RSOURCE = 50Ω, data rate = 100Mbps, push-pull driver, TA = +25°C,
unless otherwise noted.)
Typical Operating Characteristics (continued)
(VCC = +3.3V, VL = +1.8V, CI/OVCC_ = 10pF, CI/OVL_ = 15pF, RSOURCE = 50Ω, data rate = 100Mbps, push-pull driver, TA = +25°C,
unless otherwise noted.)
4
3
2
MAX13055E toc08
16
14
12
10
8
6
15
20
25
30
35
40
0.6
tFVCC
0.4
10
15
20
25
30
35
10
40
15
20
25
30
35
40
CAPACITIVE LOAD (pF)
CAPACITIVE LOAD (pF)
CAPACITIVE LOAD (pF)
RISE/FALL TIME vs. CAPACITIVE
LOAD ON I/O VL_ (DRIVING I/O VCC_)
PROPAGATION DELAY vs. CAPACITIVE
LOAD ON I/O VCC_ (DRIVING I/O VL_)
PROPAGATION DELAY vs. CAPACITIVE
LOAD ON I/O VL_ (DRIVING I/O VCC_)
2.0
1.5
1.0
0.5
tFVL
3.0
tPLH
2.5
2.0
1.5
1.0
tPHL
0.5
15
20
25
30
CAPACITIVE LOAD (pF)
35
40
3.5
3.0
tPHL
2.5
2.0
1.5
tPLH
1.0
0.5
0
0
MAX13055E toc12
3.5
4.0
PROPAGATION DELAY (ns)
tRVL
4.0
PROPAGATION DELAY (ns)
2.5
MAX13055E toc10
3.0
10
0.8
0
0
10
1.0
0.2
2
0
tRVCC
1.2
4
1
8
1.4
RISE/FALL TIME (ns)
5
18
MAX13055E toc11
VL SUPPLY CURRENT (mA)
6
20
VCC SUPPLY CURRENT (mA)
MAX13055E toc07
7
RISE/FALL TIME vs. CAPACITIVE
LOAD ON I/O VCC_ (DRIVING I/O VL_)
VCC SUPPLY CURRENT vs. CAPACITIVE
LOAD ON I/O VCC_ (DRIVING ONE I/O VL_)
MAX13055E toc09
VL SUPPLY CURRENT vs. CAPACITIVE
LOAD ON I/O VL_ (DRIVING ONE I/O VCC_)
RISE/FALL TIME (ns)
MAX13055E–MAX13058E
1.62V to 3.6V, 8-Channel, High-Speed LLT
0
10
15
20
25
30
CAPACITIVE LOAD (pF)
35
40
10
15
20
25
30
CAPACITIVE LOAD (pF)
_______________________________________________________________________________________
35
40
1.62V to 3.6V, 8-Channel, High-Speed LLT
TYPICAL I/O VL_ DRIVING
(FREQUENCY = 25MHz, CIOVCC_ = 40pF)
TYPICAL I/O VCC_ DRIVING
(FREQUENCY = 25MHz, CIOVL_ = 15pF)
MAX13055E toc13
MAX13055E toc14
I/O VL_
1V/div
I/O VCC_
2V/div
I/O VCC_
2V/div
I/O VL_
1V/div
10ns/div
10ns/div
Pin Description
PIN
NAME
FUNCTION
TQFN-EP
WLP
1, 12, 13, 14,
24, 25, 26, 27
—
N.C.
2
B1
I/O VL1
Input/Output 1 Referenced to VL
3
A1
I/O VL2
Input/Output 2 Referenced to VL
4
A2
I/O VL3
Input/Output 3 Referenced to VL
5
A3
I/O VL4
6
B3, B4, B5
GND
7
A4
I/O VL5
Input/Output 5 Referenced to VL
8
A5
I/O VL6
Input/Output 6 Referenced to VL
9
A6
I/O VL7
Input/Output 7 Referenced to VL
10
B6
I/O VL8
No Connection. N.C. is not internally connected.
Input/Output 4 Referenced to VL
Ground
Input/Output 8 Referenced to VL
Enable Control Input. Drive EN high for normal operation. Drive EN low for shutdown
mode.
11
C5
EN
15
C6
I/O VCC8
Input/Output 8 Referenced to VCC
16
D6
I/O VCC7
Input/Output 7 Referenced to VCC
17
D5
I/O VCC6
Input/Output 6 Referenced to VCC
18
D4
I/O VCC5
Input/Output 5 Referenced to VCC
19
C2, C3, C4
VCC
20
D3
I/O VCC4
+2.2V to +3.6V Power-Supply Voltage. Bypass VCC with 1µF and 0.1µF ceramic
capacitors located as close to the device as possible.
Input/Output 4 Referenced to VCC
_______________________________________________________________________________________
9
MAX13055E–MAX13058E
Typical Operating Characteristics (continued)
(VCC = +3.3V, VL = +1.8V, CI/OVCC_ = 10pF, CI/OVL_ = 15pF, RSOURCE = 50Ω, data rate = 100Mbps, push-pull driver, TA = +25°C,
unless otherwise noted.)
1.62V to 3.6V, 8-Channel, High-Speed LLT
MAX13055E–MAX13058E
Pin Description (continued)
PIN
NAME
FUNCTION
TQFN-EP
WLP
21
D2
I/O VCC3
Input/Output 3 Referenced to VCC
22
D1
I/O VCC2
Input/Output 2 Referenced to VCC
23
C1
I/O VCC1
Input/Output 1 Referenced to VCC
28
B2
VL
+1.62V to +3.2V Logic-Supply Voltage. Bypass VL with a 0.1µF ceramic capacitor
located as close to the device as possible.
—
—
EP
Exposed Pad. Connect EP to GND.
Functional Diagram
VL
VCC
MAX13055E–MAX13058E
CHANNEL 1
I/O VL1
I/O VCC1
I/O VL2
CHANNEL 2
I/O VCC2
I/O VL3
CHANNEL 3
I/O VCC3
I/O VL4
CHANNEL 4
I/O VCC4
I/O VL5
CHANNEL 5
I/O VCC5
I/O VL6
CHANNEL 6
I/O VCC6
I/O VL7
CHANNEL 7
I/O VCC7
I/O VL8
CHANNEL 8
I/O VCC8
EN
GND
NOTE: EXTERNAL PULLUP RESISTORS NOT RECOMMENDED ON I/O LINES.
10
______________________________________________________________________________________
1.62V to 3.6V, 8-Channel, High-Speed LLT
The MAX13055E–MAX13058E 8-channel, bidirectional
level translators provide the level shifting necessary for
100Mbps data transfer in multivoltage systems. The
MAX13055E–MAX13058E are ideally suited for level
translation in systems with 8 channels. Externally
applied voltages, VCC and VL, set the logic levels on
either side of the device. Logic-high signals presented
on the VL side of the device appear as a logic-high signal on the VCC side of the device and vice versa.
The MAX13055E–MAX13058E operate at full speed
with external drivers that source as little as 4mA output
current. Each I/O channel is pulled up to VCC or VL by
an internal 40µA current source, allowing the
MAX13055E–MAX13058E to be driven by either pushpull or open-drain drivers.
The MAX13055E–MAX13058E feature an enable (EN)
input that places the devices into a low-power shutdown mode when driven low. The MAX13055E–
MAX13058E feature an automatic shutdown mode that
disables the part when VCC is less than VL. The state of
I/O VCC_ and I/O VL _ during shutdown is chosen by
selecting the appropriate part version (see the Ordering
Information/Selector Guide).
The MAX13055E–MAX13058E operate with VCC voltages from +2.2V to +3.6V and VL voltages from +1.62V
to +3.2V.
Level Translation
V L while V CC is missing or less than V L , the
MAX13055E–MAX13058E automatically enter a lowpower mode. The devices also enters shutdown mode
when VEN = 0V. This allows VCC to be disconnected
and still have a known state on I/O VL _. The maximum
data rate depends heavily on the load capacitance
(see the Rise/Fall Time vs. Capacitive Load graphs in
the Typical Operating Characteristics), output impedance of the driver, and the operating voltage range.
Input Requirements
The MAX13055E–MAX13058E architecture is based on
an nMOS pass gate and rise/fall time accelerator stages
(Figure 4). The accelerators are active only when there
is a rising/falling edge on a given I/O. A short pulse is
then generated where the output accelerator stages
become active and charges/discharges the capacitance at the I/Os. Due to its architecture, both input
stages become active during the one-shot pulse. This
can lead to current feeding into the external source that
is driving the translator. However, this behavior helps to
speed up the transition on the driven side.
The MAX13055E–MAX13058E have internal current
sources capable of sourcing 40µA to pull up the I/O
lines. These internal pullup current sources allow the
inputs to be driven with open-drain drivers as well as
push-pull drivers. It is not recommended to use external
pullup resistors on the I/O lines. The architecture of the
MAX13055E–MAX13058E permits either side to be driven with a minimum of 4mA drivers or larger.
For proper operation, ensure that +2.2V ≤ VCC ≤ +3.6V,
+1.62V ≤ VL ≤ VCC - 0.2V. When power is supplied to
VL
VCC
RISE/FALL TIME
ACCELERATOR
VCC
RISE/FALL TIME
ACCELERATOR
ONE-SHOT
ONE-SHOT
VBIAS
I/O VCC_
I/O VL_
ONE-SHOT
ONE-SHOT
Figure 4. Simplified Functional Diagram for One I/O Line
______________________________________________________________________________________
11
MAX13055E–MAX13058E
Detailed Description
MAX13055E–MAX13058E
1.62V to 3.6V, 8-Channel, High-Speed LLT
Output Load Requirements
The MAX13055E–MAX13058E I/O are designed to drive
CMOS inputs. Do not load the I/O lines with a resistive
load less than 25kΩ. Do not place an RC circuit at the
input of these devices to slow down the edges. If a
slower rise/fall time is required, refer to the MAX3000E/
MAX3001E logic-level translator data sheet.
Shutdown Mode
The MAX13055E–MAX13058E feature an enable (EN)
input that places the devices into a low-power shutdown
mode when driven low. The MAX13055E–MAX13058E
feature an automatic shutdown mode that disables the
part when VCC is unconnected or less than VL.
Applications Information
state when the device is enabled. In shutdown mode,
the state of I/O VCC_ and I/O VL _ is dependent on the
selected part version (see the Ordering Information/
Selector Guide).
Open-Drain Signaling
The MAX13055E–MAX13058E are designed to pass
open-drain as well as CMOS push-pull signals. When
used with open-drain signaling, the rise time is dominated
by the interaction of the internal pullup current source and
the parasitic load capacitance. The MAX13055E–
MAX13058E include internal rise-time accelerators to
speed up transitions, eliminating any need for external
pullup resistors. For applications such as I2C or 1-Wire®
that require an external pullup resistor, refer to the
MAX3378E and MAX3396E data sheets.
Layout Recommendations
Use standard high-speed layout practices when laying
out a board with the MAX13055E–MAX13058E. For
example, to minimize line coupling, place all other signal
lines not connected to the MAX13055E–MAX13058E at
least 1x the substrate height of the PCB away from the
input and output lines of the MAX13055E–MAX13058E.
Human Body Model
Figure 5a shows the Human Body Model and Figure 5b
shows the current waveform it generates when discharged into a low impedance. This model consists of a
100pF capacitor charged to the ESD voltage of interest,
which is then discharged into the test device through a
1.5kΩ resistor.
Power-Supply Decoupling
To reduce ripple and the chance of introducing data
errors, bypass VL and VCC to ground with 0.1µF ceramic capacitors. Place all capacitors as close to the
power-supply inputs as possible. For full ESD protection, bypass VCC with a 1µF ceramic capacitor located
as close to the VCC input as possible.
Unidirectional vs. Bidirectional
Level Translator
The MAX13055E–MAX13058E bidirectional level translators can operate as a unidirectional device to translate signals without inversion. These devices provide a
small solution for unidirectional level translation without
inversion.
ESD Test Conditions
ESD performance depends on a variety of conditions.
Contact Maxim for a reliability report that documents
test setup, test methodology, and test results.
Use with External Pullup/
Pulldown Resistors
Due to the architecture of the MAX13055E–
MAX13058E, it is not recommended to use external
pullup or pulldown resistors on the bus. In certain applications, the use of external pullup or pulldown resistors
is desired to have a known bus state when there is no
active driver on the bus. The MAX13055E–MAX13058E
include internal pullup current sources that set the bus
12
IEC 61000-4-2
The IEC 61000-4-2 standard covers ESD testing and performance of finished equipment; it does not specifically
refer to integrated circuits. The MAX13055E–MAX13058E
help in designing equipment that meets level 4 (the highest level) of IEC 61000-4-2, without the need for additional ESD-protection components. The major difference
between tests done using the Human Body Model and
IEC 61000-4-2 is higher peak current in IEC 61000-4-2,
because series resistance is lower in the IEC 61000-4-2
model. Hence, the ESD withstand voltage measured to
IEC 61000-4-2 is generally lower than that measured
using the Human Body Model. Figure 6a shows the IEC
61000-4-2 model and Figure 6b shows the current waveform for the ±8kV, IEC 61000-4-2, level 4, ESD Contact
Discharge Method.
The Air Gap Method involves approaching the device
with a charged probe. The Contact Discharge Method
connects the probe to the device before the probe is
energized.
Chip Information
PROCESS: CMOS
1-Wire is a registered trademark of Maxim Integrated Products,
Inc.
______________________________________________________________________________________
1.62V to 3.6V, 8-Channel, High-Speed LLT
CHARGE-CURRENTLIMIT RESISTOR
HIGHVOLTAGE
DC
SOURCE
Cs
100pF
RD
1500Ω
IP 100%
90%
DISCHARGE
RESISTANCE
IR
36.8%
DEVICE
UNDER
TEST
STORAGE
CAPACITOR
10%
0
HIGHVOLTAGE
DC
SOURCE
Cs
150pF
TIME
tRL
tDL
CURRENT WAVEFORM
Figure 5b. Human Body Current Waveform
Figure 5a. Human Body ESD Test Model
RD
330Ω
I
100%
90%
DISCHARGE
RESISTANCE
IPEAK
CHARGE-CURRENTLIMIT RESISTOR
PEAK-TO-PEAK RINGING
(NOT DRAWN TO SCALE)
AMPERES
0
RC
50MΩ to 100MΩ
MAX13055E–MAX13058E
RC
1MΩ
DEVICE
UNDER
TEST
STORAGE
CAPACITOR
10%
tR = 0.7ns to 1ns
30ns
t
60ns
Figure 6b. IEC 61000-4-2 ESD Generator Current Waveform
Figure 6a. IEC 61000-4-2 ESD Test Model
Ordering Information/Selector Guide (continued)
PART
I/O VL_ STATE
DURING SHUTDOWN
MAX13056EEWG+**
Open Drain
MAX13056EETI+**
Open Drain
10kΩ to GND
MAX13057EEWG+**
I/O VCC_ STATE
DURING SHUTDOWN
TEMP RANGE
PIN-PACKAGE
10kΩ to GND
-40°C to +85°C
24 WLP
10kΩ to GND
-40°C to +85°C
28 TQFN-EP*
Open Drain
-40°C to +85°C
24 WLP
28 TQFN-EP*
MAX13057EETI+**
10kΩ to GND
Open Drain
-40°C to +85°C
MAX13058EEWG+
10kΩ to GND
10kΩ to GND
-40°C to +85°C
24 WLP
MAX13058EETI+
10kΩ to GND
10kΩ to GND
-40°C to +85°C
28 TQFN-EP*
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
**Future product—contact factory for availability.
______________________________________________________________________________________
13
Pin Configurations
I/O VCC7
I/O VCC8
I/O VCC6
I/O VCC5
VCC
I/O VCC3
I/O VCC4
I/O VCC2
I/O VCC1
N.C.
TOP VIEW
TOP VIEW
(BUMPS ON BOTTOM)
MAX13055E–MAX13058E
D
C
B
24 23 22 21 20 19 18 17 16 15
14 N.C.
N.C. 26
13 N.C.
MAX13055E–MAX13058E
N.C. 27
VL 28
N.C.
I/O VL2
I/O VL3
I/O VL4
6
7
8
9
10
I/O VL8
5
I/O VL7
4
I/O VL6
3
GND
2
I/O VL2
I/O VCC3
VCC
VL
I/O VL3
I/O VCC4
VCC
GND
I/O VL4
I/O VCC5
VCC
GND
I/O VL5
I/O VCC6
EN
GND
I/O VL6
2
11 EN
I/O VL5
1
1
I/O VCC2 I/O VCC1 I/O VL1
12 N.C.
*EP
+
A
+
N.C. 25
I/O VL1
MAX13055E–MAX13058E
1.62V to 3.6V, 8-Channel, High-Speed LLT
3
4
TQFN
5
*CONNECT EXPOSED PAD TO GND.
6
I/O VCC7 I/O VCC8 I/O VL8
I/O VL7
WLP
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages.
PACKAGE TYPE
PACKAGE CODE
DOCUMENT NO.
24 WLP
W241B2-1
21-0219
28 TQFN
T283555-1
21-0184
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
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© 2009 Maxim Integrated Products
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