MAX14640–MAX14644/MAX14651
USB Host Adapter Emulators
General Description
Benefits and Features
●● Improved Charger Interoperability
• USB (CDP) Emulation
• Smart CDP
• Foolproof CDP
• Meets New USB Battery Charging (BC) Revision
1.2 Specification
• Backward-Compatible with Previous USB BC Revisions
• Meets China YD/T1591-2009 Charging Specification
• Supports Standby-Mode Charging for Apple BC
Revision 1.2 Compatible Devices
●● Provide Greater Application Flexibility
• I2C Controls Multiple Modes (MAX14640/MAX14651)
• CB0 and CB1 Pins Control Multiple Automatic and
Manual Charger States
The MAX14640–MAX14644/MAX14651 are next-generation
USB 2.0 host charger adapter emulators that combine
USB Hi-Speed analog switches with a USB adapter
emulator circuit.
The MAX14640/MAX14651 feature an I2C interface to fully
configure the charging behavior with different address
options. The MAX14641–MAX14644 are controlled by
two GPIO inputs (CB1/CB0) and support USB data and
automatic charger mode. In charging downstream port
(CDP) pass-through mode, the devices emulate the
CDP function while supporting normal USB traffic. The
MAX14641/MAX14642/MAX14643 have a CEN output
for an active-high CLS enable input, and the MAX14644
has a CEN output for an active-low CLS enable input to
restart the peripheral connected to the USB host.
●● Enhance Performance with High Level of Integrated Features
• Supports Remote Wakeup
• Low-Capacitance USB 2.0 Hi-Speed Switch to
Change Charging Modes
• Automatic Current-Limit Switch Control
• ±15kV ESD Protection on DP/DM
The MAX14640–MAX14644/MAX14651 feature 2A highcurrent autodetect mode. The MAX14641 features 1A
high-current forced mode instead of regular DCP mode.
The MAX14640/MAX14651 can be configured through I2C
to support various dedicated charger modes such as DCP,
Apple® 1A/2A forced, or Apple 1A/2A automatic mode.
●● Minimize PCB Area
• 2mm x 2mm, 8-Pin TDFN Package
All the devices support CDP and standard downstream port
(SDP) charging while in the active state (S0) and support
the dedicated charging port (DCP) charging while in the
standby state (S3/S4/S5). All devices support low-speed
remote wake-up by monitoring DM, and the MAX14642
also supports remote wake-up in sleep mode (S3).
Applications
●● Laptop/Desktop Computers
●● USB Hubs
●● Universal Chargers Including iPod®/iPhone®/iPad®
The MAX14640–MAX14644/MAX14651 are available in an
8-pin (2mm x 2mm) TDFN-EP package and are specified
over the -40NC to +85NC extended temperature range.
Ordering Information and Typical Operating Circuit appear
at end of data sheet.
Selector Guide
PART
I/O MODE
CEN POLARITY
REMOTE WAKE-UP IN AM
FORCED CHARGER MODE
BIAS IN FM
MAX14640
I2C (0x35)
N/A
Optional
Yes
DP/DM short
MAX14641
GPIO
CEN
No
No
Apple 1A
MAX14642
GPIO
CEN
Yes
Yes
DP/DM short
MAX14643
GPIO
CEN
No
Yes
DP/DM short
MAX14644
GPIO
CEN
No
Yes
DP/DM short
MAX14651
I2C (0x15)
N/A
Optional
Yes
DP/DM short
Apple, iPad, iPod, and iPhone are registered trademarks of Apple, Inc.
19-6472; Rev 4; 9/16
MAX14640–MAX14644/MAX14651
USB Host Adapter Emulators
Absolute Maximum Ratings
(All voltages referenced to GND.)
VCC, TDP, TDM, DP, DM, SDA, SCL,
CB0, CB1, CEN, CEN, INT...................................-0.3V to +6V
Continuous Current into Any Terminal............................. Q30mA
Continuous Power Dissipation (TA = +70NC)
TDFN (derate 11.9mW/NC above +70NC)..................953.5mW
Operating Temperature Range........................... -40NC to +85NC
Junction Temperature......................................................+150NC
Storage Temperature Range............................. -65NC to +150NC
Lead Temperature (soldering, 10s).................................+300NC
Soldering Temperature (reflow).......................................+260NC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Package Thermal Characteristics (Note 1)
TDFN
Junction-to-Ambient Thermal Resistance (BJA)........83.9NC/W
Junction-to-Case Thermal Resistance (BJC)................37NC/W
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Electrical Characteristics
(VCC = 3.0V to 5.5V, TA = -40NC to +85NC, unless otherwise noted. Typical values are at VCC = 5.0V and TA = +25NC.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER SUPPLY
VCC Supply Voltage
VCC
CB0 = high
3.0
5.5
CB0 = low (Note 3)
4.75
5.25
MAX14641–
MAX14644
VCC Supply Current
ICC
MAX14640/
MAX14651
POR Delay
CB1 = CB0 = low (AM2
mode)
200
CB1 = CB0 = high (CM
mode)
100
CB1 = low, CB0 = high
(PM mode)
20
MODE_SEL[2:0] = 000
(AM2 mode)
200
MODE_SEL[2:0] = 011
(CM mode)
100
MODE_SEL[2:0] = 001
(PM mode)
20
V
FA
tPOR
50
ms
ANALOG SWITCHES (DP, DM, TDP, TDM)
Analog Signal Range
TDP/TDM On Resistance
VDP, VDM
RON
(Note 4)
0
VIN = 0V to VCC, IIN = 10mA
3.5
VCC
V
6.5
I
TDP/TDM On-Resistance
Matching Between Channels
DRON
VCC = 5.0V, IIN = 10mA, VIN = 0.4V
0.1
I
TDP/TDM On-Resistance
Flatness
RFLAT
VCC = 5.0V, IIN = 10mA, VIN = 0V to VCC
0.1
I
VDP = 1V, RL = 20kI on DM
70
DP/DM Short On-Resistance
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RSHORT
128
I
Maxim Integrated │ 2
MAX14640–MAX14644/MAX14651
USB Host Adapter Emulators
Electrical Characteristics (continued)
(VCC = 3.0V to 5.5V, TA = -40NC to +85NC, unless otherwise noted. Typical values are at VCC = 5.0V and TA = +25NC.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Off Leakage Current
ICOM(OFF)
VCC = 3.6V, VDP = VDM = 0.3V to 3.3V,
VTDP = VTDM = 3.3V to 0.3V
-1
1.5nA
+1
µA
On Leakage Current
ICOM(ON)
VCC = 3.6V, VDP = VDM = 0.3V to 3.3V
-1
90nA
+1
µA
DYNAMIC PERFORMANCE
Turn-On Time
tON
VTDP or VTDM = 1.5V, RL = 300I,
CL = 35pF, Figure 1 (Note 4)
20
Fs
Turn-Off Time
tOFF
VTDP or VTDM = 1.5V, RL = 300I,
CL = 35pF, Figure 1 (Note 4)
1
Fs
tPHL, tPLH
RL = RS = 50I, DP and DM connected to
TDP and TDM, Figure 2
60
ps
DP/DM Output Skew
tSKEW
RL = RS = 50I, DP and DM connected to
TDP and TDM, Figure 2
40
ps
DP/DM On-Capacitance
(Connected to TDP, TDM)
COFF
f = 240MHz, VBIAS = 0V, VIN = 500mVP-P
5
pF
TDP/TDM Propagation Delay
Bandwidth
BW
RL = RS = 50I, Figure 3
1000
MHz
Off-Isolation
VISO
VIN = 0dBm, RL = RS = 50I, f = 250MHz,
Figure 3
-20
dB
Crosstalk
VCT
VIN = 0dBm, RL = RS = 50I, f = 250MHz,
Figure 3
-25
dB
DCP INTERNAL RESISTORS
DP/DM Short Pulldown
RPD
320
500
700
RP1/RP2 Ratio
RTRP
1.485
1.5
1.515
RP1 + RP2 Resistance
RRP
92
125
158.5
RM1/RM2 Ratio
RTRM
0.844
0.85
0.864
RM1 + RM2 Resistance
RRM
68
93
118
RSS1/RSS2 Ratio
RTRSS
2.9
3
3.1
RSS1 + RSS2 Resistance
RRSS
30
40
60
kI
kI
kI
kI
CDP INTERNAL RESISTORS
DP Pulldown Resistor
RDP_CDP
CDP mode
14.25
19.53
24.80
kI
DM Pulldown Resistor
RDM_CDP
CDP mode
14.25
19.53
24.8
kI
100
161
205
mV
0.7
V
CDP HIGH-SPEED COMPARATORS
Threshold Voltage
VTH_CDP
CDP LOW-SPEED COMPARATORS
VDM_SRC Voltage
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VDM_SRC
ILOAD = 0 to 200FA
0.5
Maxim Integrated │ 3
MAX14640–MAX14644/MAX14651
USB Host Adapter Emulators
Electrical Characteristics (continued)
(VCC = 3.0V to 5.5V, TA = -40NC to +85NC, unless otherwise noted. Typical values are at VCC = 5.0V and TA = +25NC.) (Note 2)
PARAMETER
VDP_REF Voltage
VLGC Voltage
IDP_SINK Current
SYMBOL
CONDITIONS
VDP_REF
VLGC
IDP_SINK
MIN
TYP
0.25
VDP = 0.15V to 3.6V
MAX
UNITS
0.4
V
0.8
2.0
V
50
150
FA
LOGIC INPUTS (CB0, CB1, SDA, SCL)
Input Logic High Voltage
VIH
Input Logic Low Voltage
VIL
Input Leakage Current
IIN
CB0/CB1 Debounce Time
1.4
0V P VIN P VIL or VIH P VIN P VCC,
VCC = 5.5V
V
-1
tDEB_CB_
0.4
V
+1
FA
250
Fs
OPEN-DRAIN LOGIC OUTPUTS (SDA, INT, CEN, CEN)
INT, SDA, CEN Output Low
Voltage
VOL
Output asserted, ISINK = 4mA
INT, SDA, CEN Output Leakage
Current
IOH
Output not asserted, VCC = VOUT = 5.5V
CEN, INT, Output High Voltage
VOH
Output asserted, ISOURCE = 4mA
CEN, INT, Output Leakage Current
IOL
Output not asserted, VCC = 5.5V, VCEN = 0V
VBUS Toggle Time Accuracy
tVBT
0.4
V
1
FA
VCC - 0.4
V
1
FA
%
Q10
I2C TIMING CHARACTERISTICS (SEE FIGURE 4)
I2C Maximum Clock Frequency
fSCL
Bus Free Time Between STOP
and START Conditions
tBUF
1.3
Fs
START Condition Setup Time
tSU:STA
0.6
Fs
Repeated START Condition
Setup Time
tSU:STA
70% of SCL to 70% of SDA
0.6
Fs
START Condition Hold Time
tHD:STA
30% of SDA to 70% of SCL
0.6
Fs
STOP Condition Setup Time
tSU:STO
Clock Low Period
Clock High Period
400
kHz
70% of SCL to 30% of SDA
0.6
Fs
tLOW
30% to 30%
1.3
Fs
tHIGH
70% to 70%
0.6
Fs
Data Valid to SCL Rise Time
tSU:DAT
Write setup time
100
ns
Data Hold Time to SCL Fall
tHD:DAT
Write hold time
100
ns
PROTECTION SPECIFICATIONS
ESD Protection
VESD
Human Body Model
DP and DM pins
Q15
All other pins
Q2
kV
Note 2: All units are production tested at TA = +25NC. Specifications over temperature are guaranteed by design.
Note 3: The MAX1464_ is operational from 3.0V to 5.5V. However, in order for the valid Apple resistor-divider network to function,
VCC must stay within the 4.75V to 5.25V range.
Note 4: Guaranteed by design, not production tested.
Note 5: Guaranteed by design.
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Maxim Integrated │ 4
MAX14640–MAX14644/MAX14651
USB Host Adapter Emulators
Test Circuits/Timing Diagrams
VCC
VCC
LOGIC
INPUT
MAX14641–MAX14644/
MAX14651
VIN
D_
TD_
CB0
LOGIC
INPUT
CB1
VIL
50%
VOUT
RL
GND
CL INCLUDES FIXTURE AND STRAY CAPACITANCE.
RL
VOUT = VIN
RL + RON
t r < 5ns
t f < 5ns
VIH
t OFF
CL
VOUT
SWITCH
OUTPUT
0.9 x V0UT
0.9 x VOUT
0V
t ON
IN DEPENDS ON SWITCH CONFIGURATION;
INPUT POLARITY DETERMINED BY SENSE OF SWITCH.
t ON AND t OFF DO NOT INCLUDE THE CEN TOGGLE DELAY.
Figure 1. Switching Time
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Maxim Integrated │ 5
MAX14640–MAX14644/MAX14651
USB Host Adapter Emulators
Test Circuits/Timing Diagrams (continued)
MAX14641–MAX14644
RS
IN+
TDP
DP
OUT+
RISE-TIME PROPAGATION DELAY = tPLHX OR tPLHY
FALL-TIME PROPAGATION DELAY = tPHLX OR tPHLY
tSK = |tPLHX - tPLHY| OR |tPHLX - tPHLY|
RL
RS
IN-
TDM
DM
OUTRL
CB0
CB1
VCC
tINFALL
tINRISE
V+
90%
VIN+
50%
90%
50%
10%
0V
10%
V+
VIN-
50%
50%
0V
tOUTRISE
tPLHX
tOUTFALL
tPHLX
V+
90%
VOUT+
90%
50%
50%
10%
0V
10%
V+
50%
VOUT-
50%
0V
tPHLY
tPLHY
Figure 2. Propagation Delay and Output Skew
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Maxim Integrated │ 6
MAX14640–MAX14644/MAX14651
USB Host Adapter Emulators
Test Circuits/Timing Diagrams (continued)
VCC
0V OR VCC
CB0
VCC
50Ω
VIN
TDP
CB1
OFF-ISOLATION = 20log
NETWORK
ANALYZER
MAX14641–MAX14644
50Ω
V
CROSSTALK = 20log OUT
VIN
50Ω
MEAS
VOUT
DP*
VOUT
VIN
REF
50Ω
GND
MEASUREMENTS ARE STANDARDIZED AGAINST SHORTS AT IC TERMINALS.
OFF-ISOLATION IS MEASURED BETWEEN TD_ AND "OFF" D_ TERMINAL ON EACH SWITCH.
CROSSTALK IS MEASURED FROM ONE CHANNEL TO THE OTHER CHANNEL.
*FOR CROSSTALK THIS PIN IS DM.
Figure 3. Bandwidth, Off-Isolation, and Crosstalk
REPEATED START CONDITION
(Sr)
tR
START CONDITION
(S)
STOP CONDITION
(P)
tF
SDA
tBUF
tHD:STA
tHD:DAT
tHD:STA
tSU:DAT
tSU:STO
tSU:STA
SCL
tHIGH
tR
tF
tLOW
START CONDITION
(S)
Figure 4. I2C Timing Diagram. Note that tR and tF are per the I2C fast-mode specification.
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Maxim Integrated │ 7
MAX14640–MAX14644/MAX14651
USB Host Adapter Emulators
Typical Operating Characteristics
(VCC = +5V, TA = +25NC, unless otherwise noted.)
4.0
3.5
4.0
160
TA = +25°C
120
2.0
VCC = 5.5V
2.5
RON (I)
RON (I)
2.5
3.0
TA = -40°C
2.0
1.0
0.5
0.5
2.5
3.0
3.5
4.0
80
30
70
60
50
40
2
3
VDP/ DM (V)
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4
5
6
TA = +85°C
50
40
20
OFF-LEAKAGE
TA = -40°C
TA = +25°C
10
0
0
1
DEVICE IN CM
NO USB DEVICE
30
30
10
0
60
ON-LEAKAGE
20
VCC = 5.5V
ID_= 10mA
70
ICC (µA)
LEAKAGE CURRENT (nA)
TA = -40°C
VCC = 3.6V
VTDP = 3.3V
90
80
MAX14640 toc05
MAX14640 toc04
100
MAX14640 toc06
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
TA = +25°C
0
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
TDP/DP LEAKAGE CURRENT
vs. TEMPERATURE
60
10
2.0
DP/DM SHORT ON-RESISTANCE
vs. SIGNAL VOLTAGE
70
20
1.5
VDP (V)
80
40
1.0
VTDP/ TDM (V)
TA = +85°C
50
0
0.5
VTDP/ TDM (V)
100
90
VCC = 5.5V
20
0
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
80
40
0
0
VCC = 2.8V
100
60
1.5
1.0
IDP = 10mA
140
3.5
1.5
RON (I)
TA = +85°C
4.5
VCC = 2.8V
3.0
RON (I)
5.0
DP/DM SHORT ON-RESISTANCE
vs. SIGNAL VOLTAGE
MAX14640 toc02
ITD_= 10mA
MAX14640 toc01
4.5
USB SWITCH ON-RESISTANCE
vs. SIGNAL VOLTAGE
MAX14640 toc03
USB SWITCH ON-RESISTANCE
vs. SIGNAL VOLTAGE
-40
-15
10
35
60
TEMPERATURE (°C)
85
2.8 3.1 3.4 3.7 4.0 4.3 4.6 4.9 5.2 5.5
VCC (V)
Maxim Integrated │ 8
MAX14640–MAX14644/MAX14651
USB Host Adapter Emulators
Typical Operating Characteristics
(VCC = +5V, TA = +25NC, unless otherwise noted.)
LOGIC-INPUT THRESHOLD
vs. SUPPLY VOLTAGE
SUPPLY CURRENT vs. LOGIC LEVEL
ICC (µA)
50
40
30
20
10
0
VCC = 5.5V
GPIO VERSION
0.9
MAX14640 toc08
60
1.0
LOGIC-INPUT THRESHOLD (V)
MAX14640 toc07
70
CB_RISING
0.8
CB_FALLING
0.7
0.6
0.5
0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3
2.8 3.1 3.4 3.7 4.0 4.3 4.6 4.9 5.2 5.5
LOGIC LEVEL (V)
VCC (V)
AUTO DETECTION MODE
EYE DIAGRAM
MAX14640 toc10
DIFFERENTIAL SIGNAL (V)
MAX14640 toc09
MAX14640
FM TO AM2
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
DM
DP
2V/div
SDA
SCL
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
TIME (x 10*-9)s
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200ms/div
Maxim Integrated │ 9
MAX14640–MAX14644/MAX14651
USB Host Adapter Emulators
Pin Configurations
TOP VIEW
SDA
TDM
TDP
VCC
CB0
TDM
TDP
VCC
CB0
TDM
TDP
VCC
8
7
6
5
8
7
6
5
8
7
6
5
MAX14641
MAX14642
MAX14643
MAX14640
MAX14651
*EP/GND
MAX14644
*EP/GND
*EP/GND
1
2
3
4
1
2
3
4
1
2
3
4
INT
DM
DP
SCL
CEN
DM
DP
CB1
CEN
DM
DP
CB1
TDFN
(2mm x 2mm)
TDFN
(2mm x 2mm)
TDFN
(2mm x 2mm)
*CONNECT THE EXPOSED PAD (EP/GND) TO THE GROUND PLANE.
Pin Description
PIN
MAX14641/
NAME
MAX14640/
MAX14642/ MAX14644
MAX14651
MAX14643
1
—
—
1
—
—
FUNCTION
INT
Open-Drain Interrupt Output. INT asserts low when interrupt occurs.
CEN
nMOS Open-Drain Output. Pull up CEN to VCC by 10kΩ. CEN high enables the
current-limit switch and VBUS ON, and nMOS ON makes CEN low and the current-limit
switch OFF. When CB_ transitions from low to high or high to low, CEN is low for 1s
(typ).
—
—
1
CEN
pMOS Open-Drain Output. Pull down CEN to GND by 10kΩ. CEN low enables the
current-limit switch and VBUS ON, and pMOS ON makes CEN high and the currentlimit switch OFF. When CB_ transitions from low to high or high to low, CEN is high
for 1s (typ).
2
2
2
DM
USB Connector D- Connection
3
3
3
DP
USB Connector D+ Connection
4
—
—
SCL
I2C Serial-Clock Input
—
4
4
CB1
Switch Control Input Bit 1. See the Switch Control Input Truth tables (Tables 2, 3, and 4).
5
5
5
VCC
Power-Supply Input. Bypass VCC to GND with a 0.1µF ceramic capacitor as close
as possible to the device.
6
6
6
TDP
Host USB Transceiver D+ Connection
7
7
7
TDM
Host USB Transceiver D- Connection
8
—
—
SDA
I2C Serial-Data Input/Output
—
8
8
CB0
Switch Control Input Bit 0. See the Switch Control Input Truth tables (Tables 2, 3, and 4).
—
—
—
EP/
GND
Exposed Pad and Ground. The exposed pad is the ground connection for the
device. Connect EP/GND to the ground plane.
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Maxim Integrated │ 10
MAX14640–MAX14644/MAX14651
USB Host Adapter Emulators
Functional Diagram
VCC
CDP ENGINE
DEBOUNCE
MAX14640–MAX14644/
MAX14651
VDP_REF
CHARGING DOWNSTREAM PORT
EMULATION STATE MACHINE
VCC
VLGC
DEBOUNCE
VLGC
RP1
RDP_CDP
RP2
RM1
DEBOUNCE
IDP_SINK
RM2
RDM_CDP
VDM_SRC
REF1
DP
TDP
DM
TDM
DEBOUNCE
500kI
DP
POR
REF2
DEBOUNCE
DM1
CB0/
SDA**
CONTROL LOGIC
REF3
DEBOUNCE
DM2
CB1/
SCL**
REF4
DEBOUNCE
DM3
REF5
CEN/
CEN*/
INT**
GND
*CEN IS FOR MAX14644 ONLY.
**SDA, SCL, AND INT ARE FOR MAX14640/MAX14651 ONLY.
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Maxim Integrated │ 11
MAX14640–MAX14644/MAX14651
USB Host Adapter Emulators
Detailed Description
Resistor-Dividers
The MAX14640–MAX14644/MAX14651 adapter emulator devices have high-speed USB analog switches that
support USB hosts by identifying the USB port as a
charger when the USB host is in a low-power mode and
cannot enumerate USB devices. The devices feature low
4pF (typ) on-capacitance and low 4I (typ) on-resistance
when the USB switches are connected. DP and DM are
capable of handling signals between 0V and 5.5V over
the entire 3.0V–5.5V supply range.
The MAX14640/MAX14651 are controlled by an I2C
interface, while the MAX14641–MAX14644 are
controlled by the CB0 and CB1 logic inputs. The I2C
interface allows further customization over which mode
the MAX14640/MAX14651 operate in and can be used
to read back connection information.
Improvements over the MAX14600 USB detector
family include support for some smartphones that do not
connect after applying 0.6V in charging downstream
port (CDP) mode. The devices also support high-current
charging of Apple devices while in sleep mode.
The MAX14640–MAX14644/MAX14651 feature internal
resistor-divider networks on the data lines to provide
support for Apple devices. The resistor-divider is disconnected
while not in use to minimize the supply current. The
resistor-dividers are not connected in pass-through
mode. Table 1 summarizes the resistor values connected
to DP/DM in different charging modes.
Switch Control
Digital Controls
The MAX14641–MAX14644 feature two digital select
inputs, CB0 and CB1, for mode selection. Table 2,
Table 3, and Table 4 show how the CB1/CB0 inputs can
be used to enter autodetection charger mode (AM_),
pass-through mode (PM), forced charger mode (FM
and AP_), and pass-through mode with CDP emulation
(CM).
In CDP emulation mode, the peripheral device with CDP
detection capability draws charging current up to 1.5A
immediately without USB enumeration.
Table 1. DP/DM Resistor-Dividers
CHARGING MODE
DP PULLUP (kI)
DP PULLDOWN (kI)
DM PULLUP (kI)
DM PULLDOWN (kI)
AM1
75
49.9
43.2
49.9
AM2
43.2
49.9
75
49.9
Table 2. Digital Input State Table for the MAX14641
CB1
CB0
CHARGER/USB
MODE
STATUS
0
0
CHARGER
AM2
2A Autodetection Charger Mode for Apple Devices. Resistor-dividers are
connected to DP/DM.
1
0
CHARGER
AP1
Forced 1A Charger Mode for Apple Devices. Resistor-dividers are connected to
DP/DM.
0
1
USB
PM
USB Pass-Through Mode. DP/DM are connected to TDP/TDM.
1
1
USB
CM
USB Pass-Through Mode with CDP Emulation. Auto connects DP/DM to TDM/TDM
depending on CDP detection status.
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Maxim Integrated │ 12
MAX14640–MAX14644/MAX14651
USB Host Adapter Emulators
Table 3. Digital Input State Table for the MAX14642
CB1
CB0
CHARGER/USB
MODE
STATUS
2A Autodetection Charger Mode for Apple Devices. Resistor-dividers are
connected to DP/DM.
X
0
CHARGER
AM2
0
1
USB
PM
USB Pass-Through Mode. DP/DM are connected to TDP/TDM.
1
1
USB
CM
USB Pass-Through Mode with CDP Emulation. Auto connects DP/DM to TDM/TDM
depending on CDP detection status.
X = Don’t care.
Table 4. Digital Input State Table for the MAX14643/MAX14644
CB1
CB0
CHARGER/USB
MODE
STATUS
0
0
CHARGER
AM2
1
0
CHARGER
FM
Forced Dedicated Charger Mode. DP and DM are shorted.
0
1
USB
PM
USB Pass-Through Mode. DP/DM are connected to TDP/TDM.
1
1
USB
CM
USB Pass-Through Mode with CDP Emulation. Auto connects DP/DM to TDM/TDM
depending on CDP detection status.
2A Autodetection Charger Mode for Apple Devices. Resistor-dividers are
connected to DP/DM.
Table 5. Digital Input State Table for the MAX14640/MAX14651
MODE_SEL
CHARGER/USB
MODE
CHARGER
AM2
1
USB
PM
USB Pass-Through Mode. DP/DM are connected to TDP/TDM.
0
CHARGER
FM
Forced Dedicated Charger Mode. DP and DM are shorted.
1
1
USB
CM
USB Pass-Through Mode with CDP Emulation. Auto connects DP/DM to TDM/TDM
depending on CDP detection status.
1
0
0
CHARGER
AM1
1A Autodetection Charger Mode for Apple Devices. Resistor-dividers are
connected to DP/DM.
1
0
1
CHARGER
AP1
Forced 1A Charger Mode for Apple Devices. Resistor-dividers are connected to
DP/DM.
1
1
0
CHARGER
AP2
Forced 2A Charger Mode for Apple Devices. Resistor-dividers are connected to
DP/DM.
1
1
1
CHARGER
SS
[2]
[1]
[0]
0
0
0
0
0
0
1
0
STATUS
2A Autodetection Charger Mode for Apple Devices. Resistor-dividers are
connected to DP/DM.
Forced 2A Charger Mode for Samsung Galaxy Tablet
I2C Controls
Legacy D+/D- Detect
The MAX14640/MAX14651 mode is controlled by the
MODE_SEL[2:0] bits. Table 5 shows how these bits control
the device. In addition to being configurable in all modes
that the MAX14641–MAX14644 can enter, the MAX14640/
MAX14651 can be configured to be compatible with the
Apple and Samsung® Galaxy (SS mode) devices.
The MAX14640–MAX14644/MAX14651 support charging
devices that use a D+/D- short to indicate it is ready for
charging. This is done by monitoring the voltage at both
the DP and DM terminals and triggering when they are
both higher than their comparator thresholds.
Samsung is a registered trademark of Samsung Electronics, Co., Ltd.
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Maxim Integrated │ 13
MAX14640–MAX14644/MAX14651
USB Host Adapter Emulators
Auto Peripheral Reset
Pass-Through Modes
The MAX14641–MAX14644 feature an auto currentlimit switch control output. This feature resets the
peripheral connected to VBUS in the event the USB
host switches to or from standby mode. CEN or CEN
are pulsed for 1s* (typ) on the rising or falling edge of
CB0 or CB1 (Figure 5 and Figure 6).
If the MAX14640–MAX14644/MAX14651 are configured
in pass-through mode (PM), then TDP/TDM are always
connected to DP/DM and no resistor-dividers or power
sources are applied to DP/DM.
*Note: 2s (typ) for the MAX14644ETA+TCNE.
USB
TRANSCEIVER
TDM
TDP
TDM
TDP
VCC
0.1µF
GND
DP
D+
DM
D-
USB
CONNECTION
VBUS
MAX14644
150µF
VBUS
1kΩ
VCC
CURRENT-LIMIT
SWITCH
EN
+5V POWER
SUPPLY
CEN
10kΩ
PS EN
GND
CB0
PM/AM
CB1
CM/FM
SYSTEM CONTROL
Figure 5. MAX14644 Peripheral Reset Applications Diagram
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Maxim Integrated │ 14
MAX14640–MAX14644/MAX14651
USB
TRANSCEIVER
TDM
TDP
TDM
TDP
USB Host Adapter Emulators
VCC
0.1µF
GND
DP
D+
DM
D-
USB
CONNECTION
VBUS
MAX14641
MAX14642
MAX14643
150µF
VBUS
VCC
CURRENT-LIMIT
SWITCH
EN
1kΩ
+5V POWER
SUPPLY
33kΩ
CEN
PS EN
GND
CB0
PM/AM
CB1
CM/FM
SYSTEM CONTROL
Figure 6. MAX14641/MAX14642/MAX14643 Peripheral Reset Applications
Table 6. Forced Charging Modes
CHARGING MODE
DP PULLUP (kI)
DP PULLDOWN (kI)
DM PULLUP (kI)
DM PULLDOWN (kI)
FM
N/A
N/A
N/A
N/A
SS
30
10
30
10
AP1
75
49.9
43.2
49.9
AP2
43.2
49.9
75
49.9
Forced Charger Modes
The MAX14640–MAX14644/MAX14651 can be configured
in different forced dedicated charging port (DCP) modes;
VBUS is enabled and DP and DM are either shorted (FM)
or connected to resistor-dividers (all other modes). Table
6 summarizes the resistor-divider values in each forced
mode.
Automatic Detection with Remote Wake-Up
Support
The MAX14640–MAX14644/MAX14651 feature automatic
detection charger mode (AM1/AM2) for dedicated
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chargers and USB masters. In automatic detection
charger mode, the device monitors the voltages on DM
and DP with resistor-dividers connected to determine
the type of device attached.
If a USB-compliant device is connected, DP and DM
are shorted together to commence charging. Once the
charging device is removed, the short between DP and
DM is disconnected and the resistor-divider is applied.
A pulldown resistor on the shorted DP/DM node ensures
that a disconnect is detected.
Maxim Integrated │ 15
MAX14640–MAX14644/MAX14651
USB Host Adapter Emulators
USB Pass-Through Mode with CDP Emulation
The peripheral device equipped with CDP detection
capability can draw a charging current as defined in
USB battery charger specification 1.2 when the charging
host supports the CDP mode. This is a useful feature
since most host USB transceivers do not have the CDP
function. Table 7 summarizes the USB host power states.
The MAX14640–MAX14644/MAX14651 feature a passthrough mode with CDP emulation (CM). This is to support
the higher charging current capability during the passthrough mode in normal USB operation (S0 state).
Table 7. USB Host Power States
STATE
DESCRIPTION
S0
System On
S1
Power to the CPU(s) and RAM is Maintained. Devices that do not indicate that they must remain on, may be powered
down.
S2
CPU is Powered Off
S3
Standby (Suspend to Ram)—System Memory Context is Maintained. All other system context is lost.
S4
Hibernate—Platform Context is Maintained
S5
Soft Off
Register Map/Register Descriptions
REGISTER
ADDR
TYPE
POR
DeviceID
0x00
R
0x10*
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
Control1
0x01
R/W
0x87
FUO
FUO
FUO
FUO
FUO
FUO
FUO
FUO
Control2
0x02
R/W
0x50
LOW_PWR
FUO
FUO
FUO
FUO
FUO
DIS_CDP
FUO
Control3
0x03
R/W
0xE9
Control4
0x04
R/W
0x00
RFU
Control5
0x05
R/W
0x7B
INT_EN
INT
0x06
R
0x00
CDP_DEVi
BYPASS_CDPi
CDP_CNi
RFU
STATUS
0x07
R
0x00
CDP_DEVs
BYPASS_CDPs
CDP_CNs
RFU
MASK
0x08
R/W
0x00
CDP_DEVm BYPASS_CDPm
CDP_CNm
RFU
USB_XFRm
RWUm
CHIPID[3:0]
CEN_CNT[1:0]
CEN_DEL[2:0]
RFU
BIT1
BIT0
CHIPREV[3:0]
RFU
USB_SW[1:0]
MODE_SEL[2:0]
RFU
RFU
RFU
RFU
RFU
CEN_OUT
CEN_POL
FUO
RWU_DFT
RWU_LS
USB_XFRi
RWUi
CEN_TOG_STi
CEN_TOG_SPi
USB_XFRs
RWUs
RFU
CEN_TOG_SPs
CEN_TOG_STm CEN_TOG_SPm
FUO = Factory Use Only. Do not change from POR values.
RFU = Reserved for Future Use. Do not change from POR values.
*Applies to the MAX14640; the MAX14651 POR is 0x20.
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Maxim Integrated │ 16
MAX14640–MAX14644/MAX14651
USB Host Adapter Emulators
DeviceID Register
ADDRESS:
0x00
MODE:
Read Only
BIT
7
6
0
0
4
3
2
0
1
0
0
CHIPID[3:0]
NAME
RESET
CHIPID[3:0]
5
1
0
CHIPREV[3:0]
0
0
The CHIPID[3:0] bits show information about the version of the MAX14640/MAX14651.
CHIPREV[3:0] The CHIPREV[3:0] bits show information about the revision of the MAX14640/MAX14651 silicon.
Control1 Register
ADDRESS:
MODE:
BIT
0x01
7
Read/Write
6
5
4
3
2
1
0
NAME
FUO
FUO
FUO
FUO
FUO
FUO
FUO
FUO
RESET
1
0
0
0
0
1
1
1
FUO
Factory Use Only. Do not modify from reset values.
Control2 Register
ADDRESS:
0x02
MODE:
Read/Write
BIT
7
6
5
4
3
2
1
0
NAME
LOW_PWR
FUO
FUO
FUO
FUO
FUO
DIS_CDP
FUO
RESET
0
1
0
1
0
0
0
0
LOW_PWR
DIS_CDP
FUO
Low-Power Mode.
0 = MAX14640/MAX14651 is in normal operation.
1 = MAX14640/MAX14651 is in low-power mode. All circuitry other than the I2C interface is disabled.
Disable CDP Signal.
0 = CDP signaling enabled
1 = CDP signaling disabled
Factory Use Only. Do not modify from reset values.
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Maxim Integrated │ 17
MAX14640–MAX14644/MAX14651
USB Host Adapter Emulators
Control3 Register
ADDRESS:
0x03
MODE:
Read/Write
BIT
7
6
NAME
CEN_CNT[1:0]
RESET
1
1
5
4
3
2
CEN_DEL[2:0]
1
0
1
0
MODE_SEL[2:0]
1
0
CEN_CNT[1:0]
CEN State Control. Directly controls the CEN output independent of automatic cycling.
00 = CEN deasserted and CEN cycling disabled
01 = CEN cycling disabled between CB_ transitions during CDP modes and in AM mode
10 = CEN asserted
11 = CEN controlled by CDP/DCP/AM modes
CEN_DEL[2:0]
CEN Pulse Delay. Controls how long VBUS toggles last outside of AM mode.
000 = 125ms
001 = 250ms
010 = 350ms
011 = 500ms
100 = 750ms
101 = 1.0s
110 = 1.5s
111 = 2s
0
1
Operating Mode Control.
000 = AM2
001 = PM
010 = FM
MODE_SEL[2:0] 011 = CM
100 = AM1
101 = AP1
110 = AP2
111 = SS
Control4 Register
ADDRESS:
0x04
MODE:
Read/Write
BIT
7
6
5
4
3
2
1
0
NAME
RFU
RFU
RFU
RFU
RFU
RFU
RFU
RFU
RESET
0
0
0
0
0
0
0
0
RFU
Reserved for Future Use
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Maxim Integrated │ 18
MAX14640–MAX14644/MAX14651
USB Host Adapter Emulators
Control5 Register
ADDRESS:
0x05
MODE:
Read/Write
BIT
7
NAME
INT_EN
RESET
INT_EN
0
6
5
USB_SW[1:0]
1
1
4
3
2
1
0
CEN_OUT
CEN_POL
FUO
RWU_DFT
RWU_LS
1
1
0
1
1
Interrupt Enable.
0 = Interrupt disabled
1 = Interrupt enabled
USB DPDT Switch Control. When the USB switch is forced open (00) or closed (01), the state machine and CEN
output are disabled.
00 = DP/DM in high-Z
USB_SW[1:0]
01 = DP/DM connected to TDP/TDM
10 = DP/DM controlled by CDP/DCP/AM circuitry
11 = DP/DM controlled by CDP/DCP/AM circuitry
CEN_OUT
CEN/INT Function Select. Controls the function of the INT pin.
0 = INT output is used as interrupt
1 = INT output is used as CEN
CEN_POL
CEN/INT Polarity Select. Controls the polarity of the CEN/INT output.
0 = CEN/INT output is active-low CEN/INT
1 = CEN/INT output is active-high CEN/INT
FUO
RWU_DFT
RWU_LS
Factory Use Only. Do not modify from reset value.
Remote Wake-Up Default.
0 = Remote wake-up is off
1 = Remote wake-up is on
Remote Wake-Up for Low-Speed Only Select.
0 = Remote wake-up for both FS/HS and LS USB devices
1 = Remote wake-up for only LS devices
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Maxim Integrated │ 19
MAX14640–MAX14644/MAX14651
USB Host Adapter Emulators
Interrupt (INT) Register
ADDRESS:
0x06
MODE:
Read Only
BIT
7
6
5
4
3
2
NAME
CDP_DEVi
BYPASS_CDPi
CDP_CNi
RFU
USB_XFRi
RWUi
RESET
0
0
0
0
0
0
CDP_DEVi
1
0
CEN_TOG_STi CEN_TOG_SPi
0
0
CDP Device Detect Status Interrupt. CDP_DEVi is set when a CDP device is detected following the CDP
handshake procedure in CM mode.
0 = No interrupt
1 = Interrupt
Bypass CDP Running Status Interrupt. BYPASS_CDPi is set when the CDP handshake procedure is bypassed.
BYPASS_CDPi 0 = No interrupt
1 = Interrupt
CDP_CNi
RFU
CDP Connect Status Interrupt. CDP_CNi is set whenever a CDP connection check is in progress.
0 = No interrupt
1 = Interrupt
Reserved for Future Use
USB_XFRi
USB Session Interrupt. USB_XFRi is set when there is USB data detected in CM mode and DP/DM are
connected to TDP/TDM.
0 = No interrupt
1 = Interrupt
RWUi
Remote Wake-Up Status Interrupt. RWUi is set whenever a remote wake-up is performed in AM mode.
0 = No interrupt
1 = Interrupt
CEN Toggle Start Monitor Interrupt. CEN_TOG_STi is set at the start of a VBUS toggle, when VBUS is first
disabled.
CEN_TOG_STi
0 = No interrupt
1 = Interrupt
CEN Toggle Stop Monitor Interrupt. CEN_TOG_SPi is set at the end of a VBUS toggle, when VBUS is no longer
disabled.
CEN_TOG_SPi
0 = No interrupt
1 = Interrupt
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Maxim Integrated │ 20
MAX14640–MAX14644/MAX14651
USB Host Adapter Emulators
STATUS Register
ADDRESS:
0x07
MODE:
Read Only
BIT
7
6
5
4
3
2
1
0
NAME
CDP_DEVs
BYPASS_CDPs
CDP_CNs
RFU
USB_XFRs
RWUs
RFU
CEN_TOG_SPs
RESET
0
0
0
0
0
0
0
0
CDP_DEVs
CDP Device Detect Status. CDP_DEVs is set when a CDP device is detected following the CDP handshake
procedure in CM mode and cleared when it is disconnected.
0 = CDP device not detected
1 = CDP device detected
Bypass CDP Running Status. BYPASS_CDPs is set when the CDP handshake procedure is bypassed.
BYPASS_CDPs 0 = CDP signaling used
1 = CDP signaling bypassed
CDP_CNs
RFU
USB_XFRs
RWUs
CDP Connect Status. CDP_CNs is set while a CDP connection attempt is in progress.
0 = No CDP connection check in progress
1 = CDP connection check in progress
Reserved for Future Use
USB Session Status. USB_XFRs is set while there is USB data detected in CM mode and DP/DM are connected
to TDP/TDM.
0 = No USB session in progress
1 = USB session in progress
Remote Wake-Up Status. RWUs is set while a remote wake-up is in progress in AM mode.
0 = Not waiting for RWU
1 = Waiting for RWU
CEN Toggle Status. CEN_TOGs is cleared at the start of a VBUS toggle and set at the end of the VBUS toggle.
CEN_TOG_SPs 0 = VBUS toggle in progress
1 = VBUS toggle not in progress
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Maxim Integrated │ 21
MAX14640–MAX14644/MAX14651
USB Host Adapter Emulators
MASK Register
ADDRESS:
0x08
MODE:
Read/Write
BIT
NAME
7
5
CDP_DEVm BYPASS_CDPm CDP_CNm
0
RESET
CDP_DEVm
6
0
0
4
3
2
RFU
USB_XFRm
RWUm
0
0
0
1
0
CEN_TOG_STm CEN_TOG_SPm
0
0
CDP Device Detect Status Interrupt Mask. Prevents an interrupt from being generated in CDP_DEVi when
CDP_DEVs is set to 1.
0 = Masked
1 = Not masked
Bypass CDP Running Status Interrupt Mask. Prevents an interrupt from being generated in BYPASS_CDPi
when BYPASS_CDPs is set to 1.
BYPASS_CDPm
0 = Masked
1 = Not masked
CDP_CNm
RFU
CDP Connect Status Interrupt Mask. Prevents an interrupt from being generated in CDP_CNi when CDP_CNs
is set to 1.
0 = Masked
1 = Not masked
Reserved for Future Use
USB_XFRm
USB Session Interrupt Mask. Prevents an interrupt from being generated in USB_XFRi when USB_XFRs is set
to 1.
0 = Masked
1 = Not masked
RWUm
Remote Wake-Up Status Interrupt Mask. Prevents an interrupt from being generated in RWUi when RWUs is
set to 1.
0 = Masked
1 = Not masked
CEN Toggle Start Monitor Interrupt Mask. Prevents an interrupt from being generated in CEN_TOG_STi when
CEN_TOG_STs is set to 1.
CEN_TOG_STm
0 = Masked
1 = Not masked
CEN Toggle Stop Monitor Interrupt Mask. Prevents an interrupt from being generated in CEN_TOG_SPi when
CEN_TOG_SPs is set to 1.
CEN_TOG_SPm
0 = Masked
1 = Not masked
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Maxim Integrated │ 22
MAX14640–MAX14644/MAX14651
USB Host Adapter Emulators
Applications Information
Slave Address
I2C Interface
The MAX14640/MAX14651 contain an I2C-compatible
interface for data communication with a host controller
(SCL and SDA). The interface supports a clock frequency
of up to 400kHz. SCL and SDA require pullup resistors
that are connected to a positive supply.
The MAX14640 and MAX14651 are the I2C versions that
have different slave addresses (Table 8). Set the read/
write bit high to configure the MAX14640/MAX14651 to
read mode. Set the read/write bit low to configure the
MAX14640/MAX14651 to write mode. The address is the
first byte of information sent to the MAX14640/MAX14651
after the START condition.
START, STOP, and Repeated START Conditions
Bit Transfer
When writing to the MAX14640/MAX14651 using I2C,
the master sends a START condition (S) followed by the
MAX14640/MAX14651 I2C address. After the address,
the master sends the register address of the register that
is to be programmed. The master then ends communication
by issuing a STOP condition (P) to relinquish control of
the bus, or a Repeated START condition (Sr) to communicate
to another I2C slave. See Figure 7.
S
One data bit is transferred on the rising edge of each
SCL clock cycle. The data on SDA must remain stable
during the high period of the SCL clock pulse. Changes
in SDA while SCL is high and stable are considered
control signals (see the START, STOP, and Repeated
START Conditions section). Both SDA and SCL remain
high when the bus is not active.
Sr
P
SCL
SDA
Figure 7. I2C START, STOP, and Repeated START Conditions
Table 8. I2C Slave Addresses
ADDRESS FORMAT
MAX14640
HEX
BINARY
MAX14651
HEX
BINARY
7-Bit Slave ID
0x35
011 0101
0x15
001 0101
Write Address
0x6A
0110 1010
0x2A
0010 1010
Read Address
0x6B
0110 1011
0x2B
0010 1011
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Maxim Integrated │ 23
MAX14640–MAX14644/MAX14651
USB Host Adapter Emulators
Single-Byte Write
Burst Write
In this operation, the master sends an address and two
data bytes to the slave device (Figure 8). The following
procedure describes the single-byte write operation:
In this operation, the master sends an address and multiple data bytes to the slave device (Figure 9). The slave
device automatically increments the register address
after each data byte is sent, unless the register being
accessed is 0x00, in which case the register address
remains the same. The following procedure describes
the burst write operation:
1) The master sends a START condition.
2) The master sends the 7-bit slave address plus a write
bit (low).
3) The addressed slave asserts an ACK on the data line.
1) The master sends a START condition.
4) The master sends the 8-bit register address.
2) The master sends the 7-bit slave address plus a write
bit (low).
5) The slave asserts an ACK on the data line only if the
address is valid (NAK if not).
3) The addressed slave asserts an ACK on the data line.
6) The master sends eight data bits.
4) The master sends the 8-bit register address.
7) The slave asserts an ACK on the data line.
5) The slave asserts an ACK on the data line only if the
address is valid (NAK if not).
8) The master generates a STOP condition.
6) The master sends eight data bits.
7) The slave asserts an ACK on the data line.
8) Repeat 6 and 7 (N - 1) times.
9) The master generates a STOP condition.
WRITE SINGLE BYTE
S
DEVICE SLAVE ADDRESS - W
A
8 DATA BITS
A
FROM MASTER TO SLAVE
REGISTER ADDRESS
A
P
FROM SLAVE TO MASTER
Figure 8. Write-Byte Sequence
BURST WRITE
S
DEVICE SLAVE ADDRESS - W
A
REGISTER ADDRESS
A
8 DATA BITS - 1
A
8 DATA BITS - 2
A
8 DATA BITS - N
A
FROM MASTER TO SLAVE
P
FROM SLAVE TO MASTER
Figure 9. Burst Write Sequence
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Maxim Integrated │ 24
MAX14640–MAX14644/MAX14651
USB Host Adapter Emulators
Single-Byte Read
5) The slave asserts an ACK on the data line only if the
address is valid (NAK if not).
In this operation, the master sends an address plus two
data bytes and receives one data byte from the slave
device (Figure 10). The following procedure describes
the single-byte read operation:
6) The master sends a Repeated START condition.
7) The master sends the 7-bit slave address plus a read
bit (high).
1) The master sends a START condition.
8) The addressed slave asserts an ACK on the data
line.
2) The master sends the 7-bit slave address plus a
write bit (low).
9) The slave sends eight data bits.
3) The addressed slave asserts an ACK on the data
line.
10) The master asserts a NACK on the data line.
11) The master generates a STOP condition.
4) The master sends the 8-bit register address.
READ SINGLE BYTE
S
DEVICE SLAVE ADDRESS - W
A
REGISTER ADDRESS
A
Sr
DEVICE SLAVE ADDRESS - R
A
8 DATA BITS
NA
FROM MASTER TO SLAVE
P
FROM SLAVE TO MASTER
Figure 10. Read Byte Sequence
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Maxim Integrated │ 25
MAX14640–MAX14644/MAX14651
USB Host Adapter Emulators
Burst Read
6) The master sends a Repeated START condition.
In this operation, the master sends an address plus
two data bytes and receives multiple data bytes from
the slave device (Figure 11). The following procedure
describes the burst byte read operation:
7) The master sends the 7-bit slave address plus a read
bit (high).
8) The slave asserts an ACK on the data line.
1) The master sends a START condition.
9) The slave sends eight data bits.
2) The master sends the 7-bit slave address plus a
write bit (low).
10) The master asserts an ACK on the data line.
11) Repeat 9 and 10 (N - 2) times.
3) The addressed slave asserts an ACK on the data
line.
12) The slave sends the last eight data bits.
4) The master sends the 8-bit register address.
14) The master generates a STOP condition.
13) The master asserts a NACK on the data line.
5) The slave asserts an ACK on the data line only if the
address is valid (NAK if not).
BURST READ
S
DEVICE SLAVE ADDRESS - W
A
REGISTER ADDRESS
A
Sr
DEVICE SLAVE ADDRESS - R
A
8 DATA BITS - 1
A
8 DATA BITS - 2
A
8 DATA BITS - 3
A
8 DATA BITS - N
NA
FROM MASTER TO SLAVE
P
FROM SLAVE TO MASTER
Figure 11. Burst Read Sequence
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Maxim Integrated │ 26
MAX14640–MAX14644/MAX14651
USB Host Adapter Emulators
Acknowledge Bits
Data transfers are acknowledged with an acknowledge
bit (ACK) or a not-acknowledge bit (NACK). Both the
master and the MAX14640/MAX14651 generate ACK
bits. To generate an ACK, pull SDA low before the rising
edge of the ninth clock pulse, and hold it low during the
high period of the ninth clock pulse (see Figure 12). To
generate a NACK, leave SDA high before the rising edge
of the ninth clock pulse, and leave it high for the duration
of the ninth clock pulse. Monitoring for NACK bits allows
for detection of unsuccessful data transfers.
S
SCL
1
2
8
9
NOT ACKNOWLEDGE
SDA
ACKNOWLEDGE
Figure 12. Acknowledge
High-ESD Protection
RC
1MΩ
RD
1.5kΩ
CHARGE-CURRENTLIMIT RESISTOR
DISCHARGE
RESISTANCE
HIGHVOLTAGE
DC
SOURCE
CS
100pF
STORAGE
CAPACITOR
DEVICE
UNDER
TEST
Electrostatic Discharge (ESD)-protection structures are
incorporated on all pins to protect against electrostatic
discharges up to Q2kV Human Body Model (HBM)
encountered during handling and assembly. DP and DM
are further protected against ESD up to Q15kV (HBM)
without damage. The ESD structures withstand high ESD
both in normal operation and when the device is powered
down. After an ESD event, the MAX14640–MAX14644/
MAX14651 continue to function without latchup.
ESD Test Conditions
ESD performance depends on a variety of conditions.
Contact Maxim for a reliability report that documents test
setup, test methodology, and test results.
Figure 13. Human Body ESD Test Model
The MAX14640–MAX14644/MAX14651 require a 1FF
capacitor on both VCC to GND to guarantee full ESD
protection.
IPEAK (AMPS)
Ir
100%
90%
Human Body Model
PEAK-TO-PEAK RINGING
(NOT DRAWN TO SCALE)
Figure 13 shows the Human Body Model. Figure 14
shows the current waveform it generates when discharged
into a low impedance. This model consists of a 100pF
capacitor charged to the ESD voltage of interest that is
then discharged into the device through a 1.5kI resistor.
36.8%
10%
0
0
TIME
tRL
tDL
Figure 14. Human Body Current Waveform
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Maxim Integrated │ 27
MAX14640–MAX14644/MAX14651
USB Host Adapter Emulators
Typical Operating Circuit
LAPTOP
5V
SWITCHING
POWER SUPPLY
EXTERNAL
POWER
SUPPLY
OVERCURRENT
PROTECTOR
CEN
EMBEDDED
CONTROLLER
APPLE
DOCK
APPLE DOCK
CONNECTOR
USB A
Li+
BATTERY
VBUS
INT
INT
SDA
SDA
SCL
SCL
DM
DP
MAX14640
PHONE OR MP3
PLAYER
D-
USB A
D+ CONNECTOR
GND
iPod
OR
iPhone
USB A
MICRO-USB
CONNECTOR
MICRO B
LAPTOP CHIPSET
USB
TRANSCEIVER
TDM
TDP
Chip Information
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
MAX14640ETA+T
-40NC to +85NC
8 TDFN-EP*
MAX14641ETA+T
-40NC to +85NC
8 TDFN-EP*
MAX14642ETA+T
-40NC to +85NC
8 TDFN-EP*
MAX14643ETA+T
-40NC to +85NC
8 TDFN-EP*
MAX14644ETA+T
MAX14644ETA/V+
-40NC to +85NC
8 TDFN-EP*
-40NC to +85NC
8 TDFN-EP*
MAX14644ETA/V+T
-40NC to +85NC
8 TDFN-EP*
MAX14644ETA+TCNE
-40NC to +85NC
8 TDFN-EP*
MAX14651ETA+T
-40NC to +85NC
8 TDFN-EP*
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
T = Tape and reel.
/V Denotes an automotive-qualified part.
www.maximintegrated.com
PROCESS: BiCMOS
Package Information
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but the
drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
8 TDFN
T822+2
21-0168
90-0065
Maxim Integrated │ 28
MAX14640–MAX14644/MAX14651
USB Host Adapter Emulators
Revision History
REVISION
NUMBER
REVISION
DATE
PAGES
CHANGED
0
9/12
Initial release
1
4/13
Updated Electrical Characteristics table, updated Figure 4, removed TOCS 11 and
12, updated Pin Description and Register Map/Register Descriptions.
2
8/15
Updated Ordering Information
28
3
1/16
Added MAX14644ETA+TCNE to Ordering Information table
28
4
9/16
Removed future products from Ordering Information table
28
DESCRIPTION
—
3, 7, 9, 10, 16
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
© 2016 Maxim Integrated Products, Inc. │ 29
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