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MAX1473
315MHz/433MHz ASK Superheterodyne
Receiver with Extended Dynamic Range
General Description
The MAX1473 fully integrated low-power CMOS
superheterodyne receiver is ideal for receiving amplitudeshift-keyed (ASK) data in the 300MHz to 450MHz frequency
range. Its signal range is from -114dBm to 0dBm. With few
external components and a low-current power-down mode,
it is ideal for cost- and power-sensitive applications typical
in the automotive and consumer markets. The chip consists
of a low-noise amplifier (LNA), a fully differential imagerejection mixer, an on-chip phase-locked-loop (PLL) with
integrated voltage-controlled oscillator (VCO), a 10.7MHz IF
limiting amplifier stage with received-signal-strength indicator
(RSSI), and analog baseband data-recovery circuitry. The
MAX1473 also has a discrete one-step automatic gain
control (AGC) that drops the LNA gain by 35dB when the RF
input signal is greater than -57dBm.
The MAX1473 is available in 28-pin TSSOP and 32-pin
thin QFN packages. Both versions are specified for the
extended (-40°C to +85°C) temperature range.
Applications
●● Automotive Remote
Keyless Entry
●● Garage Door Openers
●● Remote Controls
●● Wireless Sensors
●● Security Systems
●● Home Automation
●● Local Telemetry
Systems
Features
●● Optimized for 315MHz or 433MHz ISM Band
●● Operates from Single 3.3V or 5.0V Supplies
●● High Dynamic Range with On-Chip AGC
●● Selectable Image-Rejection Center Frequency
●● Selectable x64 or x32 fLO/fXTAL Ratio
●● Low 5.2mA Operating Supply Current
●● < 2.5μA Low-Current, Power-Down Mode for Efficient
Power Cycling
●● 250μs Startup Time
●● Built-In 50dB RF Image Rejection
●● Receive Sensitivity of -114dBm
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
MAX1473EUI+
-40°C to +85°C
28 TSSOP
MAX1473ETJ+
-40°C to +85°C
32 Thin QFN-EP*
+ Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
Functional Diagram and Typical Application Circuit appear
at end of data sheet.
LNASRC 4
AGND 5
LNAOUT 6
25 DATAOUT
MAX1473
XTAL1
XTAL2
PWRDN
PDOUT
N.C.
28
27
26
25
N.C.
1
24
DATAOUT
24 VDD5
AGND
2
23
VDD5
23 DSP
LNAOUT
3
22
DSP
MAX1473
18
DSN
IRSEL 11
18 IFIN2
IRSEL
8
17
DFO
MIXOUT 12
17 IFIN1
DGND 13
16 XTALSEL
DVDD 14
15 AGCDIS
16
7
IFIN2
AGND
15
19 DFO
IFIN1
OPP
AGND 10
14
19
XTALSEL
6
13
MIXIN2
N.C.
20 DSN
12
DFFB
MIXIN2 9
AGCDIS
20
11
N.C.
5
DVDD
21
MIXIN1
9
4
21 OPP
10
AVDD
MIXIN1 8
DGND
22 DFFB
MIXOUT
AVDD 7
TSSOP
19-2748; Rev 7; 1/19
+
AVDD
26 PDOUT
29
27 PWRDN
LNAIN 3
LNAIN
28 XTAL2
AVDD 2
30
+
LNASRC
XTAL1 1
31
TOP VIEW
32
Pin Configurations
THIN QFN
MAX1473
315MHz/433MHz ASK Superheterodyne
Receiver with Extended Dynamic Range
Absolute Maximum Ratings
Continuous Power Dissipation (TA = +70°C)
28-Pin TSSOP (derate 12.8mW/°C above +70°C).. 1025.6mW
32-Pin Thin QFN (derate 21.3mW/°C
above +70°C)..........................................................1702.1mW
Operating Temperature Ranges
MAX1473E__...................................................... -40°C to +85°C
Storage Temperature Range............................. -60°C to +150°C
Lead Temperature (soldering 10s)................................... +300°C
Soldering Temperature (reflow)........................................ +260°C
VDD5 to AGND......................................................-0.3V to +6.0V
AVDD to AGND.....................................................-0.3V to +4.0V
DVDD to DGND.....................................................-0.3V to +4.0V
AGND to DGND....................................................-0.1V to +0.1V
IRSEL, DATAOUT, XTALSEL, AGCDIS,
PWRDN to AGND.................................... -0.3V to (VDD5 + 0.3V)
All Other Pins to AGND........................... -0.3V to (AVDD + 0.3V)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
DC Electrical Characteristics (3.3V Operation)
(Typical Application Circuit, AVDD = DVDD = VDD5 = 3.0V to 3.6V, no RF signal applied, TA = -40°C to +85°C, unless otherwise noted.
Typical values are at VDD = 3.3V and TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
Supply Voltage
VDD
3.3V nominal supply
Supply Current
IDD
V PWRDN = VDD5
Shutdown Supply Current
IPWRDN
Input Voltage Low
VIL
Input Voltage High
VIH
Input Logic Current High
IIH
V PWRDN = 0V,
VXTALSEL = 0V
MIN
TYP
MAX
UNITS
3.0
3.3
3.6
V
fRF = 315MHz
5.2
6.23
fRF = 433MHz
5.8
6.88
fRF = 315MHz
1.6
fRF = 433MHz
2.5
0.4
AVDD - 0.4
fRF = 375MHz, VIRSEL = AVDD/2
VOL
DATAOUT Voltage Output High
VOH
www.maximintegrated.com
RL = 5kΩ
V
µA
AVDD - 0.4
1.1
fRF = 315MHz, VIRSEL = 0V
DATAOUT Voltage Output Low
µA
V
10
fRF = 433MHz, VIRSEL = AVDD
Image Reject Select (Note 2)
5.3
mA
AVDD - 1.5
V
0.4
0.4
VDD5 - 0.4
V
V
Maxim Integrated │ 2
MAX1473
315MHz/433MHz ASK Superheterodyne
Receiver with Extended Dynamic Range
Electrical Characteristics (5V Operation)
(Typical Application Circuit, VDD5 = 4.5V to 5.5V, AVDD = DVDD = ~3.2V, no RF signal applied, TA = -40°C to +85°C, unless otherwise
noted. Typical values are at VDD = 5.0V and TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
Supply Voltage
VDD
5.0V nominal supply
Supply Current
IDD
V PWRDN = VDD5
IPWRDN
V PWRDN = 0V,
VXTALSEL = 0V
Shutdown Supply Current
Input Voltage Low
VIL
Input Voltage High
VIH
Input Logic Current High
IIH
MIN
TYP
MAX
UNITS
4.5
5.0
5.5
V
fRF = 315MHz
5.2
6.04
fRF = 433MHz
5.7
6.76
fRF = 315MHz
2.3
fRF = 433MHz
2.8
0.4
AVDD - 0.4
fRF = 375MHz, VIRSEL = AVDD/2
VOL
AVDD - 0.4
1.1
AVDD - 1.5
DATAOUT Voltage Output High
VOH
V
0.4
0.4
RL = 5kΩ
V
µA
fRF = 315MHz, VIRSEL = 0V
DATAOUT Voltage Output Low
µA
V
10
fRF = 433MHz, VIRSEL = AVDD
Image Reject Select (Note 2)
6.2
mA
VDD5 - 0.4
V
V
AC Electrical Characteristics
(Typical Application Circuit, AVDD = DVDD = VDD5 = 3.0V to 3.6V, all RF inputs are referenced to 50Ω, fRF = 315MHz, TA = -40°C to
+85°C, unless otherwise noted. Typical values are at VDD = 3.3V and TA = +25°C.) (Note 1).
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
GENERAL CHARACTERISTICS
Startup Time
tON
Receiver Input Frequency
fRF
Time for valid signal detection after
V PWRDN = VOH
µs
300
Maximum Receiver Input Level
PRFIN_MAX Modulation depth > 18dB
Sensitivity (Note 3)
PRFIN_MIN
AGC Hysteresis
250
Peak power level
LNA gain from low to high
450
MHz
0
dBm
-114
dBm
8
dB
150
ms
16
dB
LNA IN HIGH-GAIN MODE
Power Gain
Input Impedance (Note 4)
1dB Compression Point
Input-Referred 3rd-Order Intercept
www.maximintegrated.com
ZIN_LNA
Normalized to 50Ω
fRF = 433MHz
1 - j3.4
fRF = 375MHz
1 - j3.9
fRF = 315MHz
1 - j4.7
P1dBLNA
-22
dBm
IIP3LNA
-12
dBm
Maxim Integrated │ 3
MAX1473
315MHz/433MHz ASK Superheterodyne
Receiver with Extended Dynamic Range
AC Electrical Characteristics (continued)
(Typical Application Circuit, AVDD = DVDD = VDD5 = 3.0V to 3.6V, all RF inputs are referenced to 50Ω, fRF = 315MHz, TA = -40°C to
+85°C, unless otherwise noted. Typical values are at VDD = 3.3V and TA = +25°C.) (Note 1).
PARAMETER
SYMBOL
CONDITIONS
LO Signal Feedthrough to Antenna
Noise Figure
NFLNA
MIN
TYP
MAX
UNITS
-80
dBm
2
dB
LNA IN LOW-GAIN MODE
Input Impedance (Note 4)
1dB Compression Point
Input-Referred 3rd-Order Intercept
ZIN_LNA
Normalized to 50Ω
fRF = 433MHz
1 - j3.4
fRF = 375MHz
1 - j3.9
fRF = 315MHz
1 - j4.7
P1dBLNA
-10
dBm
IIP3LNA
-7
dBm
-80
dBm
2
dB
0
dB
35
dB
LO Signal Feedthrough to Antenna
Noise Figure
NFLNA
Power Gain
Voltage Gain Reduction
AGC enabled (depends on tank Q)
MIXER
Input-Referred 3rd-Order Intercept
Output Impedance
Noise Figure
IIP3MIX
-18
dBm
ZOUT_MIX
330
Ω
NFMIX
16
dB
Image Rejection
(not Including LNA Tank)
fRF = 433MHz, VIRSEL = AVDD
42
fRF = 375MHz, VIRSEL = AVDD/2
44
fRF = 315MHz, VIRSEL = 0V
44
Conversion Gain
330Ω IF filter load
13
dB
dB
INTERMEDIATE FREQUENCY (IF)
Input Impedance
ZIN_IF
330
Ω
10.7
MHz
3dB Bandwidth
20
MHz
RSSI Linearity
±0.5
dB
80
dB
Operating Frequency
fIF
Bandpass response
RSSI Dynamic Range
RSSI Level
PRFIN < -120dBm
1.15
PRFIN > 0dBm, AGC enabled
2.35
RSSI Gain
AGC Threshold
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14.2
LNA gain from low to high
1.45
LNA gain from high to low
2.05
V
mV/dB
V
Maxim Integrated │ 4
MAX1473
315MHz/433MHz ASK Superheterodyne
Receiver with Extended Dynamic Range
AC Electrical Characteristics (continued)
(Typical Application Circuit, AVDD = DVDD = VDD5 = 3.0V to 3.6V, all RF inputs are referenced to 50Ω, fRF = 315MHz, TA = -40°C to
+85°C, unless otherwise noted. Typical values are at VDD = 3.3V and TA = +25°C.) (Note 1).
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DATA FILTER
Maximum Bandwidth
BWDF
100
kHz
BWCMP
100
kHz
DATA SLICER
Comparator Bandwidth
Output High Voltage
VDD5
V
Output Low Voltage
0
V
CRYSTAL OSCILLATOR
fRF = 433MHz
Crystal Frequency (Note 5)
fXTAL
fRF = 315MHz
VXTALSEL = 0V
6.6128
VXTALSEL = AVDD
13.2256
VXTALSEL = 0V
4.7547
VXTALSEL = AVDD
9.5094
Crystal Tolerance
Input Capacitance
From each pin to ground
MHz
MHz
50
ppm
6.2
pF
Recommended Crystal Load
Capacitance
CLOAD
3
pF
Maximum Crystal Load
Capacitance
CLOAD
10
pF
Note 1: Note 1: 100% tested at TA = +25°C. Guaranteed by design and characterization over temperature.
Note 2: IRSEL is internally set to 375MHz IR mode. It can be left open when the 375MHz image rejection setting is desired. A 1nF
capacitor is recommended in noisy environments.
Note 3: BER = 2 x 10-3, Manchester encoded, data rate = 4kbps, IF bandwidth = 280kHz.
Note 4: Input impedance is measured at the LNAIN pin. Note that the impedance includes the 15nH inductive degeneration connected from the LNA source to ground. The equivalent input circuit is 50Ω in series with 2.2pF.
Note 5: Crystal oscillator frequency for other RF carrier frequency within the 300MHz to 450MHz range is (fRF - 10.7MHz)/64 for
XTALSEL = 0V, and (fRF - 10.7MHz)/32 for XTALSEL = AVDD.
www.maximintegrated.com
Maxim Integrated │ 5
MAX1473
315MHz/433MHz ASK Superheterodyne
Receiver with Extended Dynamic Range
Typical Operating Characteristics
(Typical Application Circuit, VDD = 3.3V, fRF = 315MHz, TA = +25°C, unless otherwise noted.)
SUPPLY CURRENT
vs. RF FREQUENCY
5.3
+25°C
5.1
MAX1473 toc02
+85°C
+25°C
3.3
3.4
3.5
3.6
250
400
450
SENSITIVITY vs. TEMPERATURE
RSSI vs. RF INPUT POWER
2.4
2.2
RSSI (V)
fRF = 433MHz
-108
-110
-112
500
VAGCDIS = VDD
1.8
VAGCDIS = 0V
1.6
0.01
20
40
60
1.0
80 100 120
-140 -120 -100
TEMPERATURE (°C)
10
50dB IMAGE
REJECTION
0
LOWER
SIDEBAND
-10
FROM RFIN TO
MIXOUT
fRF = 315MHz
-20
0
5
10
15
20
IF FREQUENCY (MHz)
www.maximintegrated.com
-60
-40
-20
2.0
1.5
1.8
0.5
1.6
1.0
0
25
50
45
40
fRF = 375MHz
fRF = 315MHz
35
fRF = 433MHz
30
30
-0.5
DELTA
-1.5
RSSI
-90
280
330
-70
-2.5
-50
-30
-10
10
IMAGE REJECTION
vs. TEMPERATURE
45
fRF = 315MHz
45
44
44
43
fRF = 375MHz
43
42
fRF = 433MHz
42
41
380
430
RF FREQUENCY (MHz)
-3.5
IF INPUT POWER (dBm)
MAX1473 toc08
20
-80
IMAGE REJECTION
vs. RF FREQUENCY
55
IMAGE REJECTION (dB)
UPPER
SIDEBAND
MAX1473 toc07
30
3.5
2.5
RF INPUT POWER (dBm)
SYSTEM GAIN vs. FREQUENCY
MAX1473 toc06
2.2
1.2
IMAGE REJECTION (dB)
0
-114
1.4
1.2
-116
-121 -120 -119 -118 -117 -116 -115
AVERAGE INPUT POWER (dBm)
2.4
1.4
fRF = 315MHz
-40 -20
0.1
RSSI AND DELTA
vs. IF INPUT POWER
IF BANDWIDTH = 280kHz
2.0
-114
SYSTEM GAIN (dB)
350
RF FREQUENCY (MHz)
-106
-30
300
SUPPLY VOLTAGE (V)
PEAK RF INPUT POWER
0.2% BER
IF BANDWIDTH = 280kHz
-104
fRF = 315MHz
480
41
-40
-15
10
35
60
85
TEMPERATURE (°C)
Maxim Integrated │ 6
DELTA (dB)
3.2
1
MAX1473 toc09
3.1
10
-40°C
4.5
MAX1473 toc04
3.0
-102
SENSITIVITY (dBm)
5.5
-40°C
-100
-118
6.0
5.0
5.0
4.9
+105°C
fRF = 433MHz
RSSI (V)
5.2
6.5
BIT-ERROR RATE (%)
+85°C
100
MAX1473 toc05
SUPPLY CURRENT (mA)
5.4
SUPPLY CURRENT (mA)
+105°C
5.5
7.0
MAX1473 toc01
5.6
BIT-ERROR RATE
vs. AVERAGE RF INPUT POWER
MAX1473 toc03
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX1473
315MHz/433MHz ASK Superheterodyne
Receiver with Extended Dynamic Range
Typical Operating Characteristics (continued)
(Typical Application Circuit, VDD = 3.3V, fRF = 315MHz, TA = +25°C, unless otherwise noted.)
MAX1473 toc10
30
0
-5
-10
S11 MAGNITUDE-LOG PLOT OF RFIN
20
10
MAGNITUDE (dB)
NORMALIZED IF GAIN (dB)
5
S11 SMITH PLOT OF RFIN
MAX1473 toc12
MAX1473 toc11
NORMALIZED IF GAIN
vs. IF FREQUENCY
600MHz
0
-10
-20
100MHz
-30
-40
-15
-50
-20
-70
315MHz
-34dB
-60
RF FREQUENCY (MHz)
REGULATOR VOLTAGE
vs. REGULATOR CURRENT
PHASE NOISE
vs. OFFSET FREQUENCY
+25°C
+85°C
+105°C
2.7
2.6
VDD = 5.0V
5
15
25
35
REGULATOR CURRENT (mA)
www.maximintegrated.com
45
fRF = 315MHz
-20
PHASE NOISE
vs. OFFSET FREQUENCY
0
-40
-60
-80
-100
fRF = 433MHz
-20
PHASE NOISE (dBc/Hz)
-40°C
2.8
2.5
0
PHASE NOISE (dBc/Hz)
3.0
2.9
10 109 208 307 406 505 604 703 802 901 1000
MAX1473 toc15
100
MAX1473 toc13
REGULATOR VOLTAGE (V)
3.1
10
IF FREQUENCY (MHz)
MAX1473 toc14
1
-40
-60
-80
-100
-120
-120
-140
1.E-05 1.E-04 1.E-03 1.E-02 1.E-01 1.E+00 1.E+01
-140
1.E-05 1.E-04 1.E-03 1.E-02 1.E-01 1.E+00 1.E+01
OFFSET FREQUENCY (MHz)
OFFSET FREQUENCY (MHz)
Maxim Integrated │ 7
MAX1473
315MHz/433MHz ASK Superheterodyne
Receiver with Extended Dynamic Range
Pin Description
PIN
TSSOP
TQFN
1
29
NAME
FUNCTION
XTAL1
1st Crystal Input. (See the Phase-Locked Loop section.)
Positive Analog Supply Voltage. For +5V operation, pin 2 (TSSOP package) is the output of an onchip +3.2V low-dropout regulator and should be bypassed to AGND with a 0.1µF capacitor as close
as possible to the pin. Pin 7 must be externally connected to the supply from pin 2 and bypassed to
AGND with a 0.01µF capacitor as close as possible to the pin (see the Voltage Regulator section and
the Typical Application Circuit).
2, 7
4, 30
AVDD
3
31
LNAIN
4
32
LNASRC
5
2
AGND
6
3
LNAOUT
8
5
MIXIN1
9
6
MIXIN2
10
7
AGND
Analog Ground
11
8
IRSEL
Image Rejection Select Pin. Set VIRSEL = 0V to center image rejection at 315MHz. Leave IRSEL
unconnected to center image rejection at 375MHz. Set VIRSEL = AVDD to center image rejection at 433MHz.
Input logic level based on AVDD, ~3.2V supply.
12
9
MIXOUT
13
10
DGND
14
11
15
12
16
14
17
15
18
16
19
17
20
18
DSN
Negative Data Slicer Input
21
19
OPP
Noninverting Op-Amp Input for the Sallen-Key Data Filter
22
20
DFFB
Data Filter Feedback Node. Input for the feedback of the Sallen-Key data filter.
23
22
DSP
Positive Data Slicer Input
24
23
VDD5
25
24
26
26
27
28
—
—
Low-Noise Amplifier Input. (See the Low-Noise Amplifier section.)
Low-Noise Amplifier Source for External Inductive Degeneration. Connect inductor to ground to set
LNA input impedance. (See the Low-Noise Amplifier section.)
Analog Ground
Low-Noise Amplifier Output. Connect to mixer through an LC tank filter. (See the Low-Noise Amplifier
section.)
1st Differential Mixer Input. Connect through a 100pF capacitor to LC tank filter from LNAOUT.
2nd Differential Mixer Input. Connect through a 100pF capacitor to AVDD side of the LC tank.
330Ω Mixer Output. Connect to the input of the 10.7MHz bandpass filter.
Digital Ground
Positive Digital Supply Voltage. Connect to both of the AVDD pins. Bypass to DGND with a 0.01µF
DVDD
capacitor as close as possible to the pin (see the Typical Application Circuit).
AGCDIS AGC Control Pin. Pull high to disable AGC. Input logic level based on VDD5 voltage.
Crystal Divider Ratio Select Pin. Drive XTALSEL low to select divider ratio of 64, or drive XTALSEL
XTALSEL
high to select divider ratio of 32. Input logic level based on AVDD, ~3.2V supply.
1st Differential Intermediate Frequency Limiter Amplifier Input. Decouple to AGND with a 1500pF
IFIN1
capacitor.
2nd Differential Intermediate Frequency Limiter Amplifier Input. Connect to the output of a 10.7MHz
IFIN2
bandpass filter.
DFO
Data Filter Output
+5V Supply Voltage. Bypass to AGND with a 0.01µF capacitor as close as possible to the pin. For
+5V operation, VDD5 is the input to an on-chip voltage regulator whose +3.2V output appears at the
pin 2 AVDD pin. (See the Voltage Regulator section and the Typical Application Circuit.)
DATAOUT Digital Baseband Data Output. Output logic level based on VDD5 voltage.
PDOUT
Peak Detector Output
27
PWRDN
Power-Down Select Input. Drive this pin with a logic high to power on the IC.
Input logic level based on VDD5 voltage.
28
1, 13,
21, 25
XTAL2
—
EP
N.C.
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2nd Crystal Input
No Connection
Exposed Pad (TQFN Only). Connect EP to GND.
Maxim Integrated │ 8
MAX1473
Detailed Description
The MAX1473 CMOS superheterodyne receiver and a few
external components provide the complete receive chain
from the antenna to the digital output data. Depending on
signal power and component selection, data rates as high
as 100kbps can be achieved. The MAX1473 is designed
to receive binary ASK data modulated in the 300MHz
to 450MHz frequency range. ASK modulation uses a
difference in amplitude of the carrier to represent logic 0
and logic 1 data.
Voltage Regulator
For operation with a single +3.0V to +3.6V supply voltage,
connect AVDD, DVDD, and VDD5 to the supply voltage.
For operation with a single +4.5V to +5.5V supply voltage,
connect VDD5 to the supply voltage. An on-chip voltage
regulator drives one of the AVDD pins to approximately
+3.2V. For proper operation, DVDD and both the AVDD
pins must be connected together. Bypass VDD5, DVDD,
and the pin 7 AVDD pin to AGND with 0.01μF capacitors,
and the pin 2 AVDD pin to AGND with a 0.1μF capacitor,
all placed as close as possible to the pins.
Low-Noise Amplifier
The LNA is an NMOS cascode amplifier with off-chip
inductive degeneration that achieves approximately 16dB
of power gain with a 2.0dB noise figure and an IIP3 of
-12dBm. The gain and noise figure are dependent on both
the antenna matching network at the LNA input and the LC
tank network between the LNA output and the mixer inputs.
The off-chip inductive degeneration is achieved by
connecting an inductor from LNASRC to AGND. This
inductor sets the real part of the input impedance at
LNAIN, allowing for a more flexible input impedance
match, such as a typical PCB trace antenna. A nominal
value for this inductor with a 50Ω input impedance is
15nH, but is affected by PCB trace. See the Typical
Operating Characteristics for the relationship between the
inductance and the LNA input impedance.
The AGC circuit monitors the RSSI output. When the
RSSI output reaches 2.05V, which corresponds to an RF
input level of approximately -57dBm, the AGC switches
on the LNA gain reduction resistor. The resistor reduces
the LNA gain by 35dB, thereby reducing the RSSI output
by about 500mV. The LNA resumes high-gain mode when
the RSSI level drops back below 1.45V (approximately
-65dBm at RF input) for 150ms. The AGC has a hysteresis
of ~8dB. With the AGC function, the MAX1473 can reliably
produce an ASK output for RF input levels up to 0dBm
with a modulation depth of 18dB.
www.maximintegrated.com
315MHz/433MHz ASK Superheterodyne
Receiver with Extended Dynamic Range
The LC tank filter connected to LNAOUT comprises L3
and C2 (see the Typical Application Circuit). Select L3 and
C2 to resonate at the desired RF input frequency. The
resonant frequency is given by:
f=
1
2 π L TOTAL × C TOTAL
where:
LTOTAL = L3 + LPARASITICS
CTOTAL = C2 + CPARASITICS
LPARASITICS and CPARASITICS include inductance and
capacitance of the PCB traces, package pins, mixer input
impedance, LNA output impedance, etc. These parasitics
at high frequencies cannot be ignored, and can have a
dramatic effect on the tank filter center frequency. Lab
experimentation should be done to optimize the center
frequency of the tank.
Mixer
A unique feature of the MAX1473 is the integrated image
rejection of the mixer. This device eliminates the need
for a costly front-end SAW filter for most applications.
Advantages of not using a SAW filter are increased
sensitivity, simplified antenna matching, less board space,
and lower cost.
The mixer cell is a pair of double balanced mixers that
perform an IQ downconversion of the RF input to the
10.7MHz IF from a low-side injected LO (i.e., fLO = fRF
- fIF). The image-rejection circuit then combines these
signals to achieve a minimum 45dB of image rejection
over the full temperature range. Low-side injection is
required due to the on-chip image rejection architecture.
The IF output is driven by a source-follower biased to
create a driving impedance of 330Ω; this provides a good
match to the off-chip 330Ω ceramic IF filter. The voltage
conversion gain is approximately 13dB when the mixer is
driving a 330Ω load.
The IRSEL pin is a logic input that selects one of the three
possible image-rejection frequencies. The input logic level
is based on the AVDD, supply voltage generated by the
on-chip voltage regulator (~3.2V). When VIRSEL = 0V, the
image rejection is tuned to 315MHz. VIRSEL = AVDD/2
tunes the image rejection to 375MHz, and when VIRSEL =
AVDD, the image rejection is tuned to 433MHz. The IRSEL
pin is internally set to AVDD/2 (image rejection at 375MHz)
when it is left unconnected, thereby eliminating the need
for an external AVDD/2 voltage.
Maxim Integrated │ 9
MAX1473
315MHz/433MHz ASK Superheterodyne
Receiver with Extended Dynamic Range
Phase-Locked Loop
The PLL block contains a phase detector, charge pump/
integrated loop filter, VCO, asynchronous 64x clock
divider, and crystal oscillator driver. Besides the crystal,
this PLL does not require any external components.
The VCO generates a low-side local oscillator (LO). The
relationship between the RF, IF, and crystal reference
frequencies is given by:
where:
fXTAL = (fRF - fIF)/(32 x M)
M = 1 (VXTALSEL = AVDD) or 2 (VXTALSEL = 0V)
causing the receiver to be tuned to 315.1MHz rather than
315.0MHz, an error of about 100kHz, or 320ppm.
In actuality, the oscillator pulls every crystal. The crystal’s
natural frequency is really below its specified frequency,
but when loaded with the specified load capacitance, the
crystal is pulled and oscillates at its specified frequency.
This pulling is already accounted for in the specification of
the load capacitance.
Additional pulling can be calculated if the electrical
parameters of the crystal are known. The frequency
pulling is given by:
Cm
1
1
To allow the smallest possible=
IF bandwidth (for best
fp
2 C case + C load C case + C spec
sensitivity), the tolerance of the reference must be
minimized.
where:
Intermediate Frequency/RSSI
The IF section presents a differential 330Ω load to
provide matching for the off-chip ceramic filter. The six
internal AC-coupled limiting amplifiers produce an overall
gain of approximately 65dB, with a bandpass filter-type
response centered near the 10.7MHz IF frequency with
a 3dB bandwidth of approximately 11.5MHz. The RSSI
circuit demodulates the IF by producing a DC output
proportional to the log of the IF signal level, with a slope
of approximately 14.2mV/dB (see the Typical Operating
Characteristics).
The AGC circuit monitors the RSSI output. When the
RSSI output reaches 2.05V, which corresponds to an RF
input level of approximately -57dBm, the AGC switches
on the LNA gain reduction resistor. The resistor reduces
the LNA gain by 35dB, thereby reducing the RSSI output
by about 500mV. The LNA resumes high-gain mode when
the RSSI level drops back below 1.45V (approximately
-65dBm at RF input) for 150ms. The AGC has a hysteresis
of ~8dB. With the AGC function, the MAX1473 can reliably
produce an ASK output for RF input levels up to 0dBm
with modulation depth of 18dB.
Applications Information
Crystal Oscillator
The XTAL oscillator in the MAX1473 is designed to
present a capacitance of approximately 3pF between the
XTAL1 and XTAL2. If a crystal designed to oscillate with
a different load capacitance is used, the crystal is pulled
away from its stated operating frequency, introducing an
error in the reference frequency. Crystals designed to
operate with higher differential load capacitance always
pull the reference frequency higher. For example, a
4.7547MHz crystal designed to operate with a 10pF load
capacitance oscillates at 4.7563MHz with the MAX1473,
www.maximintegrated.com
× 10 6
fp is the amount the crystal frequency pulled in ppm.
Cm is the motional capacitance of the crystal.
Ccase is the case capacitance.
Cspec is the specified load capacitance.
Cload is the actual load capacitance.
When the crystal is loaded as specified, i.e., Cload =
Cspec, the frequency pulling equals zero.
Data Filter
The data filter is implemented as a 2nd-order lowpass
Sallen-Key filter. The pole locations are set by the
combination of two on-chip resistors and two external
capacitors. Adjusting the value of the external capacitors
changes the corner frequency to optimize for different
data rates. The corner frequency should be set to
approximately 1.5 times the fastest expected data rate
from the transmitter. Keeping the corner frequency near
the data rate rejects any noise at higher frequencies,
resulting in an increase in receiver sensitivity.
The configuration shown in Figure 1 can create a
Butterworth or Bessel response. The Butterworth filter
offers a very flat amplitude response in the passband and
a rolloff rate of 40dB/decade for the two-pole filter. The
Bessel filter has a linear phase response, which works well
for filtering digital data. To calculate the value of C7 and
C6, use the following equations along with the coefficients
in Table 1:
Table 1. Coefficents to Calculate C7 and C6
FILTER TYPE
a
b
Butterworth (Q = 0.707)
1.414
1.000
Bessel (Q = 0.577)
1.3617
0.618
Maxim Integrated │ 10
MAX1473
315MHz/433MHz ASK Superheterodyne
Receiver with Extended Dynamic Range
C7 =
b
a (100k ) (π) (f c )
C6 =
a
4(100k ) (π) (f c )
Data Slicer
where fC is the desired 3dB corner frequency.
For example, choose a Butterworth filter response with a
corner frequency of 5kHz:
C7
1.000
(1.414) (100kΩ) (3.14) (5kHz)
≈ 450pF
Choosing standard capacitor values changes C7 to 470pF
and C6 to 220pF, as shown in the Typical Application
Circuit.
MAX1473
RSSI
RDF1
100kΩ
RDF2
100kΩ
C6
The suggested data slicer configuration uses a resistor
(R1) connected between DSN and DSP with a capacitor
(C8) from DSN to DGND (Figure 2). This configuration
averages the analog output of the filter and sets the
threshold to approximately 50% of that amplitude. With
this configuration, the threshold automatically adjusts as
the analog signal varies, minimizing the possibility for
errors in the digital data. The sizes of R1 and C8 affect
how fast the threshold tracks to the analog amplitude. Be
sure to keep the corner frequency of the RC circuit much
lower than the lowest expected data rate.
Note that a long string of zeros or 1s can cause the
threshold to drift. This configuration works best if a coding
scheme, such as Manchester coding, which has an equal
number of zeros and 1s, is used.
To prevent continuous toggling of DATAOUT in the
absence of an RF signal due to noise, hysteresis can be
added to the data slicer as shown in Figure 3.
22
DFFB
21
OPP
19
DFO
The purpose of the data slicer is to take the analog
output of the data filter and convert it to a digital signal.
This is achieved by using a comparator and comparing
the analog input to a threshold voltage. The output logic
level is based on VDD5 voltage supply. One input is
supplied by the data filter output. Both comparator inputs
are accessible off chip to allow for different methods of
generating the slicing threshold, which is applied to the
second comparator input.
For further information on Data Slicer options, please refer
to Maxim Application Note 3671, Data Slicing Techniques
C7
Figure 1. Sallen-Key Lowpass Data Filter
MAX1473
DATA
SLICER
MAX1473
DATA
SLICER
25
DATAOUT
R2
20
DSN
25
DATAOUT
23
DSP
19
DFO
R3
*OPTIONAL
C8
R1
Figure 2. Generating Data Slicer Threshold
www.maximintegrated.com
R1
19
DFO
R*
C8
20
DSN
23
DSP
Figure 3. Generating Data Slicer Hysteresis
Maxim Integrated │ 11
MAX1473
315MHz/433MHz ASK Superheterodyne
Receiver with Extended Dynamic Range
for UHF ASK Receivers.
Peak Detector
The peak detector output (PDOUT), in conjunction with
an external RC filter, creates a DC output voltage equal
to the peak value of the data signal. The resistor provides
a path for the capacitor to discharge, allowing the peak
detector to dynamically follow peak changes of the data
filter output voltage. For faster receiver startup, the circuit
shown in Figure 4 can be used.
Layout Considerations
A properly designed PCB is an essential part of any RF/
microwave circuit. On high-frequency inputs and outputs,
use controlled-impedance lines and keep them as short
as possible to minimize losses and radiation. At high
frequencies, trace lengths that are on the order of λ/10 or
longer act as antennas.
Keeping the traces short also reduces parasitic inductance.
Generally, 1in of a PCB trace adds about 20nH of parasitic
inductance. The parasitic inductance can have a dramatic
effect on the effective inductance of a passive component.
For example, a 0.5in trace connecting a 100nH inductor
adds an extra 10nH of inductance or 10%.
To reduce the parasitic inductance, use wider traces and
a solid ground or power plane below the signal traces.
Also, use low-inductance connections to ground on all
GND pins, and place decoupling capacitors close to all
power-supply pins.
www.maximintegrated.com
MAX1473
DATA
SLICER
25
DATAOUT
20
DSN
23
DSP
25kΩ
19
DFO
26
PDOUT
47nF
Figure 4. Using PDOUT for Faster Startup
Control Interface Considerations
When operating the MAX1473 with a +4.5V to +5.5V
supply voltage, the PWRDN and AGCDIS pins may be
driven by a microcontroller with either 3V or 5V interface
logic levels. When operating the MAX1473 with a +3.0V
to +3.6V supply, the microcontroller must produce logic
levels which conform to the VIH and VIL specifications in
the DC Electrical Characteristics Table for the MAX1473.
Maxim Integrated │ 12
MAX1473
315MHz/433MHz ASK Superheterodyne
Receiver with Extended Dynamic Range
Table 2. Component Values for Typical Application Circuit
COMPONENT
VALUE FOR fRF = 433MHz
VALUE FOR fRF = 315MHz
DESCRIPTION
C1
100pF
100pF
5%
C2
2.7pF
4.7pF
±0.1pF
C3
100pF
100pF
5%
C4
100pF
100pF
5%
C5
1500pF
1500pF
10%
C6
220pF
220pF
5%
C7
470pF
470pF
5%
C8
0.47µF
0.47µF
20%
C9
220pF
220pF
10%
C10
0.01µF
0.01µF
20%
C11
0.1µF
0.1µF
20%
C12
15pF
15pF
Depends on XTAL
C13
15pF
15pF
Depends on XTAL
C14
0.01µF
0.01µF
20%
C15
0.01µF
0.01µF
20%
L1
56nH
120nH
5% or better**
L2
15nH
15nH
5% or better**
L3
15nH
27nH
5% or better**
R1
5.1kΩ
5.1kΩ
5%
R2
Open
Open
—
R3
Short
Short
—
X1(÷64)
6.6128MHz*
4.7547MHz*
Crystek or Hong Kong X’tal
X1 (÷32)
13.2256MHz*
9.5094MHz*
Crystek or Hong Kong X’tal
Y1
10.7MHz ceramic filter
10.7MHz ceramic filter
Murata
*Crystal frequencies shown are for ÷64 (VXTALSEL = 0V) and ÷32 (VXTALSEL = VDD).
**Wirewound recommended.
www.maximintegrated.com
Maxim Integrated │ 13
MAX1473
315MHz/433MHz ASK Superheterodyne
Receiver with Extended Dynamic Range
Typical Application Circuit
VDD
AVDD
THEN AVDD IS
IF VDD IS
(SEE TABLE)
3.0V TO 3.6V CONNECTED TO VDD
4.5V TO 5.5V
X1
CREATED BY LDO,
AVAILABLE AT AVDD
(PIN 2)
C11
C12
C13
1
RF INPUT
2
C1
L1
3
4
L2
5
C14
AVDD
6
7
L3
C3
C2
8
9
C4
C9
10
11
**
12
13
14
XTAL1
XTAL2
AVDD
PWRDN
LNAIN
PDOUT
LNASRC
28
TO/FROM µP
POWER DOWN
DATA OUT
27
26
R2
MAX1473 DATAOUT 25
AGND
VDD5
LNAOUT
DSP
AVDD
DFFB
MIXIN1
OPP
MIXIN2
DSN
AGND
DFO
IRSEL
IFIN2
MIXOUT
IFIN1
DGND
XTALSEL
DVDD
AGCDIS
C15
24
R3
23
22
21
C7
20
19
18
17
R1
16
15
FROM µP
*
Y1
C10
C5
C6
C8
IF FILTER
IN
GND
OUT
COMPONENT VALUES
IN TABLE 2
** SEE MIXER SECTION
* SEE PHASE-LOCKED LOOP SECTION
Chip Information
PROCESS: CMOS
www.maximintegrated.com
Maxim Integrated │ 14
MAX1473
315MHz/433MHz ASK Superheterodyne
Receiver with Extended Dynamic Range
Functional Diagram
LNASRC
4
LNAIN
AVDD
VDD5
AVDD
DVDD
DGND
3
IRSEL
11
AGCDIS LNAOUT MIXIN1 MIXIN2
15
6
8
9
AUTOMATIC
GAIN
CONTROL
LNA
Q
3.2V REG
IFIN1
17
IFIN2
18
0˚
IMAGE
REJECTION
2
24
MIXOUT
12
I
IF LIMITING
AMPS
∑
90˚
MAX1473
RSSI
7
14
13
DATA
FILTER
DIVIDE
BY 64
VCO
PHASE
DETECTOR
LOOP
FILTER
5,10
AGND
1
2
CRYSTAL
DRIVER
XTALSEL
XTAL1 XTAL2
16
1
28
RDF2
100kΩ
DATA
SLICER
POWER
DOWN
27
RDF1
100kΩ
25
PWRDN DATAOUT
20
23
19
DSN DSP DFO
26
21
22
PDOUT
OPP
DFFB
Package Information
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
PACKAGE TYPE
PACKAGE CODE
OUTLINE NO.
LAND PATTERN NO.
28 TSSOP
U28+1
21-0066
90-0171
32 Thin QFN-EP
T3255+3
21-0140
90-0001
www.maximintegrated.com
Maxim Integrated │ 15
MAX1473
315MHz/433MHz ASK Superheterodyne
Receiver with Extended Dynamic Range
Revision History
REVISION
NUMBER
REVISION
DATE
PAGES
CHANGED
4
5/10
Added lead-free parts and exposed pad in Ordering Information and Pin Description
tables
1, 8
5
1/11
Updated Absolute Maximum Ratings, AC Electrical Characteristics, Pin Description,
Layout Considerations, Typical Application Circuit, Functional Diagram, and Package
Information; added Voltage Regulator section to the Detailed Description section
2, 3, 4, 8, 9, 12,
13, 14
6
1/12
Updated DC Electrical and AC Electrical Characteristics tables, replaced TOC 4,
updated Tables 1 and 2 and Figure 1; updated Phase-Locked Loop, Data Filter, Data
Slicer, and Layout Considerations sections
3, 5, 6, 10–13
7
1/19
Updated Absolute Maximum Ratings, DC Electrical Characteristics, DC Electrical
Characteristics, Pin Description table, Detailed Description, and Typical Application Circuit
2–5, 8–11, 14
DESCRIPTION
For pricing, delivery, and ordering information, please visit Maxim Integrated’s online storefront at https://www.maximintegrated.com/en/storefront/storefront.html.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
© 2019 Maxim Integrated Products, Inc. │ 16
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