EVALUATION KIT AVAILABLE
MAX1510/MAX17510
Low-Voltage DDR Linear Regulators
General Description
Features
The MAX1510/MAX17510 DDR linear regulators source
and sink up to 3A peak (typ) using internal n-channel
MOSFETs. These linear regulators deliver an accurate
0.5V to 1.5V output from a low-voltage power input (VIN =
1.1V to 3.6V). The MAX1510/MAX17510 use a separate
3.3V bias supply to power the control circuitry and drive
the internal n-channel MOSFETs.
The MAX1510/MAX17510 provide current and thermal
limits to prevent damage to the linear regulator. Additionally,
the MAX1510/MAX17510 generate a power-good
(PGOOD) signal to indicate that the output is in regulation.
During startup, PGOOD remains low until the output is in
regulation for 2ms (typ). The internal soft-start limits the
input surge current.
The MAX1510/MAX17510 power the active-DDR
termination bus that requires a tracking input reference.
The devices can also be used in low-power chipsets
and graphics processor cores that require dynamically
adjustable output voltages. The MAX1510/MAX17510 are
available in a 10-pin, 3mm x 3mm thin DFN package.
Applications
●●
●●
●●
●●
●●
Notebook/Desktop Computers
DDR Memory Termination
Active Termination Buses
Graphics Processor Core Supplies
Chipset/RAM Supplies as Low as 0.5V
Pin Configuration
Ordering Information
TEMP RANGE
PINPACKAGE
MAX1510ETB
-40°C to +85°C
10 TDFN-EP*
ARD
MAX1510ETB+
-40°C to +85°C
10 TDFN-EP*
ABD
MAX1510ATB/V+
-40°C to +85°C
10 TDFN-EP*
AWD
MAX17510ATB+
-40°C to +125°C 10 TDFN-EP*
AWQ
MAX17510ATB/V+ -40°C to +125°C 10 TDFN-EP*
AWX
PART
OUT
PGND
SHDN
OUTS
10
9
8
7
6
+Denotes a lead(Pb)-free and RoHS-compliant package.
*EP = Exposed pad.
/V denotes an automotive qualified part.
VIN
(1.1V TO 3.6V)
+
TDFN
3mm x 3mm
5
PGOOD
4
REFIN
3
AGND
VCC
REFOUT
2
A "+" SIGN WILL REPLACE THE FIRST PIN INDICATOR ON LEAD-FREE PACKAGES.
19-3279; Rev 6; 2/16
IN
OUT
VOUT = VTT
OUTS
VBIAS
(2.7V TO 3.6V)
MAX1510
MAX17510
1
TOP
MARK
Typical Operating Circuit
IN
TOP VIEW
●● Internal Power MOSFETs with Current Limit (3A typ)
●● Fast Load-Transient Response
●● External Reference Input with Reference Output
Buffer
●● 1.1V to 3.6V Power Input
●● ±15mV (max) Load-Regulation Error
●● Thermal-Fault Protection
●● Shutdown Input
●● Power-Good Window Comparator with 2ms (typ)
Delay
●● Small, Low-Profile 10-Pin, 3mm x 3mm TDFN
Package
●● Ceramic or Polymer Output Capacitors
VDDQ
(2.5V OR 1.8V)
MAX1510
MAX17510
VCC
PGND
SHDN
AGND
PGOOD
REFIN
REFOUT
VREFOUT = VTTR
MAX1510/MAX17510
Low-Voltage DDR Linear Regulators
Absolute Maximum Ratings
IN to PGND...........................................................-0.3V to +4.3V
OUT to PGND.............................................-0.3V to (VIN + 0.3V)
OUTS to AGND...........................................-0.3V to (VIN + 0.3V)
VCC to AGND........................................................-0.3V to +4.3V
REFIN, REFOUT, SHDN,
PGOOD to AGND.................................. -0.3V to (VCC + 0.3V)
PGND to AGND.....................................................-0.3V to +0.3V
REFOUT Short Circuit to AGND................................Continuous
OUT Continuous RMS Current: 100s..................................±1.6A
1s.....................................±2.5A
Continuous Power Dissipation (TA = +70°C)
10-Pin 3mm x 3mm TDFN
(derated 24.4mW/°C above +70°C)...........................1951mW
Operating Temperature Range
MAX1510ETB.................................................. -40°C to +85°C
MAX17510ATB.............................................. -40°C to +125°C
Junction Temperature.......................................................+150°C
Storage Temperature Range............................. -65°C to +150°C
Lead Temperature (soldering, 10s).................................. +300°C
Soldering Temperature (reflow)
Lead(Pb)-free packages...............................................+260°C
Packages containing lead(Pb)......................................+240°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Electrical Characteristics
(VIN = 1.8V, VCC = 3.3V, VREFIN = VOUTS = 1.25V, SHDN = VCC, circuit of Figure 1, TJ = TA = -40°C to +85°C for MAX1510ETB,
TJ = TA = -40°C to +125°C for MAX17510ATB, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
VIN
Power input
1.1
3.6
VCC
Bias supply
2.7
3.6
Quiescent Supply Current (VCC)
ICC
Load = 0, VREFIN > 0.45V
0.7
1.3
Shutdown Supply Current (VCC)
ICC(SHDN)
SHDN = GND, VREFIN > 0.45V
350
600
SHDN = GND, REFIN = GND
50
100
Quiescent Supply Current (VIN)
IIN
Load = 0
0.4
10
mA
Shutdown Supply Current (VIN)
IIN(SHDN)
SHDN = GND
0.1
10
µA
0
+4
Input-Voltage Range
Feedback-Voltage Error
VOUTS
REFIN to OUTS
IOUT = ±200mA
TA = +25°C
-4
TA = -40°C to +125°C
-6
+6
-15
+15
Load-Regulation Error
-1A ≤ IOUT ≤ +1A
Line-Regulation Error
1.4V ≤ VIN ≤ 3.3V, IOUT = ±100mA
OUTS Input-Bias Current
IOUTS
1
V
mA
µA
mV
mV
mV
-1
+1
µA
0.5
1.5
V
OUTPUT
Output Adjust Range
OUT On-Resistance
High-side MOSFET (source) (IOUT = 0.1A)
0.14
0.25
Low-side MOSFET (sink) (IOUT = -0.1A)
0.14
0.25
Ω
Output Current Slew Rate
COUT = 100µF, IOUT = 0.1A to 2A
3
A/µs
OUT Power-Supply Rejection
Ratio
PSRR
10Hz < f < 10kHz, IOUT = 200mA,
COUT = 100FF
80
dB
OUT-to-OUTS Resistance
ROUTS
12
kΩ
8
Ω
Discharge MOSFET
On-Resistance
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RDISCHARGE SHDN = GND
Maxim Integrated │ 2
MAX1510/MAX17510
Low-Voltage DDR Linear Regulators
Electrical Characteristics (continued)
(VIN = 1.8V, VCC = 3.3V, VREFIN = VOUTS = 1.25V, SHDN = VCC, circuit of Figure 1, TJ = TA = -40°C to +85°C for MAX1510ETB,
TJ = TA = -40°C to +125°C for MAX17510ATB, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
0.5
1.5
V
-1
+1
µA
0.45
V
REFERENCE
REFIN Voltage Range
VREFIN
REFIN Input-Bias Current
IREFIN
REFIN Undervoltage-Lockout
Voltage
REFOUT Voltage
REFOUT Load Regulation
TA = +25°C
Rising edge, hysteresis = 50mV
VREFOUT
ΔVREFOUT
VCC = 3.3V, IREFOUT = 0V
IREFOUT = ±5mA
0.35
VREFIN
VREFIN
VREFIN
- 0.01
+ 0.01
-20
+20
V
mV
FAULT DETECTION
Thermal-Shutdown Threshold
TSHDN
Rising edge, hysteresis = 15°C
VCC Undervoltage-Lockout
Threshold
VUVLO
Rising edge, hysteresis = 100mV
IN Undervoltage-Lockout
Threshold
Current-Limit Threshold
Soft-Start Current-Limit Time
+165
2.45
Rising edge, hysteresis = 55mV
ILIMIT
°C
2.55
2.65
V
0.9
1.1
V
TA = -40°C to +85°C
1.8
3
4.2
TA = -40°C to +85°C
1.5
3
4.2
tSS
200
A
µs
INPUTS AND OUTPUTS
PGOOD Lower Trip Threshold
With respect to feedback threshold,
hysteresis = 12mV
-200
-150
-100
mV
PGOOD Upper Trip Threshold
With respect to feedback threshold,
hysteresis = 12mV
100
150
200
mV
OUTS forced 25mV beyond PGOOD trip
threshold
5
10
35
µs
PGOOD Startup Delay
Startup rising edge, OUTS within ±100mV of
the feedback threshold
1
2
3.5
ms
PGOOD Output Low Voltage
ISINK = 4mA
0.3
V
1
µA
2.0
V
PGOOD Propagation Delay
PGOOD Leakage Current
SHDN Logic Input Threshold
SHDN Logic Input Current
tPGOOD
IPGOOD
OUTS = REFIN (PGOOD high impedance),
PGOOD = VCC + 0.3V, TA = +25°C
Logic-high
Logic-low
0.8
SHDN = VCC or GND, TA = +25°C
-1
V
+1
µA
Note 1: Limits are 100% production tested at TA = +25°C. Limits over the operating temperature range are guaranteed through
correlation using statistical-quality-control (SQC) methods.
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Maxim Integrated │ 3
MAX1510/MAX17510
Low-Voltage DDR Linear Regulators
Typical Operating Characteristics
(Circuit of Figure 1. TA = +25°C, unless otherwise noted.)
-1
0
1
1.200
3
-3
-2
-1
BIAS CURRENT (ICC)
vs. INPUT VOLTAGE (VIN)
VOUT = 0.90V
1.0
0.8
50
VOUT = 1.25V
0.6
0.4
1.0
1.5
2.0
2.5
3.0
MAX1510/MAX17510 toc07
7
VOUT = 0.90V
0
1.5
2.0
2.5
3.0
0.5
IOUT (A)
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1.5
2.0
0
MAX1510/MAX17510 toc03
3.0
VIN = 1.5V
VOUT = 1.25V
0.8
VOUT = 0.90V
0.6
ENTERING
DROPOUT
0
-1
-2
0
1
2
DROPOUT VOLTAGE
vs. OUTPUT CURRENT
VOUT = 0.90V
VOUT = 1.25V
0.6
0.5
VOUT = 1.25V
0.4
0.3
0.2
VOUT = 0.9V
0.1
1
1.0
2.5
BIAS CURRENT (ICC)
vs. LOAD CURRENT (IOUT)
1.0
3.5
VIN = 1.5V
4
3
2.0
IOUT (A)
5
2
0
1.0
6
IIN (mA)
IPGND (mA)
VOUT = 1.25V
0.05
0.5
0
INPUT CURRENT (IIN)
vs. SINK LOAD CURRENT (IOUT)
ENTERING
DROPOUT
1.5
0.2
POWER GROUND CURRENT (IPGND)
vs. SOURCE LOAD CURRENT (IOUT)
0.15
1.0
1.2
INPUT UVLO
VIN (V)
0.20
DROPOUT VOLTAGE LIMITED
0.5
0.4
VIN (V)
VIN = 1.5V
0.10
0
3.5
THERMALLY LIMITED
1.0
1.4
DROPOUT
0.1
0.5
MAX1510/MAX17510 toc02
0.5
0.2
1.5
INPUT VOLTAGE (V)
0.7
0.3
2.0
0
3
0.9
ICC (mA)
100
0.25
2
INPUT CURRENT (IIN)
vs. INPUT VOLTAGE (VIN)
VOUT = 1.25V
0
1
IOUT (A)
150
0
0
IOUT (A)
200
IIN (µA)
2
VOUT = 1.25V
MAX1510/MAX17510 toc06
250
-2
VIN = 1.5V
ICC (mA)
-3
MAX1510/MAX17510 toc04
0.84
1.225
VIN = 1.2V
0.86
VOUT = 0.9V
2.5
MAX1510/MAX17510 toc09
0.88
1.250
MAXIMUM OUTPUT CURRENT (A)
0.90
VIN = 1.8V
3.0
DROPOUT VOLTAGE (V)
VIN = 1.5V
1.275
VOUT (V)
VOUT (V)
0.92
VREFIN = 1.25V
MAX1510/MAX17510 toc05
0.94
1.300
MAX1510/MAX17510 toc08
VREFIN = 0.9V
MAX1510/MAX17510 toc01
0.96
MAXIMUM OUTPUT CURRENT
vs. INPUT VOLTAGE
OUTPUT LOAD REGULATION
OUTPUT LOAD REGULATION
-2.0
-1.5
-1.0
IOUT (A)
-0.5
0.0
0
0
0.5
1.0
1.5
2.0
2.5
3.0
OUTPUT CURRENT (A)
Maxim Integrated │ 4
MAX1510/MAX17510
Low-Voltage DDR Linear Regulators
Typical Operating Characteristics (continued)
(Circuit of Figure 1. TA = +25°C, unless otherwise noted.)
REFOUT VOLTAGE ERROR
vs. REFOUT LOAD CURRENT
STARTUP WAVEFORM
MAX1510/MAX17510 toc11
MAX1510/MAX17510 toc10
REFOUT VOLTAGE ERROR (mV)
20
15
10
5V
SHDN
0V
SHUTDOWN WAVEFORM
MAX1510/MAX17510 toc12
RLOAD = 100Ω
5V
SHDN
0V
2V
1.25V
0
VOUT
0V
1V
VOUT
0V
-5
4V
4V
-10
PGOOD
PGOOD
-15
0V
0V
5
-20
-10
-5
0
5
500µs/div
10
100µs/div
REFOUT LOAD CURRENT (mA)
SOURCE LOAD TRANSIENT
SOURCE/SINK LOAD TRANSIENT
MAX1510/MAX17510 toc13
MAX1510/MAX17510 toc14
VOUT
AC-COUPLED
5mV/div
VOUT
AC-COUPLED
1mV/div
1A
+1.5A
IOUT
IOUT
-1.5A
0A
20.0µs/div
LINE TRANSIENT
4.00µs/div
DYNAMIC OUTPUT-VOLTAGE TRANSIENT
MAX1510/MAX17510 toc15
MAX1510/MAX17510 toc16
VIN = 1.5V
3.3V
VDDQ
1.8V
VIN (1V/div)
1.5V
1.2V
VREFOUT
VOUT (10mV/div)
AC-COUPLED
0.9V
0.9V
1.2V
VOUT
0.9V
IOUT = 100mA
40µs/div
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2.5V
20.0µs/div
Maxim Integrated │ 5
MAX1510/MAX17510
Low-Voltage DDR Linear Regulators
Typical Operating Characteristics (continued)
(Circuit of Figure 1. TA = +25°C, unless otherwise noted.)
20
10
0
20.0µs/div
-4.0
-3.5
-3.0
-2.5
40
30
20
10
0
-2.0
2.5
2.0
SINK CURRENT LIMIT (A)
3.00
2.70
2.40
2.10
10
SOURCE LOAD REGULATION
DISTRIBUTION IOUT = 1A, TA = +125°C
20
10
1
2
3
4
5
6
7
8
9
SINK LOAD REGULATION (mV)
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10 11
SAMPLE PERCENTAGE (%)
30
50
MAX1510 toc23
SINK LOAD REGULATION DISTRIBUTION
IOUT = -1A, TA = +125°C
SAMPLE SIZE = 200
4.0
20
0
-2.00
-2.20
-2.60
-2.40
-3.00
-2.80
-3.20
-3.40
-3.60
30
SOURCE CURRENT LIMIT (A)
40
0
40
SINK CURRENT LIMIT (A)
MAX1510/MAX17510 toc22
50
-3.80
10
SAMPLE SIZE = 200
1.80
20
3.5
SOURCE CURRENT-LIMIT DISTRIBUTION
TA = +125°C
1.50
30
50
SAMPLE PERCENTAGE (%)
MAX1510/MAX17510 toc20
40
0
SAMPLE PERCENTAGE (%)
SAMPLE SIZE = 200
3.0
SOURCE CURRENT LIMIT (A)
SINK CURRENT-LIMIT DISTRIBUTION
TA = +125°C
-4.00
SAMPLE PERCENTAGE (%)
50
MAX1510/MAX17510 toc19
30
+25°C
+85°C
MAX1510/MAX17510 toc21
0.9V
40
SAMPLE SIZE = 200
4.20
VOUT
+85°C
50
4.50
0.9V
1.2V
+25°C
3.60
1.2V
VREFOUT
SAMPLE PERCENTAGE (%)
VDDQ
1.8V
SAMPLE SIZE = 200
3.90
50
2.5V
SOURCE CURRENT-LIMIT
DISTRIBUTION
3.30
VIN = 1.8V
SAMPLE PERCENTAGE (%)
MAX1510/MAX17510 toc17
SINK CURRENT-LIMIT
DISTRIBUTION
MAX1510/MAX17510 toc18
DYNAMIC OUTPUT-VOLTAGE TRANSIENT
SAMPLE SIZE = 200
40
30
20
10
0
-9
-8 -7 -6 -5 -4 -3 -2 -1
0
1
SOURCE LOAD REGULATION (mV)
Maxim Integrated │ 6
MAX1510/MAX17510
Low-Voltage DDR Linear Regulators
Pin Description
PIN
NAME
1
REFOUT
2
VCC
FUNCTION
Buffered Reference Output. The output of the unity-gain reference input buffer sources and sinks over
5mA. Bypass REFOUT to AGND with a 0.33µF or greater ceramic capacitor.
Analog Supply Input. Connect to the system supply voltage (+3.3V). Bypass VCC to AGND with a 1µF or
greater ceramic capacitor.
3
AGND
Analog Ground. Connect the backside pad to AGND.
4
REFIN
External Reference Input. REFIN sets the output regulation voltage (VOUTS = VREFIN).
5
PGOOD
Open-Drain Power-Good Output. PGOOD is low when the output voltage is more than 150mV (typ) above
or below the regulation point, during soft-start, and when shut down. 2ms after the output reaches the
regulation voltage during startup, PGOOD becomes high impedance.
6
OUTS
Output Sense Input. The OUTS regulation level is set by the voltage at REFIN. Connect OUTS to the
remote DDR termination bypass capacitors. OUTS is internally connected to OUT through a 12kΩ resistor.
7
SHDN
Shutdown Control Input. Connect to VCC for normal operation. Connect to analog ground to shut down the
linear regulator. The reference buffer remains active in shutdown.
8
PGND
Power Ground. Internally connected to the output sink MOSFET.
9
OUT
10
IN
Power Input. Internally connected to the output source MOSFET.
—
EP
Exposed Pad. Internally connected to AGND. Connect EP to AGND PCB ground plane to maximize
thermal performance. Not intended as an electrical connection point.
Output of the Linear Regulator
Detailed Description
The MAX1510/MAX17510 are low-voltage, low-dropout
DDR termination linear regulators with an external bias
supply input and a buffered reference output (see Figures
1 and 2). VCC is powered by a 2.7V to 3.6V supply that
is commonly available in laptop and desktop computers.
The 3.3V bias supply drives the gate of the internal pass
transistor, while a lower voltage input at the drain of the
transistor (IN) is regulated to provide VOUT. By using separate bias and power inputs, the MAX1510/MAX17510
can drive an n-channel high-side MOSFET and use a
lower input voltage to provide better efficiency.
The MAX1510/MAX17510 regulate their output voltage
to the voltage at REFIN. When used in DDR applications as a termination supply, the MAX1510/MAX17510
deliver 1.25V or 0.9V at 3A peak (typ) from an input voltage of 1.1V to 3.6V. The MAX1510/MAX17510 sink up
to 3A peak (typ) as required in a termination supply. The
MAX1510/MAX17510 provide shoot-through protection,
ensuring that the source and sink MOSFETs do not conduct at the same time, yet produce a fast source-to-sink
load transient.
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VIN =
1.1V TO 3.6V
IN
CIN2
10µF
3.3V BIAS
SUPPLY
R3
100kΩ
C1
1.0µF
POWER-GOOD
OFF
VDDQ
VCC
VOUT = VTT = VDDQ/2
COUT1
100µF
MAX1510
MAX17510
PGND
AGND
PGOOD
ON
OUTS
SHDN
R1
10kΩ
R2
10kΩ
OUT
REFIN
CREFIN
1000pF
REFOUT
VREFOUT = VTTR
CREFOUT
0.33µF
Figure 1. Standard Application Circuit
Maxim Integrated │ 7
MAX1510/MAX17510
3.3V BIAS
SUPPLY
Low-Voltage DDR Linear Regulators
VCC
EN
UVLO
OFF ON
IN
SOFTSTART
INPUT
1.1V TO 3.6V
SHDN
THERMAL
SHDN
REFIN
VDDQ
OUT
VTT
Gm
PGND
VTTR
12kΩ
REFOUT
OUTS
AGND
REFIN
+150mV
EN
8Ω
REFIN
-150mV
POWERGOOD
PGOOD
DELAY
LOGIC
MAX1510
MAX17510
Figure 2. Functional Diagram
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Maxim Integrated │ 8
MAX1510/MAX17510
The MAX1510/MAX17510 feature an open-drain PGOOD
output that transitions high 2ms after the output initially
reaches regulation. PGOOD goes low within 10μs of
when the output goes out of regulation by ±150mV. The
MAX1510/MAX17510 feature current- and thermal-limiting
circuitry to prevent damage during fault conditions.
3.3V Bias Supply (VCC)
The VCC input powers the control circuitry and provides the
gate drive to the pass transistor. This improves efficiency
by allowing VIN to be powered from a lower supply voltage.
Power VCC from a well-regulated 3.3V supply. Current
drawn from the VCC supply remains relatively constant
with variations in VIN and load current. Bypass VCC with
a 1μF or greater ceramic capacitor as close as possible to
the device.
VCC Undervoltage Lockout (UVLO)
The VCC input undervoltage-lockout (UVLO) circuitry
ensures that the regulator starts up with adequate voltage for the gate-drive circuitry to bias the internal pass
transistor. The UVLO threshold is 2.55V (typ). VCC must
remain above this level for proper operation.
Power-Supply Input (IN)
IN provides the source current for the linear regulator’s
output, OUT. IN connects to the drain of the internal
n-channel power MOSFET. IN can be as low as 1.1V,
minimizing power dissipation. The input UVLO prohibits
operation below 0.8V (typ). Bypass IN with a 10μF or
greater capacitor as close as possible to the device.
Reference Input (REFIN)
The MAX1510/MAX17510 regulate OUTS to the voltage set at REFIN, making the devices ideal for memory
applications where the termination supply must track the
supply voltage. Typically, REFIN is set by an external
resistive voltage-divider connected to the memory supply
(VDDQ) as shown in Figure 1. The maximum output voltage
of 1.5V is limited by the gate-drive voltage of the internal
n-channel power transistor.
Buffered Reference Output (REFOUT)
Low-Voltage DDR Linear Regulators
connected to ceramic bypass capacitors (0.33μF to
1.0μF). REFOUT is active when VREFIN > 0.45V and VCC
is above VUVLO. REFOUT is independent of SHDN.
Shutdown
Drive SHDN low to disable the error amplifier, gate-drive
circuitry, and pass transistor (Figure 2). In shutdown, OUT
is terminated to GND with an 8Ω MOSFET. REFOUT is
independent of SHDN. Connect SHDN to VCC for normal
operation.
Current Limit
The MAX1510/MAX17510 feature source and sink
current limits to protect the internal n-channel MOSFETs.
The source and sink MOSFETs have a typical 3A
current limit (1.8A min). This current limit prevents damage
to the internal power transistors, but the device can enter
thermal shutdown if the power dissipation increases the
die temperature above +165°C (see the Thermal-Overload
Protection section).
Soft-Start Current Limit
Soft-start gradually increases the internal source current
limit to reduce input surge currents at startup. Full-source
current limit is available after the 200μs soft-start timer
has expired. The soft-start current limit is given by:
I
×t
ILIMIT(SS) = LIMIT
t SS
where ILIMIT and tSS are from the Electrical Characteristics.
Thermal-Overload Protection
Thermal-overload protection prevents the linear regulator from overheating. When the junction temperature
exceeds +165°C, the linear regulator and reference
buffer are disabled, allowing the device to cool. Normal
operation resumes once the junction temperature cools
by 15°C. Continuous short-circuit conditions result in a
pulsed output until the overload is removed. A continuous
thermal-overload condition results in a pulsed output. For
continuous operation, do not exceed the absolute maximum junction-temperature rating of +150°C.
REFOUT is a unity-gain transconductance amplifier that
generates the DDR reference supply. It sources and
sinks greater than 5mA. The reference buffer is typically
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Maxim Integrated │ 9
MAX1510/MAX17510
SHDN
Low-Voltage DDR Linear Regulators
200µs
CURRENT LIMIT
OUTPUT OVERLOAD
CONDITION
POWER-GOOD
WINDOW
OUT
2µs STARTUP
DELAY
PGOOD
10µs
PROPAGATION
DELAY
10µs
PROPAGATION
DELAY
Figure 3. MAX1510/MAX17510 PGOOD and Soft-Start Waveforms
Power-Good (PGOOD)
The MAX1510/MAX17510 provide an open-drain PGOOD
output that goes high 2ms (typ) after the output initially
reaches regulation during startup as shown in Figure 3.
PGOOD transitions low 10μs after the output goes out of
regulation by ±150mV, or when the device enters shutdown. Connect a pullup resistor from PGOOD to VCC
for a logic-level output. Use a 100kΩ resistor to minimize
current consumption.
REFERENCE
VOLTAGE
(VREF)
CREFIN
REFIN
Applications Information
R2
Dynamic Output-Voltage Transitions
By changing the voltage at REFIN, the devices can be
used in applications that require dynamic output-voltage
changes between two set points (graphics processors).
Figure 4 shows a dynamically adjustable resistive voltage-divider network at REFIN. Using an external signal
MOSFET, a resistor can be switched in and out of the
REFIN resistordivider, changing the voltage at REFIN.
The two output voltages are determined by the following
equations:
R2
VOUT(LOW ) = VREF
R1 + R2
(R2 + R3)
VOUT(HIGH) = VREF
R1 + (R2 + R3)
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MAX1510
MAX17510
R1
VOUT(HIGH)
VOUT(LOW) =VREF
VOUT(HIGH) =VREF
VOUT(LOW)
R3
R2
R1 + R2
(R2 + R3)
R1 + (R2 + R3)
Figure 4. Dynamic Output-Voltage Change
Maxim Integrated │ 10
For a step voltage change at REFIN, the rate of change
of the output voltage is limited by the total output capacitance, the current limit, and the load during the transition.
Adding a capacitor across REFIN and AGND filters noise
and controls the rate of change of the REFIN voltage during dynamic transitions. With the additional capacitance,
the REFIN voltage slews between the two set points with
a time constant given by REQ x CREFIN, where REQ is the
equivalent parallel resistance seen by the slew capacitor.
Operating Region and Power Dissipation
The maximum power dissipation of the MAX1510/
MAX17510 depends on the thermal resistance of the 10pin TDFN package and the circuit board, the temperature
difference between the die and ambient air, and the rate
of airflow. The power dissipated in the device is:
PSRC = ISRC x (VIN - VOUT)
PSINK = ISINK x VOUT
The resulting maximum power dissipation is:
PDIS(MAX) =
TJ(MAX) - T A
θ JC + θ CA
where TJ(MAX) is the maximum junction temperature
(+150°C), TA is the ambient temperature, θJC is the
thermal resistance from the die junction to the package
case, and θCA is the thermal resistance from the case
through the PCB, copper traces, and other materials to
the surrounding air. For optimum power dissipation, use a
large ground plane with good thermal contact to the backside pad, and use wide input and output traces.
When 1 square inch of copper is connected to the device,
the maximum allowable power dissipation of a 10-pin
TDFN package is 1951mW. The maximum power dissipation is derated by 24.4mW/°C above TA = +70°C. Extra
copper on the PCB increases thermal mass and reduces
thermal resistance of the board. Refer to the MAX1510
evaluation kit for a layout example.
The devices deliver up to 3A and operates with input
voltages up to 3.6V, but not simultaneously. High output
currents can only be achieved when the input-output
differential voltages are low (Figure 5).
Dropout Operation
A regulator’s minimum input-to-output voltage differential (dropout voltage) determines the lowest usable
supply voltage. Because the devices use an n-channel
pass transistor, the dropout voltage is a function of the
drain-to-source on-resistance (RDS(ON) = 0.25Ω max)
multiplied by the load current (see the Typical Operating
Characteristics):
Low-Voltage DDR Linear Regulators
SAFE OPERATING REGION
3.5
MAXIMUM OUTPUT CURRENT (A)
MAX1510/MAX17510
DROPOUT VOLTAGE
LIMITED
MAXIMUM CURRENT LIMIT
3.0
2.5
TA = 0°C TO +70°C
2.0
1.5
VIN(MAX) - VOUT(MIN)
1.0
0.5
0
1s RMS
LIMIT
100s RMS
LIMIT
TA = +100°C
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
INPUT-OUTPUT DIFFERENTIAL VOLTAGE (V)
Figure 5. Power Operating Region—Maximum Output Current
vs. Input-Output Differential Voltage
For low output-voltage applications, the sink current is
limited by the output voltage and the RDS(ON) of the
MOSFET.
Input Capacitor Selection
Bypass IN to PGND with a 10μF or greater ceramic capacitor. Bypass VCC to AGND with a 1μF ceramic capacitor
for normal operation in most applications. Typically, the
LDO is powered from the output of a step-down controller
(memory supply) that has additional bulk capacitance
(polymer or tantalum) and distributed ceramic capacitors.
Output Capacitor Selection
The MAX1510/MAX17510 output stability is independent
of the output capacitance for COUT from 10μF to 220μF.
Capacitor ESR between 2mΩ and 50mΩ is needed to
maintain stability. Within the recommended capacitance
and ESR limits, the output capacitor should be chosen to
provide good transient response:
ΔIOUT(P-P) x ESR = ΔVOUT(P-P)
where ΔIOUT(P-P) is the maximum peak-to-peak load current step (typically equal to the maximum source load plus
the maximum sink load), and ΔVOUT(P-P) is the allowable
peak-to-peak voltage tolerance.
Using larger output capacitance can improve efficiency in
applications where the source and sink currents change
rapidly. The capacitor acts as a reservoir for the rapid
source and sink currents, so no extra current is supplied
by the MAX1510/MAX17510 or discharged to ground,
improving efficiency.
VDROPOUT = RDS(ON) x IOUT
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Maxim Integrated │ 11
MAX1510/MAX17510
Noise, PSRR, and Transient Response
The MAX1510/MAX17510 operate with low-dropout voltage and low quiescent current in notebook computers
while maintaining good noise, transient response, and AC
rejection specifications. Improved supply-noise rejection
and transient response can be achieved by increasing
the values of the input and output capacitors. Use passive
filtering techniques when operating from noisy sources.
The MAX1510/MAX17510 load-transient response graphs
(see the Typical Operating Characteristics) show two
components of the output response: a DC shift from the
output impedance due to the load-current change and the
transient response. A typical transient response for a step
change in the load current from -1.5A to +1.5A is 10mV.
Increasing the output capacitor’s value and decreasing
the ESR attenuate the overshoot.
Low-Voltage DDR Linear Regulators
PCB Layout Guidelines
The MAX1510/MAX17510 require proper layout to
achieve the intended output power level and low noise.
Proper layout involves the use of a ground plane,
appropriate component placement, and correct routing
of traces using appropriate trace widths. Refer to the
MAX1510 evaluation kit for a layout example:
●● Minimize high-current ground loops. Connect the
ground of the device, the input capacitor, and the
output capacitor together at one point.
●● To optimize performance, a ground plane is essential.
Use all available copper layers in applications where
the device is located on a multilayer board.
●● Connect the input filter capacitor less than 10mm from
IN. The connecting copper trace carries large currents
and must be at least 2mm wide, preferably 5mm wide.
●● Connect the backside pad to a large ground plane.
Use as much copper as necessary to decrease the
thermal resistance of the device. In general, more
copper provides better heatsinking capabilities.
Chip Information
PROCESS: BiCMOS
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
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PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
10 TDFN-EP
T1033+1
21-0137
90-0003
Maxim Integrated │ 12
MAX1510/MAX17510
Low-Voltage DDR Linear Regulators
Revision History
REVISION
NUMBER
REVISION
DATE
PAGES
CHANGED
0
5/04
Initial release
1
1/05
Raised Absolute Maximum rating
2
8/05
Added MAX1510ETB
3
4/09
Added automotive-qualified part MAX1510ETB/V+
4
7/09
Added MAX17510 to data sheet; added temperature grades for MAX1510ATB+ and
MAX1510ATB/V+; minor edits
5
3/11
Added MAX17510 automotive qualified part
1
6
2/16
Changed MAX17510ATB/V+ top mark in Ordering Information from AWQ to AWX
1
DESCRIPTION
—
1, 14
1
1, 2, 7, 12, 13
1, 2, 3, 6,
7, 12, 13
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
© 2016 Maxim Integrated Products, Inc. │ 13
