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MAX15158/MAX15158A
High-Voltage Multiphase Boost Controller
General Description
Benefits and Features
The switching frequency is controlled either through
an external resistor setting the internal oscillator or by
synchronizing the regulator to an external clock. The
device is designed to support 120kHz to 1MHz switching
frequencies. The controller has a dedicated enable/input
undervoltage-lockout (EN/UVLO) pin to configure for flexible
power sequencing.
●● Integration Reduces Design Footprint
• Internal LDO for Bias Supply Generation
• Multiphase Multiple Controller Synchronization and
Interleave
• Output Voltage Sense Level Shifter
MAX15158/MAX15158A is a high-voltage multiphase
boost controller designed to support up to two MOSFET
drivers and four external MOSFETs in single-phase
or dual-phase boost/inverting-buck-boost configurations.
Two devices can be stacked up for quad-phase operation.
The output voltage of MAX15158 can be dynamically
set through the 1V to 2.2V reference input (REFIN) for
modular design support. For MAX15158A the REFIN pin
is removed, and the internal 2.0V reference voltage is
selected by default.
MAX15158/MAX15158A has a dedicated RAMP pin to
adjust internal slope compensation. The device features
adjustable overcurrent protection. The device incorporates
current sense amplifiers to accurately measure the current
of each phase across external sense resistors to
implement accurate phase current sharing. The controller is also protected against output overvoltage, input
undervoltage and thermal shutdown.
The device is available in 5mm x 5mm, 32-pin TQFN
package and supports -40°C to 125°C junction temperature
range.
Applications
●● Communication
●● Industrial
●● Automotive
●● Multiphase Boost
19-100365; Rev 2; 11/19
●● Wide Operating Range
• 8V to 76V Input Voltage Range for Booost
Configuration and -8V to -76V Input Voltage Range
for Inverting-Buck-Boost Configuration
• 3.3V to 60V Output Voltage Range on the Top of
Input Voltage
• 120kHz to 1MHz Switching Frequency Range
• -40°C to +125°C Temperature Range
• Single/Dual/Quad-Phase Operation
• Active Phase Current Balance Control
●● Robust Fault Protection Improves Quality and
Reliability
• Adjustable Input Undervoltage Lockout
• Adjustable Cycle-by-Cycle Peak Current Limit
and Fast Overcurrent Protection
• Selectable Feedback Overvoltage Protection
• Thermal Shutdown
●● Flexible and Simple System Design
• Adjustable Slope Compensation
• Low-Side MOSFET Gate Monitoring for Accurate
Current Sensing
• Discontinuous-Conduction-Mode Operation is
Supported when Using a Diode in Place of the
High-Side MOSFET
●● Small 5mm x 5mm TQFN package, 0.5mm pitch
Ordering Information appears at end of data sheet.
MAX15158/MAX15158A
High-Voltage Multiphase Boost Controller
Typical Application Circuit
VIN- = -8V TO -65V
3.3V TO 60V
OUTPUT
MAX15158 /
MAX15158A
VIN-
VIN-
EN/UVLO
RAMP
VIN-
DH1
MOSFET
DRIVER
DL1
VINDRV
6V TO 14V BIAS W.R.T. VIN-
REFIN
(NC)
FREQ/CLK
1V TO 2.2V DAC W.R.T. VINSYSTEM CLK
COMP
DLFB1
POWER STAGE
CSP1
CSN1
CURRENT SENSE
VIN-
VIN- VINVIN-
VINPGOOD
OPEN-DRAIN POWER GOOD
MULTIPHASE SUPPORT / SYNCHRONIZATION
SYNC
CSIO_
SS
VINBIAS
DH2
VIN-
MOSFET
DRIVER
DL2
DLFB2
POWER STAGE
CSP2
CSN2
CURRENT SENSE
VIN-
VINILIM
OVP
OUTN
OUTP
FB
GND
VIN-
www.maximintegrated.com
VIN-
Maxim Integrated │ 2
MAX15158/MAX15158A
High-Voltage Multiphase Boost Controller
Absolute Maximum Ratings
OUTP, OUTN to GND............................................-0.3V to +80V
CSP_, CSN_ to GND............................................-0.3V to +0.3V
CSP_ to CSN_......................................................-0.3V to +0.3V
DH_, DL_ to GND................................. -0.3V to (VBIAS + 0.3V)
DLFB_ to GND......................................... -0.3V to (VDRV+ 0.3V)
DRV to GND...........................................................-0.3V to +16V
BIAS to GND............................................................-0.3V to +6V
DRV to BIAS...........................................................-0.3V to +16V
FB, PGOOD, REFIN to GND...................................-0.3V to +6V
EN/UVLO, FREQ/CLK to GND................................-0.3V to +6V
COMP, SS, ILIM, OVP, RAMP,
SYNC to GND.....................................-0.3V to (VBIAS + 0.3V)
CSION, CSIOP to GND...........................-0.3V to (VBIAS + 0.3V)
Maximum Current out of BIAS..........................................100mA
Operating Temperature Range.......................... -40°C to +125°C
Continuous Power Dissipation (TA = +70°C)
TQFN (derate 34.5mW/°C above +70°C)......................2.76W
Junction Temperature.......................................................+150°C
Storage Temperature Range............................. -40°C to +150°C
Lead Temperature (soldering, 10s).................................. +300°C
Soldering Temperature (reflow)........................................+240°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Information
PACKAGE TYPE: 32-PIN TQFN
Package Code
T3255+6
Outline Number
21-0140
Land Pattern Number
90-0603
THERMAL RESISTANCE, FOUR-LAYER BOARD
Junction to Ambient (θJA)
29°C/W
Junction to Case (θJC)
1.7°C/W
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board.
For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
www.maximintegrated.com
Maxim Integrated │ 3
MAX15158/MAX15158A
High-Voltage Multiphase Boost Controller
Electrical Characteristics
(VDRV = 9V, VEN/UVLO = 1.2V, REFIN = BIAS (MAX15158), CBIAS = 2.2μF, CSS = 10nF, RFREQ = 100kΩ (600kHz), TA = TJ = -40°C to +125°C,
unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
14
V
15.4
mA
μA
INPUT SUPPLIES
DRV Operating Range
VDRV
DRV Quiescent Current
IDRV
DRV Shutdown Current
DRV Undervoltage-Lockout
Threshold
VDRV(UVLO)
8.5
Device Switching, 2 phases, 10pF load
DH_ and DL_
10.0
EN = GND
10
19
VDRV rising
8.00
8.27
8.41
VDRV falling
7.90
8.16
8.31
IBIAS = 5mA
4.66
4.75
4.81
V
30
56
90
mA
VBIAS rising
4.10
4.24
4.40
VBIAS falling
4.00
4.19
4.32
VUVLO rising
0.98
1.00
1.03
VUVLO falling
0.88
0.90
0.93
-1
+1
μA
V
BIAS LINEAR REGULATOR
BIAS LDO Output
Voltage
VBIAS
BIAS LDO Current Limit
BIAS Undervoltage-Lockout
Threshold
VBIAS(UVLO)
V
CONTROLLER ENABLE
EN/UVLO Adjustable Undervoltage-Lockout Threshold
VUVLO
EN/UVLO Input
Leakage Current
IUVLO
VUVLO = 0V to VBIAS
V
FEEDBACK VOLTAGE LEVEL SHIFTER (OUTP, OUTN)
OUTP Current Range
IOUTP
OUTP = OUTN > 8V
0.05
3.000
mA
OUTN Bias Current
IOUTN
OUTP = OUTN > 8V
220
375
μA
OUTP Leakage Current
OUTN = OUTP = BIAS
4
10
μA
OUTN Leakage Current
OUTN = OUTP = BIAS
3
10
μA
Minimum OUTN voltage for HV FB
operations
7.0
7.2
7.4
OUTN UVLO hysteresis
6.8
OUTN Undervoltage-Lockout
Threshold
OUTN
UVLO
HV FB Voltage-Buffer Operating Range
VOUTP,
VOUTN
V
7.0
8
7.2
76
V
CONTROL LOOP
FB Regulation Threshold (Preset Mode)
VFB
FB-to-REFIN Offset Voltage (Tracking Mode)
REFIN Input Voltage Range
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VREFIN
REFIN = BIAS (MAX15158)
1.97
2.00
2.02
V
VFB – VREFIN , VREFIN = 1V to 2V
-9
+9
mV
(Note 2)
1
2.2
V
Maxim Integrated │ 4
MAX15158/MAX15158A
High-Voltage Multiphase Boost Controller
Electrical Characteristics (continued)
(VDRV = 9V, VEN/UVLO = 1.2V, REFIN = BIAS (MAX15158), CBIAS = 2.2μF, CSS = 10nF, RFREQ = 100kΩ (600kHz), TA = TJ = -40°C to +125°C,
unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
MIN
TYP
100mV hysteresis (typ)
2.30
2.36
IFB
VFB = 0V to 2V;
OUTP = OUTN = BIAS
-1
+1
μA
REFIN Input Leakage Current
IREFIN
VREFIN = 0.4V to 2.2V
-1
+1
μA
CSP_-to-CSN_ Differential Voltage Range
DVCS_
VCSP_ - VCSN_
-200
+200
mV
Current-Sense
Common-Mode Voltage Range
VCSP_,
VCSN_
With respect to GND (Note 3)
-300
+300
mV
Preset Mode REFIN Threshold
Rising
FB Input Leakage
Current
CSP_, CSN_ Current-Sense
Amplifier Gain
ACS_
CSP_ , CSN_ Input Leakage
Current
ICSP_,
ICSN_
Error-Amplifier Transconductance
GMEA
Ramp Pin Amplitude Adjustable
Range
VRAMP
Internal Slope Compensation
Ramp Voltage to VRAMP Ratio
RAMP Bias Current
CONDITIONS
VCSP_, VCSN_ = ±200 mV with respect
to AGND
-1
V/V
+1
1.1
120
UNITS
V
8.3
VRAMP = 0.3V
IRAMP
MAX
μA
mS
375
1.9
mV
V/V
VRAMP = 0V
9.4
10.0
10.6
μA
RFREQ/CLK = OPEN
293
300
305
kHz
RFREQ = 20kΩ
105
115
125
RFREQ = 25kΩ
135
150
165
RFREQ = 100kΩ (RFREQ < 120 kΩ)
550
600
650
FREQ/CLK externally applied
120
1000
kHz
0.48
4.00
MHz
SWITCHING FREQUENCY
Preset PWM Switching
Frequency
fSW
Adjustable PWM
Switching Frequency
fSW
PWM Switching
frequency range
fSW
FREQ/CLK Frequency Detection Range
fCLK
FREQ/CLK Logic Level
VCLK
FREQ/CLK Input Bias Current
ICLK
FREQ/CLK to PWM Switching
Frequency Ratio
fCLK / fSW
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Logic-high (rising)
Logic-low (falling)
VFREQ/CLK = GND
1/2/4 Phases Operation
1.80
1.5
1.6
-10.7
-10.0
4
1.85
-9.3
kHz
V
μA
kHz/kHz
Maxim Integrated │ 5
MAX15158/MAX15158A
High-Voltage Multiphase Boost Controller
Electrical Characteristics (continued)
(VDRV = 9V, VEN/UVLO = 1.2V, REFIN = BIAS (MAX15158), CBIAS = 2.2μF, CSS = 10nF, RFREQ = 100kΩ (600kHz), TA = TJ = -40°C to +125°C,
unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
1.58
1.95
UNITS
QUAD-PHASE CLOCK SYNC
SYNC Logic Threshold
VSYNC
SYNC Input Leakage Current
ISYNC
SYNC Frequency Range
fSYNC
SYNC Output Voltage Level
VSYNC
Logic high (rising)
Logic low (falling)
VSYNC = 0V to 4.6V, internal 5MΩ
pulldown
Logic-high, ISOURCE = 10mA
0.90
1.17
V
-2
+2
μA
200
2000
kHz
VBIAS - 0.4
Logic-low, ISINK = 10mA
0.4
V
OUTPUT FAULT PROTECTION
CSP_ to CSN_ Minimum
Threshold for Cycle-by-Cycle
Positive Peak Current Limit
VILIM = 0V
17
20
23
mV
CSP_ to CSN_ Maximum
Threshold for Cycle-by-Cycle
Positive Peak Current Limit
VILIM > 1.25V
94
100
106
mV
CSP_ to CSN_ Minimum
Threshold for Cycle-by-Cycle
Negative Overcurrent
Protection
VILIM > 1.25V
-80
mV
CSP_ to CSN_ Maximum
Threshold for Cycle-by-Cycle
Negative Overcurrent
Protection
VILIM = 0V
-16
mV
CSP_ to CSN_ Minimum
Threshold for Fast Positive
Overcurrent Protection
VILIM = 0V
21
26
31
mV
CSP_ to CSN_ Maximum
Threshold for Fast Positive
Overcurrent Protection
VILIM > 1.25V
121
133
145
mV
9.4
10.0
10.6
µA
ILIM Source Current
CSP_-to-CSN_ Cycle-by-Cycle
Positive Peak Current Limit
Threshold Accuracy
CSP_-to-CSN_ Negative
Overcurrent Protection
Threshold Accuracy
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0.25V < VILIM < 0.95V
-15
+ 15
%
VILIM = 500mV
-6
+6
%
VILIM = 500mV
-20
+20
%
Maxim Integrated │ 6
MAX15158/MAX15158A
High-Voltage Multiphase Boost Controller
Electrical Characteristics (continued)
(VDRV = 9V, VEN/UVLO = 1.2V, REFIN = BIAS (MAX15158), CBIAS = 2.2μF, CSS = 10nF, RFREQ = 100kΩ (600kHz), TA = TJ = -40°C to +125°C,
unless otherwise noted.) (Note 1)
PARAMETER
VILIM to |CSP_ - CSN_|
Cycle-by-Cycle Positive Peak
Current Limit Threshold Ratio
SYMBOL
Minimum REFIN and SS
Voltage for Valid FB OV Fault
CONDITIONS
MIN
VILIM = 500mV
TYP
MAX
10
UNITS
V/V
SS > 1V
1.00
1.02
1.04
V
FB Overvoltage Default
Threshold (Preset Mode)
FB OV
Measured with respect to target voltage
(REFIN = BIAS for MAX15158), VFB
falling, 3% hysteresis
8.5
10.0
12.0
%
FB Overvoltage Threshold
(Tracking Mode)
FB OV
Measured with respect to target voltage
(VREFIN = 1V for MAX15158), VFB falling,
3% hysteresis
8.5
10
11
%
Resistor connected to GND
9.4
10.0
10.6
µA
OVP Selector Output Source
Current
Fault Propagation
Delay
EN/UVLO falling to SS falling
12
μs
Cumulative cycle-by-cycle peak current
limit or negative overcurrent protection
events for hiccup
32
Events
FB OV
128
PWM CLK
Cycles
32,768
PWM CLK
Cycles
Hiccup Timeout Duration
PGOOD Threshold
PGOOD Falling and Rising
Delay
PGOOD rising (REFIN = BIAS for
MAX15158)
1.83
PGOOD falling (REFIN = BIAS for
MAX15158)
1.77
1.82
1.87
64
PWM CLK
Cycles
1.88
1.93
V
PGOOD Output Low Voltage
VPGOOD
ISINK = 3mA
20
40
mV
PGOOD Leakage Current
IPGOOD
FB = REFIN for MAX15158, VPGOOD = 5V
1
μA
Thermal Shutdown
TSHDN
15°C hysteresis
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165
°C
Maxim Integrated │ 7
MAX15158/MAX15158A
High-Voltage Multiphase Boost Controller
Electrical Characteristics (continued)
(VDRV = 9V, VEN/UVLO = 1.2V, REFIN = BIAS (MAX15158), CBIAS = 2.2μF, CSS = 10nF, RFREQ = 100kΩ (600kHz), TA = TJ = -40°C to +125°C,
unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SOFT-START (SS)
SS Amplifier
Transconductance
GM(SS)
SS Current Capability
ISS
SS Pulldown
Resistance
RSS
SS UndervoltageLockout Threshold
VUVLO(SS)
0.2
mS
Source
4.75
5.00
5.25
Sink
-5.8
-5.0
-4.2
Discharge
4.3
SS rising
55
SS falling (drivers disabled)
45
μA
Ω
mV
PWM Output
DH_, DL_ Output
Voltage Level
VDH_, VDL_
DLFB_ Leakage Current
ILK
DLFB_ Logic Threshold
VDLFB
Logic-high, ISOURCE = 10mA
VBIAS - 0.5
Logic-low, ISINK = 10mA
VDLFB_ = 9V
0.2
-1
+1
Logic high (rising)
0.75
0.80
0.85
Logic low (falling)
0.45
0.50
0.55
V
μA
V
CURRENT SHARING (MULTIPHASE APPLICATIONS ONLY)
CSIO_ Output Common-Mode
Voltage
VCSION
CSIO_ Differential Input
Resistance
RCSIO_
With respect to AGND
1.24
V
4.2
kΩ
Note 1: Limits are 100% tested at TA = +25°C. Limits over the operating temperature range and relevant supply-voltage range are
guaranteed by design and characterization.
Note 2: For MAX15158, operating REFIN below 1V is not recommended due to disabled FB overvoltage-fault protection.
Note 3: Guaranteed by design, not production tested.
www.maximintegrated.com
Maxim Integrated │ 8
MAX15158/MAX15158A
High-Voltage Multiphase Boost Controller
Typical Operating Characteristics
(TA = -40°C to +125°C, VIN- = -48V, unless otherwise noted. See the Standard Application Circuits.)
EFFICIENCY vs. LOAD CURRENT
90
Vout=5V
VOUT = 5V
Vout=9V
VOUT = 9V
Vout=12V
VOUT = 12V
Vout=14.5V
VOUT = 14.5V
Vout=35V
VOUT = 35V
Vout=55V
VOUT = 55V
88
86
84
0
5
10
15
20
12.038
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
92
12.050
12.045
12.040
12.036
12.034
12.032
12.035
VOUT = 12V
VOUT = 12V
12.030
25
0
LOAD CURRENT (A)
STARTUP WAVEFORM
EN/UVLO RISING
toc03
12.040
12.055
94
EFFICIENCY (%)
toc02
12.060
96
82
LINE REGULATION
LOAD REGULATION
toc01
98
5
10
15
LOAD CURRENT (A)
20
25
-50
-45
-40
-35
-30
5V/div
1V/div
-25
STARTUP WAVEFORM WITH
PREBIASED OUTPUT VOLTAGE
toc06
toc05
5V/div
5V/div
5V/div
VOUT
-55
INPUT VOLTAGE (V)
5V/div
VPGOOD
-60
STARTUP WAVEFORM
LX_ SWITCHING
toc04
VEN/UVLO
12.030
ILOAD = 1A
VOUT
1V/div
1V/div
VOUT
VSS
VSS
VLX1
50V/div
VLX1
50V/div
VLX2
50V/div
VLX2
50V/div
VSS
5ms/div
SHUT-DOWN WAVEFORM
EN/UVLO FALLING
VEN/UVLO
SHUT-DOWN WAVEFORM
LX_ SWITCHING
toc07
5V/div
VPGOOD
5ms/div
5ms/div
DYNAMIC REFIN RAMP RESPONSE
17.5V TO 35V OUTPUT
toc08
VSS
5V/div
VLX1
50V/div
VLX2
50V/div
1V/div
5ms/div
www.maximintegrated.com
VREFIN
1V/div
VSS
1V/div
VPGOOD
5V/div
5V/div
1V/div
VSS
10V/div
VOUT
5V/div
VOUT
toc09
VOUT
5ms/div
10ms/div
Maxim Integrated │ 9
MAX15158/MAX15158A
High-Voltage Multiphase Boost Controller
Typical Operating Characteristics (continued)
(TA = -40°C to +125°C, VIN- = -48V, unless otherwise noted. See the Standard Application Circuits.)
CLOCK SYNCHRONIZATION
toc10
VOUT
10V/div
VREFIN
1V/div
VSS
1V/div
VPGOOD
VCLK
VOUT
500mV/div
ILOAD
10A/div
50V/div
VLX2
50V/div
10ms/div
2ms/div
2µs/div
BODE PLOT
12V OUTPUT WITH 0A LOAD
BODE PLOT
12V OUTPUT WITH 25A LOAD
toc13
toc14
80
160
80
160
60
120
60
120
40
80
40
80
20
40
20
40
0
0
0
0
GAIN (dB)
100
PHASE (°)
200
100
200
-20
-40
-80
-40
-80
-60
-120
-60
-120
-80
-160
-80
-160
-100
-200
-100
-20
-40
-40
1
10
100
toc12
2V/div
VLX1
5V/div
GAIN (dB)
LOAD TRANSIENT WAVEFORM
35V OUTPUT WITH 10A LOAD STEP
toc11
FREQUENCY (kHz)
1
10
PHASE (°)
DYNAMIC REFIN STEP RESPONSE
17.5V TO 35V OUTPUT
-200
100
FREQUENCY (kHz)
AUTO-RETRY AFTER
OVERCURRENT FAULT
OUTPUT OVERCURRENT WAVEFORM
toc16
toc15
VOUT
VOUT
5V/div
ILOAD
50A/div
VSS
2V/div
VPGOOD
5V/div
5V/div
ILOAD
50A/div
VPGOOD
5V/div
50V/div
VLX
200µs/div
www.maximintegrated.com
50ms/div
Maxim Integrated │ 10
MAX15158/MAX15158A
High-Voltage Multiphase Boost Controller
DRV
GND
EN/UVLO
BIAS
NC
NC
OUTN
OUTP
DRV
GND
EN/UVLO
BIAS
NC
NC
OUTN
OUTP
Pin Configuration
TOP VIEW
5mm x 5mm
TQFN
EP
1 2 3 4 5 6 7 8
DL2
DH2
+
24 23 22 21 20 19 18 17
16
15
14
13
12
11
10
9
NC
REFIN
FB
COMP
SS
OVP
ILIM
RAMP
DLFB1
DL1
DH1
CSP1
CSN1
CSN2
CSP2
DLFB2
25
26
27
28
29
30
31
32
+
24 23 22 21 20 19 18 17
TOP VIEW
5mm x 5mm
TQFN
EP
1 2 3 4 5 6 7 8
16
15
14
13
12
11
10
9
NC
NC
FB
COMP
SS
OVP
ILIM
RAMP
DL2
DH2
SYNC
FREQ/CLK
GND
CSION
CSIOP
PGOOD
25
26
27
28
29
30
31
32
SYNC
FREQ/CLK
GND
CSION
CSIOP
PGOOD
DLFB1
DL1
DH1
CSP1
CSN1
CSN2
CSP2
DLFB2
MAX15158
T3255-6
MAX15158A
T3255-6
Pin Description
PIN
NAME
FUNCTION
1
DL2
Logic Output for Low-Side MOSFET Gate Driver for the Second Phase. Connect DL2 to the second phase
external MOSFET driver low-side input pin.
2
DH2
Logic Output for High-Side MOSFET Gate Driver for the Second Phase. Connect DH2 to the second phase
external MOSFET driver high-side input pin.
3
SYNC
Multiphase Synchronization Pin. For single IC operation, leave this pin unconnected. Tie this pin together
when two MAX15158/MAX15158A ICs are stacked-up in master/slave operation mode.
4
FREQ/
CLK
Frequency Selection/Clock Synchronization Input. MAX15158/MAX15158A supports switching frequencies
from 120kHz to 1MHz. Set the switching frequency by either selecting the appropriate external resistor to use
the internal oscillator frequency, or by synchronizing the regulator to an external system clock (see Table 2).
Leave the FREQ/CLK pin unconnected to select the preset 300kHz switching frequency or place a resistor
between FREQ/CLK and GND to set the following: fSW = (RFREQ/100k) x 600kHz
5
GND
6
CSION
Negative Input of Master/Slave Current-Sense Signal. MAX15158/MAX15158A uses a differential currentsense signal to ensure proper startup and current-balance behavior in applications where two MAX15158/
MAX15158A ICs are stacked up in master/slave operation mode.
7
CSIOP
Positive Input of Master/Slave Current-Sense Signal. MAX15158/MAX15158A uses a differential currentsense signal to ensure proper startup and current-balance behavior in applications where two MAX15158/
MAX15158A ICs are stacked up in master/slave operation mode.
PGOOD
Open-Drain Power Good Output. MAX15158/MAX15158A pulls PGOOD low when the output voltage
exceeds the OVP threshold, or drops below the output UVP threshold, during soft-start and shutdown
(EN/UVLO pulled low). The PGOOD output goes high-impedance when the controller completes soft-start
and remains in regulation.
8
Analog Ground.
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Maxim Integrated │ 11
MAX15158/MAX15158A
High-Voltage Multiphase Boost Controller
Pin Description (continued)
PIN
NAME
FUNCTION
Slope Compensation Input. A resistor connected from RAMP to GND programs the amount of slope
compensation. See the Adjustable Slope Compensation (RAMP) section.
9
RAMP
10
ILIM
CSP_-CSN_ Cycle-by-Cycle/Hiccup Current Limit Threshold Selector. Connect a resistor from ILIM to GND
to select the protection value.
11
OVP
Program Pin. Connect a resistor from OVP to GND to configure FB overvoltage protection, single-phase or
dual-phase selection and FB level shifter selection (see Table 1).
12
SS
13
COMP
14
FB
REFIN
15
16,
19–20
Soft-Start Control. The capacitance (CSS) between SS to GND sets the startup period. An internal
pulldown MOSFET holds SS low until the controller begins the startup sequence.
Compensation Amplifier Output. COMP is the output of the internal transconductance error amplifier.
Connect a type II compensation network as shown in the Typical Application Circuit (See the Compensation
Design Guidelines section).
Feedback Input. When the FB level shifter is enabled, connect a resistor from FB to GND; when the FB
level shifter is disabled, connect FB to the center of a resistive divider between the output and GND. For
MAX15158A, FB regulates to the preset 2.0V reference voltage. For MAX15158, FB tracks the REFIN
voltage (REFIN between 0.4V and 2.2V) or regulates to the preset 2.0V reference voltage by connecting
REFIN to BIAS. Operation between 0.4V < REFIN < 1V is possible but the FB OVP is disabled. When two
MAX15158/MAX15158A ICs are stacked-up in master/slave operation mode, connect FB of the slave to
BIAS.
External Reference Input of MAX15158. REFIN sets the feedback regulation voltage when supplied with a voltage between 0.4V and 2.2V. Connect REFIN pin to BIAS to select internal 2.0V reference voltage. Operation
between 0.4V < REFIN < 1V is possible but the FB OV and UV fault functions are disabled.
NC
Not Connected. For MAX15158A, this pin is NC (Not Connected), where the controller selects internal 2.0V
reference voltage.
NC
Not Connected
OUTP
Positive Differential Output Voltage Sense Input. MAX15158/MAX15158A can operate in inverting
buck-boost mode and sense output voltage differentially using its internal FB level shifter. Connect a sense
resistor between OUTP and positive node of output as shown in the Typical Application Circuit. OUTP must
be shorted to OUTN and BIAS if the internal FB level shifter is disabled.
18
OUTN
Negative Differential Output Voltage Sense Input. MAX15158/MAX15158A can operate in inverting
buck-boost mode and sense output voltage differentially using its internal FB level shifter. Connect OUTN to
the negative node of output as shown in the Typical Application Circuit. Connect OUTN to OUTP and BIAS if
the internal FB level shifter is disabled.
21
BIAS
4.75V Linear Regulator Output and Controller Bias Supply. Bypass to GND with a 2.2µF or greater ceramic
capacitor.
22
EN/UVLO
Enable Control / Adjustable Undervoltage Lockout Input for Startup/Shutdown Power Sequencing. This
pin has two voltage thresholds with hysteresis. The lower threshold (0.7V rising / 0.55V falling) determines
whether the BIAS regulator is enabled/disabled. The higher threshold (1V rising / 0.9V falling) initiates softstart / soft-shutdown and enables switching. Connect EN/UVLO to the center of a resistor divider between
the input and GND to adjust the undervoltage lockout voltage level as shown in the Typical Application
Circuit.
23
GND
Analog Ground.
24
DRV
Supply Voltage Input. Provide a 8.5V to 14V supply for internal bias generation.
17
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Maxim Integrated │ 12
MAX15158/MAX15158A
High-Voltage Multiphase Boost Controller
Pin Description (continued)
PIN
NAME
FUNCTION
25
DLFB1
External MOSFET Status Feedback Pin for the First Phase. Connect DLFB1 to the center of a resistor divider between the gate of the low-side MOSFET of the first phase and GND. See the MOSFET Gate Control
section.
26
DL1
Logic Output for Low-Side MOSFET Gate Driver for the First Phase. Connect DL1 to the first phase external
MOSFET driver low-side input pin.
27
DH1
Logic Output for High-Side MOSFET Gate Driver for the First Phase. Connect DH1 to the first phase
external MOSFET driver high-side input pin.
28
CSP1
Positive Low-Side Differential Current-Sense Input for the First Phase. MAX15158/MAX15158A uses the
differential current-sense signal in the current-mode control loop, and multiphase current sharing.
Connect CSP1 to the "MOSFET side" of the current-sense resistor.
29
CSN1
Negative Low-Side Differential Current-Sense Input for the First Phase. MAX15158/MAX15158A uses
the differential current-sense signal in the current-mode control loop, and multiphase current sharing.
Connect CSN1 to the "ground side" of the current-sense resistor.
30
CSN2
Negative Low-Side Differential Current-Sense Input for the Second Phase. MAX15158/MAX15158A uses
the differential current-sense signal in the current-mode control loop, and multiphase current sharing.
Connect CSN2 to the "ground side" of the current-sense resistor.
31
CSP2
Positive Low-Side Differential Current-Sense Input for the Second Phase. MAX15158/MAX15158A uses
the differential current-sense signal in the current-mode control loop, and multiphase current sharing.
Connect CSP2 to the "MOSFET side" of the current-sense resistor.
32
DLFB2
External MOSFET Status Feedback Pin for the Second Phase. Connect DLFB2 to the center of a resistor
divider between the gate of the low-side MOSFET of the second phase and GND. See the MOSFET Gate
Control section.
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Maxim Integrated │ 13
MAX15158/MAX15158A
High-Voltage Multiphase Boost Controller
Block Diagram
CSP2
IB2
CSN2
CSIOP
CSION
CURRENT
BALANCE
2R
R
MAX15158
2R
1.23V
CSP1
IB1
CSN1
ILI M2
ILI M
IB1
ILI M
GENERATOR
CSP1
CMP1
ILI M2
DH1
ILI M1
DL1
CSN1
CLOCK
DISTRIBUTI ON
AND SL OPE
COM PENSATI ON
FREQ/CLK
SYNC
RAMP
DLFB1
PWM
CONTROL
LOGIC
CLKUP
DH2
DL2
CLKREF
DLFB2
IB2
RAMP
GENERATOR
CMP2
OUTP
CSP2
OUTN
CSN2
FEEDBACK LEV EL S HIFT
FB
ILI M1
COM P
FB
OVP
OVP
THRESHOL D
PGOOD
COM PARATORS
ILI M1
1V
ILI M2
50mV
EN/UVLO
0.7V
RISING
DRV
2.3V
DRV UVLO
BIAS
BIAS UVLO
STARTUP
AND FAULT
LOGIC
SS
2V REF
RESTA RT
2V
HICCUP
GND
BIAS SUPPL IES
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REFIN
THERMAL
SHUTDOW N
RESET
40mV
PGOOD
Maxim Integrated │ 14
MAX15158/MAX15158A
High-Voltage Multiphase Boost Controller
Block Diagram (continued)
CSP2
IB2
CSN2
CSIOP
CSION
CURRENT
BALANCE
2R
R
1.23V
ILI M
MAX15158A
2R
CSP1
IB1
CSN1
ILI M2
ILI M
GENERATOR
IB1
CMP1
CSP1
CSN1
CLOCK
DISTRIBUTI ON
AND SL OPE
COM PENSATI ON
FREQ/CLK
SYNC
RAMP
ILI M2
DH1
ILI M1
DL1
DLFB1
PWM
CONTROL
LOGIC
CLKUP
DH2
DL2
CLKREF
DLFB2
IB2
RAMP
GENERATOR
CMP2
OUTP
CSP2
OUTN
CSN2
FEEDBACK LEV EL S HIFT
FB
ILI M1
COM P
FB
OVP
OVP
THRESHOL D
1V
EN/UVLO
PGOOD
COM PARATORS
ILI M1
ILI M2
0.7V
RISING
DRV
DRV UVLO
BIAS
BIAS UVLO
STARTUP
AND FAULT
LOGIC
SS
2V REF
RESTA RT
2V
HICCUP
GND
BIAS SUPPL IES
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THERMAL
SHUTDOW N
RESET
40mV
PGOOD
Maxim Integrated │ 15
MAX15158/MAX15158A
Detailed Description
MAX15158/MAX15158A is a high-voltage multiphase
boost controller designed to support up to two MOSFET
drivers and four external MOSFETs in single-phase
or dual-phase boost/inverting-buck-boost configurations.
Two devices can be stacked up for quad-phase operation.
When configured as inverting-buck-boost converter, the
controller has an internal high-voltage FB level shifter to
differentially sense the output voltage. The output voltage
of MAX15158 can be dynamically set through the 1V to
2.2V reference input (REFIN) for modular design support. For MAX15158A the REFIN pin is removed, and the
internal 2.0V reference voltage is selected by default.
The switching frequency is controlled either through
an external resistor setting the internal oscillator or by
synchronizing the regulator to an external clock. The
device is designed to support 120kHz to 1MHz switching frequencies. When two devices are stacked up
as master-slave for quad-phase operation, the SYNC
pin of two devices are connected to ensure the clock
synchronization and phase interleaving. The controller
has a dedicated enable/input undervoltage-lockout (EN/
UVLO) pin to configure for flexible power sequencing.
MAX15158/MAX15158A has a dedicated RAMP pin to
adjust internal slope compensation. The device features
adjustable overcurrent protection. The device incorporates current sense amplifiers to accurately measure the
current of each phase across external sense resistors to
implement accurate phase current sharing. The controller
is also protected against output overvoltage, input undervoltage and thermal shutdown.
High Voltage Internal FB Level Shifter
MAX15158/MAX15158A can support both boost and
inverting-buck-boost applications. When configured
in inverting-buck-boost operation, the GND pin of the
device must be connected to the negative input voltage
terminal (VIN-), so that the ground of the IC is different
than the ground of output capacitor and load. Output
voltage cannot be controlled using a simple resistor
divider. MAX15158/MAX15158A has a dedicated internal
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High-Voltage Multiphase Boost Controller
FB level shifter to differentially sense the output voltage.
The internal FB level shifter can be enabled or disabled
by connecting a resistor from the OVP pin to GND (See
Overvoltage Protection (OVP) section). When the internal FB
level shifter is enabled, connect OUTN to the ground node
of the output capacitor and OUTP to the output terminal
using a resistor RFB1. FB is connected to GND (VIN-)
using a resistor RFB2. The output voltage is set by these
two resistors:
VOUT = (RFB1/RFB2) x VREF
For MAX15158, VREF can be externally supplied with a
voltage between 1V and 2.2V on the REFIN pin. By connecting the REFIN pin to BIAS, the default internal 2.0V
reference voltage is selected. For MAX15158A, VREF =
2.0V and cannot be externally controlled. When the FB
level shifter is enabled, the OUTN pin has a UVLO threshold
that controls the power sequencing. If the voltage on
OUTN falls below 7.0V (typ), the controller disables the
drivers (all driver outputs are pulled low) and discharges
the SS capacitor through a 4.3Ω pulldown MOSFET.
VOUT
RFB1
MAX15158 /
MAX15158A
OUTP
OUTN
FB
RFB2
GND
VIN-
Figure 1. Using Internal FB Level Shifter
Maxim Integrated │ 16
MAX15158/MAX15158A
High-Voltage Multiphase Boost Controller
For inverting-buck-boost applications where VIN is higher
than 76V, MAX15158/MAX15158A can still be used but
an external level shifter is required. The internal FB level
shifter must be disabled. Pin OUTP and OUTN must be
tied to BIAS. An example of using external FB level shifter
is shown in Figure 2. Two matched PNP transistors are
used. The output voltage is given by:
differential voltage across CSP_ and CSN_ does not
exceed the cycle-by-cycle peak current limit threshold
(see the Overcurrent Protection (OCP) section). The
differential voltage across CSP_ and CSN_ is amplified 8
times by a current sense amplifier. A high-frequency RC
noise filter is suggested across the sense resistor. The RC
time constant should not exceed 30ns.
VOUT = (1 + RFB1/RFB2) x VREF
When operating in boost mode, the internal FB level shifter
is disabled. Pin OUTP and OUTN must be tied to BIAS,
and the FB pin must be connected to the center of a resistor divider from output to GND as shown in Figure 3. When
the resistor divider is used, the output voltage is given by:
The error between the output voltage feedback (VFB)
and reference voltage (VSS) is fed to the input of
an error amplifier. The output of the error amplifier
(COMP) is required to connect to a type-II compensation
network for control loop stability (see the Compensation
Design Guidelines section). A slope compensation ramp
generator is also used. The slope of the compensation
ramp can be adjusted by connecting a resistor between
RAMP and GND (see the Adjustable Slope Compensation
(RAMP) section).
VOUT = (1 + RFB1/RFB2) x VREF
Peak-Current-Mode Control Loop
The controller relies on a fixed-frequency, peak-currentmode architecture to regulate the output. A detailed
block diagram of the control loop is shown in Figure 4.
A sense resistor is required between the source of the
low-side MOSFET and GND for current sensing. The
sense resistor should be selected so that the maximum
The controller drives on the low-side MOSFET (DL_
driven high) on each rising clock edge. When the PWM
comparator detects that the sum of the current-sense
amplifier output (VCS_), the slope compensation ramp
and the phase current imbalance signal exceeds the
COMP voltage, the controller pulls DL_ low and drives
DH_ high.
VOUT
VOUT
RFB1
RFB1
MAX15158 /
MAX15158A
MAX15158 /
MAX15158A
BIAS
OUTP
OUTP
OUTN
DISABLE INTERNAL
FB LEVEL SHIFTER
BIAS
OUTN
DISABLE INTERNAL
FB LEVEL SHIFTER
FB
FB
RFB2
RFB2
GND
RFB1
GND
VINVIN-
Figure 2. Using External FB Level Shifter
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Figure 3. Using External FB Resistor Divider
Maxim Integrated │ 17
MAX15158/MAX15158A
VIN
L
High-Voltage Multiphase Boost Controller
VOUT*
HIGHSIDE
MOSFET
MAX15158 /
MAX15158A
IRAMP
RAMP
LOWSIDE
MOSFET
CLOCK
DH_
RAMP
GENERATOR
RRAMP
VSLOPE = 1.9 × IRAMP × RRAMP
PHASE CURRENT
IMBALANCE
GND
GND
CSP_
RSENSE
VCS_ = 8.3 × (VCSP_ - VCSN_)
∑
CSN_
ERROR
AMPLIFIER
FB
GND
GND
CCOMP
PWM
CONTROL
LOGIC
DL_
PWM
COMPARATOR
SS
RCCOMP
COMP
GND
CPAR
TYPE-II COMPENSATION
*FOR BOOST APPLICATIONS VOUT IS REFERRED TO GND; FOR INVERTING-BUCK-BOOST
APPLICATIONS VOUT IS REFERRED TO VIN
Figure 4. Peak-Current-Mode Control Loop
Compensation Design Guidelines
MAX15158/MAX15158A utilizes a fixed-frequency, peak
current-mode control scheme to provide easy compensation
and fast transient response. It is by nature for boost or
inverting-buck-boost converters to have a right half plane
(RHP) zero in their small signal control-to-output transfer
function. For boost converters, the location of RHP zero
is calculated by:
fRHP = VOUT x (1 - D)2 / (2 x π x IOUT(MAX) x L)
where:
IOUT(MAX) = Maximum load current per phase
For stable operation, it is required that the bandwidth
of control loop (BW) is sufficiently lower than fRHP and
switching frequency (fSW).
BW ≤ Minimum(fRHP/7, fSW/10)
A type-II compensation network is required to be
connected between COMP and GND (RCOMP, CCOMP
and CPAR in Figure 4) to provide sufficient phase margin
and gain margin to the control loop. The value of the
compensation network can be selected by:
RCOMP = 16 x π x BW x RSENSE x COUT x VOUT/
[N x (1 - D) x GMEA x VREF]
CCOMP = 5/(π x RCOMP x BW)
CPAR = 1/(2 x π x RCOMP x fSW)
D = Duty cycle = 1 - VIN/VOUT
L = Value of the inductor
For inverting-buck-boost converters, the location of RHP
zero is calculated by:
fRHP = VOUT x (1 - D)2 / (2 x π x IOUT(MAX) x L x D)
where,
RSENSE = Value of the sense resistor
COUT = Value of the output capacitor
where:
N = Number of phases
D = Duty cycle = VOUT/(|VIN| + VOUT)
GMEA = Error Amplifier Transconductance (1.1mS, typ)
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Maxim Integrated │ 18
MAX15158/MAX15158A
Adjustable Slope Compensation (RAMP)
When MAX15158/MAX15158A operates at a duty cycle
greater than 50%, additional slope compensation is
required to ensure stability and prevent subharmonic
oscillations that occurs naturally in peak-current-mode
controlled converters operating in continuous-conductionmode (CCM). MAX15158/MAX15158A provides RAMP
input to select the internal slope compensation ramp
within a range of 230mV ~ 730mV. It is recommended
that discontinuous-conduction-mode (DCM) designs also
use this minimum amount of slope compensation to
provide better noise immunity and jitter-free operation.
As shown in Figure 4, by connecting a resistor (RRAMP)
between RAMP and GND, the amplitude of the slope
compensation ramp is calculated as:
VSLOPE = 1.9 x VRAMP = 1.9 x IRAMP x RRAMP
where IRAMP is the current sourced from RAMP to GND
(10μA typ)
To guarantee stable and jitter-free operation, it is
suggested to select the RAMP resistor that:
RRAMP ≥ 5 x (VOUT(MAX) - VIN(MIN))
x RSENSE/(IRAMP x fSW x L)
where:
VOUT(MAX) = Maximum output voltage referred to GND
VIN(MIN) = Minimum input voltage referred to GND
RSENSE = Value of the sense resistor
fSW = Switching frequency
L = Value of the inductor
DRV Supply and Bias Regulator (BIAS)
The controller requires an external 8.5V to 14V DRV supply.
The DRV supply powers the internal linear regulator that
generates a regulated 4.75V bias supply to power the
internal analog and digital control circuitry as shown in
the Block Diagram. Bypass the BIAS pin with a 2.2μF
or greater ceramic capacitor to maintain noise immunity
and stability. The BIAS regulator provides up to 50mA of
load current and the controller requires up to 5mA, so the
remaining load capability can be used to support pullup
resistors.
The controller has an undervoltage-lockout threshold on
DRV. The undervoltage-protection circuits inhibit switching
until DRV rises above 8.196V (typ).
If DRV drops below its undervoltage threshold, the controller determines that there is insufficient supply voltage
to make valid control decisions. To protect the regulator
and the output, the controller immediately pulls PGOOD
low, disables the drivers (all driver outputs pulled low),
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High-Voltage Multiphase Boost Controller
and discharges the SS capacitor through an internal
4.3Ω discharge MOSFET, placing the regulator into a
high-impedance output state, so the output capacitance
passively discharges through the load current.The BIAS
linear regulator and internal reference power up only
when DRV exceeds its undervoltage-lockout threshold
and EN/UVLO is driven high.
EN/UVLO and Soft-Start/Shutdown
The EN/UVLO pin allows the input voltage operating
range to be externally adjusted for power-sequence
control. Connect EN/UVLO to the center of a resistor
divider between the input and GND to adjust the undervoltage lockout voltage level as shown in the Typical
Application Circuit. In the case where the DRV voltage
threshold of the external MOSFET driver is higher than
the undervoltage lockout threshold of the DRV pin, the
EN/UVLO pin should also be pulled to GND before the
external MOSFET driver is enabled. The EN/UVLO pin
has two levels of thresholds with hysteresis. At powerup, once the voltage of the EN/UVLO pin is higher than
0.7V (typ) and DRV voltage is higher than its UVLO
threshold, the internal 4.75V BIAS regulator is enabled.
Once the voltage of EN/UVLO is higher than 1V (typ),
and the internal reference stabilizes, the controller starts
the initialization period where the OVP pin configuration
is checked. During this initialization period, the controller pulls SS low through a 4.3Ω discharge MOSFET. As
long as initialization is complete, the controller starts the
soft-start sequence by charging the SS capacitor with a
constant 5μA current source until the SS voltage reaches
either the preset 2.0V target voltage (MAX15158A or
MAX15158 with REFIN connected to BIAS), or the externally driven REFIN voltage (MAX15158, VREFIN = 1V to
2.2V). The drivers start switching once SS exceeds 50mV
and the controller detects that FB voltage is below the
SS voltage. The controller enables the overvoltage faultprotection circuitry when SS exceeds 1V.
At power-down, once the voltage of EN/UVLO is below
0.9V (typ), the controller pulls PGOOD low and initiates the
soft-shutdown sequence by discharging the SS capacitor
with a constant 5μA current load. Since the output voltage
tracks the SS voltage, the regulator actively discharges
the output capacitors. Once the SS and FB voltage
reaches 40mV, the controller stops switching and enters
a low-power shutdown state. The device does not restart
until the soft-shutdown sequence has completed. During
the soft-shutdown cycle, the overvoltage fault protection remains active until the SS voltage falls below 1V. If
the voltage of EN/UVLO is below 0.55V (typ) after softshutdown is complete, the 4.75V BIAS regulator is then
disabled (see Figure 5).
Maxim Integrated │ 19
MAX15158/MAX15158A
High-Voltage Multiphase Boost Controller
DRV
1V
EN/UVLO
0.9V
0.7V
0.55V
tDELAY
BIAS
SS
tINIT
50mV
40mV
PWM
PGOOD
Figure 5. Soft-Start and Shutdown Sequence with EN/UVLO
Overcurrent Protection (OCP)
A current-sense resistor (R40 and R41 in the Standard
Application Circuits) is connected between the source of
the low-side MOSFET and GND. MAX15158/MAX15158A
detects the current-sense signal (CSP_ to CSN_) and
compares it with the cycle-by-cycle peak current limit
threshold during low-side on-time. When the current
exceeds the cycle-by-cycle peak current limit threshold,
the device turns off the low-side MOSFET and turns on
the high-side MOSFET to allow the inductor current to
be discharged until the end of that switching cycle. Each
phase has an independent up-down counter to accumulate
the number of consecutive peak current limit events. If
the counter exceeds 32, the device disables the drivers
(all driver outputs are pulled low) and discharges the SS
capacitor. After 32,768 clock cycles, the device automatically
attempts to restart using the soft-start sequence.
There is a secondary fast positive overcurrent protection
(FPOCP) threshold, which is 33% higher than the cycleby-cycle peak current limit threshold. If the inductor peak
current exists the FPOCP threshold for two cycles, the
device disables the drivers (all driver outputs are pulled
low) and discharges the SS capacitor. After 32,768 clock
cycles, the device automatically attempts to restart using
the soft-start sequence.
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The cycle-by-cycle peak current limit threshold is set by a
resistor at ILIM pin. A 10μA source current flows into the
resistor and generates a voltage level. This voltage level
is internally scaled by a factor of 0.10 to set cycle-by-cycle
peak current limit threshold. The minimum and maximum
settable current limit levels are 20mV and 100mV. The
cycle-by-cycle peak current limit level is given by:
VOCP = 0.10 x 10μA x RILIM
The maximum peak inductor current is set by both VOCP
and the current-sense resistor (RSENSE).
IPEAK(MAX) = VOCP/RSENSE
The device also has a negative overcurrent protection
(NOCP) threshold which is -83% of the cycle-by-cycle
peak current limit threshold. When the low-side MOSFET
is turned on and the inductor current is below the NOCP
threshold, the device will command to keep the low-side
MOSFET on to allow the inductor current to be charged
by the input voltage, until the inductor current is above
the NOCP threshold. Each phase has an independent
up-down counter to accumulate the number of consecutive
NOCP events. If the counter exceeds 32, the device
disables the drivers (all driver outputs are pulled low) and
discharges the SS capacitor. After 32,768 clock cycles,
the device automatically attempts to restart using the
soft-start sequence.
Maxim Integrated │ 20
MAX15158/MAX15158A
High-Voltage Multiphase Boost Controller
Overvoltage Protection (OVP)
MAX15158/MAX15158A has an OVP comparator to
monitor the FB voltage. The device can be configured
to disable OVP or select OVP threshold of 110% by
connecting a resistor from the OVP pin to GND. FB OVP
is also disabled when the voltage on the SS pin is below
1V. Once OVP is enabled, the drivers start switching, and
voltage on the SS pin is higher than 1V, the FB overvoltage
comparator trips if the feedback voltage exceeds the SS
voltage by 110% for more than 128 PWM clock cycles. If
the overvoltage comparator is triggered, the controller pulls
PGOOD low, discharges the SS capacitor and disables
the drivers. The controller immediately restarts once the
fault condition has been removed. When OVP is disabled,
the PGOOD will remain high when FB voltage is higher
than the reference voltage.
The resistor from OVP pin to GND is also used to enable
or disable the FB level shifter and select single or dual
phase operation. Refer to the Table 1.
Thermal Shutdown (TSHDN)
The controller features a thermal fault-protection circuit.
When the junction temperature rises above +165°C,
the internal thermal sensor triggers the fault protection,
disables the drivers, and discharges the SS capacitor.
The controller remains disabled until the junction
temperature cools by 15°C. Once the device has cooled
down the controller automatically restarts using the
soft-start sequence.
Switching Frequency (FREQ/CLK)
The controller supports 120kHz to 1MHz switching
frequencies. Leave FREQ/CLK unconnected to select
the preset 300kHz switching frequency. To adjust the
switching frequency, either place an external resistor from
FREQ/CLK to AGND, or drive FREQ/CLK with an external
system clock (see Table 2). The resistively programmable
switching frequency is determined by:
Table 1. FB OVP Settings, Phase and FB Level Shifter Configuration
OVP PIN VOLTAGE (V)
ROVP
FB OVP THRESHOLD
FB LEVEL SHIFTER
0.10 ± 0.05
GND
110%
DISABLED
0.33 ± 0.05
33kΩ
DISABLED
ENABLED
0.68 ± 0.05
68kΩ
110%
ENABLED
1.00 ± 0.05
100kΩ
DISABLED
DISABLED
1.33 ± 0.05
133kΩ
DISABLED
ENABLED
1.69 ± 0.05
169kΩ
110%
ENABLED
2.05 ± 0.05
205kΩ
DISABLED
DISABLED
2.53 ± 0.05
OPEN
110%
DISABLED
PHASE CONFIGURATION
Dual-phase or
quad-phase operations
Single-phase operation
Table 2. Phase and Master/Slave Configurations
NUMBER OF PHASES
NUMBER OF
MAX15158/MAX15158A
FB OF SLAVE
CONNECTED TO BIAS
CLK FREQUENCY
1
1
N/A
4 x fSW
2
1
N/A
4 x fSW
4
2
Yes
4 x fSW
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Maxim Integrated │ 21
MAX15158/MAX15158A
fSW = (RFREQ/100kΩ) x 600kHz
Phase and Master/Slave Configurations
MAX15158/MAX15158A can be configured in singlephase, dual-phase or quad-phase operation modes.
When supporting quad-phase operation, two MAX15158/
MAX15158A ICs are used as master and slave. The
controller identifies the number of phases by the resistor
at the OVP pin. This identification is used to determine
how the controller responds to the multiphase clock signal
generated by the primary phase.
For proper synchronization between two devices, connect
the SYNC, SS, COMP, CSIOP and CSION of the master
and slave devices. The FB, REFIN, OUTP and OUTN of
the slave device are connected to its BIAS pin (see the
Standard Application Circuits).
The two phases of the same device are interleaved 180°.
When two MAX15158/MAX15158A ICs are stacked up,
there is a 90° phase shift between master and slave
(Figure 6).
Multiphase Current Balance
MAX15158/MAX15158A monitors the low side MOSFET
current of each phase for active phase current balancing in
multiphase operations. The current imbalance is applied
to the cycle-by-cycle current sensing circuitry as a feedback, helping regulating so that load current is evenly
shared between the two phases (see the Block Diagram).
In quad phase operation, the device uses the differential
CSIO_ connections to communicate the average per-chip
current between master and slave. The current-mode
master and slave devices regulate their current so that all
four phases share the load current equally.
MOSFET Gate Control
High-Voltage Multiphase Boost Controller
MAX15158/MAX15158A must be used with external
MOSFET drivers to drive power MOSFETs for typical
high-voltage applications. The device has dedicated
DLFB_ pins to detect the gate voltage of the low-side
MOSFETs to ensure no-shoot-through between the highand low-side MOSFETs due to the mismatch delays
caused by the external MOSFET driver. The DLFB_ pins
have a rising threshold of 0.8V (typ) and falling threshold
of 0.5V (typ). A resistor divider can be used from the gate
of the low-side MOSFET to DLFB_ pins to match the
MOSFET gate threshold voltage and the DLFB_ threshold
(see the Standard Application Circuits), to allow robust
operation with a wide range of MOSFETs while minimizing
dead-time power losses.
Inductor Selection
A larger inductor value results in reduced inductor ripple
current, leading to a reduced inductor core loss. However,
a larger inductor value results in either a larger physical
size or a higher series resistance (DCR) and a lower
saturation current rating. Typically, inductor value is
chosen to have current ripple (ΔIL) around 50% of
average inductor current. The average inductor current is
can be calculated by:
IL(AVE) = ILOAD(MAX)/[(1 – D) x N]
where:
N = Number of phases
The inductor can be chosen with the following formula:
L = D x VIN/(fSW x ΔIL)
Output Capacitor Selection
The output capacitors are selected to improve stability,
output voltage ripple and load transient performance. To
meet output voltage ripple (VRIPPLE) requirement, the
output capacitor can be selected by:
COUT(RIPPLE) = ILOAD(MAX) x D/(N x fSW x VRIPPLE)
CLK
MASTER
PHASE 1
MASTER
PHASE 2
SLAVE
PHASE 3
SLAVE
PHASE 4
For some applications it is desired to limit output voltage
overshoot and undershoot during load transient. To meet
the load transient requirement, the output capacitor can
be selected by:
COUT(TRANSIENT) = ΔILOAD/(3 x BW x ΔVOUT)
where:
ΔILOAD = Load current step,
BW = The control loop bandwidth (see Compensation
Design Guidelines),
ΔVOUT = The desired output voltage overshoot or undershoot.
Figure 6. Quad Phase Synchronization (Master/Slave)
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Maxim Integrated │ 22
MAX15158/MAX15158A
The final output capacitance should be selected as:
COUT ≥ Maximum (COUT(RIPPLE), COUT(TRANSIENT))
Input Capacitor Selection
The input capacitors are selected to help reduce input
voltage ripple (VIN_RIPPLE). For boost converters, the
input current is continuous. Neglecting ESR and ESL of
the input capacitor, the input capacitor can be selected by:
CIN = ΔIL/(8 x N x fSW x VIN_RIPPLE)
For inverting-buck-boost converters, the input current is
discontinuous. The input capacitor can be selected by:
CIN = ILOAD(MAX) x D/(N x fSW x VIN_RIPPLE).
PCB Layout Guidelines
PCB layout can dramatically affect the performance of the
power converter. A poorly designed board can degrade
efficiency, thermal performance, noise control, and even
control-loop stability. At higher switching frequencies, layout issues are especially critical.
As a general guideline, the input capacitors, inductor,
MOSFETs, sense resistor and output capacitors should
be placed close together to minimize the high frequency
current path. The MOSFET driver should be placed close
to the MOSFETs and the switching node (SW) to keep
the gate drive, BST and SW traces short. MAX15158/
MAX15158A should keep some distance from the high
dv/dt SW, BST, and gate drive traces. The peripheral RC
components should be placed as close to the controller as
possible. Priority should be given to the pins that are
sensitive to noise (COMP, SS, REFIN, FB, etc.). It is
suggested to place both differential-mode and commonmode filters between the CSP_ pin, CSN_ pin, and sense
resistor (see the Standard Application Circuits).
www.maximintegrated.com
High-Voltage Multiphase Boost Controller
For high power applications, it is suggested to use
planes for the power traces VIN, VOUT, and GND. It is
important to have enough vias connecting the power
planes in different layers. The signal and power grounds
must be seperated. All the power components, including
input and output capacitors, MOSFETs, sense resistor
and MOSFET driver should be connected to the power
ground. MAX15158/MAX15158A and its peripheral RC
components must be connected to the signal ground. It
is suggested to have an island of signal ground in the
closest internal layer underneath the controller. Multiple
vias can be used to connect the signal ground island to
the exposed pad of the controller and the ground nodes of
the noise sensitive signal (COMP, SS, REFIN, FB, etc.).
Signal ground should be tied to power ground through a
short trace or 0Ω resistor, close to the power ground node
of the sense resistor and input capacitors.
When the FB level shifter is used, the OUTP/OUTN
sense lines must be routed differentially directly from the
load points. The current sense lines from sense resistor
to CSP_ and CSN_ should also be routed differentially.
When the controller is configured to multiphase operation,
the current sense lines of different phases should be kept
apart to avoid signal coupling. Keep all sense lines and
other noise sensitive signals (CSIO_, COMP, SS, REFIN,
FB, etc.) away from the noisy traces (SW, BST, gate
drives, FREQ/CLK, SYNC, etc.).
Maxim Integrated │ 23
MAX15158/MAX15158A
High-Voltage Multiphase Boost Controller
Standard Application Circuits
Dual-Phase Inverting Buck-Boost Converter
C1, C2... C16
16x 1210 4.7µF X7R 100V
VIN- = -8V TO -65V
R19 200kΩ
C29 47nF
VINEN/UVLO
R20 30kΩ
DRV
8V TO 14V
W.R.T. VIN-
VIN-
DRV
C39 1µF
ILIM
R17 55kΩ
R14
35kΩ
OUTN
FB
R24 2kΩ
VIN-
BIAS
C40 2.2µF
R32 10kΩ
C21 0.1µF
DH
L1 10µH
SER2915H-103KL
COMP
C36 100pF
C33 47nF
R53 3kΩ
R54 1kΩ
C25 1nF
R40
3mΩ 1%
C17 1nF
CSN1
C26 1nF
VIN-
DRV
8V TO 14V W.R.T. VINVIN-
FREQ/CLK DH2
IN_H
VDD BST
C23 0.1µF
DH
R16 41.2kΩ
L2 10µH
SER2915H-103KL
MAX15013
R21 39.2kΩ
RAMP
GND
VIN-
GND
CSIOP
CSIOP
CSION
CSION
MULTIPHASE SIGNALS
SYNC
R55 3kΩ
R56 1kΩ
C25 1nF
VIN-
CSP2
R36 10Ω
CSN2
C28 1nF
N4 150V NFET
BSC110N15NS5
VIN-
R41
3mΩ 1%
C18 1nF
VIN-
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DL
VIN-
DLFB2
N3 150V NFET
BSC110N15NS5
HS
IN_L
DL2
EP
SYNCCLK
C41 to C50
10x 1210 10µF X7R 63V
R7 10Ω
VIN-
SS
VIN-
R6 10Ω
VIN-
CSP1
VIN-
N2 150V NFET
BSC110N15NS5
DL
VIN-
DLFB1
N1 150V NFET
BSC110N15NS5
HS
IN_L
DL1
REFIN
C32 10nF
CLK
DH1
VDD BST
GND
PGOOD
C35 68nF
IN_H
VIN-
PGOOD
R22 6.2kΩ
DRV
8V TO 14V W.R.T. VIN-
MAX15013
VIN-
R8 100kΩ
C31 to C40
10x 1210 10µF OUT
17.5V TO 38.5V
X7R 63V
VIN-
OVP
R18 33kΩ
REFIN
1V TO 2.2V
W.R.T. VIN-
OUTP
MAX15158
VIN-
VIN-
R37 10Ω
VIN-
Maxim Integrated │ 24
MAX15158/MAX15158A
High-Voltage Multiphase Boost Controller
Standard Application Circuits (continued)
Single-Phase Boost Converter
C1, C2... C16
16x 1210 4.7µF X7R 50V
VIN = 8V TO 24V
R19 200kΩ
C31 to C40
10x 1210 10µF
X7R 63V
C29 47nF
R20 30kΩ
DRV
8V TO 14V
C39 1µF
EN/UVLO
DRV
DRV 8V TO 14V
MAX15158A
R17 55kΩ
R18 220kΩ
C40 2.2µF
ILIM
IN_H
DH1
DH
BIAS
GND
DLFB1
C25 1nF
C33 47nF
SS
N1 80V NFET
BSC030N08NS5
DL
R53 3kΩ
N2 80V NFET
BSC030N08NS5
R54 1kΩ
R6 10Ω
C17 1nF
CSN1
COMP
C35 68nF
L1 4.7µH
SER2915H-472KL
HS
IN_L
DL1
CSP1
C36 100pF
C21 0.1µF
MAX15013
PGOOD
R22 6.2kΩ
VDD BST
OVP
R8 100kΩ
PGOOD
R40
3mΩ 1%
R7 10Ω
C26 1nF
R14
46kΩ
FB
CLK
OUT 48V
FREQ/CLK
R16 41.2kΩ
R24 2kΩ
DH2
R21 39.2kΩ
RAMP
GND
EP
DL2
DLFB2
CSP2
CSN2
CSIOP
CSIOP
CSION
CSION
OUTP
SYNC
OUTN
SYNCCLK
VBIAS
MULTIPHASE SIGNALS
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Maxim Integrated │ 25
MAX15158/MAX15158A
High-Voltage Multiphase Boost Controller
Standard Application Circuits (continued)
Quad Phase Interconnects (Inverting Buck-Boost Converter)
EN
CLK
CSION
SS
OUTN
FB
OUTP
BIAS/PV
SS
OUTN
REFIN
OUTP
FB
REFIN
BIAS/PV
SYSTEM
CSIOP
SYNC
COMP
SYNC
COMP
DAC
EN/UVLO
FREQ/CLK
U2-SLAVE
CSION
CSIOP
EN/UVL
O
-48V
FREQ/CLK
U1_MASTER
-48V
-48V -48V
-48V
-48V
-48V
LOAD
OUTPUT
-48V
-48V
POWER STAGE
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POWER STAGE
-48V
POWER STAGE
-48V
POWER STAGE
Maxim Integrated │ 26
MAX15158/MAX15158A
High-Voltage Multiphase Boost Controller
Ordering Information
PART NUMBER
TEMP RANGE
PIN-PACKAGE
MAX15158ATJ+
-40°C to +125°C
32 TQFN-EP*
MAX15158ATJ+T
-40°C to +125°C
32 TQFN-EP*
MAX15158AATJ+
-40°C to +125°C
32 TQFN-EP*
MAX15158AATJ+T
-40°C to +125°C
32 TQFN-EP*
+ Denotes a lead(Pb)-free/RoHS-complian package.
T = Tape and reel.
*EP = Exposed pad.
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Maxim Integrated │ 27
MAX15158/MAX15158A
High-Voltage Multiphase Boost Controller
Revision History
REVISION
NUMBER
REVISION
DATE
PAGES
CHANGED
0
6/18
Initial release
1
9/18
Updated Electrical Characteristics table, Block Diagrams, OVP section, added
Inductor Selection section, and update Ordering Information table
2
11/19
Updated General Description, Benefits and Features sections, Electrical
Characteristics, Pin Description, Block Diagrams, and Detailed Description
DESCRIPTION
—
4, 6, 7, 13, 14,
16, 17, 19, 21, 25
1, 4–7, 10, 11,
13–20
For pricing, delivery, and ordering information, please visit Maxim Integrated’s online storefront at https://www.maximintegrated.com/en/storefront/storefront.html.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
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