19-2861; Rev 2; 1/05
KIT
ATION
EVALU
E
L
B
AVAILA
Dual Step-Down Controllers with Saturation
Protection, Dynamic Output, and Linear Regulator
Features
The MAX1540/MAX1541 dual pulse-width modulation
(PWM) controllers provide the high efficiency, excellent
transient response, and high DC-output accuracy necessary for stepping down high-voltage batteries to generate low-voltage chipset and RAM power supplies in
notebook computers.
The Maxim proprietary Quick-PWM™ controllers are
free running, constant on-time with input feed forward.
This configuration provides ultra-fast transient
response, wide input-output (I/O) differential range, low
supply current, and tight load-regulation characteristics. The controllers can accurately sense the inductor
current across an external current-sense resistor in
series with the output to ensure reliable overload and
inductor saturation protection. Alternatively, the controllers can use the synchronous rectifier itself or lossless inductor current-sensing methods to provide
overload protection with lower power dissipation.
♦ Inductor-Saturation Protection
♦ Accurate Differential Current-Sense Inputs
♦ Dual Ultra-High-Efficiency Quick-PWMs with
100ns Load-Step Response
♦ MAX1540
1.8V/1.2V Fixed or 0.7V to 5.5V Adjustable
Output (OUT1)
2.5V/1.5V Fixed or 0.7V to 5.5V Adjustable
Output (OUT2)
Fixed 5V, 100mA Linear Regulator
♦ MAX1541
External Reference Input (REFIN1)
Dynamically Selectable Output Voltage—0.7V
to 5.5V (OUT1)
2.5V/1.8V Fixed or 0.7V to 5.5V Adjustable
Output (OUT2)
Optional Power-Good and Fault Blanking
During Transitions
Fixed 5V or Adjustable 100mA Linear Regulator
♦ 1% VOUT Accuracy over Line and Load
♦ 2V to 28V Battery Input Range
♦ 170kHz to 620kHz Selectable Switching
Frequency
♦ Overvoltage/Undervoltage-Protection Option
♦ 1.7ms Digital Soft-Start
♦ Drives Large Synchronous-Rectifier FETs
♦ 2V ±0.7% Reference Output
♦ Separate Power-Good Window Comparators
For a single step-down PWM controller with inductorsaturation protection, external-reference input voltage,
and dynamically selectable output voltages, refer to the
MAX1992/MAX1993 data sheet.
Applications
Notebook Computers
Core/IO Supplies as Low as 0.7V
0.7V to 5.5V Supply Rails
CPU/Chipset/GPU with Dynamic Voltage Core
Supplies (MAX1541)
Pin Configurations
Ordering Information
ON1
ON2
CSP1
CSN1
FB1
OUT1
PGOOD1
DH1
30
29
28
27
26
25
OVP/UVP
1
24
LX1
SKIP
2
23
BST1
TEMP RANGE
PIN-PACKAGE
LSAT
3
22
LDOON
MAX1540ETJ
-40°C to +85°C
32 Thin QFN 5mm x 5mm
TON
4
21
DL1
MAX1541ETL
-40°C to +85°C
40 Thin QFN 6mm x 6mm
VCC
5
20
LDOOUT
ILIM1
6
19
V+
ILIM2
7
18
DL2
REF
8
17
GND
9
10
11
12
13
14
15
16
CSP2
FB2
OUT2
PGOOD2
DH2
LX2
BST2
MAX1540
CSN2
PART
TOP VIEW
31
Active Termination Buses (MAX1541)
32
DDR Memory Termination (MAX1541)
THIN QFN
Quick-PWM is a trademark of Maxim Integrated Products, Inc.
Pin Configurations continued at end of data sheet.
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX1540/MAX1541
General Description
MAX1540/MAX1541
Dual Step-Down Controllers with Saturation
Protection, Dynamic Output, and Linear Regulator
ABSOLUTE MAXIMUM RATINGS
V+, LDOON to GND ...............................................-0.3V to +28V
LDOOUT to GND (MAX1540, Note 1) ......................-0.3V to +6V
LDOOUT to GND (MAX1541, Note 1) ....................-0.3V to +28V
VDD to GND (MAX1541, Note 1) ..............................-0.3V to +6V
VCC, ON_ to GND.....................................................-0.3V to +6V
SKIP, PGOOD_ to GND............................................-0.3V to +6V
FB_, CSP_, ILIM_ to GND.........................................-0.3V to +6V
TON, OVP/UVP, LSAT to GND ...................-0.3V to (VCC + 0.3V)
REF, OUT_ to GND.....................................-0.3V to (VCC + 0.3V)
LDOIN to GND (MAX1541).....................................-0.3V to +28V
REFIN1, GATE, OD, FBLDO to GND (MAX1541).....-0.3V to +6V
FBLANK, CC1 to GND (MAX1541).............-0.3V to (VCC + 0.3V)
DL_ to GND (Note 1) ..................................-0.3V to (VDD + 0.3V)
CSN_ to GND ............................................................-2V to +30V
DH_ to LX_..................................................-0.3V to (BST + 0.3V)
LX_ to GND................................................................-2V to +30V
BST_ to LX_ ..............................................................-0.3V to +6V
REF Short Circuit to GND ...........................................Continuous
Continuous Power Dissipation (TA = +70°C)
32-Pin 5mm x 5mm Thin QFN (derated 21.3mW/°C
above +70°C).............................................................1702mW
40-Pin 6mm x 6mm Thin QFN (derated 26.3mW/°C
above +70°C).............................................................2105mW
Operating Temperature Range
MAX154_ET_ ...................................................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Note 1: For the MAX1540, the gate-driver input supply (VDD) is internally connected to the fixed 5V linear-regulator output (LDOOUT),
and the linear-regulator input supply (LDOIN) is internally connected to the battery voltage input (V+).
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V+ = 15V, VCC = VDD = ON1 = ON2 = 5V, SKIP = GND, LDOIN (MAX1541) = V+, TA = 0°C to +85°C, unless otherwise noted. Typical
values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
INPUT SUPPLIES (Note 1)
VIN
Input Voltage Range
VBIAS
VLDOIN
MAX1540: battery voltage, V+ > VLDOOUT
5.5
28
MAX1541: battery voltage, V+ > VLDOOUT
2
28
VCC, VDD (MAX1541)
4.5
5.5
MAX1541: LDO input supply,
VLDOIN > VLDOOUT
4.5
28
FB1 and FB2 forced above the regulation
point, LSAT = GND
Quiescent Supply Current (VCC)
Quiescent Supply Current
(VDD, MAX1541 Only)
Quiescent Supply Current (V+)
ICC
IDD
IV+
Standby Supply Current (VCC)
2
ILDOIN
1.5
mA
FB1 and FB2 forced above the regulation
point, ON1 or ON2 = VCC, VLSAT > 0.5V
FB1 and FB2 forced above the regulation
point, ON1 or ON2 = VCC
1.8
ILOAD + COUT V
dt
Adding a capacitor across REFIN1 and GND filters
noise and controls the rate of change of the REFIN1
The maximum input voltage for the linear regulator is
28V, while the minimum input voltage is determined by
the 800mV (max) dropout voltage (V LDOIN(MIN) =
VLDOOUT + VDROPOUT) at 50mA load. Bypass the linear regulator’s output (LDOOUT) with a 4.7µF or
greater capacitor, providing at least 1µF per 5mA of
internal and external load on the linear regulator. The
LDO can source up to 100mA for powering the controller or supplying a small external load.
For the MAX1540, the linear regulator provides the 5V
bias supply that powers the gate drivers and analog
controller (Figure 1), providing stand-alone capability.
The linear regulator’s input is internally connected to
the battery voltage input (LDOIN = V+), and the gatedriver input supply is internally connected to the linear
regulator’s output (VDD = LDOOUT). Figure 13 is the
internal linear-regulator functional diagram.
For the MAX1541, the linear regulator supports Dual
Mode operation to allow the selection of a 5V output
voltage without requiring external components (Figure
1). Connect FBLDO to GND for a fixed 5.0V output. The
linear regulator’s output voltage can be adjusted from
1.25V to 5.5V using a resistive voltage-divider (Figure
12). The MAX1541 regulates FBLDO to a 1.25V feedback voltage. The adjusted output voltage is:
⎛ R11 ⎞
VLDOOUT = VFBLDO ⎜1+
⎟
⎝ R12 ⎠
where VFBLDO = 1.25V. If unused, disable the MAX1541
linear regulator by connecting LDOON to GND.
______________________________________________________________________________________
33
MAX1540/MAX1541
L
LX_
voltage during dynamic transitions. With the additional
capacitance, the REFIN1 voltage slews between the
two set points with a time constant given by R EQ x
CREFIN1, where REQ is the equivalent parallel resistance seen by the slew capacitor. Looking at Figure 12,
the time constant for a positive REFIN1 voltage transition is:
⎡ R8 × (R9+R10) ⎤
τPOS = ⎢
⎥ CREFIN1
⎣ R8+(R9+R10) ⎦
MAX1540/MAX1541
Dual Step-Down Controllers with Saturation
Protection, Dynamic Output, and Linear Regulator
+5V BIAS
SUPPLY
INPUT (VIN)*
7V TO 20V
CIN
(2) 4.7µF
C1
1µF
VDD
DBST
NH1
V+
DBST
MAX1541
DH1
DH2
BST1
BST2
CBST1
0.1µF
NL1
DL1
L1
1.8µH
NH2
CBST
0.1µF
LX1
LX2
DL1
DL2
SKIP
GND
CSP1
CSP2
NL2
DL2
RCS2
15mΩ
RCS1
15mΩ
OUTPUT 1
VOUT(HIGH) = 1.5V
VOUT(LOW) = 1.0V
VOUT(LOW) = VREF
(
VOUT(HIGH) = VREF
L2
4.3µH
COUT1
470µF
CSN1
CSN2
OUT1
OUT2
FB1
CCC1
47pF
)
R9
(R8 + R9 )
COUT2
220µF
FB2
OUTPUT 2
VOUT2 = 2.5V
OVP/UVP
CC1
LSAT
CREF
0.22µF
(R9 + R10)
[R8 + (R9 + R10)]
TON
OPEN (ILIM(VAL) x 1.75)
REF (485kHz/355kHz)
REF
CILIM1
470pF
ILIM1
R3
49.9kΩ
CILIM2
470pF
ON
LDOON
ON1
ON2
R2
100kΩ
OFF
R1
20Ω
+5V BIAS
SUPPLY
VCC
C2
1µF
R4
100kΩ
R7
100kΩ
R6
100kΩ
ILIM2
R5
49.9kΩ
PGOOD1
POWER-GOOD
PGOOD2
VOUT(LOW)
R13
10Ω
GATE
VOUT(HIGH)
OPEN
(ENABLED, 140µs)
+5V BIAS
SUPPLY
LDOIN
C3
4.7µF
FBLANK
REFIN1
REF
R8
75kΩ
LDOOUT
R9
75kΩ
R11
32.4kΩ
OD
CREFIN
470pF
R10
150kΩ
C4
22µF
LDO OUTPUT
VLDOOUT = 3.3V
FBLDO
R12
20kΩ
POWER GROUND
SEE TABLE 1 FOR COMPONENT SPECIFICATIONS.
ANALOG GROUND
*LOWER INPUT VOLTAGES REQUIRE
ADDITIONAL INPUT CAPACITANCE.
Figure 12. MAX1541 Standard Application Circuit
34
______________________________________________________________________________________
Dual Step-Down Controllers with Saturation
Protection, Dynamic Output, and Linear Regulator
MAX1540/MAX1541
INTERNAL LDOIN
OPTION BETWEEN
THE MAX1540/MAX1541
V+
LDOOUT
*LDOIN
VL REG
AND REF
LDOON
INTERNAL VDD
OPTION BETWEEN
THE MAX1540/MAX1541
GATE DRIVER
AND ERROR
AMP
*VDD
FIXED 5V
*FBDLO
INTERNAL FBLDO
OPTION BETWEEN
THE MAX1540/MAX1541
0.2V
*MAX1541 ONLY.
Figure 13. Internal Linear-Regulator Functional Diagram
Design Procedure
Firmly establish the input voltage range and maximum
load current before choosing a switching frequency
and inductor operating point (ripple-current ratio). The
primary design trade-off lies in choosing a good switching frequency and inductor operating point, and the following four factors dictate the rest of the design:
• Input voltage range: The maximum value (VIN(MAX))
must accommodate the worst-case, high AC-adapter
voltage. The minimum value (VIN(MIN)) must account
for the lowest battery voltage after drops due to connectors, fuses, and battery selector switches. If there
is a choice at all, lower input voltages result in better
efficiency.
•
Maximum load current: There are two values to
consider. The peak load current (ILOAD(MAX)) determines the instantaneous component stresses and filtering requirements and thus drives output capacitor
selection, inductor saturation rating, and the design of
the current-limit circuit. The continuous load current
(ILOAD) determines the thermal stresses and thus drives the selection of input capacitors, MOSFETs, and
other critical heat-contributing components.
•
Switching frequency: This choice determines the
basic trade-off between size and efficiency. The
optimal frequency is largely a function of maximum
input voltage due to MOSFET switching losses that
are proportional to frequency and VIN2. The optimum frequency is also a moving target, due to
rapid improvements in MOSFET technology that are
making higher frequencies more practical.
•
Inductor operating point: This choice provides
trade-offs between size vs. efficiency and transient
response vs. output ripple. Low inductor values
provide better transient response and smaller physical size, but also result in lower efficiency and
higher output ripple due to increased ripple currents. The minimum practical inductor value is one
that causes the circuit to operate at the edge of critical conduction (where the inductor current just
touches zero with every cycle at maximum load).
Inductor values lower than this grant no further sizereduction benefit. The optimum operating point is
usually found between 20% and 50% ripple current.
When pulse skipping (SKIP low and light loads), the
inductor value also determines the load-current
value at which PFM/PWM switchover occurs.
______________________________________________________________________________________
35
MAX1540/MAX1541
Dual Step-Down Controllers with Saturation
Protection, Dynamic Output, and Linear Regulator
Inductor Selection
Setting the Current Limit
The switching frequency and inductor operating point
determine the inductor value as follows:
The minimum current-limit threshold must be great
enough to support the maximum load current when the
current limit is at the minimum tolerance value. The valley of the inductor current occurs at ILOAD(MAX) minus
half the ripple current; therefore:
L=
VOUT (VIN - VOUT )
VIN × fSW x ILOAD(MAX) × LIR
For example: ILOAD(MAX) = 4A, VIN = 12V, VOUT2 =
2.5V, fSW = 355kHz, 30% ripple current or LIR = 0.3:
L=
2.5V × (12V - 2.5V)
= 4.65µH
12V × 355kHz x 4 A × 0.3
Find a low-loss inductor with the lowest possible DC
resistance that fits in the allotted dimensions. Ferrite
cores are often the best choice, although powdered
iron is inexpensive and can work well at 200kHz. The
core must be large enough not to saturate at the peak
inductor current (IPEAK):
⎛ LIR ⎞
IPEAK = ILOAD(MAX) ⎜1+
⎟
⎝
2 ⎠
Most inductor manufacturers provide inductors in standard values, such as 1.0µH, 1.5µH, 2.2µH, 3.3µH, etc.
Also look for nonstandard values, which can provide a
better compromise in LIR across the input voltage
range. If using a swinging inductor (where the no-load
inductance decreases linearly with increasing current),
evaluate the LIR with properly scaled inductance values.
Transient Response
The inductor ripple current also impacts transientresponse performance, especially at low VIN - VOUT differentials. Low inductor values allow the inductor
current to slew faster, replenishing charge removed
from the output filter capacitors by a sudden load step.
The amount of output sag is also a function of the maximum duty factor, which can be calculated from the ontime and minimum off-time:
⎡⎛ V
⎤
×K⎞
L(∆ILOAD(MAX) )2 ⎢⎜ OUT
+ t OFF(MIN) ⎥
⎟
⎢⎣⎝ VIN ⎠
⎥⎦
VSAG =
⎡⎛ ( VIN - VOUT ) × K ⎞
⎤
2COUT × VOUT ⎢⎜
⎟ - t OFF(MIN) ⎥
VIN
⎢⎝
⎥
⎠
⎣
⎦
where t OFF(MIN) is the minimum off-time (see the
Electrical Characteristics) and K is from Table 3.
The amount of overshoot during a full-load to no-load transient due to stored inductor energy can be calculated as:
VSOAR
36
2
∆ILOAD(MAX) ) L
(
≈
2COUT × VOUT
⎛ VOUT (VIN(MIN) - VOUT ) ⎞
ILIM(VAL) > ILOAD(MAX) - ⎜
⎟
2VIN(MIN) fSW L ⎠
⎝
where ILIM(VAL) equals the minimum valley current-limit
threshold voltage divided by the current-sense resistance (RSENSE). For the 50mV default setting, the minimum valley current-limit threshold is 40mV.
Connect ILIM_ to VCC for a default 50mV valley currentlimit threshold. In adjustable mode, the valley currentlimit threshold is precisely 1/10th the voltage seen at
ILIM_. For an adjustable threshold, connect a resistive
divider from REF to analog ground (GND) with ILIM_
connected to the center tap. The external 250mV to 2V
adjustment range corresponds to a 25mV to 200mV
valley current-limit threshold. When adjusting the
current limit, use 1% tolerance resistors and a divider
current of approximately 10µA to prevent significant
inaccuracy in the valley current-limit tolerance.
The current-sense method (Figure 14) and magnitude
determine the achievable current-limit accuracy and
power loss (Table 9). Typically, higher current-sense
voltage limits provide tighter accuracy, but also dissipate more power. Most applications employ a valley
current-sense voltage (VLIM(VAL)) of 50mV to 100mV,
so the sense resistor may be determined by:
RSENSE = VLIM(VAL) / ILIM(VAL)
For the best current-sense accuracy and overcurrent
protection, use a 1% tolerance current-sense resistor
between the inductor and output as shown in Figure
14a. This configuration constantly monitors the inductor
current, allowing accurate valley current-limiting and
inductor-saturation protection.
For low-output-voltage applications that require higher
efficiency, the current-sense resistor can be connected
between the source of the low-side MOSFET (NL_) and
power ground (Figure 14b) with CSN_ connected to the
drain of NL_ and CSP_ connected to power ground. In
this configuration, the additional current-sense resistance only dissipates power when NL_ is conducting
current. Inductor-saturation protection must be disabled with this configuration (LSAT = GND) since the
inductor current is only properly sensed when the lowside MOSFET is turned on.
______________________________________________________________________________________
Dual Step-Down Controllers with Saturation
Protection, Dynamic Output, and Linear Regulator
L
= CEQ × REQ
RL
where RL is the inductor’s series DC resistance. In this
configuration, the current-sense resistance is equivalent to the inductor’s DC resistance (RSENSE = RL). Use
the worst-case inductance and RL values provided by
the inductor manufacturer, adding some margin for the
inductance drop over temperature and load.
In all cases, ensure an acceptable valley current-limit
threshold voltage and inductor-saturation configurations despite inaccuracies in sense-resistance values.
Output Capacitor Selection
The output filter capacitor must have low enough equivalent series resistance (ESR) to meet output ripple and
load-transient requirements, yet have high enough ESR
to satisfy stability requirements.
For processor-core voltage converters and other applications where the output is subject to violent load transients, the output capacitor’s size depends on how
much ESR is needed to prevent the output from dipping
too low under a load transient. Ignoring the sag due to
finite capacitance:
RESR ≤
VSTEP
∆ILOAD(MAX)
In applications without large and fast load transients,
the output capacitor’s size often depends on how much
ESR is needed to maintain an acceptable level of output voltage ripple. The output ripple voltage of a stepdown controller equals the total inductor ripple current
multiplied by the output capacitor’s ESR. Therefore, the
maximum ESR required to meet ripple specifications is:
VRIPPLE
RESR ≤
∆ILOAD(MAX) × LIR
The actual capacitance value required relates to the
physical size needed to achieve low ESR, as well as to
the chemistry of the capacitor technology. Thus, the
capacitor is usually selected by ESR and voltage rating
rather than by capacitance value (this is true of tantalums, OS-CONs, polymers, and other electrolytics).
When using low-capacity filter capacitors, such as
ceramic capacitors, size is usually determined by the
capacity needed to prevent V SAG and V SOAR from
causing problems during load transients. Generally,
once enough capacitance is added to meet the overshoot requirement, undershoot at the rising load edge
is no longer a problem (see the VSAG and VSOAR equations in the Transient Response section). However, lowcapacity filter capacitors typically have high-ESR zeros
that may affect the overall stability (see the OutputCapacitor Stability Considerations section).
Table 9. Current-Sense Configurations
CURRENT-SENSE
ACCURACY
INDUCTOR-SATURATION
PROTECTION
CURRENT-SENSE POWER LOSS
(EFFICIENCY)
a) Output current-sense resistor
High
Allowed
(highest accuracy)
RSENSE x IOUT2
b) Low-side current-sense resistor
High
Not allowed
(LSAT = GND)
⎛ VOUT ⎞
2
⎜1- V ⎟ × RSENSE × IOUT
⎝
IN ⎠
c) Low-side MOSFET on-resistance
Low
Not allowed
(LSAT = GND)
No additional loss
d) Equivalent inductor DC resistance
Low
Allowed
No additional loss
METHOD
______________________________________________________________________________________
37
MAX1540/MAX1541
For high-power applications that do not require highaccuracy current sensing or inductor-saturation protection, the MAX1540/MAX1541 can use the low-side
MOSFET’s on-resistance as the current-sense element
(RSENSE = RDS(ON)) by connecting CSN_ to the drain
of NL_ and CSP_ to the source of NL_ (Figure 14c). Use
the worst-case maximum value for RDS(ON) from the
MOSFET data sheet, and add some margin for the rise
in RDS(ON) with temperature. A good general rule is to
allow 0.5% additional resistance for each °C of temperature rise. Inductor-saturation protection must be disabled with this configuration (LSAT = GND) since the
inductor current is only properly sensed when the lowside MOSFET is turned on.
Alternatively, high-power applications that require
inductor saturation can constantly detect the inductor
current by connecting a series RC circuit across the
inductor (Figure 14d) with an equivalent time constant:
MAX1540/MAX1541
Dual Step-Down Controllers with Saturation
Protection, Dynamic Output, and Linear Regulator
VIN
DH
CIN
RSENSE
L
VOUT
LX
MAX1540
MAX1541
COUT
DL
GND
CONNECT TO
PREFERRED
LSAT SETTING
CSP
LSAT
CSN
a) OUTPUT SERIES RESISTOR SENSING
VIN
CIN
DH
L
VOUT
LX
MAX1540
MAX1541
COUT
DL
CSN
RSENSE
DISABLE
LSAT
CSP
GND
LSAT
b) LOW-SIDE SERIES RESISTOR SENSING
VIN
DH
CIN
L
VOUT
LX
COUT
CSN
MAX1540
MAX1541
DISABLE
LSAT
DL
VIN
CSP
LSAT
DH
GND
CIN
INDUCTOR
RL
L
VOUT
LX
c) LOW-SIDE MOSFET SENSING
MAX1540
MAX1541
DL
GND
CONNECT TO
PREFERRED
LSAT SETTING
COUT
REQ
CEQ
CSP
LSAT
CSN
d) LOSSLESS INDUCTOR SENSING
RBIAS = REQ
Figure 14. Current-Sense Configurations
38
______________________________________________________________________________________
Dual Step-Down Controllers with Saturation
Protection, Dynamic Output, and Linear Regulator
Input-Capacitor Selection
The input capacitor must meet the ripple current
requirement (IRMS) imposed by the switching currents:
f
fESR ≤ SW
π
where
fESR =
1
2πRESRCOUT
For a typical 300kHz application, the ESR zero frequency must be well below 95kHz, preferably below 50kHz.
Tantalum and OS-CON capacitors in widespread use
at the time of publication have typical ESR zero frequencies of 25kHz. In the design example used for
inductor selection, the ESR needed to support 25mVP-P
ripple is 25mV/1.2A = 20.8mΩ. One 220µF/4V Sanyo
polymer (TPE) capacitor provides 15mΩ (max) ESR.
This results in a zero at 48kHz, well within the bounds
of stability.
Do not put high-value ceramic capacitors directly
across the feedback sense point without taking precautions to ensure stability. Large ceramic capacitors can
have a high-ESR zero frequency and cause erratic,
unstable operation. However, it is easy to add enough
series resistance by placing the capacitors a couple of
inches downstream from the feedback sense point,
which should be as close as possible to the inductor.
Unstable operation manifests itself in two related but
distinctly different ways: double pulsing and fast-feedback loop instability. Double pulsing occurs due to
noise on the output or because the ESR is so low that
there is not enough voltage ramp in the output voltage
signal. This “fools” the error comparator into triggering
a new cycle immediately after the 400ns minimum offtime period has expired. Double pulsing is more annoying than harmful, resulting in nothing worse than
increased output ripple. However, it can indicate the
possible presence of loop instability due to insufficient
ESR. Loop instability can result in oscillations at the output after line or load steps. Such perturbations are usually damped, but can cause the output voltage to rise
above or fall below the tolerance limits.
The easiest method for checking stability is to apply a
very fast zero-to-max load transient and carefully
observe the output voltage ripple envelope for overshoot and ringing. It can help to monitor simultaneously
the inductor current with an AC current probe. Do not
allow more than one cycle of ringing after the initial
step-response under/overshoot.
(IOUT1)2 VOUT1(VIN − VOUT1 ) +
IRMS =
(IOUT2 )2 VOUT2 (VIN − VOUT2 )
VIN
For most applications, nontantalum chemistries (ceramic, aluminum, or OS-CON) are preferred due to their
resistance to power-up surge currents typical of systems with a mechanical switch or connector in series
with the input. If the MAX1540/MAX1541 are operated
as the second stage of a two-stage power conversion
system, tantalum input capacitors are acceptable. In
either configuration, choose a capacitor that has less
than 10°C temperature rise at the RMS input current for
optimal reliability and lifetime.
Power MOSFET Selection
Most of the following MOSFET guidelines focus on the
challenge of obtaining high load-current capability
when using high-voltage (>20V) AC adapters. Low-current applications usually require less attention.
The high-side MOSFET (NH) must be able to dissipate
the resistive losses plus the switching losses at both
VIN(MIN) and VIN(MAX). Ideally, the losses at VIN(MIN)
should be roughly equal to the losses at VIN(MAX), with
lower losses in between. If the losses at VIN(MIN) are
significantly higher, consider increasing the size of NH.
Conversely, if the losses at VIN(MAX) are significantly
higher, consider reducing the size of NH. If VIN does
not vary over a wide range, maximum efficiency is
achieved by selecting a high-side MOSFET (N H) that
has conduction losses equal to the switching losses.
Choose a low-side MOSFET (NL) that has the lowest possible on-resistance (RDS(ON)), comes in a moderate-sized
package (i.e., 8-pin SO, DPAK, or D2PAK), and is reasonably priced. Ensure that the MAX1540/MAX1541 DL_
gate driver can supply sufficient current to support the
gate charge and the current injected into the parasitic
drain-to-gate capacitor caused by the high-side MOSFET
turning on; otherwise, cross-conduction problems may
occur. Switching losses are not an issue for the low-side
MOSFET since it is a zero-voltage switched device when
used in the step-down topology.
______________________________________________________________________________________
39
MAX1540/MAX1541
Output-Capacitor Stability Considerations
For Quick-PWM controllers, stability is determined by
the value of the ESR zero relative to the switching frequency. The boundary of instability is given by the following equation:
MAX1540/MAX1541
Dual Step-Down Controllers with Saturation
Protection, Dynamic Output, and Linear Regulator
Power-MOSFET Dissipation
Worst-case conduction losses occur at the duty factor
extremes. For the high-side MOSFET (NH), the worstcase power dissipation due to resistance occurs at
minimum input voltage:
⎛V
⎞
PD (NH Resistance) = ⎜ OUT ⎟ (ILOAD )2 × RDS(ON)
⎝ VIN ⎠
Generally, use a small high-side MOSFET to reduce
switching losses at high input voltages. However, the
RDS(ON) required to stay within package power-dissipation limits often restricts how small the MOSFET can
be. The optimum occurs when the switching losses
equal the conduction (R DS(ON) ) losses. High-side
switching losses do not become an issue until the input
is greater than approximately 15V.
Calculating the power dissipation in high-side
MOSFETs (NH) due to switching losses is difficult, since
it must allow for difficult-to-quantify factors that influence the turn-on and turn-off times. These factors
include the internal gate resistance, gate charge,
threshold voltage, source inductance, and PC board
layout characteristics. The following switching loss calculation provides only a very rough estimate and is no
substitute for breadboard evaluation, preferably including verification using a thermocouple mounted on NH:
PD (NH
2
VIN(MAX) ) CRSS × fSW × ILOAD
(
Switching) =
IGATE
where CRSS is the reverse transfer capacitance of NH,
and IGATE is the peak gate-drive source/sink current
(1A typ).
Switching losses in the high-side MOSFET can become
a heat problem when maximum AC adapter voltages
are applied due to the squared term in the switchingloss equation (C ✕ VIN2 ✕ fSW). If the high-side MOSFET chosen for adequate R DS(ON) at low-battery
voltages becomes extraordinarily hot when subjected
to VIN(MAX), consider choosing another MOSFET with
lower parasitic capacitance.
For the low-side MOSFET (NL), the worst-case power
dissipation always occurs at maximum battery voltage:
⎡ ⎛ V
⎞⎤
PD (NL Resistance) = ⎢1- ⎜ OUT ⎟ ⎥ (ILOAD )2 × RDS(ON)
⎢⎣ ⎝ VIN(MAX) ⎠ ⎥⎦
40
The absolute worst case for MOSFET power dissipation
occurs under heavy overload conditions that are
greater than ILOAD(MAX) but are not high enough to
exceed the current limit and cause the fault latch to trip.
To protect against this possibility, “overdesign” the circuit to tolerate:
⎛V
(V − VOUT ) ⎞
ILOAD = IVALLEY(MAX) + ⎜ OUT IN
⎟
2
V
⎝
⎠
IN fSW L
where I VALLEY(MAX) is the maximum valley current
allowed by the current-limit circuit, including threshold
tolerance and sense-resistance variation. The
MOSFETs must have a relatively large heatsink to handle the overload power dissipation.
Choose a Schottky diode (DL) with a forward-voltage
drop low enough to prevent the low-side MOSFET’s
body diode from turning on during the dead time. As a
general rule, select a diode with a DC current rating
equal to 1/3 the load current. This diode is optional and
can be removed if efficiency is not critical.
Applications Information
Step-Down Converter Dropout
Performance
The output-voltage adjustable range for continuousconduction operation is restricted by the nonadjustable
minimum off-time one-shot. For best dropout performance, use the slower (200kHz) on-time setting. When
working with low input voltages, the duty-factor limit
must be calculated using worst-case values for on- and
off-times. Manufacturing tolerances and internal propagation delays introduce an error to the TON K-factor.
This error is greater at higher frequencies (Table 3).
Also, keep in mind that transient-response performance
of buck regulators operated too close to dropout is
poor, and bulk output capacitance must often be
added (see the VSAG equation in the Design Procedure
section).
The absolute point of dropout is when the inductor current ramps down during the minimum off-time (∆IDOWN)
as much as it ramps up during the on-time (∆IUP). The
ratio h = ∆IUP/∆IDOWN indicates the controller’s ability
to slew the inductor current higher in response to
increased load, and must always be greater than 1. As
h approaches 1, the absolute minimum dropout point,
the inductor current cannot increase as much during
each switching cycle, and V SAG greatly increases
unless additional output capacitance is used.
______________________________________________________________________________________
Dual Step-Down Controllers with Saturation
Protection, Dynamic Output, and Linear Regulator
VIN(MIN) =
VOUT + VDROP1
⎛ h × t OFF(MIN) ⎞
1- ⎜
⎟
K
⎠
⎝
where V DROP1 is the parasitic voltage drop in the
charge path (see the On-Time One-Shot section),
tOFF(MIN) is from the Electrical Characteristics, and K is
taken from Table 3. The absolute minimum input voltage
is calculated with h = 1.
If the calculated VIN(MIN) is greater than the required
minimum input voltage, then operating frequency must
be reduced or output capacitance added to obtain an
acceptable VSAG. If operation near dropout is anticipated, calculate VSAG to be sure of adequate transient
response.
Dropout Design Example
•
VOUT2 = 2.5V
•
fSW = 355kHz
•
K = 3.0µs, worst-case KMIN = 3.3µs
•
tOFF(MIN) = 500ns
•
VDROP1 = 100mV
•
h = 1.5
VIN(MIN) =
put voltages, it can produce three or more output voltages if required by using discrete logic or a DAC.
Figure 15 shows an application circuit providing four
voltage levels using discrete logic. Switching resistors
in and out of the resistor network changes the voltage
at REFIN1. An edge-detection circuit is added to generate a 1µs pulse on GATE to trigger the fault blanking
and forced-PWM operation. When using PWM mode
(SKIP = VCC or open) on the main controller, the edgedetection circuit is only required if fault blanking is
enabled. Otherwise, leave OD unconnected.
Active Bus Termination
(MAX1541 OUT1 Only)
Active-bus-termination power supplies generate a voltage rail that tracks a set reference. They are required to
source and sink current. DDR memory architecture
requires active bus termination. In DDR memory architecture, the termination voltage is set at exactly half the
memory supply voltage. Configure the main MAX1541
controller (OUT1) to generate the termination voltage
using a resistive voltage-divider at REFIN1. In such an
application, the main MAX1541 controller (OUT1) must
be kept in PWM mode (SKIP = VCC or open) in order
for it to source and sink current. Figure 16 shows the
main MAX1541 controller configured as a DDR termination regulator. Connect GATE and FBLANK to GND
when unused.
REF
2.5V + 0.1V
= 3.47V
⎛ 1.5 × 500ns ⎞
1- ⎜
⎟
⎝ 3.0µs ⎠
R4
R1
REFIN1
B
Calculating again with h = 1 and the typical K-factor
value (K = 3.3µs) gives the absolute limit of dropout:
VIN(MIN) =
R3
C1
2.5V + 0.1V
= 3.06V
⎛ 1 × 500ns ⎞
1- ⎜
⎟
⎝ 3.3µs ⎠
Therefore, VIN must be greater than 3.06V, even with
very large output capacitance, and a practical input voltage with reasonable output capacitance would be 3.47V.
Multi-Output Voltage Settings
(MAX1541 OUT1 Only)
R2
MAX1541
A
GND
1.5kΩ
1000pF
GATE
1.5kΩ
1000pF
While the main MAX1541 controller (OUT1) is optimized
to work with applications that require two dynamic outFigure 15. Multi-Output Voltage Settings
______________________________________________________________________________________
41
MAX1540/MAX1541
A reasonable minimum value for h is 1.5, but adjusting
this up or down allows trade-offs between VSAG, output
capacitance, and minimum operating voltage. For a
given value of h, the minimum operating voltage can be
calculated as:
MAX1540/MAX1541
Dual Step-Down Controllers with Saturation
Protection, Dynamic Output, and Linear Regulator
VDDQ
VCC
VIN
SKIP
DH1
CIN
L
10kΩ
RSENSE
V
VTT = DDQ
2
LX1
REFIN1
10nF
COUT
DL1
MAX1541 GND
10kΩ
CSP1
OD
CSN1
GATE
OUT1
FBLANK
FB1
VDDQ = DDR MEMORY SUPPLY VOLTAGE
VTT = TERMINATION SUPPLY VOLTAGE
Figure 16. Active Bus Termination
Voltage Positioning
In applications where fast load transients occur, the output voltage changes instantly by ESRCOUT x ∆ILOAD.
Voltage positioning allows the use of fewer output
capacitors for such applications, and maximizes the output voltage AC and DC tolerance window in tight-tolerance applications.
Figure 17 shows the connection of OUT_ and FB_ in
voltage-positioned and nonvoltage-positioned circuits.
In nonvoltage-positioned circuits, the MAX1540/
MAX1541 regulate at the output capacitor. In voltagepositioned circuits, the MAX1540/MAX1541 regulate on
the inductor side of the current-sense resistor. VOUT_ is
reduced to:
VOUT(VPS) = VOUT(NO LOAD) - RSENSE x ILOAD
Figure 18 shows the voltage-positioning transient
response.
PC board traces is a difficult task that must be
approached in terms of fractions of centimeters,
where a single milliohm of excess trace resistance
causes a measurable efficiency penalty.
•
Minimize current-sensing errors by connecting
CSP_ and CSN_ directly across the current-sense
resistor (RSENSE_).
•
When trade-offs in trace lengths must be made, it is
preferable to allow the inductor charging path to be
made longer than the discharge path. For example,
it is better to allow some extra distance between the
input capacitors and the high-side MOSFET than to
allow distance between the inductor and the lowside MOSFET or between the inductor and the output filter capacitor.
•
Route high-speed switching nodes (BST_, LX_,
DH_, and DL_) away from sensitive analog areas
(REF, FB_, CSP_, CSN_).
PC Board Layout Guidelines
Layout Procedure
Careful PC board layout is critical to achieving low
switching losses and clean, stable operation. The
switching power stage requires particular attention
(Figure 19). If possible, mount all the power components on the top side of the board, with their ground terminals flush against one another. Follow these
guidelines for good PC board layout:
• Keep the high-current paths short, especially at the
ground terminals. This practice is essential for stable, jitter-free operation.
1) Place the power components first, with ground terminals adjacent (NL _ source, CIN, COUT_, and DL _
anode). If possible, make all these connections on
the top layer with wide, copper-filled areas.
•
42
Keep the power traces and load connections short.
This practice is essential for high efficiency. Using
thick copper PC boards (2oz vs. 1oz) can enhance
full-load efficiency by 1% or more. Correctly routing
2) Mount the controller IC adjacent to the low-side
MOSFET, preferably on the back side opposite NL _
and NH_ in order to keep LX_, GND, DH_, and the
DL_ gate-drive lines short and wide. The DL_ and
DH_ gate traces must be short and wide (50 mils to
100 mils wide if the MOSFET is 1in from the controller IC) to keep the driver impedance low and for
proper adaptive dead-time sensing.
______________________________________________________________________________________
Dual Step-Down Controllers with Saturation
Protection, Dynamic Output, and Linear Regulator
MAX1540/MAX1541
R1
+5V BIAS
SUPPLY
C2
VDD
VCC
DBST
C1
V+
INPUT (VIN)
CIN
BST_
NH
DH_
CBST
MAX1540
MAX1541
L1
VOLTAGE-POSITIONED
OUTPUT (VOUT(VPS))
RSENSE
LX_
NL
COUT
DL
DL_
GND
CSP_
OUT_
FB
CSN_
VOUT(VPS) = VOUT(NO LOAD) - RSENSEIOUT
Figure 17. Voltage Positioning
VOLTAGE POSITIONING THE OUTPUT
CAPACITIVE SOAR
(dV/dt = IOUT/COUT)
ESR VOLTAGE STEP
(ISTEP x RESR)
A
1.4
VOUT
1.4
B
CAPACITIVE SAG
(dV/dt = IOUT/COUT)
RECOVERY
50mV/div
A. CONVENTIONAL CONVERTER
B. VOLTAGE-POSITIONED OUTPUT
ILOAD
Figure 18. Voltage-Positioning Transient Response
______________________________________________________________________________________
43
MAX1540/MAX1541
Dual Step-Down Controllers with Saturation
Protection, Dynamic Output, and Linear Regulator
VIA TO POWER
GROUND
CONNECT GND
AND PGND TO THE
CONTROLLER AT
ONE POINT ONLY
AS SHOWN
CONNECT THE
EXPOSED PAD TO
ANALOG GROUND
VIA TO VCC
BYPASS CAPACITOR
VIA TO VCC PIN
VIA TO REF PIN
VIA TO REF
BYPASS CAPACITOR
MAX1540
TOP LAYER
MAX1540
BOTTOM LAYER
KELVIN-SENSE VIAS
UNDER THE SENSE RESISTOR
(REFER TO EVALUATION KIT)
DUAL
N-CHANNEL
MOSFET
INDUCTOR
SINGLE
N-CHANNEL
MOSFETS
INDUCTOR
DH
LX
DL
COUT
CIN
CIN
INPUT
COUT
OUTPUT
COUT
OUTPUT
INPUT
GROUND
GROUND
HIGH-POWER LAYOUT
LOW-POWER LAYOUT
Figure 19. PC Board Layout
3) Group the gate-drive components (BST_ diode and
capacitor, VDD bypass capacitor) together near the
controller IC.
4) Make the DC-DC controller ground connections as
shown in Figures 1 and 12. This diagram can be
viewed as having two separate ground planes:
power ground, where all the high-power components go, and an analog ground plane for sensitive
analog components. The analog ground plane and
power ground plane must meet only at a single
point directly at the IC.
44
5) Connect the output power planes directly to the output filter capacitor positive and negative terminals
with multiple vias. Place the entire DC-DC converter
circuit as close to the load as is practical.
Chip Information
TRANSISTOR COUNT: 8612
PROCESS: BiCMOS
______________________________________________________________________________________
Dual Step-Down Controllers with Saturation
Protection, Dynamic Output, and Linear Regulator
OUT1
34
LX1
FB1
35
31
CSN1
36
PGOOD1
CSP1
37
DH1
FBLANK
38
32
ON2
39
33
ON1
40
TOP VIEW
OVP/UVP
1
30
BST1
SKIP
2
29
LDOON
LSAT
3
28
DL1
TON
4
27
FBLDO
VCC
5
GATE
MAX1541
26
LDOOUT
6
25
VDD
15
16
17
18
19
20
OUT2
PGOOD2
DH2
LX2
BST2
GND
FB2
21
14
DL2
10
REF
CSN2
22
13
9
CSP2
V+
ILIM2
12
LDOIN
23
11
24
8
OD
7
REFIN1
CC1
ILIM1
MAX1540/MAX1541
Pin Configurations (continued)
THIN QFN
______________________________________________________________________________________
45
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
QFN THIN.EPS
MAX1540/MAX1541
Dual Step-Down Controllers with Saturation
Protection, Dynamic Output, and Linear Regulator
D2
D
MARKING
b
C
L
0.10 M C A B
D2/2
D/2
k
L
XXXXX
E/2
E2/2
C
L
(NE-1) X e
E
DETAIL A
PIN # 1
I.D.
E2
PIN # 1 I.D.
0.35x45∞
e
(ND-1) X e
DETAIL B
e
L1
L
C
L
C
L
L
L
e
e
0.10 C
A
C
0.08 C
A1 A3
PACKAGE OUTLINE,
16, 20, 28, 32L THIN QFN, 5x5x0.8mm
-DRAWING NOT TO SCALE-
46
21-0140
______________________________________________________________________________________
G
1
2
Dual Step-Down Controllers with Saturation
Protection, Dynamic Output, and Linear Regulator
COMMON DIMENSIONS
EXPOSED PAD VARIATIONS
PKG.
20L 5x5
28L 5x5
32L 5x5
16L 5x5
SYMBOL MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX.
A
A1
0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80
0
A3
b
D
E
L1
0
0.02 0.05
0
0.20 REF.
0.20 REF.
0.02 0.05
0
0.02 0.05
0.20 REF.
0.20 REF.
0.25 0.30 0.35 0.25 0.30 0.35 0.20 0.25 0.30 0.20 0.25 0.30
4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10
4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10
e
k
L
0.02 0.05
0.65 BSC.
0.80 BSC.
0.50 BSC.
0.50 BSC.
0.25 - 0.25 - 0.25 - 0.25
0.30 0.40 0.50 0.45 0.55 0.65 0.45 0.55 0.65 0.30 0.40 0.50
-
-
-
-
-
N
ND
NE
16
4
4
20
5
5
JEDEC
WHHB
WHHC
-
-
-
-
-
28
7
7
WHHD-1
-
-
32
8
8
WHHD-2
NOTES:
1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.
3. N IS THE TOTAL NUMBER OF TERMINALS.
D2
L
E2
PKG.
CODES
MIN.
NOM. MAX.
MIN.
NOM. MAX.
±0.15
T1655-1
T1655-2
T1655N-1
3.00
3.00
3.00
3.10 3.20 3.00
3.10 3.20 3.00
3.10 3.20 3.00
3.10 3.20
3.10 3.20
3.10 3.20
T2055-2
T2055-3
T2055-4
3.00
3.00
3.00
3.10 3.20 3.00
3.10 3.20 3.00
3.10 3.20 3.00
3.10 3.20
3.10 3.20
3.10 3.20
**
**
**
**
T2055-5
T2855-1
T2855-2
T2855-3
T2855-4
T2855-5
T2855-6
T2855-7
T2855-8
T2855N-1
T3255-2
T3255-3
T3255-4
T3255N-1
3.15
3.15
2.60
3.15
2.60
2.60
3.15
2.60
3.15
3.15
3.00
3.00
3.00
3.00
3.25
3.25
2.70
3.25
2.70
2.70
3.25
2.70
3.25
3.25
3.10
3.10
3.10
3.10
3.25
3.25
2.70
3.25
2.70
2.70
3.25
2.70
3.25
3.25
3.10
3.10
3.10
3.10
4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL
CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE
OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1
IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE.
3.35
3.35
2.80
3.35
2.80
2.80
3.35
2.80
3.35
3.35
3.20
3.20
3.20
3.20
3.15
3.15
2.60
3.15
2.60
2.60
3.15
2.60
3.15
3.15
3.00
3.00
3.00
3.00
3.35
3.35
2.80
3.35
2.80
2.80
3.35
2.80
3.35
3.35
3.20
3.20
3.20
3.20
**
**
0.40
DOWN
BONDS
ALLOWED
NO
YES
NO
NO
YES
NO
Y
**
NO
NO
YES
YES
NO
**
**
0.40
**
**
**
**
**
NO
YES
Y
N
NO
YES
NO
NO
**
**
**
**
** SEE COMMON DIMENSIONS TABLE
5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm
FROM TERMINAL TIP.
6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.
7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.
8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT EXPOSED PAD DIMENSION FOR T2855-1,
T2855-3 AND T2855-6.
10. WARPAGE SHALL NOT EXCEED 0.10 mm.
11. MARKING IS FOR PACKAGE ORIENTATION REFERENCE ONLY.
12. NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY.
-DRAWING NOT TO SCALE-
PACKAGE OUTLINE,
16, 20, 28, 32L THIN QFN, 5x5x0.8mm
21-0140
G
2
2
______________________________________________________________________________________
47
MAX1540/MAX1541
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
QFN THIN 6x6x0.8.EPS
MAX1540/MAX1541
Dual Step-Down Controllers with Saturation
Protection, Dynamic Output, and Linear Regulator
D2
D
CL
D/2
b
D2/2
k
E/2
E2/2
(NE-1) X e
E
CL
E2
k
e
L
(ND-1) X e
e
L
CL
CL
L1
L
L
e
A1
A2
e
A
PACKAGE OUTLINE
36, 40, 48L THIN QFN, 6x6x0.8mm
21-0141
48
______________________________________________________________________________________
E
1
2
Dual Step-Down Controllers with Saturation
Protection, Dynamic Output, and Linear Regulator
NOTES:
1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.
3. N IS THE TOTAL NUMBER OF TERMINALS.
4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1
SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE
ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE.
5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm
FROM TERMINAL TIP.
6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.
7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.
8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT FOR 0.4mm LEAD PITCH PACKAGE T4866-1.
PACKAGE OUTLINE
36, 40, 48L THIN QFN, 6x6x0.8mm
10. WARPAGE SHALL NOT EXCEED 0.10 mm.
21-0141
E
2
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 49
© 2005 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products, Inc.
MAX1540/MAX1541
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
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