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Highly Integrated, 4-Channel Sequencer and
Supervisor
General Description
The MAX16165/MAX16166 monitor up to five voltages
and sequence up to four voltages. These devices
provide an adjustable delay as each supply is turned on
as well as monitor each power-supply voltage, including
the input voltage VDD.
The MAX16165/MAX16166 operate from a supply range
of 2.7V to 16V and have an internal regulator output
(ABP), power internal circuits, and supply more than
1mA additional current to any external circuitry.
The sequencing is enabled by two inputs, ON and OFF.
A rising edge on the ON input initiates power-on
sequencing of the channels whereas a falling edge on
OFF input initiates power-off sequencing. During the
power-on sequencing, when all of the voltages reach
their final values, a sequencing done output DONE
asserts high followed by a Power-OK (POK) output after
the reset delay timer has expired, allowing the
microcontroller (μC) to operate. If any voltage falls below
its threshold, the reset output asserts and all voltage
supplies are turned off. When the sequencer initiates a
power-off sequencing, the MAX16165/MAX16166 can
reverse sequence the outputs.
Output options available are open-drain (MAX16165)
and push-pull (MAX16166). The MAX16165/MAX16166
can be daisy-chained unlimited amount to time to control
any number of voltages in a system.
MAX16165/MAX16166
Applications
•
•
•
•
•
•
Latch-Up Prevention and Inrush Current Protection
in Multi-Supply Systems
FPGA/ASIC Power Supply Sequencing
Servers and Security Cameras
Test Equipment
Networking Equipment
Industrial Sensors and Motor Controls
Benefits and Features
•
•
•
•
•
•
•
•
•
•
•
•
•
2.7V to 16.0V Wide Operating Voltage Range
Monitor Up to Five Voltages
Sequence Up to Four Voltages
Power-Off in Reverse Order or Simultaneously
Unlimited Daisy-Chain
Capacitor-Adjustable Sequencing Delay
Capacitor-Adjustable Power-Good Timeout
Resistor-Configurable Power-Supply On and
Off Thresholds
Open-Drain (MAX16165)/Push-Pull (MAX16166)
Outputs
POK Output for System Microcontroller Reset
Bidirectional FAULT Input/Output
4 x 5-Bump WLP and 20L TQFN Package
-40°C to +125°C Operating Temperature Range
Ordering Information appears at end of data sheet.
The MAX16165/MAX16166 feature a bidirectional active
low FAULT input/output, which asserts low during any
fault condition. FAULT stays low as long as an
undervoltage event is present at UVSET Input and it is a
one-shot output during all other FAULT conditions. An
external signal pulling FAULT low disables all outputs
immediately. The MAX16165/MAX16166 are available
in a 1.63mm x 2.03mm, 20-bump Wafer-Level Package
(WLP) and a 4mm x 4mm, 20L TQFN package. The
device is fully specified over the -40°C to +125°C
operating temperature range.
19-101178; Rev 0; 11/21
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MAX16165/MAX16166
Highly Integrated, 4-Channel Sequencer and
Supervisor
Typical Application Circuit
5.0 V
UVSET
EN
3.6 V
2.5 V
1.8V
1.2V
VDD
ABP
FAULT
ON
DONE
OFF
POK
SET1
OUT1
MAX16165
MAX16166
SET2
OUT2
SET3
OUT3
OUT4
SET4
IOS
PGT
DLY
RIOS
CDLY
GND
CPGT
5.0 V
1.2V
FPGA
DSP
SoC
1.8V
2.5V
3.6 V
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DC-DC
DC-DC
DC-DC
DC-DC
Analog Devices | 2
MAX16165/MAX16166
Highly Integrated, 4-Channel Sequencer and
Supervisor
Absolute Maximum Ratings
VDD to GND ..........................................................-0.3V to +30V
Input/Output Current ......................................................... 20mA
OUT_ (Open-drain) to GND ...................................-0.3V to +30V
Continuous Power Dissipation, WLP, Multilayer Board
(TA =
+70°C, derate 18.02mW/°C above +70°C) ................ 1441.7mW
OUT_ (Push-pull) to GND ........... -0.3 to Min.(VABP + 0.3V, +6V)
DONE, POK (Open-drain) to GND ..........................-0.3V to +6V
Continuous Power Dissipation, TQFN, Multilayer Board
(TA
= +70°C, derate 25.60mW/°C above +70°C) ............. 2051.3mW
DONE (Push-pull) to GND .......... -0.3 to Min.(VABP + 0.3V, +6V)
Operating Temperature Range ......................... -40°C to +125°C
POK (Push-pull) to GND ............. -0.3 to Min.(VABP + 0.3V, +6V)
Junction Temperature ..................................................... +150°C
SET_, FAULT, ON, OFF to GND .............................-0.3V to +6V
Storage Temperature Range ............................. -40°C to +150°C
UVSET, ABP, IOS, DLY, PGT to GND ....................-0.3V to +6V
Soldering Temperature (reflow) ....................................... +260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any
other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
Package Information
WLP
Package Code
W201C2+2
Outline Number
21-0779
Land Pattern Number
Refer to Application Note 1891
THERMAL RESISTANCE, FOUR-LAYER BOARD
Junction-to-Ambient (θJA)
55.49°C/W
Junction-to-Case Thermal Resistance (θJC)
N/A
TQFN
Package Code
T2044+3C
Outline Number
21-0139
Land Pattern Number
90-0037
THERMAL RESISTANCE, FOUR-LAYER BOARD
Junction-to-Ambient (θJA)
39°C/W
Junction-to-Case Thermal Resistance (θJC)
6°C/W
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character,
but the drawing pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
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Analog Devices | 3
MAX16165/MAX16166
Highly Integrated, 4-Channel Sequencer and
Supervisor
Electrical Characteristics
(VDD = 2.7V to 16.0V, VEN = VABP, TA = -40ºC to +125ºC, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
2.7
16
V
2.45
3.20
V
2.35
V
SUPPLY VOLTAGE
Operating Voltage
Range
Regulated Supply
Voltage
VDD
VABP
Undervoltage Lockout
VUVLO
Undervoltage Lockout
Hysteresis
VUVLO_HYS
Supply Current
IDD
IABP = +1mA (external sourcing current
from ABP)
Minimum voltage on ABP, ABP rising
1.7
ABP falling
100
VDD = 5V, all OUT_ = HIGH, No load
105
170
μA
mV
ON, OFF INPUTS
ON Input Threshold
VON_TH
ON rising
0.496
0.5
0.504
V
OFF Input Threshold
VOFF_TH
OFF falling
0.496
0.5
0.504
V
ON, OFF Threshold
Tempco
ON, OFF Input Current
20
ION_OFF
-100
ppm/°C
100
nA
0.504
V
MONITORED ANALOG INPUTS (UVSET, SET_)
UVSET, SET_
Threshold
UVSET, SET_
Threshold Hysteresis
UVSET, SET_
Threshold Tempco
UVSET, SET_ Input
Current
VTH
UVSET, SET_ falling
VHYST
UVSET, SET_ rising
VUVSET = VSET_ = 0.5V
0.496
0.5
1
%VTH
20
ppm/°C
-100
+100
nA
0.5075
V
OFFSET CURRENT SETTING INPUT (IOS)
Offset Current Voltage
Source
Offset Current Voltage
Source Tempco
0.4925
0.5
30
Offset Current Range
Offset Current Error
ppm/°C
RIOS = 10kΩ to 1MΩ
0.5
50
0.5µA to 5µA
-25
+25
5µA to 50µA
-5
+5
μA
%
DELAY TIMER INPUT (DLY) AND POWER-GOOD TIMER INPUT (PGT)
Source Current
-40°C to +85°C
3.8
4
4.2
-40°C to +125°C
3.8
4
4.4
Voltage Threshold
0.5
μA
V
SEQUENCER OUTPUTS (OUT_)
OUT_ Output Voltage
Low
VOUTL
OUT_ Output Voltage
High
VOUTH
OUT_ Leakage Current
IOUT_LKG
MAX16165, Open-drain Output,
ISINK = 3.2mA
MAX16166, Push-pull Output,
ISINK = 3.2mA
MAX16166, Push-pull Output,
ISOURCE = 1mA
MAX16165, Open-drain Output,
OUT_ = HIGH, VOUT_= 5V
0.3
V
0.3
0.85 x
VABP
V
1
μA
FAULT INPUT/OUTPUT
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Analog Devices | 4
MAX16165/MAX16166
Highly Integrated, 4-Channel Sequencer and
Supervisor
(VDD = 2.7V to 16.0V, VEN = VABP, TA = -40ºC to +125ºC, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
FAULT Output Voltage
Low
VFAULTL
CONDITIONS
MIN
TYP
ISINK = 3.2mA
FAULT Leakage Current
IFAULT_LKG
FAULT = HIGH, VFAULT = 5V
FAULT Input Threshold
VFAULT_TH
FAULT falling
MAX
UNITS
0.3
V
1
μA
0.5
V
POWER-OK OUTPUT (POK)
POK Output Voltage
Low
VPOKL
POK Output Voltage
High
VPOKH
POK Leakage Current
IPOK_LKG
MAX16165, Open-drain Output,
ISINK = 3.2mA
MAX16166, Push-pull Output,
ISINK = 3.2mA
MAX16166, Push-pull Output,
ISOURCE = 1mA
MAX16165, Open-drain Output,
POK = HIGH, VPOK = 5V
0.3
V
0.3
0.85 x
VABP
V
1
μA
DONE OUTPUT (DONE)
DONE Output Voltage
Low
VDONEL
DONE Output Voltage
High
VDONEH
DONE Leakage Current
IDONE_LKG
MAX16165, Open-drain Output,
ISINK = 3.2mA
MAX16166, Push-pull Output,
ISINK = 3.2mA
MAX16166, Push-pull Output,
ISOURCE = 1mA
MAX16165, Open-drain Output,
DONE = HIGH, VDONE = 5V
0.3
V
0.3
0.85 x
VABP
V
1
μA
+15
%
TIMING
POK Reset Timeout
Accuracy
tPOK_ACC
-15
ON Input Pulse Width
tON_PW
ON rising
6
μs
OFF Input Pulse Width
tOFF_PW
OFF falling
6
μs
FAULT falling
6
μs
External FAULT Input
Pulse Width
ON Input, OFF Input,
External FAULT Input
Transient Immunity
FAULT Output Hold
Timeout
SET_ to FAULT, OUT_
Low Delay Time
External FAULT to
OUT_ Low Delay Time
ON to FAULT, OUT_
low Delay Time
OFF to FAULT, OUT_
Low Delay Time
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tFAULT_PW
68
80
1
μs
92
μs
tSET_FAULT
SET_ falling below VTH
1
μs
tFAULT_OUT
FAULT falling below VTH
3
μs
ON rising above VTH
3
μs
OFF falling below VTH
3
μs
Analog Devices | 5
MAX16165/MAX16166
Highly Integrated, 4-Channel Sequencer and
Supervisor
Typical Operating Characteristics
VDD = 5.0V, VEN = VABP, TA = 25°C, unless otherwise noted.
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Analog Devices | 6
MAX16165/MAX16166
Highly Integrated, 4-Channel Sequencer and
Supervisor
VDD = 5.0V, VEN = VABP, TA = 25°C, unless otherwise noted.
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Analog Devices | 7
MAX16165/MAX16166
Highly Integrated, 4-Channel Sequencer and
Supervisor
VDD = 5.0V, VEN = VABP, TA = 25°C, unless otherwise noted.
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Analog Devices | 8
MAX16165/MAX16166
Highly Integrated, 4-Channel Sequencer and
Supervisor
Pin Configurations
WLP
TOP VIEW
(BUMP SIDE DOWN)
MAX16165
MAX16166
1
2
3
4
5
A
UVSET
VDD
ABP
OUT1
OUT2
B
SET1
ON
POK
FAULT
OUT3
C
SET2
OFF
IOS
DONE
OUT4
D
SET3
SET4
DLY
PGT
GND
+
20-Bump WLP (1.63mm x 2.03mm)
17
OUT3
18
OUT4
19
DONE
20
OUT1
ABP
VDD
UVSET
12
11
MAX16165
MAX16166
*EP
+
GND
1
2
3
4
5
SET4
FAULT
13
IOS
16
14
DLY
POK
15
PGT
TOP VIEW
OUT2
TQFN
10
ON
9
OFF
8
SET1
7
SET2
6
SET3
20L TQFN
(4mm × 4mm)
*EP = EXPOSED PAD
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Analog Devices | 9
MAX16165/MAX16166
Highly Integrated, 4-Channel Sequencer and
Supervisor
Pin Descriptions
PIN
NAME
20 WLP
TQFN
A1
11
UVSET
A2
12
VDD
A3
13
ABP
A4
14
OUT1
A5
15
OUT2
B1
8
SET1
B2
10
ON
B3
16
POK
B4
17
FAULT
B5
18
OUT3
FUNCTION
Set Monitored Threshold Input. Monitor a voltage by setting the threshold with an external
resistive divider. The threshold is 0.5V.
Device Power-Supply Input. Connect to 2.7V to 16V. Bypass VDD to GND with a 0.1μF
capacitor.
Internal Supply Bypass Input. Connect a 1μF capacitor from ABP to GND. ABP is an
internally generated voltage that powers internal circuits, and can supply more than 1mA
additional current to any external circuitry. Do not leave ABP unconnected or short to GND.
MAX16165: Open-Drain Output 1. Upon power-on sequencing (ON input rises from low to
above 0.5V), OUT1 changes from low to high impedance after sequence delay t DLY. During
power-off sequencing, when the voltage at the SET2 pin falls below 0.5V, OUT1 goes from
high impedance to low after sequence delay tDLY. OUT1 requires an external pullup resistor.
MAX16166: Push-Pull Output 1. Upon power-on sequencing (ON input rises from low to
above 0.5V), OUT1 changes from low to high after sequence delay tDLY. During power-off
sequencing, when the voltage at the SET2 pin falls below 0.5V, OUT1 goes from high to low
after sequence delay tDLY.
MAX16165: Open-Drain Output 2. During power-on sequencing, when the voltage at SET1
rises above threshold voltage (Rising), OUT2 goes from low to high impedance after
sequence delay tDLY. During power-off sequencing, when the voltage at the SET3 pin falls
below 0.5V, OUT2 goes from high impedance to low after sequence delay tDLY. OUT2
requires an external pullup resistor.
MAX16166: Push-Pull Output 2. During a power-on sequencing, when the voltage at SET1
rises above threshold voltage (Rising), OUT2 goes from low to high after sequence delay
tDLY. During a power-off sequencing, when the voltage at SET3 pin falls below 0.5V, OUT2
goes from high to low after sequence delay tDLY.
Set Monitored Threshold 1 Input. Monitor a voltage by setting the threshold with an external
resistive divider. The SET1 threshold is 0.5V. To disable Channel 1, connect SET1 to ABP.
Do not leave SET1 unconnected or short to GND. Connect OUT1 directly to SET1 for
sequencing without monitoring Channel 1.
Noninverting Comparator Input. A rising voltage above 0.5V on this pin initiates power-on
sequencing.
MAX16165: Open-Drain Power-OK Output. During power-on sequencing, when SET4 voltage
rises above 0.5V, this output changes from low to high impedance after the reset timeout
period. This output is driven low if the voltage on any SET_ or UVSET input drops below 0.5V
or when FAULT is pulled low by an an external signal. POK requires an external pullup
resistor.
MAX16166: Push-Pull Power-OK Output. During power-on sequencing, when SET4 voltage
rises above 0.5V, this output changes from low to high after the reset timeout period. This
output is driven low if the voltage on any SET_ or UVSET input drops below 0.5V or
when FAULT is pulled low by an external signal.
Bidirectional Input and Active Low Open-Drain Output. When an internal fault is detected, this
pin is asserted low. An external signal pulling this pin low disables all outputs and sets the
MAX16165/66 to initialization state.
MAX16165: Open-Drain Output 3. During power-on sequencing, when the voltage at SET2
rises above threshold voltage (Rising), OUT3 goes from low to high impedance after
sequence delay tDLY. During power-off sequencing, when the voltage at SET4 pin falls
below 0.5V, OUT3 goes from high impedance to low after sequence delay tDLY. OUT3
requires an external pullup resistor.
MAX16166: Push-Pull Output 3. During power-on sequencing, when the voltage at SET2
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Analog Devices | 10
MAX16165/MAX16166
C1
7
SET2
C2
9
OFF
C3
4
IOS
C4
20
DONE
C5
19
OUT4
Highly Integrated, 4-Channel Sequencer and
Supervisor
rises above threshold voltage (Rising), OUT3 goes from low to high after sequence delay
tDLY. During power-off sequencing, when the voltage at the SET4 pin falls below 0.5V, OUT3
goes from high to low after sequence delay tDLY.
Set Monitored Threshold 2 Input. Monitor a voltage by setting the threshold with an external
resistive divider. The SET2 threshold is 0.5V. To disable Channel 2, connect SET2 to ABP.
Do not leave SET2 unconnected or short to GND. Connect OUT2 directly to SET2 for
sequencing without monitoring Channel 2.
Noninverting Comparator Input. A falling voltage below 0.5V on this pin initiates power-off
sequencing.
Offset Current Setting Input. Connect a resistor (10kΩ to 1MΩ) to GND to set the offset
current during power-off sequencing. Do not leave it unconnected or short to GND.
MAX16165: Open-Drain Sequencing Done Output. When power-on sequencing is complete,
DONE changes from low to high impedance. During power-off sequencing, the pin remains
high impedance until SET1 voltage drops below its threshold. When a fault occurs, this pin is
asserted low.
MAX16166: Push-Pull Sequencing Done Output. When power-on sequencing is complete,
DONE changes from low to high. During power-off sequencing, the pin remains high until
SET1 voltage drops below its threshold. When a fault occurs, this pin is asserted low.
MAX16165: Open-Drain Output 4. During power-on sequencing, when the voltage at SET3
rises above threshold Voltage (Rising), OUT4 goes from low to high impedance after
sequence delay tDLY. During power-off sequencing, when the voltage at the OFF pin falls
below 0.5V, OUT4 goes from high impedance to low after sequence delay tDLY. OUT4
requires an external pullup resistor.
MAX16166: Push-Pull Output 4. During power-on sequencing, when the voltage at SET3
rises above 0.5V, OUT4 goes from low to high after sequence delay t DLY. During power-off
sequencing, when the voltage at the OFF pin falls below 0.5V, OUT4 goes from high to low
after sequence delay tDLY.
Set Monitored Threshold 3 Input. Monitor a voltage by setting the threshold with an external
resistive divider. The SET3 threshold is 0.5V. To disable Channel 3, connect SET3 to ABP.
Do not leave SET3 unconnected or short to GND. Connect OUT3 directly to SET3 for
sequencing without monitoring Channel 3.
Set Monitored Threshold 4 Input. Monitor a voltage by setting the threshold with an external
resistive divider. The SET4 threshold is 0.5V. To disable channel 4, connect SET4 to ABP. Do
not leave SET4 unconnected or short to GND. Connect OUT4 directly to SET4 for sequencing
without monitoring the Channel 4.
Adjustable Sequence Delay Timing Input. Connect a capacitor from DLY to GND to set the
sequence delay between each OUT_. Leave DLY unconnected for a 40μs (typ) delay.
Monitored Power-Supply Power-Good Timer Setting Input. The capacitor connected to this
input to GND sets the time allowed between OUT_ being enabled and SET_ voltage goes
above its threshold voltage (Rising). If SET_ does not rises above its threshold voltage
(Rising) before the timer expires, the MAX16165/MAX16166 generates a fault condition and
enters initialization state. Leave PGT unconnected for a 5μs (typ) delay.
D1
6
SET3
D2
5
SET4
D3
3
DLY
D4
2
PGT
D5
1
GND
Ground.
-
-
EP
Exposed Pad. EP is internally connected to GND. Connect EP to the GND plane for improved
heat dissipation. Do not use EP as the only ground connection.
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Analog Devices | 11
MAX16165/MAX16166
Highly Integrated, 4-Channel Sequencer and
Supervisor
Functional Diagrams
VDD
MAX16165
MAX16166
ABP
ABP LINEAR
REGULATOR
UVSET
UVLO
0.5V
ON
POK
0.5V
FAULT
OFF
0.5V
SET1
0.5V
IOFFSET
OUT1
SET2
OUT2
SET3
CONTROL
LOGIC
SET4
OUT3
OUT4
IOS
0.5V
IOFFSET
DLY
4µA
DONE
0.5V
PGT
4µA
0.5V
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Analog Devices | 12
MAX16165/MAX16166
Highly Integrated, 4-Channel Sequencer and
Supervisor
Detailed Description
The MAX16165/MAX16166 enable four power supplies when the sequencer turns on and disable the four power supplies in
reverse order when the sequencer turns off. The MAX16165/MAX16166 monitor each power supply once they are turned
on. The device also includes an undervoltage (UV) sensing input (UVSET) that monitors VDD or any other power supply.
When the sequencer initiates power-on sequencing, the MAX16165/MAX16166 provide a capacitor-adjustable delay time
(tDLY) before the first output is enabled. After the first output is enabled, the MAX16165/MAX16166 monitor the enabled
power supply voltage by feeding it back to the voltage sensing input SET1. If the voltage at SET1 reaches its threshold (V TH
+ VHYST) within a capacitor-adjustable power-good timeout period (tPGT), the sequencer waits for the delay time tDLY and
enables the second output. The power-on sequencing repeats until the fourth output is enabled and the voltage at SET4
reaches its threshold. At that time, a sequencing done output DONE asserts high and a POK output asserts high after the
reset timeout period (tRP), allowing a system microcontroller (μC) to reset and start to operate. The MAX16165/MAX16166
monitor each sequenced voltage fed back on SET_ after the respective channel is enabled. The MAX16165/MAX16166 also
monitor UVSET input for undervoltage condition after power up. If any voltage falls below its threshold, the POK and DONE
outputs deassert and all outputs are disabled simultaneously to turn off all sequenced power supplies. During any fault
condition except UVSET undervoltage detection, a one-shot pulse of pulse width 80µs (typ) is asserted on the FAULT pin.
The device enters into the fault condition and initializes the state machine, waiting for a power-on sequencing command
again. If an undervoltage condition is present at UVSET, FAULT stays low as long as the undervoltage condition persists.
When the sequencer initiates a power-off sequencing, the MAX16165/MAX16166 provide the delay time t DLY before the
fourth output is disabled. At the time the fourth output is disabled, the device injects a resistor-programmable offset current
(IOFFSET) to SET4 input and monitors the voltage at SET4. When SET4 voltage drops below its threshold, the
MAX16165/MAX16166 wait for another delay time tDLY, and then disable the third output. The power-off sequencing repeats
until the first output is disabled. When the power-off sequencing is completed, DONE output asserts low. The
MAX16165/MAX16166 can be cascaded to control a higher number of power supplies in a system.
FAULT Input/Output
FAULT is bidirectional. It is an active low input and active low open-drain output. When an internal fault is detected, this pin
is asserted low. An external signal pulling this pin low disables all outputs and sets the MAX16165/MAX16166 to a fault
condition. See the State Diagram for all the conditions that assert a FAULT. During any fault condition except UVSET
undervoltage detection, a one-shot pulse of pulse width 80µs (typ) is asserted. See the Applications Information section to
understand how the FAULT output can be modified to achieve extended assert duration in applications where DC-DC
converters having slow powerup are used.
For multichip solutions, all of the FAULT input/outputs can be connected together. In case of a fault condition, all outputs on
every device are turned off simultaneously.
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Analog Devices | 13
MAX16165/MAX16166
Highly Integrated, 4-Channel Sequencer and
Supervisor
EXERNAL FAULT
INPUT RELEASE
NORMAL OPERATION
INITIALIZATION
tFAULT_TIMEOUT
______
FAULT IN
WAIT POWER ON
SEQUENCING
OUT_
tFAULT_OUT
DONE
POK
Note : Typical value of t FAULT_TIMEOUT is 80µs
Typical value of tFAULT_OUT is 3us
Rising Edge on EN initiates the Power ON Sequencing after Initialization State
Figure 1. External Fault Response
INITIALIZATION
NORMAL OPERATION
VUVSET
VUVSET > VTH +VHYST
WAIT POWER ON
SEQUENCING
VUVSET < VTH
______
FAULT OUT
tFAULT_TIMEOUT
OUT_
tUVSET_FAULT
DONE
POK
Note : Typical value of t FAULT_TIMEOUT is 80µs
Typical value of tUVSET_FAULT is 1us
Rising Edge on EN initiates the Power ON Sequencing after Initialization State
Figure 2. UVSET Fault Response
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Analog Devices | 14
MAX16165/MAX16166
NORMAL OPERATION
VOUT_
______
FAULT OUT
Highly Integrated, 4-Channel Sequencer and
Supervisor
INITIALIZATION
WAIT POWER ON
SEQUENCING
VSET_ < VTH
tFAULT_HOLD
OUT_
tSET_FAULT
DONE
POK
Note : Typical value of tFAULT_TIMEOUT is 80µs
Typical value of tSET_FAULT is 1us
Rising Edge on EN initiates the Power ON Sequencing
VOUT_ is the LDO output
Figure 3. SET Fault Response
Skip or Disable Channels
If fewer than four channels are required, skip a channel by connecting the SET_ pin to ABP pin. The sequencing is similar
with four-channel sequencing, just treat the MAX16165/MAX16166 like fewer channels. For example, if SET2 is connected
to ABP, all logic for Channel 2 is removed from the state machine so there is not a delay, timer, UV detection, or fault triggered
from this channel. If all channels are skipped, the device asserts DONE and POK immediately after initialization.
Channel skipping decision is decided during the initialization phase after every fault condition. The MAX16165/MAX16166
checks for the respective SET_ voltage during the initialization phase. If the voltage at SET_ is above 0.5V, the corresponding
channel gets skipped. Therefore, it is important to ensure the voltage at SET_ is below 0.5V after each fault condition. If the
power supplies are not properly loaded, it can take a long time to discharge the channel SET_ voltage. This situation is more
crucial when VOFF voltage levels are low or the load current of the power supply is less. See the Applications Information
section for more information on how to avoid the false skipping of channels in this situation.
ON and OFF Inputs
The ON and OFF inputs are edge triggered inputs with a threshold of 500mV, which are used to initiate power sequencing.
If no FAULT condition persists, a rising edge on the ON input initiates power-on sequencing while a falling edge on OFF
initiates a power-down sequencing in the reverse order. A falling edge on ON input and a rising edge on OFF input are
ignored. Normally ON and OFF inputs are tied together and used separately in special cases such as daisy-chaining.
It is important to ensure a voltage above 0.5V at ON input until the sequencing gets completed. If the ON input voltage falls
below 0.5V or another rising edge happens at ON input, a FAULT is asserted resulting in stopping the sequencing and
simultaneous power-off of all the outputs. See the Daisy-Chaining the MAX16165/MAX16166 and Typical Application
Circuits sections for more information.
State Diagram
www.analog.com
Analog Devices | 15
MAX16165/MAX16166
Highly Integrated, 4-Channel Sequencer and
Supervisor
EXIT UVLO
F
INITIALIZATION
OUT1: LOW DONE: LOW
OUT2: LOW POK: LOW
OUT3: LOW FAULT OUT: LOW
OUT4: LOW IOFFSET: OFF
VALID CHANNEL DETECTION
NOTE: F = FAULT CONDITION
FAULT HOLD TIMEOUT and
FAULT IN: HIGH and
VUVSET > VTH
TURN OFF IOS
IOFFSET: OFF
VSET1 < VTH
F
F
F
F
F
F
F
FAULT IN: LOW or
ON: RISING EDGE or
VUVSET < VTH
FAULT IN: LOW or
ON: RISING EDGE or
(VUVSET or VSET1) < VTH
FAULT IN: LOW or
ON: RISING EDGE or
(VUVSET or VSET1) < VTH
FAULT IN: LOW or
ON: RISING EDGE or
(VUVSET or VSET1 or VSET2) < VTH
FAULT IN: LOW or
ON: RISING EDGE or
(VUVSET or VSET1 or VSET2) < VTH
FAULT IN: LOW or
ON: RISING EDGE or
(VUVSET or VSET1 or VSET2 or VSET3) < VTH
FAULT IN: LOW or
ON: RISING EDGE or
(VUVSET or VSET1 or VSET2 or VSET3) < VTH
DISABLE OUT1
INJECT IOFFSET ON SET1
OUT1: LOW
tDLY EXPIRES
DELAY 1
DELAY TIMER STARTS
VSET2 < VTH
DISABLE OUT2
INJECT IOFFSET ON SET2
OUT2: LOW
tDLY EXPIRES
DELAY 2
DELAY TIMER STARTS
VSET3 < VTH
DISABLE OUT3
INJECT IOFFSET ON SET3
OUT3: LOW
tDLY EXPIRES
DELAY 3
DELAY TIMER STARTS
VSET4 < VTH
DISABLE OUT4
INJECT IOFFSET ON SET4
OUT4: LOW
FAULT IN: LOW or
tDLY EXPIRES
ON: RISING EDGE or
DELAY 4
(VUVSET or VSET1 or VSET2 or VSET3 or VSET4) < VTH
DELAY TIMER STARTS
F
WAIT POWER-ON SEQUENCING
OUT1: LOW DONE: LOW
OUT2: LOW POK: LOW
OUT3: LOW FAULT OUT: HIGH
OUT4: LOW IOFFSET: OFF
ON: RISING EDGE
DELAY 1
DELAY TIMER STARTS
tDLY EXPIRES
ENALE OUT1
OUT1: HIGH
POWER GOOD TIMER STARTS
VSET1 > VTH
DELAY 2
DELAY TIMER STARTS
tDLY EXPIRES
ENALE OUT2
OUT2: HIGH
POWER GOOD TIMER STARTS
VSET2 > VTH
DELAY 3
DELAY TIMER STARTS
tDLY EXPIRES
ENALE OUT3
OUT3: HIGH
POWER GOOD TIMER STARTS
VSET3 > VTH
DELAY 4
DELAY TIMER STARTS
tDLY EXPIRES
ENALE OUT4
OUT4: HIGH
POWER GOOD TIMER STARTS
VSET4 > VTH
DEASSERT POK
POK: LOW
IOFFSET: ON
OFF: FALLING EDGE
www.analog.com
POWER-ON SEQUENCING DONE
DONE: HIGH
POK RESET TIMER STARTS
tRP EXPIRES
SET POK (NORMAL OPERATION)
POK: HIGH
FAULT IN: LOW or
VUVSET < VTH
F
FAULT IN: LOW or
OFF: FALLING EDGE or
VUVSET < VTH
F
FAULT IN: LOW or
OFF: FALLING EDGE or
VUVSET < VTH or
tPGT EXPIRES
F
FAULT IN: LOW or
OFF: FALLING EDGE or
(VUVSET or VSET1) < VTH
F
FAULT IN: LOW or
OFF: FALLING EDGE or
(VUVSET or VSET1) < VTH or
tPGT EXPIRES
F
FAULT IN: LOW or
OFF: FALLING EDGE or
(VUVSET or VSET1 or VSET2) < VTH
FAULT IN: LOW or
OFF: FALLING EDGE or
(VUVSET or VSET1 or VSET2) < VTH or
tPGT EXPIRES
FAULT IN: LOW or
OFF: FALLING EDGE or
(VUVSET or VSET1 or VSET2 or VSET3) < VTH
FAULT IN: LOW or
OFF: FALLING EDGE or
(VUVSET or VSET1 or VSET2 or VSET3) < VTH or
tPGT EXPIRES
FAULT IN: LOW or
ON: RISING EDGE or
(VUVSET or VSET1 or VSET2 or VSET3 or VSET4) < VTH
FAULT IN: LOW or
ON: RISING EDGE or
(VUVSET or VSET1 or VSET2 or VSET3 or VSET4) < VTH
F
F
F
F
F
F
Analog Devices | 16
MAX16165/MAX16166
Highly Integrated, 4-Channel Sequencer and
Supervisor
Applications Information
Selecting SET_ Feedback Resistors and Offset Current
For each sequenced power supply, choose a voltage when the power supply is considered to be ON during power-on
sequencing (VON) and a voltage when the power supply is considered to be OFF during power-off sequencing (VOFF).
During power-off sequencing, an offset current IOFFSET is injected to the SET_ pin so that VOFF is lower than VON (see
Figure 4). Calculate resistor values according to the following equations:
𝑉𝑂𝑁 − 𝑉𝑂𝐹𝐹
R1 = (
)
𝐼𝑂𝐹𝐹𝑆𝐸𝑇
R2 = R1 × (
0.5𝑉
)
𝑉𝑂𝑁
Use the formula shown below to calculate the RIOS for an offset current IOFFSET:
0.5𝑉
𝑅𝐼𝑂𝑆 = (
)
𝐼𝑂𝐹𝐹𝑆𝐸𝑇
For example, if power supply V1 nominal voltage is 1.8V, choose VON = 1.71V and VOFF = 0.8V, offset current IOFFSET =
5μA, R1 = 182kΩ, R2 = 75.21kΩ.
1.71𝑉 − 0.8𝑉
) = 182𝑘Ω
5µ𝐴
0.5𝑉
R2 = 182kΩ × (
) = 75.21𝑘Ω
1.71𝑉 − 0.5𝑉
0.5𝑉
𝑅𝐼𝑂𝑆 = (
) = 10𝑘Ω
5µ𝐴
R1 = (
V1
V1 Nominal = 1.8V
VON = 1.71V
VOFF = 0.8V
I1
IOFFSET
R1
SET1
I2
IOFFSET
R2
0.5V
MAX16165
MAX16166
Figure 4. Design of SET_ Feedback Resistors and Offset Current
Connect a resistor with 1% tolerance from 10kΩ to 1MΩ at the IOS pin to achieve an offset current from 0.5µA to 50µA. To ensure
correct power-down sequencing, adhere to the calculations provided in this section and calculate the SET_ divider resistors in
accordance with the IOFFSET chosen. The resistor connected at IOS decides the IOFFSET of all the channels.
www.analog.com
Analog Devices | 17
MAX16165/MAX16166
Highly Integrated, 4-Channel Sequencer and
Supervisor
Sequence Delay Time Input
When the power-on sequence starts, the sequence delay time input (DLY) has an internal switch in series with an internal
current source of 4µA, which is connected to the CDLY present at the DLY pin. This current charges the CDLY linearly until the
voltage reaches the threshold of 0.5V and signal to continue enabling the subsequent channel. Connect a capacitor (CDLY)
between DLY and GND to adjust the sequencing delay period (tDLY) that occurs between sequenced channels. Use the
following formula to estimate the delay:
𝑡𝐷𝐿𝑌 = 125𝐾𝛺 𝑋 𝐶𝐷𝐿𝑌
where tDLY is in seconds and CDLY is in Farads. Leave DLY unconnected for the minimum 40μs (typ) delay. After each tDLY
the DLY capacitor discharges (internal 4Ω) with typical 40µs (tDISCHARRGE) shown in Figure 5. The accuracy of the tDLY is
affected by the CDLY capacitor leakage and tolerance. A low leakage ceramic capacitor is recommended.
EN
(ON/OFF)
0.5V
CDLY
CDLY discharge
First channel
Fixed 40µs
delay
Second
channel
tDLY
CPGT discharge
Fixed 40µs
delay
CPGT
tP
Note : tP is time between OUT_ high to SET_ > 0.5V, for no fault condition t P < tPGT
CDLY and CPGT capacitors are discharged with
typical) internal resistor
Figure 5. Charging and Discharging of DLY and PGT Capacitor
Power-Good Timer (PGT) and Power-Good Time Input
The Power Good Timer is used to check the capability of a power supply to reach a set voltage within a capacitor adjustable
delay (tPGT). The FAULT output is asserted when any enabled voltage cannot reach its threshold on the SET_ pin within
tPGT. The internal state machine should stop the PGT if SET_ voltage reaches 0.5V before the PGT expires. The
MAX16165/MAX16166 do not have to wait for tPGT to expire before moving to the next step. The PGT is only for power-on
sequencing and not used during power-off sequencing. Like the DLY timer, the PGT circuit is also enabled by a 4μA current
source to charge the CPGT capacitor.
Connect a capacitor (CPGT) between PGT and GND to adjust the sequencing delay period (t PGT). Use the following formula
to estimate the delay:
𝑡𝐷𝐿𝑌 = 5µ𝑠 + 125𝐾𝛺 𝑋 𝐶𝐷𝐿𝑌
where tPGT is in seconds and CPGT is in Farads. Leave PGT unconnected for a minimum 5μs (typ) delay. The accuracy of the
delay is affected by the CPGT capacitor leakage and tolerance. A low-leakage ceramic capacitor is recommended.
Pullup Resistor Values
The exact value of the pullup resistors for the open-drain outputs is not critical, but some consideration should be made to
ensure the proper logic levels when the device is sinking current. For example, if V DD = 3.3V and the pullup voltage is 5V,
keep the sink current less than 3.2mA as shown in the Electrical Characteristics table. As a result, the pullup resistor should
be greater than 1.6kΩ. For a 12V pullup, the resistor should be larger than 3.74kΩ.
www.analog.com
Analog Devices | 18
MAX16165/MAX16166
Highly Integrated, 4-Channel Sequencer and
Supervisor
Daisy-Chaining the MAX16165/MAX16166
Multiple MAX16165/MAX16166 devices can be daisy-chained to sequence and monitor a large number of voltages. When a
fault occurs on any of the monitored inputs, FAULT goes low which signals a fast power-down. Connect all FAULT pins of
the MAX16165/MAX16166 together to ensure that all power supplies are turned off during a fault. Figure 13 shows an
example of two daisy-chained devices.
Selector Guide
MAX1616_ _ __ _+T
SUF
OUTPUT
SUF
TEMPERATURE
RANGE
SUF
PACKAGE
5
OPENDRAIN
A
-40°C TO +125°C
WP
WLP
6
PUSHPULL
TP
TQFN
SUF
A
B
C
D
E
F
G
H
I
J
K
L
M
POK RESET
TIMEOUT (NOM)
20us
1ms
5ms
10ms
20ms
30ms
50ms
100ms
200ms
300ms
500ms
1000ms
2000ms
Layout and Bypassing
For better noise immunity, bypass VDD to GND with a 0.1μF capacitor installed as close to the device as possible. Bypass
ABP to GND with a 1μF capacitor installed as close to the device as possible. Minimize stray capacitance on the SET_
inputs. The layout of the divider resistors should be as close to the MAX16165/MAX16166 as possible. Connect the exposed
pad (EP) to the ground plane for improved heat dissipation. Do not use EP as the only ground connection for the device.
www.analog.com
Analog Devices | 19
MAX16165/MAX16166
Highly Integrated, 4-Channel Sequencer and
Supervisor
Typical Application Circuits
Sequence Four Power Supplies, Monitor VDD, and Power-Good/Power-OK Outputs
5V
MAX16165 ONLY
UVSET
EN
VDD
ABP
FAULT
POK
SYSTEM
RESET
DONE
NEXT
MAX16165/6
ON
OFF
SET1
SET1
OUT1
PG2
SET2
PG3
SET3
OUT3
PG4
SET4
OUT4
MAX16165
MAX16166
IOS
DLY
PGT
SET1
EN
IN
3.3V
OUT
OUT2
EN
IN OUT
PG
2.5V
PG2
EN
GND
IN OUT
PG
1.8V
PG3
EN
IN OUT
PG
1.2V
PG4
Figure 6. Sequence Four Power Supplies, Monitor VDD, V1 = 3.3V, and Power-Good Signals of the Other Three Power Supplies.
Monitor VDD and Sequence Four Power Supplies, without Monitoring
5V
MAX16165 ONLY
UVSET
EN
VDD
ABP
FAULT
ON
POK
OFF
DONE
OUT1
SET1
OUT1
OUT2
SET2
OUT3
SET3
OUT3
OUT4
SET4
OUT4
MAX16165
MAX16166
IOS
DLY
PGT
OUT2
SYSTEM
RESET
OUT1
NEXT
MAX16165/6
EN
IN
3.3V
OUT
OUT2
OUT3
EN
IN
2.5V
OUT
OUT4
GND
EN
IN
1.8V
OUT
EN
IN
OUT
1.2V
Figure 7. Sequence Four Power Supplies, without Monitoring. Only Monitor V DD.
www.analog.com
Analog Devices | 20
MAX16165/MAX16166
EN
(ON/OFF )
Highly Integrated, 4-Channel Sequencer and
Supervisor
tDISCHARGE
tDLY
OUT1
tP
tDISCHARGE
OUT2
tP
tDLY
tDLY
OUT3
tP
tDLY
OUT4
tP
DONE
tRP
POK
Note : 1.Typical value of t DISCHARGE is 40µs
2. tP is time between OUT_ high to SET_ > 0.5V, for no fault condition t P < tPGT
Figure 8. Power-Up Sequencing Timing Diagram. See the Typical Application Circuit (Figure 3).
EN
(ON/OFF )
tDISCHARGE
OUT4
tDLY
OUT3
tDLY
OUT2
tDLY
OUT1
tDLY
DONE
POK
OFF to POK
Delay
Note : Typical value of t DISCHARGE is 43µs
Typical value of OFF to POK delay is 1-2us
Figure 9. Power-Down Sequencing Timing Diagram. See the Typical Application Circuit (Figure 3).
www.analog.com
Analog Devices | 21
MAX16165/MAX16166
Highly Integrated, 4-Channel Sequencer and
Supervisor
Sequence and Monitor Four Power Supplies and Monitor VDD
5V
MAX16165 ONLY
UVSET
EN
1.2V 1.8V 2.5V 3.6V
VDD
ABP
VDD
FAULT
ON
POK
OFF
DONE
SET1
OUT3
SET4
OUT4
DLY
PGT
EN
OUT2
SET3
IOS
NEXT
MAX16165/6
OUT1
MAX16165
MAX16166
SET2
RESET
EN
EN
GND
EN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
3.6V
2.5V
FPGA
DSP
SoC
1.8V
1.2V
DC-DC CONVERTERS
Figure 10. Sequence Four Power Supplies and Monitor VDD and the Four Power Supplies.
EN
(ON/OFF )
VOUT1
VOUT2
VOUT3
VOUT4
tP
tDLY
SET1 > 0.5V
tDISCHARGE
tP
tDLY
SET2 > 0.5V
tP
tDLY
SET3 > 0.5V
tP
tDLY
SET4 > 0.5V
DONE
tRP
POK
Note : 1.Typical value of t DISCHARGE is 40µs
2. tP is time between OUT_ high to SET_ > 0.5V, for no fault condition t P < tPGT
3 VOUT_ is the LDO output
Figure 11. Power-Up Monitoring Timing Diagram. See the Typical Application Circuit (Figure 6).
www.analog.com
Analog Devices | 22
MAX16165/MAX16166
EN
(ON/OFF )
Highly Integrated, 4-Channel Sequencer and
Supervisor
tDISCHARGE
VOUT4
SET4 < 0.5V
tDLY
SET3 < 0.5V
VOUT3
tDLY
VOUT2
SET2 < 0.5V
tDLY
VOUT1
SET1 < 0.5V
tDLY
DONE
POK
OFF to POK
Delay
Note : 1 Typical value of t DISCHARGE is 43µs
2 Typical value of OFF to POK delay is 1-2u
3 VOUT_ is the LDO output
Figure 12. Power-Down Monitoring Timing Diagram. See the Typical Application Circuit (Figure 6).
Daisy-Chaining Using MAX16165/MAX16166
EN
VDD
MAX16165 ONLY
UVSET
VDD
ABP
FAULT
FAULT
GND
OFF
V1
SET1
OUT1
V2
SET2
V3
V4
FAULT
DONE
ON
MAX16165
MAX16166
OUT2
OUT3
SET3
SET4
OUT4
ABP
OFF
DONE
GND
V5
SET1
OUT1
V6
SET2
OUT4
V7
SET3
V8
OUT2
OUT3
SET4
OUT4
PGT
POK
DCDC
DLY
OUT7
OUT8
DCDC
IOS
VDD
OUT6
DCDC
V1 V2 V3 V4
MAX16165
MAX16166
MAX16165 ONLY
OUT5
DCDC
DCDC
POK
OUT3
DCDC
PGT
OUT2
DCDC
DLY
VDD
MAX16165 ONLY VDD
OUT1
DCDC
IOS
UVSET
ON
V5 V6 V7 V8
POK
Figure 13. Sequence and Monitor Eight Power Supplies and Monitor V DD.
www.analog.com
Analog Devices | 23
MAX16165/MAX16166
Highly Integrated, 4-Channel Sequencer and
Supervisor
Ordering Information
PART NUMBER
TEMP. RANGE
MAX16166AWPH+T
-40°C to +125°C
MAX16166A---+T*
-40°C to +125°C
MAX16165A---+T*
-40°C to +125°C
PIN-PACKAGE
20 WLP
See Selector
Guide for
information
See Selector
Guide for
information
OUTPUTS
POK RESET
TIMEOUT
Push-pull
100ms
Push-pull
See Selector Guide for
information
Open-drain
See Selector Guide for
information
+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
*Future product—contact factory for availability.
www.analog.com
Analog Devices | 24
MAX16165/MAX16166
Highly Integrated, 4-Channel Sequencer and
Supervisor
Revision History
REVISION
NUMBER
0
REVISION
DATE
11/21
DESCRIPTION
Release for Market Intro
PAGES
CHANGED
—
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is
assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that
may result from its use. Specifications subject to change without notice. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the
property of their respective owners.
w w w . a n a l o g . c o m
Analog Devices | 25
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