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MAX16712
General Description
The MAX16712 is a dual-output, fully integrated, highly
efficient, step-down DC-DC switching regulator. The
device operates from 2.7V to 16V input supplies, and
each output can be regulated from 0.5V to 5.8V. The IC
delivers up to 6A of load current per output. The two
outputs can be connected in parallel as a single-output,
dual-phase regulator that supports up to 12A load
current.
Dual-Output, 6A, 2MHz, 2.7V to 16V
Step-Down Switching Regulator
Benefits and Features
•
High Power Density with Low Component Count
• Dual-Output or Dual-Phase Operation
• Single-Supply Operation with Integrated LDO for
Bias Generation
• Compact 2.2mm x 3.5mm, 28-Bump WLP
• Internal Compensation
•
Wide Operating Range
• 2.7V to 16V Input Voltage Range
• 0.5V to 5.8V Output Voltage Range
• 500kHz to 2MHz Configurable Switching
Frequency
• -40°C to +125°C Junction Temperature Range
• Three Programming Pins to Select Different
Configurations
• Independent Enable and Power Good for Each
Output
•
Optimized Performance and Efficiency
• 90.5% Peak Efficiency with VDDH = 12V,
VOUT = 1.8V, and fSW = 1MHz
• Interleaved 180° Out-of-Phase Operation
• AMS to Improve Load Transient
• Selectable DCM to Improve Light Load Efficiency
• Active Current Balancing for Dual-Phase Operation
The switching frequency of the device can be configured
from 500kHz to 2.0MHz and provides the capability of
optimizing the design in terms of solution size and
performance.
The MAX16712 utilizes fixed-frequency, current-mode
control with internal compensation. The dual-switching
regulators operate 180° out-of-phase. The IC features
an advanced modulation scheme (AMS) and selectable
discontinuous current mode (DCM) operation to provide
improved performance. Operation settings and
configurable features can also be selected by
connecting a pin-strap resistor from PGM0 pin to ground.
The MAX16712 has an internal 1.8V LDO output to
power the gate drives (VCC) and internal circuitry
(AVDD).
The MAX16712 integrates multiple protections including
positive and negative overcurrent protection, output
overvoltage protection and overtemperature protection
to ensure robust design.
The device is available in a compact 2.2mm x 3.5mm
wafer-level package (WLP). It supports -40°C to +125°C
junction temperature operation.
Applications
•
•
•
•
•
•
•
Communications Equipment
Networking Equipment
Servers and Storage Equipment
Point-of-Load (POL) Voltage Regulators
μP Chipsets
Memory VDDQ
I/O Pins of an FPGA/DSP/MCU
DESCRIPTION
CURRENT
RATING*
(DUALPHASE)
(A)
12
INPUT
VOLTAGE
(V)
OUTPUT
VOLTAGE
(V)
Electrical Rating
2.7 to 16
0.5 to 5.8
Thermal Rating
TA = +55°C,
12
12
3.3
200LFM Airflow
Thermal Rating
TA = +85°C,
10
12
0.8
No Airflow
*Maximum TJ = +125°C. For specific operating conditions, see
the Safe Operating Area (SOA) curves in the Typical Operating
Characteristics section.
Ordering Information appears at end of data sheet.
19-101017; Rev 1; 2/22
© 2022 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective ow ners.
O ne An al o g W ay , W i l mi ngt o n, MA 0 18 87 U.S .A. | T el : 7 81. 32 9. 47 00 | © 202 2 An al o g Dev i c es , I nc . Al l ri g hts r es erv ed .
MAX16712
Dual-Output, 6A, 2MHz, 2.7V to 16V
Step-Down Switching Regulator
Simplified Block Diagram
DUAL-OUTPUT APPLICATION CIRCUIT
2.7V TO 16V INPUT
MAX16712
VDDH1
BST2
VDDH2
LX2
OUTPUT2: 0.5V TO 5.8V, 6A
SNSP2
VCC
AVDD
BST1
PGOOD1
LX1
PGOOD2
EN1
OUTPUT1: 0.5V TO 5.8V, 6A
SNSP1
EN2
CONNECT TO AGND
OR AVDD OR OPEN
PGM2
PGM1
PGM0
AGND
PGND
SINGLE-OUTPUT, DUAL-PHASE APPLICATION CIRCUIT
2.7V to 16V INPUT
MAX16712
VDDH1
BST2
VDDH2
LX2
OUTPUT: 0.5V to 5.8V, 12A
AVDD
VCC
SNSP2
AVDD
PGOOD1
PGOOD2
EN1
EN2
CONNECT TO AGND
OR AVDD OR OPEN
BST1
COUPLED
INDUCTOR
OR
DISCRETE
INDUCTORS
LX1
SNSP1
PGM2
PGM1
PGM0
AGND
www.maximintegrated.com
PGND
19-101017; Rev 1; 2/22
Maxim Integrated | 2
Dual-Output, 6A, 2MHz, 2.7V to 16V
Step-Down Switching Regulator
MAX16712
Absolute Maximum Ratings
VDDH1, VDDH2 to PGND (Note 1) ......................... -0.3V to +19V
PGND to AGND .................................................. -0.3V to +0.3V
LX1, LX2 to PGND (DC) ..................................... -0.3V to +19V
VCC to PGND ...................................................... -0.3V to +2.5V
LX1, LX2 to PGND (AC) (Note 2) ........................ -10V to +23V
AVDD to AGND .................................................. -0.3V to +2.5V
VDDH1 to LX1 (DC) (Note 1) ................................ -0.3V to +19V
EN1, EN2 to AGND ............................................... -0.3V to +4V
VDDH1 to LX1 (AC) (Note 2) ................................. -10V to +23V
PGOOD1, PGOOD2 to AGND .............................. -0.3V to +4V
VDDH2 to LX2 (DC) (Note 1) ................................ -0.3V to +19V
VDDH2 to LX2 (AC) (Note 2) ................................. -10V to +23V
BST1, BST2 to PGND (DC) ............................. -0.3V to +21.5V
BST1, BST2 to PGND (AC) (Note 2) .................. -7V to +25.5V
BST1 to LX1 ....................................................... -0.3V to +2.5V
BST2 to LX2 ....................................................... -0.3V to +2.5V
SNSP1, SNSP2 to AGND .......................-0.3V to AVDD + 0.3V
PGM0, PGM1, PGM2 to AGND..............-0.3V to AVDD + 0.3V
Peak LX_ Current ................................................. -12A to +19A
Junction Temperature (TJ) (Note 3) ............................... +150°C
Storage Temperature Range .......................... -65°C to +150°C
Peak Reflow Temperature Lead-Free ........................... +260°C
Note 1: Input HF capacitors placed not more than 40 mils away from the VDDH pin required to keep inductive voltage spikes within
Absolute Maximum limits.
Note 2: AC is limited to 25ns.
Note 3: Recommended operating junction temperature from -40°C to +125°C. The device guarantees 90k hours of continuous
operation with 6A output current per output/phase at +85°C junction temperature, or 40k hours of continuous operation with
4.8A output current per output/phase at +105°C junction temperature, for a typical application with 12V input, 1.2V output.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or
any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Information
28 WLP
Package Code
Outline Number
Land Pattern Number
Junction-to-Ambient Thermal Resistance (θJA) JEDEC
Junction-to-Ambient Thermal Resistance (θJA) on
W282D3Z+1
21-100392
Refer to Application Note 1891
42.26°C/W
27.3°C/W
MAX16712EVKIT# (no heat sink, no airflow)
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations,
refer to www.maximintegrated.com/thermal-tutorial.
www.analog.com
Analog Devices | 3
Dual-Output, 6A, 2MHz, 2.7V to 16V
Step-Down Switching Regulator
MAX16712
Electrical Characteristics
(See the Typical Application Circuits VDDH = 12V, TA = TJ = -40°C to +125°C, unless otherwise noted. Specifications are production
tested at TA = +32°C; limits within the operating temperature range are guaranteed by design and characterization.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
16
V
INPUT SUPPLY
Input Voltage Range
VDDH
Input Supply Current
IVDDH
Internal LDO Regulated
Output
Lockout
VDDH_ Overvoltage
EN_ = AGND
VCC
2.2
1.71
mA
1.95
80
Linear Regulator
Current Limit
AVDD Undervoltage
Lockout
AVDD Undervoltage
Lockout Hysteresis
VDDH_ Undervoltage
Lockout
VDDH_ Undervoltage
Lockout Hysteresis
VDDH_ Overvoltage
2.7
VCC < 1.6V
AVDDUVLO
Rising
mA
20
1.65
1.67
1.70
55
VDDH_UVLO
Rising
2.4
2.5
Rising
17.3
17.8
2.6
V
mV
18.3
500
Lockout Hysteresis
V
mV
100
VDDH_OVLO
V
V
mV
OUTPUT VOLTAGE RANGE AND ACCURACY
Internal Reference
Voltage
Voltage Sense Leakage
Current
TA = TJ = 0°C to +85°C
ISNSP_
0.495
0.500
0.505
0.497
0.500
0.503
TA = TJ = +25°C
1
V
μA
SWITCHING FREQUENCY
500
600
750
Switching Frequency
fSW_
1000
kHz
1200
1500
2000
Switching Frequency
Accuracy
Phase Shift Between
Two Outputs/Phases
Minimum Controllable
On-Time
Minimum Controllable
Off-Time
-10
+10
180
%
degrees
IOUT = 0A (Note 4)
50
ns
IOUT = 0A (Note 4)
110
ns
ENABLE AND STARTUP
Initialization Time
EN_ Threshold
www.analog.com
tINIT
800
Rising
Falling
µs
0.9
0.6
V
Analog Devices | 4
Dual-Output, 6A, 2MHz, 2.7V to 16V
Step-Down Switching Regulator
MAX16712
(See the Typical Application Circuits VDDH = 12V, TA = TJ = -40°C to +125°C, unless otherwise noted. Specifications are production
tested at TA = +32°C; limits within the operating temperature range are guaranteed by design and characterization.)
PARAMETER
SYMBOL
tEN_RISING_DE
EN_ Filtering Delay
CONDITIONS
MIN
TYP
Rising
200
Falling
2
MAX
LAY
tEN_FALLING_D
UNITS
μs
ELAY
Soft-Start Time
tSS
3
ms
POWER-GOOD AND FAULT PROTECTIONS
IPGOOD_ = 4mA
PGOOD_ Output Low
Output Undervoltage
(UV) Threshold
Output UV Deglitch
Delay
Output Overvoltage
Protection (OVP)
Threshold
Output OVP Deglitch
Delay
Positive Overcurrent
Protection (POCP)
Threshold
-16
10
BST UVLO Threshold
Hysteresis
Overtemperature
Protection (OTP) Rising
Threshold
POCP
%
μs
13
16
8.1
9.0
9.9
Inductor Peak Current, POCP = 6A
5.4
6.0
6.6
Inductor Peak Current, POCP = 4.5A
4.05
4.50
4.95
36
FPOCP
NOCP
12.5
With respect to POCP threshold (typ)
14.5
VBST
Rising
1.47
OTP
OTP Hysteresis
tHICCUP
OVP, POCP, or NOCP
1.57
A
ns
16.5
-83
-20
%
μs
Inductor Peak Current, POCP = 9A
OTP Accuracy
Hiccup Protection Time
-10
2
NOCP Accuracy
BST UVLO Threshold
V
2
POCP Deglitch Delay
Fast Positive
Overcurrent Protection
(FPOCP) Threshold
Negative Overcurrent
Protection (NOCP)
Threshold to POCP
Threshold Ratio
-13
0.4
A
%
+20
%
1.62
V
60
mV
155
°C
6
%
20
°C
20
ms
DCM OPERATION MODE
DCM Comparator
Threshold to Enter DCM
DCM Comparator
Threshold to Exit DCM
POCP = 9A, Inductor Valley Current
-440
POCP = 6A, Inductor Valley Current
-310
POCP = 4.5A, Inductor Valley Current
-220
Inductor Valley Current
100
mA
mA
PROGRAMMING PINS
PGM0 Pin Resistor
Range
www.analog.com
0.095
115
kΩ
Analog Devices | 5
Dual-Output, 6A, 2MHz, 2.7V to 16V
Step-Down Switching Regulator
MAX16712
(See the Typical Application Circuits VDDH = 12V, TA = TJ = -40°C to +125°C, unless otherwise noted. Specifications are production
tested at TA = +32°C; limits within the operating temperature range are guaranteed by design and characterization.)
PARAMETER
SYMBOL
CONDITIONS
MIN
PGM0 Resistor
Accuracy
TYP
-1
PGM_ Pin OPEN
+1
%
0.9
V
0.24 ×
AVDD
PGM_ Pin Connected to AGND or PGM0
PGM1/PGM2 Input
Current
UNITS
AVDD 0.23
PGM_ Pin Connected to AVDD
PGM1/PGM2 3-Level
Detection Thresholds
MAX
PGM_ Pin Connected to AVDD
140
PGM_ Pin Connected to AGND or PGM0
-125
μA
Note 4: Guaranteed by design.
Typical Operating Characteristics
(VDDH = 12V, tested on MAX16712EVKIT#, TA = +25°C, unless otherwise noted.)
EFFICIENCY (MAX16712)
(SINGLE-PHASE, L = PA5003.XXXNLT)
(VDDH = 12V, fSW = 1MHz)
toc01
toc02
100
95
90
90
80
VOUT = 0.8V
VOUT = 1.0V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 3.3V
VOUT = 5.0V
75
70
65
0
1
2
3
4
85
80
VOUT = 0.8V
VOUT = 1.0V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 3.3V
75
70
65
5
0
6
1
toc04
80
1.001
2
3
4
50
40
30
DCM ENABLED
DCM DISABLED
5
65
6
0
0
0.1
0.2
0.3
0.4
LOAD CURRENT (A)
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0.5
2
3
4
5
6
LOAD AND LINE REGULATIONS
(SINGLE-PHASE OPERATION)
(VOUT = 1.0V)
SAFE OPERATING AREA (MAX16712)
(VDDH = 12V, fSW = 1MHz)
(400LFM AIRFLOW, NO HEATSINK, 2 PHASE)
toc05
toc06
14
12
1.0006
1.0004
1.0002
1
0.9998
0.9996
VIN = 2.7V
VIN = 5.0V
VIN = 9.0V
VIN = 12V
VIN = 16V
0.9994
0.999
0.6
1
LOAD CURRENT (A)
0.9992
20
VOUT = 0.8V
VOUT = 1.0V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 3.3V
VOUT = 5.0V
70
OUTPUT CURRENT (A)
MEASURED OUTPUT VOLTAGE (V)
EFFICIENCY (%)
60
80
75
1.0008
70
85
LOAD CURRENT (A)
LOAD CURRENT (A)
EFFICIENCY
(MAX16712, DCM vs CCM)
(VDDH = 12V, VOUT = 1.0V, fSW = 1MHz)
EFFICIENCY (%)
95
90
85
toc03
100
95
EFFICIENCY (%)
EFFICIENCY (%)
100
EFFICIENCY (MAX16712)
(SINGLE-PHASE, L = PA5005.XXXNLT)
(VDDH = 12V, fSW = 500kHz)
EFFICIENCY (MAX16712)
(SINGLE-PHASE, L = PA5003.XXXNLT)
(VDDH = 5V, fSW = 1MHz)
0
1
2
3
4
LOAD CURRENT (A)
5
10
8
6
VOUT = 0.8V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 3.3V
VOUT = 5.0V
4
2
0
6
35
45
55
65
75
85
95
105 115 125
AMBIENT TEMPERATURE (°C)
Analog Devices | 6
Dual-Output, 6A, 2MHz, 2.7V to 16V
Step-Down Switching Regulator
MAX16712
(VDDH = 12V, tested on MAX16712EVKIT#, TA = +25°C, unless otherwise noted.)
toc07
12
10
10
10
6
VOUT = 0.8V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 3.3V
VOUT = 5.0V
4
8
6
VOUT = 0.8V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 3.3V
VOUT = 5.0V
4
2
0
0
35
45
55
65
75
85
95
OUTPUT CURRENT (A)
12
8
35
105 115 125
45
55
65
85
95
OUTPUT CURRENT (A)
10
8
6
4
VOUT = 0.8V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 3.3V
2
0
35
45
55
65
95
4
VOUT = 0.8V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 3.3V
EN1
2V/div
45
55
65
85
95
105 115 125
2V/div
10V/div
500μs/div
toc15
toc14
VOUT1
20mV/div
500mV/div
EN1
2V/div
PGOOD1
2V/div
10V/div
LX1
VOUT2
20mV/div
10V/div
10V/div
LX2
10V/div
500μs/div
toc12
OUTPUT-VOLTAGE RIPPLE
(SINGLE-PHASE OPERATION)
(VOUT1 = 1.0V, VOUT2 = 2.0V, fSW = 1MHz)
VOUT1
LX1
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STARTUP
(SINGLE-PHASE OPERATION)
(IOUT = 6A)
LX1
75
PGOOD1
LX1
105 115 125
VOUT1
SHUTDOWN
(SINGLE-PHASE OPERATION)
(IOUT = 3A)
VOUT1
95
6
PRE-BIASED STARTUP
(SINGLE-PHASE OPERATION)
(VPREBIAS = 0.5V)
2V/div
85
PGOOD1
AMBIENT TEMPERATURE (°C)
200mV/div
75
8
AMBIENT TEMPERATURE (°C)
toc13
65
2V/div
35
105 115 125
55
EN1
0
85
45
200mV/div
2
75
35
toc11
14
10
VOUT = 0.8V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 3.3V
AMBIENT TEMPERATURE (°C)
SAFE OPERATING AREA (MAX16712)
(VDDH = 5V, fSW = 1MHz)
(NO AIRFLOW, NO HEATSINK, 2 PHASE)
12
4
105 115 125
SAFE OPERATING AREA (MAX16712)
(VDDH = 5V, fSW = 1MHz)
(200LFM AIRFLOW, NO HEATSINK, 2 PHASE)
12
6
0
75
AMBIENT TEMPERATURE (°C)
toc10
8
2
AMBIENT TEMPERATURE (°C)
14
toc09
14
12
2
OUTPUT CURRENT (A)
toc08
14
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
14
SAFE OPERATING AREA (MAX16712)
(VDDH = 5V, fSW = 1MHz)
(400LFM AIRFLOW, NO HEATSINK, 2 PHASE)
SAFE OPERATING AREA (MAX16712)
(VDDH = 12V, fSW = 1MHz)
(NO AIRFLOW, NO HEATSINK, 2 PHASE)
SAFE OPERATING AREA (MAX16712)
(VDDH = 12V, fSW = 1MHz)
(200LFM AIRFLOW, NO HEATSINK, 2 PHASE)
2μs/div
1μs/div
Analog Devices | 7
Dual-Output, 6A, 2MHz, 2.7V to 16V
Step-Down Switching Regulator
MAX16712
(VDDH = 12V, tested on MAX16712EVKIT#, TA = +25°C, unless otherwise noted.)
OUTPUT-VOLTAGE RIPPLE
(DCM OPERATION)
(VOUT = 1.8V, IOUT = 100mA)
LOAD-TRANSIENT RESPONSE
(SINGLE-PHASE OPERATION)
(VOUT = 1.0V, 1A TO 6A, 10A/μs)
toc16
CURRENT BALANCE
(DUAL-PHASE OPERATION)
(IOUT = 0A to 8A LOAD TRANSIENT)
toc17
toc18
VOUT
VOUT1
100mV/div
VOUT1
50mV/div
20mV/div
2A/div
2A/div
5V/div
LX1
5A/div
IOUT1
ILX2
ILX1
5A/div
IOUT
toc19
100
BODE PLOT
(SINGLE-PHASE OPERATION)
(VOUT = 1.0V, IOUT = 6A, fSW1 = 1MHz)toc20
80
VOUT
50mV/div
GAIN (dB)
ILX1
ILX2
60
2A/div
2A/div
120
80
20
40
0
0
-20
-40
BANDWIDTH = 140kHz
5A/div
500mV/div
-80
IL1
5A/div
PGOOD1
2V/div
-120
GAIN MARGIN = 34dB
-80
-160
-100
-200
10
4μs/div
VOUT1
160
PHASE MARGIN = 57°
-60
IOUT
200
40
-40
POSITIVE OVERCURRENT PROTECTION
(SINGLE-PHASE OPERATION)
(VOUT = 1.2V, fSW = 1MHz, POCP = 9A)toc21
PHASE (°)
CURRENT BALANCE
(DUAL-PHASE OPERATION)
(IOUT = 8A to 0A LOAD TRANSIENT)
4μs/div
100μs/div
20μs/div
100
1000
LX1
10V/div
200μs/div
FREQUENCY (kHz)
POCP HICCUP AND AUTORETRY
(SINGLE-PHASE OPERATION)
(VOUT = 1.2V, fSW = 1MHz, POCP = 9A)toc22
VOUT1
500mV/div
IL1
5A/div
PGOOD1
2V/div
LX1
10V/div
10ms/div
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Analog Devices | 8
Dual-Output, 6A, 2MHz, 2.7V to 16V
Step-Down Switching Regulator
MAX16712
Pin Configuration
28-Bump WLP
D
C
B
A
BST2
LX2
LX1
BST1
VDDH2
LX2
LX1
VDDH1
PGND
LX2
LX1
PGND
PGND
PGND
PGND
PGND
EN2
PGOOD1
PGOOD2
VCC
PGM0
PGM2
PGM1
EN1
SNSP2
AVDD
AGND
SNSP1
1
2
3
4
5
6
7
(TOP VIEW)
Pin Descriptions
PIN
NAME
A1
BST1
Bootstrap Pin for Output 1. Connect 0.22μF ceramic capacitor from BST1 to LX1.
FUNCTION
A2
VDDH1
Regulator Input Supply for Output 1. VDDH1 and VDDH2 should be connected on PCB.
A3, A4,
B4, C4,
D3, D4
PGND
Power Ground.
A5
VCC
Internal 1.8V LDO Output. Connect a 2.2μF or greater ceramic capacitor from VCC to PGND.
A6
EN1
Output Enable for Output 1.
Output 1 Voltage Sense Feedback Pin. Connect SNSP1 to VOUT1 at the load. A resistive voltage divider
A7
SNSP1
B1, B2, B3
LX1
B5
PGOOD2
can be inserted between the output and SNSP1 to regulate the output above the 0.5V fixed reference
voltage.
Switching Node of Output 1. Connect LX1 directly to the output inductor.
Open-Drain Power-Good Output for Output 2.
B6
PGM1
Program Input. Connect this pin to AGND or AVDD or leave it unconnected.
B7
AGND
Analog Ground.
C1, C2,
C3
LX2
C5
PGOOD1
C6
PGM2
C7
AVDD
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Switching Node of Output 2. Connect LX2 directly to the output inductor.
Open-Drain Power-Good Output for Output 1.
Program Input. Connect this pin to AGND or AVDD or leave it unconnected.
1.8V Supply for Analog Circuitry. Connect a 2.2Ω to 4.7Ω resistor from AVDD to VCC. Connect a 1μF or
greater ceramic capacitor from AVDD to AGND.
Analog Devices | 9
Dual-Output, 6A, 2MHz, 2.7V to 16V
Step-Down Switching Regulator
MAX16712
D1
BST2
Bootstrap Pin for Output 2. Connect 0.22μF ceramic capacitor from BST2 to LX2.
D2
VDDH2
Regulator Input Supply for Output 2. VDDH1 and VDDH2 should be connected on PCB.
D5
EN2
D6
PGM0
Program Input. Connect this pin to ground though a programming resistor.
Output 2 Voltage Sense Feedback Pin. Connect SNSP2 to VOUT2 at the load. A resistive voltage divider
D7
SNSP2
can be inserted between the output and SNSP2 to regulate the output above the 0.5V fixed reference
voltage. Connect SNSP2 to AVDD to select dual-phase operation.
Output Enable for Output 2.
Block Diagram
EN1
CLOCK
PGM0
PGM1
PGM2
PGOOD1
EN2
DIGITAL CORE
PGOOD2
OTP BANK
LDO
TO ANALOG/
DIGITAL CORE
RADC
SNSP1
CONTROLLER
1
VCC
AVDD
MODULATOR
1
OVP
PGOOD
TO
GATE
DRIVE
FAULT
DETECT
BST
PWM
LOGIC
HS
DRIVER
VDDH1
LX1
IRECON
LS
DRIVER
ZERO
CROSS
OVP
PGOOD
FAULT
DETECT
SNSP2
CONTROLLER
2
AGND
MODULATOR
2
BST
PGND1
BST2
VDDH2
PWM
LOGIC
HS
DRIVER
BANDGAP
CORE
LX2
IRECON
BIAS
MAX16712
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BST1
ZERO
CROSS
LS
DRIVER
PGND2
Analog Devices | 10
Dual-Output, 6A, 2MHz, 2.7V to 16V
Step-Down Switching Regulator
MAX16712
Detailed Description
Dual-Output or Dual-Phase Operation
The MAX16712, by default, is configured as a dual-output step-down regulator. It supports a single-input supply from
2.7V to 16V and two independent output rails of up to 6A load. The selection of DCM operation applies to both outputs.
The device has two independent control loops for the two outputs and the loop parameters can be selected by predefined
scenarios (see Pin-Strap Programmability).
The device can also be configured as a single-output, dual-phase 12A converter by connecting the SNSP2 pin to AVDD.
When configured to dual-phase operation, only the control loop for OUTPUT1 will work and the control loop for OUTPUT2
is bypassed. EN1 and PGOOD1 are used in dual-phase operation mode to enable the device and indicate power-good
status. EN2 and PGOOD2 can be disconnected.
Control Architecture
Fixed-Frequency Peak Current Mode Control Loop
The MAX16712 control loop is based on fixed-frequency peak current-mode control architecture. A simplified control
architecture is shown in Figure 1. The loop contains an error amplifier stage, internal voltage loop compensation network,
current sense, internal slope compensation, and a PWM modulator that generates the PWM signals to drive high-side
and low-side MOSFETs. The device has a fixed 0.5V reference voltage (VREF). The difference of VREF and the sensed
output voltage is amplified by the first error amplifier. Its output voltage (VERR_) is used as the input of the voltage loop
compensation network. The output of the compensation network (VCOMP_) is fed to a PWM comparator with currentsense signal (VISENSE_) and the slope compensation (VRAMP_). The output of the PWM comparator is the input of the
PWM modulator. The turning on of the high-side MOSFET is aligned with an internal clock. It is a fixed-frequency phase
shifted clock generated by the advanced modulation scheme (AMS) block.
AMS_ENABLE
CLOCK
FIXED_CLK
AMS_CLK
VREF
VSNSP_
VERR_
VOLTAGE LOOP
COMPENSATION
NETWORK
VISENSE_
PWM
MODULATOR
VCOMP_
∑
VRAMP_
Figure 1. Simplified Control Architecture
Advanced Modulation Scheme (AMS)
The device offers an advanced modulation scheme (AMS) to provide improved transient response. AMS provides a
significant advantage over conventional fixed-frequency PWM schemes. The AMS feature allows for modulation at both
leading and trailing edges, which result a temporary increase or decrease of the switching frequency during large load
transients. Figure 2 shows the scheme to include leading-edge modulation to the traditional trailing-edge modulation when
AMS is enabled in the device. The modulation scheme allows the turn on and off with minimal delay. Since the total
inductor current increases very quickly, thus satisfying the load demand, the current drawn from output capacitors is
reduced. With AMS enabled, the system closed-loop bandwidth can be extended without phase-margin penalty. As a
result, the output capacitance can be minimized.
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Analog Devices | 11
Dual-Output, 6A, 2MHz, 2.7V to 16V
Step-Down Switching Regulator
MAX16712
FIXED_CLK
-VERR_
AMS_RAMP
AMS_CLK
PWM
Figure 2. AMS Operation
Discontinuous Current Mode (DCM) Operation
Discontinuous current mode (DCM) operation can be enabled to improve light-load efficiency. It is required that VDDH is
at least 2V higher than desired VOUT for the device to operate in DCM. The device has a DCM current-detection
comparator to monitor the inductor valley current while operating in CCM. At light load, if the inductor valley current is
below the DCM comparator threshold for 48 consecutive cycles, the device transition seamlessly to DCM. Once in DCM,
the switching frequency decreases as load decreases. The MAX16712 transitions back to CCM operation as soon as the
inductor valley current is higher than 100mA.
Active Current Balancing
When configured to dual-phase operation, the MAX16712 implements active current balancing for enhanced dynamiccurrent sharing or balancing between two phase currents. This feature maintains current balance during load transients,
even at a load-step frequency close to switching frequency or its harmonics. In the device, the active current balancing
circuit adjusts the individual phase-current control signal in order to minimize the phase-current imbalance.
Internal Linear Regulator
The MAX16712 contains an internal 1.8V linear regulator (LDO). The 1.8V LDO output voltage on VCC is derived from
VDDH1 pin. The 1.8V voltage on the VCC pin supplies the current to the MOSFET drivers of both outputs. A decoupling
capacitor of at least 2.2μF must be connected between VCC and PGND. The AVDD pin of the MAX16712 also requires
a 1.8V supply to power the device’s internal analog circuitry. A 2.2Ω to 4.7Ω resistor must be connected between AVDD
and VCC. A 1μF or greater decoupling capacitor must be used between AVDD and AGND.
Startup and Shutdown
The startup and shutdown timing is shown in Figure 3. When the AVDD pin voltage is above its rising UVLO threshold,
the device goes through an initialization procedure. The dual-output or dual-phase operation is detected. Configuration
settings on the PGM_ pins are read. Once initialization is complete, the device detects VDDH UVLO and EN_ status.
When both are above their rising thresholds, the soft-start begins and switching is enabled. The output voltage of the
enabled output starts to ramp up. The soft-start ramp time is 3ms. If there are no faults, the open-drain PGOOD_ pin is
released from being held low after the soft-start ramp is complete. The device supports smooth startup with the output
pre-biased.
During operation, if either VDDH UVLO or EN_ falls below its threshold, switching is stopped immediately. The PGOOD_
pin is driven low. The output voltage is discharged by load current.
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Analog Devices | 12
Dual-Output, 6A, 2MHz, 2.7V to 16V
Step-Down Switching Regulator
MAX16712
VDDH
VCC AND AVDD
tINIT
EN_
tSS
tEN_FALLING_DELAY
VOUT_
(PRE-BIASED)
INTERNAL
SOFT-START RAMP
tEN_RISING_DELAY
PGOOD_
LX_
tINIT = 800µs
tEN_RISING_DELAY = 200µs
tSS = 3ms
tEN_FALLING_DELAY = 2µs
Figure 3. Startup and Shutdown Timing
Fault Handling
Input Undervoltage and Overvoltage Lockout (VDDH UVLO, VDDH OVLO)
The MAX16712 internally monitors the VDDH voltage level. When the input supply voltage is below the UVLO threshold
or above the OVLO threshold, the device stops switching and drives the PGOOD_ pin low. The device restarts after 20ms
if the VDDH UVLO or OVLO status is cleared. See Startup and Shutdown for the startup sequence.
Output Overvoltage Protection (OVP)
The feedback voltage on SNSP_ is monitored for output overvoltage once the soft-start ramp is complete. If the feedback
voltage is above the OVP threshold beyond the OVP deglitch filtering delay, the device stops switching and drives the
PGOOD_ pin low. The OVP is a hiccup protection, and the device restarts after 20ms if the OVP status is cleared. When
configured to dual-output operation, the OVP of one output does not affect the operation of the other output.
Positive Overcurrent Protection (POCP)
The device’s peak current mode control architecture provides inherent current limiting and short-circuit protection. The
inductor current is continuously monitored while switching. The inductor peak current is limited on a cycle-by-cycle basis.
In each switching cycle, once the sensed inductor current exceeds the POCP threshold, the device turns off the high-side
MOSFET and turns on the low-side MOSFET to allow the inductor current to be discharged by output voltage. An updown counter is used to accumulate the number of consecutive POCP events each switching cycle. If the counter exceeds
1024, the device stops switching and drives the PGOOD_ pin low. The POCP is a hiccup protection, and the device
restarts after 20ms. When configured to dual-output operation, the POCP of one output does not affect the operation of
the other output.
The MAX16712 offers three POCP thresholds (9A, 6A, and 4.5A) for each output, which can be selected by the PGM1
and PGM2 pins (see Pin-Strap Programmability). Due to POCP deglitch delay, for a specific application use case, the
actual POCP threshold should be higher (see Output Inductor Selection).
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Analog Devices | 13
Dual-Output, 6A, 2MHz, 2.7V to 16V
Step-Down Switching Regulator
MAX16712
Negative Overcurrent Protection (NOCP)
The device also has negative overcurrent protection against inductor valley current. The NOCP threshold is -83% of the
POCP threshold. In each switching cycle, once the sensed inductor current exceeds the NOCP threshold, the device
turns off the low-side MOSFET and turns on the high-side MOSFET for a fixed 100ns time to allow the inductor current
to be charged by input voltage. Same as POCP, an up-down counter is used to accumulate the number of consecutive
NOCP events. If the counter exceeds 1024, the device stops switching and drives PGOOD_ pin low. The device restarts
after 20ms. When configured to dual-output operation, NOCP of one output does not affect the operation of the other
output.
Overtemperature Protection (OTP)
The overtemperature protection threshold is +155°C with 20°C hysteresis. If the junction temperature reaches the OTP
threshold during operation, the device stops switching and drives the PGOOD_ pin low. The device restarts if the OTP
status is cleared.
Pin-Strap Programmability
The MAX16712 has three program pins (PGM0, PGM1, and PGM2) to set some of the key configurations of the device.
The PGM values are read during startup initialization. PGM0 has 32 detection levels. A pin-strap resistor is connected
from PGM0 pin to AGND to select one of the 32 PGM0 codes. PGM0 is used to select the switching frequency and a
predefined scenario, which is defined in Table 4. PGM1 and PGM2 each have three levels. PGM1 or PGM2 can be
connected to AVDD or AGND (PGM0) or left OPEN to select the POCP level of each output. When the device is configured
to dual-phase operation, the POCP level of each phase is only selected by PGM1. PGM2 code is ignored in the IC.
Table 1. PGM0 Switching Frequency and Scenario Selections
PGM0
CODES
R
(Ω)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
95.3
200
309
422
536
649
768
909
1050
1210
1400
1620
1870
2150
2490
2870
3740
8060
12400
16900
21500
26100
30900
36500
42200
48700
56200
64900
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SWITCHING
FREQUENCY
(kHz)
500
600
750
1000
1200
1500
SCENARIO
#
A
B
C
D
E
A
B
C
D
E
A
B
C
D
E
A
B
C
D
E
A
B
C
D
E
A
B
C
Analog Devices | 14
Dual-Output, 6A, 2MHz, 2.7V to 16V
Step-Down Switching Regulator
28
29
30
31
75000
86600
100000
115000
MAX16712
D
E
A
B
2000
Table 2. PGM1 POCP Selection for Output 1
PGM1
CODES
0
1
2
PGM1
CONNECTION
AVDD
AGND or PGM0
OPEN
POCP1
(A)
9
6
4.5
Table 3. PGM2 POCP Selection for Output 2
PGM2
CODES
0
1
2
PGM2
CONNECTION
AVDD
AGND or PGM0
OPEN
POCP2
(A)
9
6
4.5
The MAX16712 has five predefined scenarios for each selectable switching frequency, where the control loop is optimized
to cover the most commonly used applications, which are summarized in Table 4. See Voltage Loop Gain for information
about how to select the voltage loop gain resistance (RVGA) for optimized control loop performance. The scenario is
selected by a pin-strap resistor connected from the PGM0 pin to AGND.
Table 4. Predefined Scenarios
SCENARIO
#
A
B
C
D
E
RVGA
(kΩ)
74.5
52.2
37.3
52.2
37.3
DCM
OPTION
Disabled
Disabled
Disabled
Enabled
Enabled
Reference Design Procedure
Output Voltage Sensing
The MAX16712 has an internal 0.5V reference voltage. When the desired output voltage is higher than 0.5V, it is required
to use resistor-dividers RFB1 and RFB2 to sense the output voltage (see Typical Application Circuits). It is recommended
that the value of RFB2 does not exceed 5kΩ. The resistor-divider ratio is given by the following equation:
VOUT = VREF × (1+
RFB1
)
RFB2
where:
VOUT = Output voltage
VREF = 0.5V fixed reference voltage
RFB1 = Top resistor-divider
RFB2 = Bottom resistor-divider
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Analog Devices | 15
Dual-Output, 6A, 2MHz, 2.7V to 16V
Step-Down Switching Regulator
MAX16712
Switching Frequency Selection
The MAX16712 offers a wide range of selectable switching frequencies from 500kHz to 2MHz. Switching frequency
selection can be optimized for different applications. Higher switching frequencies are recommended for applications
prioritizing solution size, so that the value and size of output LC filter can be reduced. Lower switching frequencies are
recommended for applications prioritizing efficiency and thermal dissipation, due to reduced switching losses. The
frequency must be selected so that the minimum controllable on-time and minimum controllable off-time are not violated.
The maximum recommended switching frequency is calculated by the following equation:
VOUT
VDDHMIN - VOUT
fSWMAX = MIN {
,
}
tONMIN × VDDHMAX tOFFMIN × VDDHMIN
where:
fSWMAX = Maximum selectable switching frequency
VDDHMAX = Maximum input voltage
VDDHMIN = Minimum input voltage
tONMIN = Minimum controllable on-time
tOFFMIN = Minimum controllable off-time
The MAX16712 internally has a slope compensation applied to the current loop during on-time to guarantee stability and
improve noise immunity. To avoid the slope compensation saturating the current loop, it is required that the maximum ontime be limited by:
I
I
1.6Ω
5pF [800mV- ( OUTMAX + RIPPLE ) ×
]
N
2
25
tONMAX =
3.7uA
where:
tONMAX = Maximum on-time of the high-side MOSFET
IOUTMAX = Maximum load current
N = Number of phases
IRIPPLE = Inductor current ripple peak-to-peak value
The minimum recommended switching frequency is calculated by the following equation:
fSWMIN =
VOUT
tONMAX ×VDDHMIN
where:
fSWMIN = Minimum selectable switching frequency
Due to system noise injection, even at steady-state operation, typically the LX rising and falling edges would have some
random jittering noise. The selection of the switching frequency (fSW) should take into consideration the jittering, be higher
than fSWMIN, and be lower than fSWMAX. To improve the LX jittering, it is recommended to use smaller inductor values
and lower voltage loop gain to minimize the noise sensitivity.
Output Inductor Selection
The output inductor has an important influence on the overall size, cost, and efficiency of the voltage regulator. Since the
inductor is typically one of the larger components in the system, a minimum inductor value is particularly important in
space-constrained applications. Smaller inductor values also permit faster transient response, reducing the amount of
output capacitance needed to maintain transient tolerance.
To improve current loop noise immunity, typically the output inductor is selected so that the inductor current ripple is at
least 1A. The inductor value is calculated by the following equation:
L=
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VOUT (VDDH - VOUT )
VDDH × IRIPPLE × fSW
Analog Devices | 16
Dual-Output, 6A, 2MHz, 2.7V to 16V
Step-Down Switching Regulator
MAX16712
where:
VDDH = Input voltage
The inductor should also be selected so that maximum load current delivery can be guaranteed by the selected POCP
threshold. The MAX16712 offers three POCP thresholds (9A, 6A, and 4.5A) for each output, which can be selected by
the PGM1 and PGM2 pins (see Pin-Strap Programmability). Due to deglitch delay from the POCP comparator tripping to
the high-side MOSFET turning off, for a specific application use case, the adjusted POCP threshold should take into
consideration the inductor value, input voltage, and output voltage, which can be calculated by the following equation:
POCPADJUST = POCP +
(VDDH - VOUT ) × tPOCP
L
where：
POCPADJUST = Adjusted POCP threshold
POCP = POCP level specified in the EC table
tPOCP = POCP deglitch delay (36ns, typ)
It needs to be verified that the peak inductor current in normal operation does not exceed the minimum adjusted POCP
threshold:
IOUTMAX IRIPPLE
+
< POCPADJUST(MIN)
N
2
where:
POCPADJUST(MIN) = Minimum adjusted POCP threshold, calculated with the minimum value of the POCP threshold
Table 5 shows some suitable inductor part numbers which are verified on the MAX16712 evaluation kit to offer optimal
performance.
Table 5. Recommended Inductors
COMPANY
VALUE (μH)
TDK
TDK
Pulse
Pulse
Pulse
Pulse
0.22
0.33
0.47
0.56
1.0
2.2
ISAT
(A)
9
8.4
26
22.2
16.5
10
RDC
(mΩ)
8
10
3.75
4.05
6.9
13.2
FOOTPRINT
(mm)
2.5 × 2.0
3.2 × 2.5
5.5 × 5.3
5.5 × 5.3
5.5 × 5.3
5.5 × 5.3
HEIGHT
(mm)
1.2
1.2
2.9
2.9
2.9
2.9
PART NUMBER
TFM252012ALMAR22MTAA
TFM322512ALMAR33MTAA
PA5003.471NLT
PA5003.561NLT
PA5003.102NLT
PA5003.222NLT
Output Capacitor Selection
One major factor in determining the total required output capacitance is the output-voltage ripple. To meet the outputvoltage ripple requirement, the minimum output capacitance should satisfy the following equation:
COUT ≥
IRIPPLE
8 × N × fSW × (VOUTRIPPLE - ESR × IRIPPLE )
where:
VOUTRIPPLE = Maximum allowed output-voltage ripple
ESR = ESR of output capacitors
The other important factors in determining the total required output capacitance are the maximum allowable output-voltage
overshoot and undershoot during load transients. For a given loading or unloading current step, the minimum required
output capacitance should also satisfy the following equation:
2
2
ΔI I
ΔI I
( + RIPPLE ) × L × N
( + RIPPLE ) × L × N
N
N
2
2
COUT ≥ MAX
,
2 × ΔVOUT × (VDDH - VOUT ) 2 × ΔVOUT × VOUT
{
}
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Analog Devices | 17
Dual-Output, 6A, 2MHz, 2.7V to 16V
Step-Down Switching Regulator
MAX16712
where:
COUT = Output capacitance
△I = Loading or unloading current step
△VOUT = Maximum allowed output-voltage undershoot or overshoot
Input Capacitor Selection
The selection of input capacitance is determined by the requirement of input-voltage ripple. The VDDH1 and VDDH2 pins
of the MAX16712 should be connected on the PCB. When configured to dual-output operation, the input capacitance is
shared between the two outputs. The minimum required input capacitance is estimated by the following equation:
CIN ≥ MAX {
IOUT1(MAX) × VOUT1 IOUT2(MAX) × VOUT2
,
}
fSW1 × VDDH × VINPP fSW2 × VDDH × VINPP
where:
IOUT_(MAX) = Maximum output current of OUTPUT_
VOUT_ = Output voltage of OUTPUT_
fSW_ = Switching frequency of OUTPUT_
VINPP = Peak-to-peak input voltage ripple
When configured to dual-phase operation, the minimum required input capacitance is estimated by the following equation:
CIN ≥
IOUT(MAX) × VOUT
2 × fSW × VDDH × VINPP
Besides the minimum required input capacitance, it is required to also place 0.1μF and 1μF high-frequency decoupling
capacitors next to each VDDH_ pin to suppress the high-frequency switching noises.
Voltage Loop Gain
For stability purposes, it is recommended that the voltage loop bandwidth (BW) be lower than 1/5 of the switching
frequency. Consider the case of using MLCC output capacitors that have nearly ideal impedance characteristics in the
frequency range of interest with negligible ESR and ESL. The voltage loop BW can be estimated with the following
equation:
R
RFB2
× VGA
RFB2 + RFB1 10kΩ
2π × 20mΩ × COUT
N×
BW =
where:
RVGA = The voltage loop gain resistance, which is set by the scenario selected (Table 4).
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Analog Devices | 18
Dual-Output, 6A, 2MHz, 2.7V to 16V
Step-Down Switching Regulator
MAX16712
Typical Reference Designs
See the Typical Application Circuits for examples of reference schematics. Reference design examples for some common
output voltages are shown in Table 6.
Table 6. Reference Design Examples
VOUT
(V)
0.8
0.9
1.0
1.2
1.8
3.3
5.0
IOUT (A)
(PER
PHASE)
6
6
6
6
6
5
4
fSW
(kHz)
RFB1
(kΩ)
RFB2
(kΩ)
PGM0
(kΩ)
750
1000
1000
1000
1500
2000
2000
1.82
2.40
3.01
4.22
7.87
16.9
22.6
3.01
3.01
3.01
3.01
3.01
3.01
2.49
1.62
3.74
3.74
3.74
56.2
115
115
PGM1
OR
PGM2
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AGND
L
(μH)
CIN (PER EACH
VDDH_ PIN)
COUT
0.47
0.47
0.47
0.56
0.56
1.0
2.2
10μF +1μF +0.1μF
10μF +1μF +0.1μF
10μF +1μF +0.1μF
10μF +1μF +0.1μF
10μF +1μF +0.1μF
10μF +1μF +0.1μF
10μF +1μF +0.1μF
3 × 47μF
3 × 47μF
3 × 47μF
3 × 47μF
2 × 47μF
2 × 47μF
1 × 47μF
PCB Layout Guidelines
• For electrical and thermal reasons, the second layer from the top and bottom of the PCB should be reserved for power
ground (PGND) planes.
•
The input decoupling capacitor should be located the closest to the IC and no more than 40mils from the VDDH_ pins.
•
The VCC decoupling capacitors should be connected to PGND and placed as close as possible to VCC pin.
• An analog ground copper polygon or island should be used to connect all analog control-signal grounds. This “quiet”
analog ground copper polygon or island should be connected to the PGND through a single connection close to AGND
pin. The analog ground can be used as a shield and ground reference for the control signals (PGM_ and SNSP_).
•
The AVDD decoupling capacitors should be connected to AGND and placed as close as possible to AVDD pin.
• The boost capacitors should be placed as close as possible to LX_ and BST_ pins, on the same side of the PCB with
the IC.
• The feedback resistor-divider and optional external compensation network should be placed close to the IC to minimize
the noise injection.
• The voltage-sense line should be routed directly from an output capacitor, shielded by ground plane, and kept away
from the switching node and inductor.
•
Multiple vias are recommended for all paths that carry high currents and for heat dissipation.
• The input capacitors and output inductors should be placed near the IC and the traces to the components should be
kept as short and wide as possible to minimize parasitic inductance and resistance.
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Analog Devices | 19
Dual-Output, 6A, 2MHz, 2.7V to 16V
Step-Down Switching Regulator
MAX16712
Typical Application Circuits
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Analog Devices | 20
Dual-Output, 6A, 2MHz, 2.7V to 16V
Step-Down Switching Regulator
www.analog.com
MAX16712
Analog Devices | 21
Dual-Output, 6A, 2MHz, 2.7V to 16V
Step-Down Switching Regulator
MAX16712
Ordering Information
PART NUMBER
MAX16712AWI+
MAX16712AWI+T
+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
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TEMP RANGE
-40°C to +125°C
-40°C to +125°C
PIN-PACKAGE
28 WLP
28 WLP
Analog Devices | 22
Dual-Output, 6A, 2MHz, 2.7V to 16V
Step-Down Switching Regulator
MAX16712
Revision History
REVISION
NUMBER
0
REVISION
DATE
2/21
1
2/22
DESCRIPTION
Initial release
Updated Benefits and Features, Detailed Description, and Reference Design Procedure
PAGES
CHANGED
—
1, 11, 13,
15–17
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is
assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that
may result from its use. Specifications subject to change without notice. No license is granted by implication or
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property of their respective owners.
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