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30A, 1.5MHz, 2.7V to 16V Integrated StepDown Switching Regulator
General Description
The MAX16731 is a fully integrated, highly efficient,
step-down DC-DC switching regulator. The regulator is
able to operate from 2.7V to 16V input supplies, and the
output can be adjusted from 0.5V to 5.8V, delivering up
to 30A of load current.
The switching frequency of the device can be configured
from 500kHz to 1.5MHz and can optimize the design in
terms of size and performance.
The MAX16731 utilizes fixed frequency, current-mode
control with internal compensation. The IC features
advanced modulation scheme (AMS) and selectable
discontinuous current mode (DCM) operation to provide
improved performance. Operation settings and
configurable features can be selected by three
programming pins PGM0, PGM1, and PGM2.
The MAX16731 has an internal 1.8V linear regulator
(LDO) output to power the gate drives (VCC) and
internal circuitry (AVDD).
The IC has multiple protections, including positive and
negative overcurrent protection, output overvoltage
protection, and overtemperature protection to ensure
robust design.
The device is available in a compact 2.52mm x 4.89mm
WLP package. It supports -40°C to +125°C junction
temperature operation.
Applications
• Communications Equipment
• Networking Equipment
• Servers and Storage Equipment
• Point-of-Load Voltage Regulators
• Memory VDDQ
Ordering Information appears at end of data sheet.
MAX16731
Benefits and Features
•
High Power Density with Low Component Count
• Compact 2.52mm x 4.89mm, 45-Bump, WLP
Package
• Internal Compensation
• Single Supply Operation with Integrated LDO for
Bias Generation
•
Wide Operating Range
• 2.7V to 16V Input Voltage Range
• 0.5V to 5.8V Output Voltage Range
• 500kHz to 1.5MHz Configurable Switching
Frequency
• -40°C to +125°C Junction Temperature Range
• Three Programming Pins to Select Different
Configurations
•
Optimized Performance and Efficiency
• 91.2% Peak Efficiency with VDDH = 12V, VOUT =
1.2V, and fSW = 500kHz
• AMS to Improve Load Transient
• Selectable DCM to Improve Light Load Efficiency
• Differential Remote Sense
DESCRIPTION
CURRENT
RATING*
(A)
30
INPUT
VOLTAGE
(V)
2.7 to 16
OUTPUT
VOLTAGE
(V)
0.5 to 5.8
Electrical Rating
Thermal Rating
TA = 55°C,
29
12
1.8
200LFM air flow
Thermal Rating
TA = 85°C, no air
21
12
0.8
flow
*Maximum TJ = 125°C. For specific operating conditions, see
the Safe Operating Area (SOA) curves in the Typical
Operating Characteristics section.
19-101248; Rev 0; 12/21
© 2021 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.
O ne An al o g W ay , W i l mi n g ton , M A 01 88 7 U .S. A. | Tel : 7 81 .3 29. 47 0 0 | © 20 21 An al og D ev i c es , Inc . Al l ri gh ts r es e rv e d.
MAX16731
30A, 1.5MHz, 2.7V to 16V Integrated Step-Down
Switching Regulator
Simplified Application Circuit
2.7V to 16V INPUT
CIN
MAX16731
VDDH
VCC
AVDD
PGOOD
EN
CONNECT TO AGND
OR AVDD OR OPEN
BST
L
LX
SNSP
RFB1
0.5V to 5.8V, 30A
COUT
RFB2
SNSN
PGM2
PGND
PGM1
PGM0
AGND
RPGM0
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Analog Devices | 2
MAX16731
30A, 1.5MHz, 2.7V to 16V Integrated Step-Down
Switching Regulator
Absolute Maximum Ratings
VDDH to PGND (Note 1) ......................................... -0.3V to +19V
VCC to PGND ........................................................ -0.3V to +2.5V
LX to PGND (DC) ................................................... -0.3V to +19V
AVDD to AGND..................................................... -0.3V to +2.5V
LX to PGND (AC) (Note 2) ...................................... -10V to +23V
EN, PGOOD to AGND ............................................. -0.3V to +4V
VDDH to LX (DC) (Note 1) ....................................... -0.3V to +19V
SNSP to AGND ........................................... -0.3V to AVDD+0.3V
VDDH to LX (AC) (Note 2) ........................................ -10V to +23V
SNSN to AGND..................................................... -0.3V to +0.3V
BST to PGND (DC) ............................................. -0.3V to +21.5V
PGM0, PGM1, PGM2 to AGND .................. -0.3V to AVDD+0.3V
BST to PGND (AC) (Note 2) .................................. -7V to +25.5V
Peak LX Current ..................................................... -54A to +56A
BST to LX .............................................................. -0.3V to +2.5V
Junction Temperature (TJ) (Note 3) .................................+150°C
PGND to AGND .................................................... -0.3V to +0.3V
Storage Temperature Range ............................. -65°C to +150°C
Peak Reflow Temperature Lead-Free ..............................+260°C
Note 1: Input HF capacitors placed not more than 40 mils away from the VDDH pin to keep inductive voltage spikes within
Absolute Maximum limits.
Note 2: AC is limited to 25ns.
Note 3: Recommended operating junction temperature from -40°C to +125°C. The device guarantees 90k hours of continuous
operation with 30A output current at +85°C junction temperature, or 40k hours of continuous operation with 24A output
current at +105°C junction temperature, for a typical application with 12V input, 1.2V output.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any
other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
Package Information
Package Code
Outline Number
Land Pattern Number
Thermal Resistance
Junction-to-Ambient Thermal Resistance (θJA) JEDEC
Junction-to-Ambient Thermal Resistance (θJA) on
MAX16731EVKIT# (no heat sink, no airflow)
W452A4Z+1
21-100425
Refer to Application Note 1891
35.73°C/W
14.5°C/W
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character,
but the drawing pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
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Analog Devices | 3
MAX16731
30A, 1.5MHz, 2.7V to 16V Integrated Step-Down
Switching Regulator
Electrical Characteristics
(See Typical Application Circuit. VDDH = 12V, TA = TJ = -40°C to +125°C, unless otherwise noted. Specifications are production tested
at TA =+32°C; limits within the operating temperature range are guaranteed by design and characterization.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input Supply
Input Voltage Range
VDDH
Input Supply Current
IVDDH
Internal LDO Regulated
Output
AVDD Undervoltage
Lockout
AVDD Undervoltage
Lockout Hysteresis
VDDH Undervoltage
Lockout
VDDH Undervoltage
Lockout Hysteresis
VDDH Overvoltage
Lockout
VDDH Overvoltage
Lockout Hysteresis
2.7
EN = AGND
VCC
AVDD
16
0.25
1.71
Rising
1.65
1.67
mA
1.95
V
1.70
V
55
Rising
2.4
2.5
mV
2.6
100
Rising
17.3
17.8
V
V
mV
18.3
500
V
mV
Output Voltage Range and Accuracy
Internal Reference
Voltage
Positive Voltage Sense
Leakage Current
Negative Voltage Sense
Input Range
Negative Voltage Sense
Leakage Current
TA = TJ = 0°C to +85°C
ISNSP
TA = TJ = +25°C
VSNSN
0.495
0.500
0.505
0.497
0.500
0.503
V
-1
1
μA
-100
+100
mV
550
μA
ISNSN
Switching Frequency
500
600
Switching Frequency
750
FSW
kHz
1000
1200
1500
Switching Frequency
Accuracy
-10
Minimum Controllable
On-Time
+10
Inductor Valley Current ≤ 0A (Note 4)
35.0
51.3
Inductor Valley Current > 0A (Note 4)
32.8
45.3
Minimum Controllable
Off-Time
%
ns
100
ns
540
μs
Enable and Startup
Initialization Time
tINIT
Rising
EN Threshold
EN Filtering Delay
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0.9
Falling
tEN_RISING_DE
LAY
Rising
0.6
200
V
μs
Analog Devices | 4
MAX16731
30A, 1.5MHz, 2.7V to 16V Integrated Step-Down
Switching Regulator
(See Typical Application Circuit. VDDH = 12V, TA = TJ = -40°C to +125°C, unless otherwise noted. Specifications are production tested
at TA =+32°C; limits within the operating temperature range are guaranteed by design and characterization.)
PARAMETER
SYMBOL
tEN_FALLING_D
ELAY
Soft-Start Time
CONDITIONS
MIN
Falling
TYP
MAX
UNITS
2
tSS
3
ms
Power Good and Fault Protections
PGOOD Output Low
IPGOOD_ = 4mA
Output Undervoltage
(UV) Threshold
Falling
-13
-10
-10
10
13
16
Inductor Peak Current, POCP = 38A
34.6
38.0
41.4
Inductor Peak Current, POCP = 33A
29.9
33.0
36.1
Inductor Peak Current, POCP = 28A
25.1
28.0
30.9
51
Fast Positive
Overcurrent Protection
(FPOCP) Threshold
Negative Overcurrent
Protection (NOCP)
Threshold to POCP
Threshold Ratio
44
48
-20
VBST
Rising
1.48
BST UVLO Threshold
Hysteresis
Overtemperature
Protection (OTP) Rising
Threshold
1.56
%
A
ns
52
-84
NOCP Accuracy
%
μs
2
tPOCP
V
μs
4
Positive Overcurrent
Protection (POCP)
Threshold
BST UVLO Threshold
-16
Rising
Output UV Deglitch
Delay
Output Overvoltage
Protection (OVP)
Threshold
Output OVP Deglitch
Delay
POCP Deglitch Delay
0.4
A
%
+20
%
1.64
V
52
mV
155
°C
OTP Accuracy
6
%
OTP Hysteresis
20
°C
Hiccup Protection Time
20
ms
DCM Operation Mode
DCM Comparator
Threshold to Enter DCM
DCM Comparator
Threshold to Exit DCM
POCP = 38A, Inductor Valley Current
-1.73
POCP = 33A, Inductor Valley Current
-1.57
POCP = 28A, Inductor Valley Current
-1.26
Inductor Valley Current
A
0.6
A
Programming Pins
PGM0 Pin Resistor
Range
PGM0 Resistor
Accuracy
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0.095
115
kΩ
-1
+1
%
Analog Devices | 5
MAX16731
30A, 1.5MHz, 2.7V to 16V Integrated Step-Down
Switching Regulator
(See Typical Application Circuit. VDDH = 12V, TA = TJ = -40°C to +125°C, unless otherwise noted. Specifications are production tested
at TA =+32°C; limits within the operating temperature range are guaranteed by design and characterization.)
PARAMETER
SYMBOL
CONDITIONS
PGM_ Pin Connected to AVDD
PGM1 / PGM2 3-Level
Detection Thresholds
PGM_ Pin OPEN
MIN
TYP
UNITS
AVDD –
0.2
0.68
V
0.24 ×
AVDD
PGM_ Pin Connected to AGND or PGM0
PGM1 / PGM2 Input
Current
MAX
PGM_ Pin Connected to AVDD
250
PGM_ Pin Connected to AGND or PGM0
-315
μA
Note 4: Guaranteed by design.
Typical Operating Characteristics
(Typical Application Circuit, tested on MAX16731EVKIT#, VDDH = 12V, FSW = 500kHz, TA = +25°C, Inductor = FP1008R5-R220-R or
744309047 for VOUT > 2.5V, unless otherwise noted.)
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Analog Devices | 6
MAX16731
30A, 1.5MHz, 2.7V to 16V Integrated Step-Down
Switching Regulator
(Typical Application Circuit, tested on MAX16731EVKIT#, VDDH = 12V, FSW = 500kHz, TA = +25°C, Inductor = FP1008R5-R220-R or
744309047 for VOUT > 2.5V, unless otherwise noted.)
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Analog Devices | 7
MAX16731
30A, 1.5MHz, 2.7V to 16V Integrated Step-Down
Switching Regulator
(Typical Application Circuit, tested on MAX16731EVKIT#, VDDH = 12V, FSW = 500kHz, TA = +25°C, Inductor = FP1008R5-R220-R or
744309047 for VOUT > 2.5V, unless otherwise noted.)
Pin Configurations
A
B
C
D
E
PGND
PGND
PGND
PGND
PGND
LX
LX
LX
LX
LX
PGND
PGND
PGND
PGND
PGND
LX
LX
LX
LX
LX
PGND
PGND
PGND
PGND
PGND
LX
LX
LX
LX
LX
BST
VDDH
VDDH
VDDH
VDDH
VCC
PGM1
PGM2
SNSN
EN
PGM0
AVDD
AGND
SNSP
PGOOD
9
8
7
6
5
4
3
2
1
(TOP VIEW)
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Analog Devices | 8
MAX16731
30A, 1.5MHz, 2.7V to 16V Integrated Step-Down
Switching Regulator
Pin Descriptions
PIN
NAME
FUNCTION
A1
PGM0
Program Input. Connect this pin to ground though a programming resistor.
B1
AVDD
1.8V Supply for Analog Circuitry. Connect a 2.2Ω to 4.7Ω resistor from AVDD to VCC. Connect a
1μF or greater ceramic capacitor from AVDD to AGND.
C1
AGND
Analog Ground.
D1
SNSP
Output Voltage Remote Sense Positive Input Pin. Connect SNSP to output voltage at the load.
A resistive voltage divider can be inserted between the output and SNSP to regulate the output
above the reference voltage.
E1
PGOOD
Open-Drain Power Good Output.
A2
VCC
Internal 1.8V LDO Output. Connect a 4.7μF or greater ceramic capacitor from VCC to PGND.
B2
PGM1
Program Input. Connect this pin to AGND or AVDD or leave it unconnected.
C2
PGM2
Program Input. Connect this pin to AGND or AVDD or leave it unconnected.
D2
SNSN
Output Voltage Remote Sense Negative Input.
E2
EN
Output Enable.
A3
BST
Bootstrap Pin. Connect a 0.47μF ceramic capacitor from BST to LX.
B3, C3,
D3, E3
A4-E4, A6E6, A8-E8
A5-E5, A7E7, A9-E9
VDDH
Regulator Input Supply.
LX
Switching Node. Connect LX directly to the output inductor.
PGND
Power Ground.
Block Diagram
EN
Clock
PGM0
PGM1
PGM2
PGOOD
Digital Core
AVDD
OTP Bank
LDO
To Analog /
Digital Core
To Gate
Drive
RADC
SNSP
Controller
SNSN
OVP
PGOOD
FAULT
Detect
BST
PWM
Logic
HS
Driver
LX
Bangap
Core
BIAS
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BST
VDDH
Modulator
IRECON
AGND
VCC
MAX16731
Zero
Cross
LS
Driver
PGND
Analog Devices | 9
MAX16731
30A, 1.5MHz, 2.7V to 16V Integrated Step-Down
Switching Regulator
Detailed Description
Control Architecture
Fixed-Frequency, Peak-Current-Mode Control Loop
The MAX16731 control loop is based on the fixed-frequency, peak-current-mode control architecture. A simplified control
architecture is shown in Figure 1. The loop contains an error amplifier stage, internal voltage loop compensation network,
current sense, internal slope compensation, and a PWM modulator that generates the PWM signals to drive high-side and
low-side MOSFETs. The device has a fixed 0.5V reference voltage (VREF). The difference of VREF and the sensed output
voltage is amplified by the first error amplifier. Its output voltage (VERR) is used as the input of the voltage loop compensation
network. The output of the compensation network (VCOMP) is fed to a PWM comparator with the current-sense signal
(VISENSE) and the slope compensation (VRAMP). The output of the PWM comparator is the input of the PWM modulator.
The turning on of the high-side MOSFET is aligned with an internal clock. It is a fixed-frequency phase-shifted clock generated
by the AMS block (see the Advanced Modulation Scheme (AMS)).
AMS_ENABLE
CLOCK
FIXED_CLK
AMS_CLK
VREF
VSNSP– VSNSN
VERR_
VOLTAGE LOOP
COMPENSATION
NETWORK
VISENSE
PWM
MODULATOR
VCOMP
∑
VRAMP
Figure 1. Simplified Control Architecture
Advanced Modulation Scheme (AMS)
The device offers the AMS to provide improved transient response. The AMS provides a significant advantage over
conventional fixed-frequency PWM schemes. The AMS feature allows for modulation at both the leading and trailing edges,
which result in a temporary increase or decrease of the switching frequency during large load transients. Figure 2 shows the
scheme to include the leading-edge modulation to the traditional trailing-edge modulation when AMS is enabled in the device.
The modulation scheme allows the turn on and off with minimal delay. Since the total inductor current increases very quickly,
satisfying the load demand, the current drawn from the output capacitors is reduced. With AMS enabled, the system closedloop bandwidth can be extended without phase-margin penalty. As a result, the output capacitance can be minimized.
FIXED_CLK
-VERR_
AMS_RAMP
AMS_CLK
PWM
Figure 2. AMS Operation
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Analog Devices | 10
MAX16731
30A, 1.5MHz, 2.7V to 16V Integrated Step-Down
Switching Regulator
Discontinuous Current Mode (DCM) Operation
The discontinuous current mode (DCM) operation can be enabled to improve the light load efficiency. The device has a DCM
current detection comparator to monitor the inductor valley current while operating in the continuous current mode (CCM).
At light load, if the inductor valley current is below the DCM comparator threshold for 48 consecutive cycles, the device
transitions seamlessly to the DCM. Once in the DCM, the switching frequency decreases as the load decreases. The
MAX16731 transitions back to the CCM operation as soon as the inductor valley current is higher than 0.6A.
Internal Linear Regulator
The MAX16731 contains an internal 1.8V linear regulator (LDO). The 1.8V LDO output voltage on VCC is derived from VDDH
pin. It provides the supply voltage for the MOSFET gate drives. A decoupling capacitor of at least 4.7μF must be connected
between the VCC and PGND. The AVDD pin of the MAX16731 also requires a 1.8V supply to power the device’s internal
analog circuitry. A 2.2Ω to 4.7Ω resistor must be connected between the AVDD and VCC. A 1μF or greater decoupling
capacitor must be used between the AVDD and AGND.
Startup and Shutdown
The startup and shutdown timings are shown in Figure 3. When the AVDD pin voltage is above its rising UVLO threshold,
the device goes through an initialization procedure. The configuration settings on the PGM_ pins are read. Once initialization
is complete, the device detects VDDH UVLO and EN status. When both are above their rising thresholds, the soft-start begins
and switching is enabled. The output voltage of the enabled output starts to ramp up. The soft-start ramp time is 3ms. If there
are no faults, the open drain PGOOD pin is released from being held low after the soft-start ramp is complete. The device
supports smooth startup with output pre-biased.
During operation, if either the VDDH UVLO or EN falls below their thresholds, switching is stopped immediately. The output
voltage is discharged by the load current.
VDDH
VCC AND AVDD
tINIT
EN_
tSS
tEN_FALLING_DELAY
VOUT_
(PRE-BIASED)
INTERNAL
SOFT-START RAMP
tEN_RISING_DELAY
PGOOD_
LX_
tINIT = 540µs
tEN_RISING_DELAY = 200µs
tSS = 3ms
tEN_FALLING_DELAY = 2µs
Figure 3. Startup and Shutdown Timing
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Analog Devices | 11
MAX16731
30A, 1.5MHz, 2.7V to 16V Integrated Step-Down
Switching Regulator
Fault Handling
Input Undervoltage and Overvoltage Lockout (VDDH UVLO, VDDH OVLO)
The MAX16731 internally monitors the VDDH voltage level. When the input supply voltage is below the UVLO threshold or
above the OVLO threshold, the device stops switching and drives the PGOOD pin low. The device restarts after 20ms if the
UVLO or OVLO status is cleared. See the Startup and Shutdown for startup sequence.
Output Overvoltage Protection (OVP)
The feedback voltage of VSNSP – VSNSN is monitored for output overvoltage once the soft-start ramp is complete. If the
feedback voltage is above the OVP threshold beyond the deglitch filtering delay, the device stops switching and drives
PGOOD pin low. The device restarts after 20ms if the OVP status is cleared.
Positive Overcurrent Protection (POCP)
The device’s peak current mode control architecture provides inherent current limiting and short circuit protection. The
inductor current is continuously monitored while switching. The inductor peak current limits on a cycle-by-cycle basis. In each
switching cycle, once the sensed inductor current exceeds the POCP threshold, the device turns off the high-side MOSFET
and turns on the low-side MOSFET to allow the inductor current to be discharged by output voltage. An up-down counter is
used to accumulate the number of consecutive POCP events each switching cycle. If the counter exceeds 512, the device
stops switching and drives the PGOOD pin low. The POCP is a hiccup protection, and the device restarts after 20ms.
The MAX16731 offers three POCP thresholds (38A, 33A, and 28A), which can be selected by the PGM1 and PGM2 pins
(see the Pin-Strap Programmability). Due to the POCP deglitch delay, for a specific application use case, the actual POCP
threshold should be higher (see the Selecting the Output Inductor).
Negative Overcurrent Protection (NOCP)
The device also has negative overcurrent protection against inductor valley current. The NOCP threshold is -84% of the
POCP threshold. In each switching cycle, once the sensed inductor current exceeds the NOCP threshold, the device turns
off the low-side MOSFET and turns on the high-side MOSFET for a fixed 180ns time to allow the inductor current to be
charged by input voltage. Same as POCP, an up-down counter is used to accumulate the number of consecutive NOCP
events. If the counter exceeds 1024, the device stops switching and drives the PGOOD pin low. The NOCP is a hiccup
protection, and the device restarts after 20ms.
Overtemperature Protection (OTP)
The overtemperature protection threshold is 155°C with 20°C hysteresis. If the junction temperature reaches OTP threshold
during operation, the device stops switching and drives the PGOOD pin low. The device restarts after 20ms if the OTP status
is cleared.
Pin-Strap Programmability
The MAX16731 has three program pins (PGM0, PGM1, and PGM2) to set some of the key configurations of the device. The
PGM_ values are read during startup initialization. The PGM0 has 32 detection levels. A pin-strap resistor is connected from
PGM0 pin to AGND to select one of the 32 PGM0 codes. See Table 1 for the PGM0 switching frequencies and scenario
selections. The PGM0 is used to select the switching frequency and a pre-defined scenario, which is defined in Table 3. The
PGM1 and PGM2 each has three levels. The PGM1 or PGM2 can be connected to AVDD or AGND (PGM0) or left OPEN to
select the POCP level and DCM operation mode of the device as shown in Table 2.
Table 1. PGM0 Switching Frequency and Scenario Selections
PGM0
CODES
RPGM0
(Ω)
0
1
2
3
4
5
6
7
95.3
200
309
422
536
649
768
909
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SWITCHING
FREQUENCY
(kHz)
500
600
SCENARIO #
A
B
C
D
E
F
A
B
Analog Devices | 12
MAX16731
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
30A, 1.5MHz, 2.7V to 16V Integrated Step-Down
Switching Regulator
1050
1210
1400
1620
1870
2150
2490
2870
3740
8060
12400
16900
21500
26100
30900
36500
42200
48700
56200
64900
75000
86600
100000
115000
C
D
E
F
A
B
C
D
E
F
A
B
C
D
E
F
A
B
C
D
E
F
A
B
750
1000
1200
1500
Table 2. PGM1 and PGM2 Settings
PGM1&2
CODES
0
1
2
3
4
5
6
7
8
PGM1
CONNECTION
OPEN
AGND or PGM0
AVDD
PGM2
CONNECTION
OPEN
AGND
AVDD
OPEN
AGND
AVDD
OPEN
AGND
AVDD
DCM
Disable
Enable
Disable
Enable
Disable
Enable
Disable
Enable
Disable
POCP (A)
38
28
38
28
33
The MAX16731 has six predefined scenarios as summarized in Table 3, which can be selected by a pin-strap resistor
connected from PGM1 pin to AGND. See the Voltage Loop Gain for information to select the voltage loop gain resistance
(RVGA) for optimized control loop performance.
Table 3. Predefined Scenarios
SCENARIO #
A
B
C
D
E
F
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RVGA (kΩ)
15.7
22.7
31.3
44.8
52.9
62.3
Analog Devices | 13
MAX16731
30A, 1.5MHz, 2.7V to 16V Integrated Step-Down
Switching Regulator
Reference Design Procedure
Output Voltage Sensing
The MAX16731 has an internal 0.5V reference voltage. When the desired output voltage is higher than 0.5V, it is required to
use a resistor divider RFB1 and RFB2 to sense the output voltage (see the Typical Application Circuit). It is recommended
the value of RFB2 does not exceed 5kΩ. The resistor divider ratio is given by the following equation:
𝑉𝑂𝑈𝑇 = 𝑉𝑅𝐸𝐹 (1 +
𝑅𝐹𝐵1
)
𝑅𝐹𝐵2
where:
VOUT = Output voltage
VREF = 0.5V fixed reference voltage
RFB1 = Top divider resistor
RFB2 = Bottom divider resistor
Selecting the Switching Frequency
The MAX16731 offers a wide range of selectable switching frequencies from 500kHz to 1.5MHz. The selection of switching
frequency can be optimized for different applications. Higher switching frequencies are recommended for the applications
prioritizing solution size so that the value and size of the output LC filter can be reduced. Lower switching frequencies are
recommended for the applications prioritizing efficiency and thermal dissipation, due to reduced switching losses. It is
required that the frequency be selected so that the minimum controllable on-time and minimum controllable off-time are not
violated. The maximum recommended switching frequency is calculated by the following equation:
𝑉𝑂𝑈𝑇
𝑉𝐷𝐷𝐻𝑀𝐼𝑁 − 𝑉𝑂𝑈𝑇
𝑓𝑆𝑊𝑀𝐴𝑋 = 𝑀𝐼𝑁 {
,
}
𝑇𝑂𝑁𝑀𝐼𝑁 × 𝑉𝐷𝐷𝐻𝑀𝐴𝑋 𝑇𝑂𝐹𝐹𝑀𝐼𝑁 × 𝑉𝐷𝐷𝐻𝑀𝐼𝑁
where:
fSWMAX = Maximum selectable switching frequency
VDDHMAX = Maximum input voltage
VDDHMIN = Minimum input voltage
TONMIN = Minimum controllable on-time
TOFFMIN = Minimum controllable off-time
Due to system noise injection, even at steady-state operation, typically the LX rising and falling edges would have some
random jittering noise. The selection of the switching frequency fSW should consider the jittering and be lower than fSWMAX.
To improve the LX jittering, use smaller inductor values and lower voltage loop gain to minimize the noise sensitivity.
Selecting the Output Inductor
The output inductor has an important influence on the overall size, cost, and efficiency of the voltage regulator. Since the
inductor is typically one of the larger components in the system, a minimum inductor value is particularly important in spaceconstrained applications. Smaller inductor values also permit faster transient response, reducing the amount of output
capacitance needed to maintain transient tolerance. Typically, the output inductor is selected so that the inductor current
ripple is 20% to 40% of the maximum load current for optimized performance. To improve current loop noise immunity, it is
recommended that the inductor current ripple is at least 5A. The inductor value is calculated by the following equation:
𝐿=
𝑉𝑂𝑈𝑇 (𝑉𝐷𝐷𝐻 − 𝑉𝑂𝑈𝑇 )
𝑉𝐷𝐷𝐻 × 𝐼𝑅𝐼𝑃𝑃𝐿𝐸 × 𝑓𝑆𝑊
where:
VDDH = Input voltage
IRIPPLE = Inductor current ripple peak-to-peak value
The inductor should also be selected so that maximum load current delivery can be guaranteed by the selected POCP
threshold. The MAX16731 offers three POCP thresholds (38A, 33A, and 28A), which can be selected by PGM1 and PGM2
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Analog Devices | 14
MAX16731
30A, 1.5MHz, 2.7V to 16V Integrated Step-Down
Switching Regulator
pins (see the Pin-Strap Programmability). Due to deglitch delay from the POCP comparator tripping to high-side MOSFET
turning off, for a specific application use case, the adjusted POCP threshold should consider the inductor value, input voltage
and output voltage, which are calculated by the following equation:
𝑃𝑂𝐶𝑃𝐴𝐷𝐽𝑈𝑆𝑇 = 𝑃𝑂𝐶𝑃 +
(𝑉𝐷𝐷𝐻 − 𝑉𝑂𝑈𝑇 ) × 𝑡𝑃𝑂𝐶𝑃
𝐿
where:
POCPADJUST = Adjusted POCP threshold
POCP = POCP level specified in the EC table
tPOCP = POCP deglitch delay (51ns typical)
Verify that the peak inductor current in normal operation does not exceed the minimum adjusted POCP threshold:
𝐼𝑂𝑈𝑇𝑀𝐴𝑋 +
𝐼𝑅𝐼𝑃𝑃𝐿𝐸
< 𝑃𝑂𝐶𝑃𝐴𝐷𝐽𝑈𝑆𝑇(𝑀𝐼𝑁)
2
where:
IOUTMAX = Maximum load current
POCPADJUST(MIN) = Minimum adjusted POCP threshold, calculated with minimum value of the POCP threshold
Table 4 shows some suitable inductor part numbers verified on the MAX16731 evaluation kit to offer optimal performance.
Table 4. Recommended Inductors
COMPANY
Eaton
Eaton
Eaton
Wurth
Wurth
VALUE (nH)
180
220
270
330
470
ISAT (A)
70
58
44
62.5
40.5
RDC (mΩ)
0.17
0.17
0.17
0.165
0.165
FOOTPRINT (mm)
10.8 × 8.0
10.8 × 8.0
10.8 × 8.0
14.0 × 13.0
14.0 × 13.0
HEIGHT (mm)
8.0
8.0
8.0
9.0
9.0
PART NUMBER
FP1008R5-R180-R
FP1008R5-R220-R
FP1008R5-R270-R
744309033
744309047
Selecting the Output Capacitor
One major factor in determining the total required output capacitance is the output voltage ripple. To meet the output voltage
ripple requirement, the minimum output capacitance should satisfy the following equation:
𝐶𝑂𝑈𝑇 =
𝐼𝑅𝐼𝑃𝑃𝐿𝐸
(𝑉
8 × 𝑓𝑆𝑊 × 𝑂𝑈𝑇𝑅𝐼𝑃𝑃𝐿𝐸 − 𝐸𝑆𝑅 × 𝐼𝑅𝐼𝑃𝑃𝐿𝐸 )
where:
VOUTRIPPLE = Maximum allowed output voltage ripple
ESR = ESR of output capacitors
The other important factors in determining the total required output capacitance are the maximum allowable output voltage
overshoot and undershoot during load transients. For a given loading or unloading current step, the minimum required output
capacitance should also satisfy the following equation:
𝐶𝑂𝑈𝑇
2
𝐼𝑅𝐼𝑃𝑃𝐿𝐸 2
𝐼
) ×𝐿
(𝛥𝐼 + 𝑅𝐼𝑃𝑃𝐿𝐸
) ×𝐿
2
2
≥ 𝑀𝐴𝑋 {
,
}
2 × 𝛥𝑉𝑂𝑈𝑇 × (𝑉𝐷𝐷𝐻 − 𝑉𝑂𝑈𝑇 ) 2 × 𝛥𝑉𝑂𝑈𝑇 × 𝑉𝑂𝑈𝑇
(𝛥𝐼 +
where:
COUT = Output capacitance
△I = Loading or unloading current step
△VOUT = Maximum allowed output voltage undershoot or overshoot
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Analog Devices | 15
MAX16731
30A, 1.5MHz, 2.7V to 16V Integrated Step-Down
Switching Regulator
Selecting the Input Capacitor
The selection of input capacitance is determined by the requirement of input voltage ripple. The minimum required input
capacitance is estimated by the following equation:
𝐶𝐼𝑁 ≥
𝐼𝑂𝑈𝑇(𝑀𝐴𝑋) × 𝑉𝑂𝑈𝑇
𝑓𝑆𝑊 × 𝑉𝐷𝐷𝐻 × 𝑉𝐼𝑁𝑃𝑃
where:
IOUT(MAX) = Maximum output current
VOUT = Output voltage
fSW = Switching frequency
VINPP = Peak-to-peak input voltage ripple
Besides, the minimum required input capacitance, also place 0.1μF and 1μF high-frequency decoupling capacitors next to
the VDDH pin to suppress the high-frequency switching noises.
Voltage Loop Gain
For stability purpose, the voltage loop bandwidth (BW) must be lower than 1/5 of the switching frequency. Consider the case
of using the MLCC output capacitors with nearly ideal impedance characteristics in the frequency range of interest with
negligible ESR and ESL. The voltage loop BW is estimated by the following equation:
𝑅
𝑅𝐹𝐵2
× 𝑉𝐺𝐴
𝑅𝐹𝐵2 + 𝑅𝐹𝐵1 10𝑘𝛺
𝐵𝑊 =
2𝜋 × 4𝑚𝛺 × 𝐶𝑂𝑈𝑇
where:
RVGA = The voltage loop gain resistance, which is set by the scenario selected (see Table 3).
Typical Reference Designs
See the Typical Application Circuit or examples of reference schematics. Reference design examples for some common
output voltages are shown in Table 5.
Table 5. Reference Design Examples
VOUT
(V)
0.8
0.9
1.0
1.2
1.8
3.3
5.0
IOUT
(A)
30
30
30
30
25
20
15
fSW
(kHz)
500
500
500
600
750
750
1000
RFB1
(kΩ)
1.82
2.40
3.01
4.22
7.87
16.9
22.6
RFB2
(kΩ)
3.01
3.01
3.01
3.01
3.01
3.01
2.49
PGM0
(Ω)
200
200
200
1050
2490
2870
26100
PGM1
PGM2
L (nH)
CIN
COUT
OPEN
OPEN
OPEN
OPEN
OPEN
AVDD
OPEN
OPEN
OPEN
OPEN
OPEN
OPEN
AVDD
AVDD
220
220
220
220
220
470
470
4 × 22μF +1μF +0.1μF
4 × 22μF +1μF +0.1Μf
4 × 22μF +1μF +0.1μF
4 × 22μF +1μF +0.1μF
4 × 22μF +1μF +0.1μF
4 × 22μF +1μF +0.1μF
4 × 22μF +1μF +0.1μF
8 × 100μF
8 × 100μF
8 × 100μF
8 × 100μF
6 × 100μF
6 × 100μF
4 × 100μF
PCB Layout Guidelines
•
•
•
•
•
•
For electrical and thermal reasons, the second layer from the top and bottom of the PCB should be reserved for power
ground (PGND) planes.
The input decoupling capacitor should be located closest to the IC and no more than 40mils from the VDDH pin.
The VCC decoupling capacitors should be connected to PGND and placed as close as possible to the VCC pin.
An analog ground copper polygon or island should be used to connect all analog control-signal grounds. This “quiet”
analog ground copper polygon or island should be connected to the PGND through a single connection close to the
AGND pin. The analog ground can be used as a shield and ground reference for the control signals.
The AVDD decoupling capacitors should be connected to AGND and placed as close as possible to the AVDD pin.
The boost capacitors should be placed as close as possible to the LX and BST pins, on the same side of the PCB with
the IC.
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Analog Devices | 16
MAX16731
•
•
•
•
30A, 1.5MHz, 2.7V to 16V Integrated Step-Down
Switching Regulator
The feedback resistor-divider and optional external compensation network should be placed close to the IC to minimize
the noise injection.
Output voltage should be sensed with differential remote sense lines routed directly from an output capacitor from the
load point, shielded by the ground plane, and must be kept away from the switching node and the inductor.
Multiple vias are recommended for all paths that carry high currents and for heat dissipation.
The input capacitors and output inductors should be placed near the IC and the traces to the components should be kept
as short and wide as possible to minimize the parasitic inductance and resistance.
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Analog Devices | 17
MAX16731
30A, 1.5MHz, 2.7V to 16V Integrated Step-Down
Switching Regulator
Typical Application Circuit
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Analog Devices | 18
MAX16731
30A, 1.5MHz, 2.7V to 16V Integrated Step-Down
Switching Regulator
Ordering Information
PART NUMBER
TEMP RANGE
PIN-PACKAGE
MAX16731AWX+
-40°C to +125°C
45-Bump WLP
MAX16731AWX+T
-40°C to +125°C
45-Bump WLP
+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
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Analog Devices | 19
MAX16731
30A, 1.5MHz, 2.7V to 16V Integrated Step-Down
Switching Regulator
Revision History
REVISION
NUMBER
0
REVISION
DATE
12/21
DESCRIPTION
Initial release
PAGES
CHANGED
—
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