MAX17330X22+T

厂商：
AD(亚德诺)
封装：
15-WFBGA,WLBGA
描述：
电池电量计 IC 锂离子/聚合物 15-WLP（1.91x2.45）

数据手册：

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MAX17330X22+T 数据手册

EVALUATION KIT AVAILABLE Click here to ask an associate for production status of specific part numbers. MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector General Description Benefits and Features The MAX17330 is a 28μA IQ stand-alone charger, fuel gauge, protector, and battery internal self-discharge detection IC for 1-cell lithium-ion/polymer batteries. When a voltage source is present, the MAX17330 regulates charging by modulating the charge N-FET, using Ac cuCharge™ charger technology. The MAX17330 regulates charge voltage, current, and FET temperature. Stand-alone charging is supported by flexible configuration in nonvolatile memory. The IC supports the following: ● Non-Volatile Programmable Stand-Alone AccuCharge Charger ● Low-Power Charging • 1mA to 500mA directly from universal 5V USB • No USB identification/coordination needed ● High-Power Parallel Packs (>1000mA) • Independently charges parallel packs • Prevents cross-charging for parallel batteries • Coordinates external DC-DC with alerts • Minimizes dropout and heat • • • • • 0.2% Charge Voltage 3.6V to 4.8V, Configurable 1% Charge Current, 256 Current Settings FET Temperature Limit and Heat Regulation Prequal and Step-Charging Options JEITA—6 Temperature Regions ● Battery Health + Programmable Safety/Protection • Overvoltage/Overcharge-Current • Temperature Region Dependent • Overcharge/Discharge/Short-Circuit Current • Over/Under Temperature • Zero-Volt or Greater than 1.8V Charging Option • Undervoltage + SmartEmpty ● Protection and Charging Control—pack or host side ● Pushbutton Wakeup/Factory Ship Mode (0.5μA) ● ModelGauge m5 EZ Algorithm • Percent, Capacity, Time-to-Empty/Full, Age • Cycle+™ Age Forecast The MAX17330 ideal diode circuit supports a quick response to system transients and adapter removal with low voltage drop across the CHG FET. ● Dynamic Power—Estimates Power Capability ● SHA-256 Authentication to Prevent Cloning ● Precision Measurement Without Calibration The IC uses the ModelGauge™ m5 EZ algorithm that combines the short-term accuracy and linearity of a coulomb counter with the long-term stability of a voltagebased fuel gauge to provide industry-leading accuracy. The IC automatically compensates for cell aging, temperature, and discharge rate while providing accurate state-ofcharge (SOC) in milliampere-hours (mAh) or percentage (%) over a wide range of operating conditions. The IC monitors the voltage, current, temperature, and state of the battery to provide protection against over/undervoltage, overcurrent, short-circuit, over/undertemperature and overcharge conditions, and internal self-discharge protection using external high-side N-FETs to ensure that the lithium-ion/polymer battery operates under safe conditions which prolongs the life of the battery. Applications ● ● ● ● ● ● ● ● USB PPS and Direct Charging Smart Batteries and Hybrid Supercap Batteries Dual Screen Smartphones, Tablets Hearables, Wearables, Smartwatches Medical Devices, Health, Fitness Monitors Handheld Radios, Computers, Accessories Home/Building Automation, Sensors, Cameras Parallel Battery AR/VR Systems Ordering Information appears at end of data sheet. ModelGauge, AccuCharge, and Cycle+ are trademarks of Maxim Integrated Products, Inc. SMBus is a trademark of Intel Corp. • Current, Voltage, Power, Time, Cycles • Die Temperature and two Thermistors ● History Logging, User Data ● Low Quiescent Current • FETs Enabled: 28µA Active, 21µA Hibernate • FETs Disabled: 8µA Ship, 0.5µA/0.1µA Shutdown ● 2-wire (I2C/SMBus™) ● 1.9mm x 2.5mm 15-bump 0.5mm pitch WLP Simple Charger, Fuel Gauge with Protector Diagram CHARGE SOURCE SYSTEM MAX17330 CHARGER PROTECTOR FUEL GAUGE MAX17330 CHARGER PROTECTOR FUEL GAUGE PARALLEL BATTERY 19-100962; Rev 1; 4/23 © 2023 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector TABLE OF CONTENTS General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Benefits and Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Simple Charger, Fuel Gauge with Protector Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 15 WLP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 WLP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Charge Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Charging Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Step Charging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Zero-Volt Charging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 End-of-Charge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Charger Restart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Parallel Battery Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Ideal Diode Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Protector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Battery Internal Self-Discharge Detection (ISD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Protector Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Voltage Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Current Thresholds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Fast Overcurrent Comparators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Slow Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Overcurrent Comparator Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Temperature Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Other Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Permanent Failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Disabling FETs by Pin-Control or I2C Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Fuel Gauge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 ModelGauge m5 EZ Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Wakeup/Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 www.analog.com Analog Devices | 2 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector TABLE OF CONTENTS (CONTINUED) Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Power Mode Transition State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Pushbutton Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Component Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Sense Resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Charging and Protection FETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 ESD and Optional Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Register Description Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Standard Register Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Nonvolatile Backup and Initial Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Register Naming Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Charging Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Charging Status and Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 ChgStat Register (0A3h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 nChgCfg0 Register (1C2h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 nChgCfg1 Register (1CBh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 nMiscCfg2 Register (1E4h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Charging Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 ChargingVoltage Register (02Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 ChargingCurrent Register (028h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 nIChgTerm Register (19Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 nVChgCfg Register (1D9h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 nIChgCfg Register (1D8h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 nStepChg Register (1DBh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Protection Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Voltage Protection Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 nUVPrtTh Register (1D0h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 nOVPrtTh Register (1DAh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Current Protection Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 nODSCTh Register (1DDh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 nODSCCfg Register (1DEh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 nIPrtTh1 Register (1D3h)—Overcurrent Protection Thresholds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Temperature Protection Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 nTPrtTh1 Register (1D1h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 nTPrtTh2 Register (1D5h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 nTPrtTh3 Register (1D2h) (beyond JEITA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Fault Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 www.analog.com Analog Devices | 3 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector TABLE OF CONTENTS (CONTINUED) nDelayCfg Register (1DCh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Battery Internal Self-Discharge Detection Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Status/Configuration Protection Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 nProtCfg Register (1D7h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 nBattStatus Register (1A8h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 ProtStatus Register (0D9h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 ProtAlrt Register (0AFh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 HProtCfg2 Register (0F1h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 FProtStat Register (0DAh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Other Protection Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 nProtMiscTh Register (1D6h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 ModelGauge m5 Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 ModelGauge m5 EZ Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 ModelGauge m5 EZ Algorithm Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 RepCap Register (005h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 RepSOC Register (006h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 FullCapRep Register (010h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 TTE Register (011h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 TTF Register (020h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Age Register (007h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Cycles Register (017h) and nCycles (1A4h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 TimerH Register (0BEh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 FullCap Register (035h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 nFullCapNom Register (1A5h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 RCell Register (014h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 VRipple Register (0B2h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 nVoltTemp Register (1AAh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 ModelGauge m5 EZ Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 OCV Estimation and Coulomb Count Mixing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Empty Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Fuel Gauge Learning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Converge-To-Empty . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Determining Fuel-Gauge Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Initial Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Cycle+ Age Forecasting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 nAgeFcCfg Register (1E2h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 AgeForecast Register (0B9h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Age Forecasting Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Enabling Age Forecasting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 www.analog.com Analog Devices | 4 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector TABLE OF CONTENTS (CONTINUED) Battery Life Logging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Life Logging Data Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Determining Number of Valid Logging Entries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Reading History Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 History Data Reading Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 ModelGauge m5 EZ Algorithm Input Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 nXTable0 (180h) to nXTable11 (18Bh) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 nOCVTable0 (190h) to nOCVTable11 (19Bh) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 nQRTable00 (1A0h) to nQRTable30 (1A3h) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 nFullSOCThr Register (1C6h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 nVEmpty Register (19Eh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 nDesignCap Register(1B3h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 nRComp0 Register (1A6h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 nTempCo Register (1A7h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 ModelGauge m5 EZ Algorithm Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 nFilterCfg Register (19Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 nRelaxCfg Register (1B6h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 nTTFCfg Register (1C7h)/CV_MixCap (0B6h) and CV_HalfTime (0B7h) Registers . . . . . . . . . . . . . . . . . . . . 91 nConvgCfg Register (1B7h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 nRippleCfg Register (1B1h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 nMiscCfg Register (1B2h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 ModelGauge m5 EZ Algorithm Additional Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Timer Register (03Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 dQAcc Register (045h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 dPAcc Register (046h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 QResidual Register (00Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 VFSOC Register (0FFh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 VFOCV Register (0FBh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 QH Register (4Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 AvCap Register (01Fh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 AvSOC Register (00Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 MixSOC Register (00Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 MixCap Register (02Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 VFRemCap Register (04Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 SOCHold Register (0D0h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 FStat Register (03Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 nLearnCfg Register (19Fh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 ModelGauge m5 EZ Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 www.analog.com Analog Devices | 5 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector TABLE OF CONTENTS (CONTINUED) Nonvolatile Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Nonvolatile Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 100 Record Life Logging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 nNVCfg0 Register (1B8h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 nNVCfg1 Register (1B9h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 nNVCfg2 Register (1BAh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Enabling and Freeing Nonvolatile vs. Defaults. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Shadow RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Shadow RAM and Nonvolatile Memory Relationship . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Nonvolatile Memory Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 COPY NV BLOCK [E904h] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 NV RECALL [E001h] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 HISTORY RECALL [E2XXh] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Nonvolatile Block Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Determining Number of Remaining Updates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Memory Locks and Write Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 CommStat Register (061h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 NV LOCK [6AXXh] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Locking Memory Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Reading Lock State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Analog Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Voltage Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 VCell Register (01Ah). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 AvgVCell Register (019h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 MaxMinVolt Register (0008h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Cell1 Register (0D8h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 AvgCell1 Register (0D4h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Batt Register (0D7h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 PCKP Register (0DBh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 MinVolt Register (0ADh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Current Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Current Measurement Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Current Register (01Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 AvgCurrent Register (01Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 MaxMinCurr Register (00Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 nCGain Register (1C8h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 CGTempCo (0B8h)/nCGTempCo (0x1C9) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Copper Trace Current Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 MinCurr Register (0AEh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 www.analog.com Analog Devices | 6 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector TABLE OF CONTENTS (CONTINUED) Temperature Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Temperature Measurement Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Temp Register (01Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 AvgTA Register (016h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 MaxMinTemp Register (009h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 nThermCfg Register (1CAh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 DieTemp (034h) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 AvgDieTemp (040h) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 FETTemp (015h) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 nADCCfg Register (1C9h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Status and Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 DevName Register (021h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 nROMID0 (1BCh)/nROMID1 (1BDh)/nROMID2 (1BEh)/nROMID3 (1BFh) Registers . . . . . . . . . . . . . . . . . . . . 121 Status Register (000h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Status2 Register (0B0h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 nI2CCfg Register (1B4h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 nPackCfg Register(1B5h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 I2CCmd Register(12Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 nConfig Register (1B0h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 nHibCfg Register (1BBh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 nRSense Register (1CFh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 nDesignVoltage Register (1E3h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 AtRate Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 AtRate Register (004h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 AtQResidual Register (0DCh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 AtTTE Register (0DDh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 AtAvSOC Register (0CEh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 AtAvCap Register (0DFh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Alert Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 nVAlrtTh Register (18Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 nTAlrtTh Register (18Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 nSAlrtTh Register (18Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 nIAlrtTh Register (0ACh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Smart Battery Compliant Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 SBS Compliant Memory Space (I2C Interface Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 sRemCapAlarm/sRemTimeAlarm Registers (101h/102h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 At-Rate Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 sAtRate Register (104h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 www.analog.com Analog Devices | 7 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector TABLE OF CONTENTS (CONTINUED) sAtTTF Register (105h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 sAtTTE Register (105h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 sAtRateOK Register (107h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 sTemperature Register (108h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 sPackVoltage Register (109h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 sChargingCurrent Register (114h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 sDesignVolt Register (119h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 sSpecInfo Register (11Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 sSerialNumber Register (11Ch to 11Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 sManfctrName Register (120h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 sDeviceName Register (121h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 sDevChemistry Register (122h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 sManfctData Registers (123h to 12Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 sFirstUsed Register (136h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 sCell1 Register (13Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 sAvgCell1 Register (14Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 sAvCap Register (167h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 sMixCap Register (168h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 sManfctInfo Register (170h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Nonvolatile SBS Register Back-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 nCGain and Sense Resistor Relationship . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Dynamic Battery Power Technology (DBPT) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 MaxPeakPower Register (0A4h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 SusPeakPower Register (0A5h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 sPackResistance (0A6h) and nPackResistance (1C5h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 SysResistance (0A7h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 MinSysVoltage() (0A8h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 MPPCurrent (0A9h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 SPPCurrent (0AAh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 SHA-256 Authentication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Authentication Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Procedure to Verify a Battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Alternate Authentication Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Battery Authentication without a Host Side Secret . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Secret Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Single-Step Secret Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Single-Step Secret Generation Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Multi-Step Secret Generation Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Multi-Step Secret Generation Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 www.analog.com Analog Devices | 8 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector TABLE OF CONTENTS (CONTINUED) 2-Stage Authentication Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Create a Unique Intermediate Secret . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Procedure for 2-Stage Authentication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Determining Number of Remaining Updates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Authentication Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 COMPUTE MAC WITHOUT ROM ID [3600h] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 COMPUTE MAC WITH ROM ID [3500h] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 COMPUTE NEXT SECRET WITHOUT ROM ID [3000h] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 COMPUTE NEXT SECRET WITH ROM ID [3300h] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 CLEAR SECRET [5A00h] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 LOCK SECRET [6000h] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 COPY TEMPORARY SECRET FROM NVM [3800] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 COMPUTE NEXT TEMPORARY SECRET WITH ROMID [3900] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 COMPUTE NEXT TEMPORARY SECRET WITHOUT ROMID [3A00] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 COMPUTE MAC FROM TEMPORARY SECRET WITHOUT ROMID [3C00] . . . . . . . . . . . . . . . . . . . . . . . . 145 COMPUTE MAC FROM TEMPORARY SECRET WITH ROMID [3D00]. . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Reset Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 HARDWARE RESET [000Fh to address 060h] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 CONFIGURATION RESET [8000h to address 0ABh] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Summary of Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 2-Wire Bus System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Hardware Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 2-Wire Bus Interface Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 I/O Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Bit Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Bus Idle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 START and STOP Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Acknowledge Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Data Order. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Slave Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Read/Write Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 2-Wire Bus Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 I2C Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 I2C Write Data Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 I2C Read Data Protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 SBS Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 www.analog.com Analog Devices | 9 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector TABLE OF CONTENTS (CONTINUED) SBS Write Word Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Example SBS Write Word Communication Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 SBS Read Word Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Example SBS Read Word Communication Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 SBS Write Block Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 SBS Read Block Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Example SBS Read Block Communication Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Valid SBS Read Block Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Packet Error Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 PEC CRC Generation Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Appendix A: Reading History Data Pseudo-Code Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Appendix B: Parallel Cell Management Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Typical Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Typical Application Schematic with Fuse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 Pushbutton Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Typical Application Schematic for System Side Implementaiton . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 www.analog.com Analog Devices | 10 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector LIST OF FIGURES Figure 1. Li+/Li-Poly Charge Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 2. Step-Charging State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 3. Zero-Volt Charge Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 4. FullCapRep Learning at End-of-Charge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Figure 5. Supplement and Charging Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 6. Charging and Discharging States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Figure 7. Simplified Protector State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Figure 8. Programmable Voltage Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Figure 9. Programmable Current Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Figure 10. Example of Internal Self-Discharge with Temperature Variation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Figure 11. Fast, Medium, and Slow Overdischarge Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Figure 12. Overcurrent Comparator Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Figure 13. Merger of Coulomb Counter and Voltage Based Fuel Gauge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Figure 14. ModelGauge m5 EZ Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Figure 15. Power Mode Transition State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Figure 16. ModelGauge m5 EZ Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Figure 17. Voltage and Coulomb Count Mixing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Figure 18. ModelGauge m5 EZ Typical Accuracy Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Figure 19. Handling Changes in Empty Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Figure 20. FullCapNom Learning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Figure 21. Converge-To-Empty . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Figure 22. Benefits of Age Forecasting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Figure 23. Sample Life Logging Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Figure 24. Write Flag Register and Valid Flag Register Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Figure 25. Cell Relaxation Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Figure 26. Shadow RAM and Nonvolatile Memory Relationship . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Figure 27. Procedure to Verify a Battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Figure 28. Battery Authentication without a Host Side Secret . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Figure 29. Single-Step Secret Generation Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Figure 30. Multi-Step Secret Generation Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Figure 31. Create a Unique Intermediate Secret . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Figure 32. Procedure for 2-Stage Authentication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Figure 33. 2-Wire Bus Interface Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Figure 34. 2-Wire Bus Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Figure 35. Example I2C Write Data Communication Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Figure 36. Example I2C Read Data Communication Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Figure 37. Example SBS Write Word Communication Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Figure 38. Example SBS Read Word Communication Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Figure 39. Example SBS Read Block Communication Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 www.analog.com Analog Devices | 11 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector LIST OF FIGURES (CONTINUED) Figure 40. PEC CRC Generation Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 www.analog.com Analog Devices | 12 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector LIST OF TABLES Table 1. Charging Current with Step Charging and JEITA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 2. Charging Voltage with Step Charging and JEITA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 3. Parallel Management FET Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 4. AvgCurrDet Threshold when using 10mΩ and Default nProtMiscTh.CurrDet = 7.5mA . . . . . . . . . . . . . . . . . . 37 Table 5. Summary of Protector Registers by Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 6. Voltage Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 7. Current Threshold Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 8. Other Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table 9. Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Table 10. MAX17330 Ship Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Table 11. Recommended nHibCfg Settings and the Impact on IQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Table 12. MAX17330 Standard Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Table 13. Sense Resistor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Table 14. ModelGauge Register Standard Resolutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Table 15. ChgStat (0A3h) Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Table 16. nChgCfg0 Register (1C2h) Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Table 17. nChgCfg1 (1CBh) Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Table 18. HeatLim Range and Resolution for Different Sense Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Table 19. nMiscCfg2 Register (1E4h) Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Table 20. nVChgCfg Register (1D9h) Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table 21. nIChgCfg Register (1D8h) Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Table 22. Charging Current for Different Sense Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Table 23. nStepChg Register (1DBh) Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Table 24. nUVPrtTh Register (1D0h) Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Table 25. nOVPrtTh Register (1DAh) Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Table 26. nODSCTh Register (1DDh) Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Table 27. OCTH, SCTh, and ODTH Sample Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Table 28. nODSCCfg Register (1DEh) Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Table 29. nIPrtTh1 Register (1D3h) Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Table 30. nTPrtTh1 Register (1D1h) Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Table 31. nTPrtTh2 (1D5h) Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Table 32. nTPrtTh3 Register (1D2h) Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Table 33. nDelayCfg (1DCh) Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Table 34. UVPTimer Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Table 35. TempTimer Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Table 36. TempTrans Configuration Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Table 37. PermFailTimer Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Table 38. OverCurrTimer Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Table 39. OVPTimer Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 www.analog.com Analog Devices | 13 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector LIST OF TABLES (CONTINUED) Table 40. FullTimer Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Table 41. ChgWDT/ChgRm Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Table 42. nProtCfg2 Register (1DFh) Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Table 43. Alert and Fault Mode Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Table 44. LeakCurrRep Register (0x16F) Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Table 45. nProtCfg Register (1D7h) Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Table 46. nBattStatus Register (1A8h) Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Table 47. ProtStatus Register (0D9h) Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Table 48. ProtAlrt Register (0AFh) Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Table 49. HProtCfg2 (0F1h) Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Table 50. FProtStat Register (0DAh) format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Table 51. nProtMiscTh Register (1D6h) Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Table 52. nCycles Register (1A4h) Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Table 53. nNVCfg2.FibScl Setting Determines LSb of nNVCfg2.CyclesCount . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Table 54. nVoltTemp Register (1AAh) Format when nNVCfg2.enVT = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Table 55. nAgeFcCfg Register (1E2h) Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Table 56. Minimum and Maximum Cell Sizes for Age Forecasting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Table 57. Life Logging Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Table 58. Reading History Page Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Table 59. Decoding History Page Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Table 60. Reading History Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Table 61. nFullSOCThr (1C6h)/FullSOCThr (013h) Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Table 62. nVEmpty (19Eh) Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Table 63. FilterCfg (029h)/nFilterCfg (19Dh) Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Table 64. RelaxCfg (0A0h)/nRelaxCfg (1B6h) Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Table 65. nTTFCfg Register (1C7h) Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Table 66. nConvgCfg Register (1B7h) Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Table 67. nRippleCfg Register (1B1h) Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Table 68. MiscCfg (00Fh)/nMiscCfg (1B2h) Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Table 69. SOCHold (0D0h) Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Table 70. FStat Register (03Dh) Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Table 71. LearnCfg (0A1h)/nLearnCfg (19Fh) Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Table 72. Top Level Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Table 73. Individual Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Table 74. ModelGauge m5 EZ Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Table 75. Nonvolatile Register Memory Map (Slave Address 0x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Table 76. Fibonacci Configuration Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Table 77. Eventual Matured Update Interval (in battery cycles) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Table 78. Saving Schedule Example with the Most Preferred Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 www.analog.com Analog Devices | 14 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector LIST OF TABLES (CONTINUED) Table 79. nNVCfg0 Register (1B8h) Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Table 80. nNVCfg1 Register (1B9h) Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Table 81. nNVCfg2 Register (1BAh) Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Table 82. Making Nonvolatile Memory Available for User Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Table 83. Nonvolatile Memory Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Table 84. History Recall Command Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Table 85. Number of Remaining Config Memory Updates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Table 86. CommStat Register (061h) Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Table 87. Format of LOCK Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Table 88. Format of Lock Register (07Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Table 89. MaxMinVolt (008h)/nMaxMinVolt (1ACh) Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Table 90. Current Measurement Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Table 91. Current Measurement Range and Resolution vs. Sense Resistor Value . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Table 92. MaxMinCurr (00Ah)/nMaxMinCurr (1ABh) Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Table 93. nCGain Register (1C8h) Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Table 94. Copper Trace Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Table 95. Temperature Measurement Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Table 96. MaxMinTemp (009h)/nMaxMinTemp (1ADh) Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Table 97. Register Settings for Common Thermistor Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Table 98. nADCCfg (0x1C9) Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Table 99. DevName Register (021h) Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Table 100. nROMID Registers (1BCh to 1BFh) Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Table 101. Status Register (000h) Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Table 102. Status2 Register (0B0h) Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Table 103. nI2CCfg Register (1B4h) Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Table 104. nPackCfg (1B5h) Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Table 105. I2C Address Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Table 106. Thermistor Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Table 107. I2CCmd (12Bh) Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Table 108. GoToSID Address Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Table 109. nConfig Register (1B0h) Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Table 110. Config Register (00Bh) Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Table 111. Config2 Register (0ABh) Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Table 112. nHibCfg Register (1BBh) Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Table 113. Recommended nRSense Register Values for Common Sense Resistors . . . . . . . . . . . . . . . . . . . . . . . . . 126 Table 114. nDesignVoltage Register (1E3h) Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Table 115. VAlrtTh (001h)/nVAlrtTh (18Ch) Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Table 116. TAlrtTh (002h)/nTAlrtTh (18Dh) Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Table 117. SAlrtTh (003h)/nSAlrtTh (18Fh) Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 www.analog.com Analog Devices | 15 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector LIST OF TABLES (CONTINUED) Table 118. IAlrtTh (0ACh)/nIAlrtTh (18Eh) Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Table 119. SBS Register Space Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Table 120. SpecInfo (11Ah) Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Table 121. SBS to Nonvolatile Memory Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Table 122. nCGain Register Settings to Meet SBS Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Table 123. Number of Remaining Secret Updates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Table 124. All Function Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Table 125. 2-Wire Slave Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Table 126. Valid SBS Read Block Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 www.analog.com Analog Devices | 16 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector Absolute Maximum Ratings CP to BATT .................................................... -0.3V to BATT +6V CHG to BATT .................................................. -0.3V to CP +0.3V Continuous Source Current for BATT (during zero-volt charging) ............................................................................. 50mA Continuous Sink Current for SDA, ALRT, PFAIL ................ 20mA Continuous Source Current for PFAIL ................................. 20mA Continuous Sink Current for ZVC ........................................ 50mA Operating Temperature Range ............................ -40°C to +85°C Storage Temperature Range .............................. -55°C to +125°C Soldering Temperature (reflow) ........................................ +260°C Lead Temperature (soldering 10s) ................................... +300°C BATT to GND ............................................................ -0.3V to +6V ALRT to GND .......................................................... -0.3V to +17V TH, PFAIL to GND .......................................-0.3V to BATT +0.3V ZVC/TH2 to GND ...................................................... -0.3V to +6V REG to GND .......................................................... -0.3V to +2.2V CSN to BATT ................................... BATT - 0.3V to BATT +0.3V CSP to BATT ................................... BATT - 0.3V to BATT +0.3V DIS to GND ...................................................... -0.3V to CP +0.3V PCKP to GND ......................................................... -0.3V to +28V SDA, SCL to GND ................................................... -0.3V to +20V Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Package Information 15 WLP Package Code W151J2+1 Outline Number 21-100433 Land Pattern Number Refer to Application Note 1891 Thermal Resistance, Four-Layer Board: Junction to Ambient (θJA) 62°C/W Junction to Case (θJC) N/A www.analog.com Analog Devices | 17 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector Pin 1 Ind ic a tor COMMON DIMENSIONS E 1 Ma rking see Note 7 A AAAA D A1 0.64 0.05 0.24 0.03 A2 0.40 REF A3 0.04 BASIC 0.31 0.03 A b D TOP VIEW E SIDE VIEW A1 A S A2 0.025 0.025 E1 1.00 BASIC 2.00 BASIC e 0.50 BASIC SD 0.00 BASIC D1 A3 1.908 2.448 0.00 BASIC DEPOPULATED BUMPS: NONE SE 0.05 S FRONT VIEW E1 SE e B NOTES: 1. Term ina l p itc h is d efined b y term ina l c enter to c enter va lue. 2. Outer d im ension is d efined b y c enter lines b etw een sc rib e lines. 3. All d im ensions in m illim eter. 4. Ma rking show n is for p a c ka g e orienta tion referenc e only. 5. Tolera nc e is ± 0.02 unless sp ec ified otherw ise. 6. All d im ensions a p p ly to Pb Free (+) p a c ka g e c od es only. 7. Front - sid e finish c a n b e either Bla c k or Clea r. SD C B D1 A 1 2 3 4 A BOTTOM VIEW - DRAWING NOT TO SCALE - 5 b 0.05 M maxim integrated S AB TITLE TM PACKAGE OUTLINE 15 BUMPS WLP PKG. 0.5 m m PITCH, W151J2+1 APPROVAL DOCUMENT CONTROL NO. 21-100433 REV. A 1 1 For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial. www.analog.com Analog Devices | 18 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector Electrical Characteristics (VBATT = 2.16V to 4.9V, typical value at 3.6V (Note 1), TA = -40°C to +85°C, typical values are TA = +25°C, see the Functional Diagram. Limits are 100% tested at TA = +25°C. Limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 4.9 V 0.1 μA μA POWER SUPPLY Supply Voltage VBATT (Note 1) 2.16 Undervoltage Shutdown Supply Current IDD0 Undervoltage shutdown DeepShip Supply Current IDD1 TA ≤ +50°C, typical at +25°C 0.5 1.1 11 24 IDD2 DpShpEn = 0, TA ≤ +50°C, typical at +25°C, protection FETs off 1.4s updates Ship Supply Current 5.625s updates 8 Hibernate Supply Current IDD3 TA ≤ +50°C, typical at +25°C, average current, CHG and DIS on, 1.4s updates 21 42 μA Active Supply Current IDD4 TA ≤ +50°C, typical at +25°C, average current, not including thermistor measurement current 28 52 μA Regulation Voltage VREG μA 1.8 V CHARGE ACCURACY Charge Voltage Accuracy Charge Voltage Range Charge Current Accuracy Charge Current Range VGERR VFS IGERR IFS nVChgCfg setting, TA = +25°C -7.5 +7.5 nVChgCfg setting, -40ºC ≤ TA ≤ +85ºC -20 +20 nVChgCfg setting, 5mV resolution 3.56 4.835 nIChgCfg vs. CSP-CSN, Charge Current set 10mV to 25.6mV -1.1 +1.1 nIChgCfg vs. CSP-CSN, Charge Current set 6mV to 10mV -1.15 +1.15 nIChgCfg vs. CSP-CSN, nIChgCfg from 4mV to 6mV -1.25 +1.25 % of Reading nIChgCfg vs. CSP-CSN, nIChgCfg from 2.5mV to 4mV -1.4 +1.4 % nIChgCfg setting, 400mA to 2560mA, 10mA steps (with 10mΩ) 2.5 25.6 mV V % nChgCfg1.HeatLim; RSENSE = 10mΩ; multiply RSENSE/10mΩ for other sense resistors Charge Heat Regulation Max Setting mV 3264 mW ANALOG-TO-DIGITAL CONVERSION TA = +25°C, 2.3V ≤ VBATT ≤ 4.9V -7.5 +7.5 -40ºC ≤ TA ≤ +85ºC, 2.3V ≤ VBATT ≤ 4.9V -20 +20 Voltage Measurement Error VGERR Voltage Measurement Resolution VLSB Current Measurement Offset Error IOERR CSP = CSN = 3.6V, long-term average (Note 2) Current Measurement Gain Error IGERR CSP between CSN-50mV and CSN+50mV www.analog.com -1 mV 78.125 μV ±1.5 μV +1 % of Reading Analog Devices | 19 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector Electrical Characteristics (continued) (VBATT = 2.16V to 4.9V, typical value at 3.6V (Note 1), TA = -40°C to +85°C, typical values are TA = +25°C, see the Functional Diagram. Limits are 100% tested at TA = +25°C. Limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Current Measurement Resolution ILSB 1.5625 μV Current Measurement Range IFS ±51.2 mV Internal Temperature Measurement Error TIGERR ±1 ºC Internal Temperature Measurement Resolution TILSB 0.00391 ºC Auxiliary Ratiometric Measurement Error TEGERR PCKP Measurement Resolution VPLSB PCKP Measurement Range VPFS PCKP Versus BATT Measurement Error VP2Berr TH (Note 2) -0.5 +0.5 312.5 TA = +25ºC % of Reading μV 1.5 BATT + 5.12 V -10 +10 mV PCKP PCKP Startup Voltage 3.1 PCKP Startup Hysteresis 100 PCKP Current PCKP Pulldown Resistor BATT = PCKP 170 220 mV 1.2 2.5 μA 24 40 60 kΩ 2x VBATT 0.4 2x VBATT 0.2 2x VBATT V TA < +85°C, typical at TA = +25°C RPDPCKP V CHARGE PUMP CP Output Voltage VCP Battery only CHG Output High VOHC IOH = -1mA CHG Output Low VOLC IOL = 1mA DIS Output High VOHD IOH = -100μA DIS Output Low VOLD IOL = 100μA ICHG + IDIS = 1μA CHG DRIVER VCP 0.4 V BATT + 0.4 V DIS DRIVER VCP 0.4 V 0.1 V ZERO-VOLT CHARGE Voltage Drop Between ZVC and BATT www.analog.com VZVCDROP 30mA into ZVC BATT = 0V 1.4 2 BATT = 2.3V 0.15 0.5 V Analog Devices | 20 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector Electrical Characteristics (continued) (VBATT = 2.16V to 4.9V, typical value at 3.6V (Note 1), TA = -40°C to +85°C, typical values are TA = +25°C, see the Functional Diagram. Limits are 100% tested at TA = +25°C. Limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 0.4 V INPUT/OUTPUT Output Drive Low, ALRT, SDA, PFAIL VOL IOL = 4mA, VBATT = 2.3V 0.01 Output Drive High, PFAIL VOH IOH = -1mA, VBATT = 2.3V VBATT 0.1 V Input Logic High, SCL, SDA, PIO VIH 1.5 V Input Logic Low, SCL, SDA, PIO VIL PIO Wake Debounce PIO_WD Ship mode 100 External Thermistance Resistance REXT10 nPackCfg.R100 = 0 10 REXT100 nPackCfg.R100 = 1 100 0.5 V ms kΩ RESISTANCE AND LEAKAGE Leakage Current, CSN, CSP, ALRT, TH ILEAK Input Pulldown Current IPD VALRT < 15V -1 SDA, SCL pin = 0.4V 0.2 +1 μA 0.5 μA COMPARATORS Overcharge Current Threshold Offset Error OCOE OC comparator -0.8 +0.8 mV Overdischarge Current Threshold Offset Error ODOE OD comparator -1.5 +1.5 mV Short-Circuit Threshold Offset Error SCOE SC comparator -2.5 +2.5 mV Overcurrent Threshold Gain Error ODOCSCGE OC, OD, or SC comparator -4.0 +4.0 % of Threshold 6 μs Overcurrent Comparator Delay Supplement Mode Comparator Threshold Falling PCKP Versus BATT OCDLY VSUP_TH_F OD or SC comparator, 20mV minimum input overdrive, delay configured to minimum 2 BATT ≥ 3.4V, PCKP sweep down 30 mV TIMING Time-Base Accuracy tERR TA = +25°C SHA Calculation Time tSHA VBATT > 3V tPRE Time between turning on the TH bias and analog-to-digital conversions TH Precharge Time Task Period -1 4.5 +1 % 10 ms 8.48 tTP ms 351.5 ms NONVOLATILE MEMORY Nonvolatile Access Voltage VNVM For block programming and recalling, applied on BATT 3.0 Programming Supply Current IPROG Current from BATT at 2.9V for block programming 2 www.analog.com V 5.5 10 mA Analog Devices | 21 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector Electrical Characteristics (continued) (VBATT = 2.16V to 4.9V, typical value at 3.6V (Note 1), TA = -40°C to +85°C, typical values are TA = +25°C, see the Functional Diagram. Limits are 100% tested at TA = +25°C. Limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 368 7360 ms 64 1280 ms 5 ms Block Programming Time tBLOCK Page Programming Time tUPDATE Nonvolatile Memory Recall Time tRECALL Write Capacity, Configuration Memory nCONFIG (Notes 2, 3, 4) 7 writes Write Capacity, SHA Secret nSECRET (Notes 2, 3, 4) 5 writes Write Capacity, Learned Parameters nLEARNED (Notes 2, 3, 4) 99 writes Data Retention SHA secret update or learned parameters update tNV (Note 2) 10 SCL Clock Frequency fSCL (Note 5) 0 Bus Free Time Between a STOP and START Condition tBUF years 2-WIRE INTERFACE Hold Time (Repeated) START Condition tHD:STA (Note 6) 400 kHz 1.3 μs 0.6 μs Low Period of SCL Clock tLOW 1.3 μs High Period of SCL Clock tHIGH 0.6 μs Setup Time for a Repeated START Condition tSU:STA 0.6 μs Data Hold Time tHD:DAT (Notes 7, 8) Data Setup Time tSU:DAT (Note 7) 0 0.9 100 μs ns Rise Time of Both SDA and SCL Signals tR 5 300 ns Fall Time of Both SDA and SCL Signals tF 5 300 ns Setup Time for STOP Condition tSU:STO 0.6 Spike Pulse Width Suppressed by Input Filter tSP Capacitive Load for Each Bus Line CB SCL, SDA Input Capacitance μs (Note 9) CBIN 6 50 ns 400 pF pF Note 1: All voltages are referenced to GND. Note 2: Specification is guaranteed by design (GBD) and not production tested. www.analog.com Analog Devices | 22 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector Note 3: Write capacity numbers shown have one write subtracted for the initial write performed during manufacturing test to set nonvolatile memory to a known value. Note 4: Due to the nature of one-time programmable memory, write endurance cannot be production tested. Follow the nonvolatile memory and SHA secret update procedures detailed in the data sheet. Note 5: Timing must be fast enough to prevent the IC from entering shutdown mode due to bus low for a period greater than the shutdown timer setting. Note 6: fSCL must meet the minimum clock low time plus the rise/fall times. Note 7: The maximum tHD:DAT has to only be met if the device does not stretch the low period (tLOW) of the SCL signal. Note 8: This device internally provides a hold time of at least 100ns for the SDA signal (referred to the minimum VIH of the SCL signal) to bridge the undefined region of the falling edge of SCL. Note 9: On 10mΩ RSENSE www.analog.com Analog Devices | 23 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector Typical Operating Characteristics (TA = +25°C, unless otherwise noted.) www.analog.com Analog Devices | 24 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector Typical Operating Characteristics (continued) (TA = +25°C, unless otherwise noted.) www.analog.com Analog Devices | 25 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector Typical Operating Characteristics (continued) (TA = +25°C, unless otherwise noted.) Pin Configuration WLP TOP VIEW (BUMP SIDE DOWN) 1 2 A TH B C MAX17330X22 3 4 5 GND CSP CSN REG CP PFAIL ZVC/ TH2 ALRT/ PIO SCL BATT CHG DIS PCKP SDA + (1.9mm x 2.5mm, 0.5mm PITCH) Pin Description PIN NAME A1 TH Battery Thermistor Connection. Connect an external 10kΩ or 100kΩ thermistor between TH and GND to measure the battery temperature. Connect to BATT if not used. B1 CP Charge Pump Output. CP provides the voltage for driving external charge and discharge protection N-FETs. Connect a bypass 0.1μF capacitor between CP and BATT. C1 BATT Battery Connection. The MAX17330 receives power from BATT and measures cell voltage at BATT. Connect BATT to positive terminal of the battery with a 10Ω resistor and bypass with a 0.1μF capacitor to GND. B2 PFAIL Permanent Failure Indicator (Optional). Connect to secondary protector to take action in case of primary FET failure detection. Disconnect if not used, or connect to GND with a 2MΩ resistor. www.analog.com FUNCTION Analog Devices | 26 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector Pin Description (continued) PIN NAME A3 CSP Current-Sense-Resistor Positive Input. Kelvin-connect to the Pack+ side of the sense resistor. FUNCTION A4 CSN Current-Sense Negative Input. Kelvin connect to the cell side of the sense resistor. A5 REG 1.8V Regulator. REG provides a 1.8V supply for the IC. Bypass with a 0.47μF capacitor between REG and GND. C5 SDA Serial Data Input/Output for I2C Communication Modes. Open-drain output driver. Connect to the DATA terminal of the battery pack. SDA has an internal pulldown (IPD) for sensing pack disconnection. B5 SCL Serial Clock Input for I2C Communication. Input only. For I2C communication, connect to the clock terminal of the battery pack. SCL has an internal pulldown (IPD) for sensing pack disconnection. Alert Output. ALRT is open-drain and active-low. Connect an external pullup resistor to indicate alerts. See the Alerts section for more details. B4 ALRT/PIO C4 PCKP C3 DIS Discharge FET Control. DIS enables/disables battery discharge by driving an external N-FET between CP and GND. B3 ZVC/TH2 Zero-Volt Charge Input Pin. Connect to PCKP through a resistor for ZVC function. Alternative function is temperature sense for CHG-FET, connect to Thermistor. Leave disconnected or connect to GND if unused. C2 CHG Charge FET Control. CHG blocks/allows battery charge by controlling an external N-FET between CP and BATT. A2 GND IC GND www.analog.com Pushbutton Wakeup. Connect to the host-system's power button to GND without any external pullup since the IC has an internal pullup. The IC wakes up from shutdown mode when the button is pressed. Pack Positive Terminal or System Positive Terminal. PCKP pin is used for charger detection, input voltage measurement, and overcurrent fault removal detection. Analog Devices | 27 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector SYS + N N Functional Diagram CHG DIS PCKP CP CP GND BATT CHARGE DETECT CSP ALRT/PIO MODELGAUGE m5 CSN PFAIL MUX INTERNAL TEMPERATURE SENSOR BATT 1.8V REG OUT IN REGULATOR I 2C INTERFACE ADC MAX17330 CP SHA-256 PROTECTOR CONTROL CHARGE PUMP OPTIONAL ZVC SDA SCL TH BIAS GENERATOR TH ZERO-VOLT CHARGING ZVC/TH2 GND OPTIONAL TH2 SYS – www.analog.com Analog Devices | 28 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector Detailed Description General Description The MAX17330 is a 28μA IQ stand-alone charger, fuel gauge IC with protector and SHA-256 authentication for 1-cell lithium-ion/polymer batteries. The MAX17330 implements Maxim Integrated's ModelGauge m5 EZ fuel gauge algorithm without requiring host interaction for configuration, which makes the MAX17330 an excellent charger, protector, and fuel gauge. Using AccuCharge charger technology, the MAX17330 charges the battery with programmable voltage and current based on measured temperature and battery state using a configurable profile of voltage and current based on temperature and cell voltage. The MAX17330 monitors the voltage, current, temperature, and state of the battery to ensure that the lithium-ion/polymer battery is operating under safe conditions to prolong the life of the battery. Voltage of the battery pack is measured at the BATT connection. Current is measured with an external sense resistor placed between the CSP and CSN pins. Power and average power are also reported. An external NTC thermistor connection allows the IC to measure the temperature of the battery pack by monitoring the TH pin and optionally calculate the temperature of the FET with the ZVC/TH2 pin. The TH/TH2 pins provides an internal pull-up for the thermistor that is disabled internally when temperature is not being measured. Internal die temperature of the IC is also measured and can be a proxy for the protection/charge FET temperature if it is located close to the IC, or used with the TH2 thermistor to calculate the FET temperature if located further from the IC. The MAX17330 controls charging in current, voltage, temperature, and power limit modes. Each of these limits is set in non-volatile memory, and the battery is charged at the highest rate within these limits. The voltage and current are adjusted over temperature to comply with the 6 zone JEITA temperature settings and with 3 zone step-charging based on the battery voltage. For additional functionality, see the Charger section. The MAX17330 scales the charging current based on the sense resistor, making it well suited to many types of batteries, ranging from less than 10mAh in wearable applications to greater than 10,000mAh in parallel packs or large capacity applications. The MAX17330 provides programmable discharge protection for overdischarge currents (fast, medium, and slow protection), overtemperature, and undervoltage. The IC also provides programmable charge protection for overvoltage, over/undertemperature, overcharge currents (fast and slow), charge done, charger communication timeout, and overcharge capacity fault. The IC provides ideal diode discharge behavior even while a charge fault persists. The IC provides programmable charging current/voltage prescription following JEITA temperature regions as well as stepcharging. The MAX17330 provides additional protection to permanently disable the battery by overriding a secondary protector or blowing a fuse in severe fault conditions. This is useful when the IC has detected FET failure and is unable to block charge/discharge any other way. Additional functionality is described in the Protector section. The ModelGauge m5 EZ algorithm combines the short-term accuracy and linearity of a coulomb counter with the longterm stability of a voltage-based fuel gauge, along with temperature compensation to provide industry-leading fuelgauge accuracy. Additionally, the algorithm does not suffer from abrupt corrections that normally occur in coulombcounter algorithms since tiny continual corrections are distributed over time. The MAX17330 automatically compensates for aging, temperature, and discharge rate and provides accurate state of charge (SOC) in milliampere-hours (mAh) or percentage (%) over a wide range of operating conditions. Fuel gauge errors always converge to 0% as the cell approaches empty. Dynamic power functionality provides instantaneous maximum battery output power which can be delivered to the system without violating the minimum system input voltage. The IC provides accurate estimates of timeto-empty and time-to-full and provides three methods for reporting the age of the battery: reduction in capacity, increase in battery resistance, and cycle odometer. In addition, age forecasting allows the user to estimate the expected lifespan of the cell. To prevent battery clones, the IC integrates SHA-256 authentication with a 160-bit secret key. Every IC also incorporates a 64-bit unique identification number (ROM ID). Additionally, up to 122 bytes of user memory (NVM) can be made available to store custom information. The IC supports three low-power modes: undervoltage shutdown (0.1μA), deepship (0.1μA or 0.5μA), and ship (8μA). The IC can enter these low-power modes by command, communication collapsed (if enabled), or undervoltage shutdown. The IC can wake up from these low-power modes by communication, charger detection, or pushbutton wakeup (if enabled and installed). Pushbutton wakeup disconnects the battery from the system during shipping, yet wakes up immediately upon the user pressing the button so the user does not need to plug in a charger. www.analog.com Analog Devices | 29 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector Communication to the host occurs over a standard I2C interface. SCL is an input from the host, and SDA is an open-drain I/O pin that requires an external pullup. The ALRT pin is an output that can be used as an external interrupt to the host processor if certain application conditions are detected. Charge Control Lithium-ion/polymer batteries are very common in a wide variety of portable electronic devices because they have very high energy density, minimal memory effect, and low self-discharge. However, care must be taken to avoid overheating or overcharging these batteries to prevent damage to the batteries, potentially resulting in dangerous outcomes/explosive results. By operating in safe temperature ranges, at safe voltages and under safe current levels, the overall safety of the lithium-ion/polymer batteries can be assured throughout the life of the battery. Using AccuCharge technology, the MAX17330 controls the charging voltage and current dynamically based on the JEITA charge profile, step-charging, battery temperature, and temperature of the charging FET. The charge current is reduced at low battery voltage (prequal), low and high temperature, or when the charging FET is at a temperature or power dissipation limit. Figure 1 shows the typical charge profile through the operating range of a battery. MAX17330 has several regulation and control options, shown in the following list. ● Autonomous Charger with non-volatile configuration. ● Constant Current Regulation Configurable in 10mA steps, 350mA to 2560mA (with a 10mΩ sense resistor), with 1% accuracy. Scalable with sense resistor for larger or smaller currents and batteries. See Table 13. ● Constant Voltage Regulation Configurable in 5mV steps from 3.56V to 4.835V with 0.2% accuracy. ● Constant Power Regulation MAX17330 measures the pack and battery voltage, as well as charging current to calculate the power in the FET and sense resistor. The IC regulates heat with a configurable threshold (scalable with sense resistor). ● Temperature Regulation The IC regulates the FET temperature to a configurable threshold. ● Supplement Mode quickly supported with ideal diode. ● Parallel Cell Management including cross-charge blocking. ● Zero Volt Charging/Blocking and Battery Prequalification. Table 1 and Table 2 show an example of the charge profile with step charging and JEITA profile changing the target charge current and charge voltage. See nIChgCfg, nVChgCfg, nStepChg, and nTPrtTh1, nTPrtTh2, nTPrtTh3 for configuration details. Table 1. Charging Current with Step Charging and JEITA TEMPERATURE TOO COLD COLD ROOM WARM HOT TOO HOT 55°C Step 2 No Charging 0.19C 0.25C 0.22C 0.15C No Charging Step 1 No Charging 0.38C 0.5C 0.44C 0.31C No Charging Step 0 No Charging 0.75C 1C 0.88C 0.625C No Charging TOO HOT Table 2. Charging Voltage with Step Charging and JEITA TEMPERATURE TOO COLD COLD ROOM WARM HOT 55°C Step 2 No Charging 4.14V 4.2V 4.18V 4.16V No Charging Step 1 No Charging 4.1V 4.16V 4.14V 4.12V No Charging Step 0 No Charging 4.06V 4.12V 4.1V 4.08V No Charging www.analog.com Analog Devices | 30 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector BATTERY VOLTAGE DONE TOP-OFF RESTART FAST CHARGE (CV) DONE TOP-OFF FAST CHARGE (CV) FAST CHARGE (CC) STEP CHARGING OPTIONAL LOW-BATTERY PREQUALIFICATION CHARGING VOLTAGE ZERO-VOLT CHARGING STATES NOT TO SCALE. DRAWN WITHOUT STEP CHARGING. NO CONSTANT POWER OR CONSTANT TEMPERATURE MODES VRSTRT VPREQUAL VBATTMIN (2.16V) 0V BATTERY CHARGE CURRENT TIME CHARGING CURRENT IPQL ICHGTERM IZVC 0A CHARGER ENABLED TIME Figure 1. Li+/Li-Poly Charge Profile VBATTMIN: Minimimum operating voltage of MAX17330. If ZVC is used, the battery is charged through the external resistor and ZVC pin until the IC powers on. VPREQUAL: Enabled in nProtCfg. The battery is charged at a limited rate to check if it is safe to charge. Prequal Voltage and Current are set in nChgCfg0 register. Charging Voltage: The battery is charged to this terminal voltage. The voltage is set in the nVChgCfg register for room temperature and other temperatures. VRSTRT: Once the CHG FET turns off, the cell voltage drops over time as the cell relaxes. If the cell voltage drops below the restart threshold, the CHG FET turns on and brings the cell voltage up again. IZVC: Zero-Volt Charging current. See the Zero-Volt Charging section for details. ICHGTERM: The charger goes into top off mode after this current is reached. Top off ends based on a programmable timer. Set IChgTerm in the nIchgTerm register. IPQL: Prequal Charge Current. Set in nChgCfg0. Charging Current: Fast Charging current. The current is set in nIChgCfg register for room temperature and other www.analog.com Analog Devices | 31 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector temperatures. In Fast Charge CC state, the regulation current is adjusted by nStepChg. The charging current and voltage are configured by the Charging Calculation registers. See the Charging Calculation section below. The Power Limit, FET Temperature limit, and second thermistor configuration are set in the nChgCfg1 register. More details on each register are available in the Charging Registers section. Charging Calculation The MAX17330 calculates the safe charging voltage and charging current depending on the state of the battery and the temperature. The ChargingVoltage and ChargingCurrent registers provide the settings according to the charge profile, cell voltage, and cell temperature. This safe voltage and current, along with the power and temperature limits, are used to control the charge current to the battery. As the temperature of the battery changes significantly above and below room temperature, most cell manufacturers recommend charging at reduced current and lower termination voltage to assure safety and improve lifespan. The MAX17330 can be configured to change its charging when the temperature crosses the TooCold/Cold/Room/Warm/Hot/ TooHot programmable temperature thresholds (see nTPrtTh1/2/3). Both charging current and voltage are updated at Cold/Warm/Hot (see nVChgCfg and nIChgCfg). See Figure 8 and Figure 9. Additionally, the IC provides step-charging to improve lifespan of the battery and charge speed by applying a stepcharging profile (see the Step-Charging section) as shown in Figure 2. Step Charging A step-charging profile sets three charge voltages, three corresponding charge currents, and manages a state-machine to transit through the stages as shown in Figure 2. FULL VOLTAGE STEPVOLT1 STEPVOLT0 90% STEPCURR0 SOC 50% 30% CURRENT VC E LL STEPCURR1 SOC STEPCURR2 ICHGTERM IPREQUAL MEDIUM CURRENT HIGHEST CURRENT, LOWEST VOLTAGE PROTTMRSTAT.CHARGESTEP STAGE 0 VCELL > STEPVOLT0 STAGE 1 REDUCED CURRENT UNTIL FULL VCELL > STEPVOLT1 TIME STAGE 2 NOT CHARGING/DISCHARGING NOT CHARGING/DISCHARGING Figure 2. Step-Charging State Machine www.analog.com Analog Devices | 32 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector As a result, charging takes place in three stages: 1. Stage 0: Highest current, lowest voltage. ChargingCurrent comes from nIChgCfg until VCell > StepVolt0. After VCell > StepVolt0, ChargingCurrent becomes defined by Stage 1. 2. Stage 1: Medium current. ChargingCurrent comes from nIChgCfg x (StepCurr1 + 1)/16, which is a ratio from 1/16 to 16/16 until VCell > StepVolt1. When VCell > StepVolt1, ChargingCurrent becomes defined by Stage 2. 3. Stage 2: Reduced current until full. ChargingCurrent comes from nIChgCfg x (StepCurr2 + 1)/16, which is a ratio from 1/16 to 16/16 until full. For example, a charge can start with a ChargingCurrent of 2000mA until the cell voltage reaches 4.12V. At that point, the ChargingCurrent is reduced to 1000mA until the cell voltage reaches 4.16V. Then, the ChargingCurrent is further reduced to 500mA where it remains until the current begins to taper off naturally as the cell voltage is regulated at FullVoltage. Disconnecting the charge source, or discharging the battery causes the state-machine to return to Stage 0. Zero-Volt Charging When in undervoltage protection, the MAX17330 turns both FETs off and then enters a low quiescent state. After a long time in the undervoltage state, it is possible for the battery voltage to fall below the minimum 2.16V operating voltage, making it unable to wakeup by communications or pushbutton. In this situation, an external charge voltage must be applied to the system side positive node of MAX17330 (PCKP or SYSP) in order to wake up the IC. Zero-Volt Charge Recovery In the ZVC circuit configuration (connect ZVC/TH2 PCKP through a current-limiting resistor), even a battery at zero volts can be charged by applying a charger at PCKP. If a secondary protector is used, zero-volt charge recovery must be enabled. If a secondary protector is not used, ZVC/TH2 can be connected to GND, a second thermistor for FET Temperature measurement, or used as an auxiliary voltage measurement pin. Zero-Volt Charge current can be calculated as IZVC = (VPCKP - VZVCDROP)/RZVC as shown in Figure 3. RZVC must be selected to keep ZVC current below the 50mA rated limit for the ZVC/TH2 pin. N N PACK+ RSENSE RPCKP 1kΩ CHG DIS PCKP ZERO-VOLT RECOVERY CURRENT PATH RIN 10Ω BATT ZVC RZVC BATT+ Figure 3. Zero-Volt Charge Recovery End-of-Charge The IC stops charging the battery when the current falls below the IChgTerm register value while the VFSOC value is above the FullSOCThr register value. Once the End-of-Charge conditions are met and nDelayCfg.FullTmr delay is reached, the CHG FET is turned off. The IC rejects false end-of-charge events such as application load spikes or early charge source removal. When charge termination is detected, the device learns a new FullCapRep register value based on the RepCap register output. If the old FullCapRep value was too high, it is adjusted on a downward slope near the www.analog.com Analog Devices | 33 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector end-of-charge as defined by the MiscCfg.FUS setting until it reaches RepCap. If the old FullCapRep value was too low, it is adjusted upward to match RepCap. This prevents the calculated state-of-charge from ever reporting a value greater than 100%. See Figure 4. Charge termination occurs when all of the following conditions are met: • VFSOC > FullSOCThr • Current < IChgTerm • AvgCurrent < IChgTerm CHARGING • FullTimer Expired AVGCURRENT CURRENT ICHGTERM DISCHARGING 0mA CORRECT END-OF-CHARGE DETECTION AREA CASE 1: OLD FULLCAPREP TOO HIGH NEW FULLCAPREP CASE 2: OLD FULLCAPREP TOO LOW REPCAP Figure 4. FullCapRep Learning at End-of-Charge Charger Restart MAX17330 supports restart charging if the charge source is plugged in for an extended period. This allows topping off the battery for charge lost due to normal self discharge. In the Charge done state, the IC begins charging the battery when VFOCV falls below ChargeVoltage - dFullOCV - 10mV. Set nMiscCfg2.dFullOCV = 0 to disable this function. Parallel Battery Management The MAX17330 supports automation to manage parallel charging or discharging of multiple batteries and prevent one battery from charging the other (cross-charging) with the following features and benefits: ● Converge cell voltages faster with independent control www.analog.com Analog Devices | 34 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector • Priority to charge emptiest battery first • Priority to discharge fullest battery first • Charge and discharge in parallel once cell voltages converge ● Prevent cross-charge to optimize heat and dropout • Break-Before-Make Control • Charge Source Insertion: Discharge blocking applies before enabling charge. • Charger Source Removal: Charge blocking applies before enabling discharge. Set nPackCfg.ParEn = 1 to enable the Parallel Battery Management functionality. When enabled, a timeout automatically sequences charge/discharge blocking and enabling. The automatic charge-blocking feature allows the host to determine which battery must be charged first and charge only the battery that is selected. Automatic discharge blocking prevents batteries at a higher state from charging batteries at a lower state. ● To block discharging while allowing charging, set Config2.BlockDisEn = 1. ● Status.AllowChgB is internally set every 1.4s. Parallel Applications: ● Low-Power Parallel Charging (less than 500mA total). This application eliminates the USB-charge-controller IC. A 5V source, such as USB, connects directly (or by USB-switch) to the system as well as both packs. USB detection (such as BC1.2) is often not necessary since all generations of USB provide 500mA. Charging parallel batteries (multiple MAX17330 ICs) with greater than 500mA is not recommended without determining the source capability. The combined charging current should be limited to less than the source capability to prevent oscillations in charging current. Example: Two batteries each charging less than 250mA, the CHG FET heat is lower than 350mW across 99% of the charge curve, and less than 200mW for the majority of charging. During charging, a lithium battery exceeds 3.6V for 99% of the charge curve. Heat dissipated = 250mA x (5.0V - 3.6V) = 350mW. ● High-Power Parallel Charging (>500mA total). A USB-charger or other configurable DC-DC should deliver voltage about 50mV above the battery voltage. The charging source must operate as a voltage source. By operating near dropout, the MAX17330 has reduced heat in the charge MOSFET. In this application, charge currents beyond 2500mA are achievable. Host Responsibility (See the Appendix B: Parallel Cell Management Example): ● Declare the presence of charge source. Only the host has this knowledge. Repeatedly write STATUS = 0xFFDF (AllowChgB = 0). The IC automatically blocks charging if AllowChgB is not cleared repeatedly before the 1.4s timeout. After this timeout, all MAX17330 ICs revert to allow-discharge and block-charge state. ● Configure to prevent cross-charging. If cell voltages differ by more than 400mV, configure the higher voltage packs to block discharging. Note that the higher voltage pack resumes discharge when charge-source-presence is no longer indicated. • Determine if emptiest cell can support system load (3.3V, for example). Until lowest cell charges enough to support system loading, there is a risk of system crash while higher-voltage packs are denied discharge support. Cross-charging should be allowed/tolerated during the limited time associated with VCell less than 3.3V. • Block discharge on packs identified as cross-charging risk. Set Config2.BlockDis = 1. ● Manage DC-DC voltage setting (applications greater than 500mA). Use the dropout-alert and heat-alert of all MAX17330 ICs to decide to step DC-DC voltage up or down. Table 3. Parallel Management FET Logic PAREN BLOCKDIS ALLOWCHGB CHG FET DIS FET 0 x x NORMAL NORMAL 1 0 0 NORMAL NORMAL 1 0 1 (timeout) BLOCK READY NORMAL 1 1 0 NORMAL BLOCK READY 1 1 1 (timeout) BLOCK READY NORMAL www.analog.com Analog Devices | 35 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector In the BLOCK READY state, the CHG or DIS FET is ready to block and is turned off if charging or discharging current is observed. In the NORMAL case, the CHG/DIS FET is controlled by standard protection and charging control. Ideal Diode Behavior While the CHG FET is in the OFF state (CHG fault present) or in regulation mode (Charging), if a discharge current is requested from the battery, the MAX17330 provides automatic control to operate the CHG FET as a 30mV Ideal-Diode using a comparator for fast response. The CHG FET: ● Quickly turns on upon discharge detection ● Quickly turns off upon charge detection Upon discharge, the CHG FET is fully enhanced to prevent voltage drop when a comparator detects VPCKP < VBATT 30mV (typ). This prevents the 600mV voltage drop and associated heat during discharging. Upon charge, a current-sense comparator detects charging when the sense voltage exceeds 1mV (typ) and turns off the CHG FET. The MAX17330 then decides whether or not to start or resume charging. Charge faults continue to block charging. If there are no faults, the MAX17330 starts or resumes regulated charging. See Figure 5. The ideal diode operates during discharge as well as charge regulation. During charge regulation, the system can briefly and repeatedly overload the charge source, demanding the battery to briefly support a load pulse. The charging regulation is paused until the load pulse finishes, and the MAX17330 resumes charging regulation. N CSN CSP CHG N BATT+ SYS+ DIS CHARGE CURRENT DETECTION CHG CONTROL BATT MAX1733x SUPPLEMENT COMPRARATOR Figure 5. Supplement and Charging Comparators The IC uses these comparators combined with additional information to detect charger presence and absence. During discharge, any charge faults, such as overvoltage fault or overtemperature fault, are preserved. The CHG FET is turned on fully to allow discharging and returned to the OFF state when a charger is detected. See Figure 6. www.analog.com Analog Devices | 36 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector (VPCKP – VBATT)*> + 30mV AvgCurrent* > +1.4mA * ADC MEASUREMENTS 10m RSENSE Current* > +7.5mA CC COMPARATOR (VCSP-VCSN) > +180mA CHARGE SOURCE PRESENT CHARGE SOURCE ABSENT IsDis = 0 , CHG = AUTO IsDis = 1, CHG = AUTO CHG FET AUTOMATION: * CHARGE REGULATION * FULL-ENHANCEMENT UPON DISCHARGE * CHG OFF DURING PROTECTION CHARGE REGULATOR DISABLED IDEAL DIODE BLOCKS CHARGE AN DC nD REM HAR G ela yCf OVAL E SO COMPARATOR g ( U T 11. IMEO RCE 25s VPCKP - VBATT < - 30mV UT DE FAU Current* < -7.5mA +7.5mA LT) AvgCurrent* < -1.4mA +1.4mA +30mV WHILE CHARGING SEEK ABSENCE OF CHARGE-SOURCE CHARGE BLOCKING SEEK DISCHARGE EVIDENCE (PCKP – BATT)* < -30mV Figure 6. Charging and Discharging States ADC Measurements corresponding to Current, AvgCurrent, and PCKP enhance the accuracy of charger detection. The charge source removal timeout waits for 11.25s (configurable with nDelayCfg.ChgWDT) of charge source absence before turning off the charge regulation. This allows charging to quickly resume after many seconds of battery-supplement when the system load exceeds charge source current-limit. nProtMiscTh.CurrDet configures the previous current-detection thresholds, corresponding with ±1.4mA and ±7.5mA (on 10mΩ). Analog Devices recommends these settings which are optimized according to the ADC noise. Table 4. AvgCurrDet Threshold when using 10mΩ and Default nProtMiscTh.CurrDet = 7.5mA AVGCURRENT FILTER CONFIGURATION (nFilterCfg.nCurr) www.analog.com Analog Devices | 37 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector Table 4. AvgCurrDet Threshold when using 10mΩ and Default nProtMiscTh.CurrDet = 7.5mA (continued) 1 (0.7s) 2 (1.4s) 3 (2.8s) 4 (5.6s) 5 (11.25s) 6 (22.5s) 7 (45s) 8 (90s) 1.41mA 0.94mA 0.94mA 0.7mA Active (0.351s) 4.22mA 2.34mA 2.34mA 1.41mA (default) Hibernate (1.4s) 7.5mA 4.2mA 4.2mA 2.3mA 2.3mA 1.4mA 1.4mA 0.94mA Hibernate (2.8s) 7.5mA 7.5mA 7.5mA 4.2mA 4.2mA 2.3mA 2.3mA 1.4mA The fast responses in Table 4 correspond with the 0.351s ADC update rate. The more accurate slow responses correspond with the AvgCurrent filter delay configuration. Protector Simple protection schemes are available to protect a battery from exceeding the safe levels. These schemes include protection for overdischarge current, short-circuit current, overcharge current, undervoltage, and overvoltage. The next level of protection offers smart protection schemes which include protection for under OCV (SmartEmpty), long overdischarge current, overtemperature limits for charge and discharge, undertemperature charge limits, and chargedone protection. The MAX17330 provides all of these simple and smart protection schemes with programmable thresholds and programmable timer delays for each fault. The MAX17330 provides additional protection functionality beyond these schemes as follows: Discharging Protection Functionality: ● Overcurrent: (see nODSCCfg and nODSCTh) • Fast Short-Circuit (70μs to 985μs): The short-circuit comparator is programmable from 5.12mV to 158.72mV with delay programmable from 70μs to 985μs. • Medium (1ms to 15ms): The overdischarge current comparator is programmable from 2.55mV to 79.36mV with delay programmable from 1ms to 15ms. • Slow (351ms to 35s): Slow overdischarge protection is programmable from 0mV to 51.2mV in 0.2mV steps with delay programmable from 351ms to 35s (see nDelayCfg and nIPrtTh1). ● Overtemperature: • Hot (OTPD—Overtemperature Discharge): Discharge overtemperature (OTPD, see nProtMiscTh) is separately programmable from charge overtemperature (OTPC). OTPD is typically a higher temperature than OTPC, since charging while hot is more hazardous than discharging. OTPD is programmable in 1°C steps, with a programmable timer (see nDelayCfg). • Die-Hot: The MAX17330 measures die temperature as well as a thermistor's temperature. Since the IC is generally located close to the external FETs, the die temperature can indicate when the FETs are overheating. This separately programmable threshold (see nProtMiscTh) blocks both charging and discharging. • Permanent-Fail-Hot: When a severe overtemperature is detected, the fault is recorded into NVM and permanently disables the charge and discharge FETs and blows the three-terminal fuse if enabled. ● Too Cold Discharge: If enabled, the IC blocks discharging if the cell temperature is too low. It prevets discharge of a cell when cell impedance due to temperautre is too large to support the application load. ● Undervoltage (UVP): Undervoltage is protected by three thresholds: UVP (undervoltage protect), UVShdn (undervoltage shutdown), and UOCVP (under OCV protect—SmartEmpty). UOCVP provides a deep-discharge-state protection that is immune from load and cell impedance/resistance variations. Charging Protection Functionality: ● Overvoltage Protection (OVP): Overvoltage protection is programmable with 10mV resolution (see nOVPrtTh). Temperature-region dependent OVP protection is also provided for cold/room/warm and hot temperature regions (see nVChgCfg). OVP detection is debounced with a programmable timer (see nDelayCfg). An additional higher OVP permanent failure threshold is programmable, which records any excessive OVP into NVM and permanently blocks charging. ● Charge Temperature Protection: Temperature protection thresholds are debounced with a programmable timer (see nDelayCfg). www.analog.com Analog Devices | 38 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector • Hot (OTPC): Charging temperature protection is programmable with 1°C resolution (see nTPrtTh1) and 1°C hysteresis. • Cold (UTP): Charging is blocked at cold, programmable with 1°C resolution (see nTPrtTh1) and 1°C hysteresis. ● Overcharge-Current Protection: • Fast: Overcharge current is detected by a programmable hardware comparator and debounce timer between 0mV to 39.375mV and 1ms to 15ms thresholds. • Slow: A lower and slower overcharge current protection ensures that more moderate high currents do not persist for a long time. With a 10mΩ sense resistor, this is programmable up to 5.12A in 40mA steps, with an additional delay programmable between 0.35s and 22.5s. Additionally, with nNVCfg1.enJP = 1, this overcurrent protection threshold is modulated according to temperature region (see nIChgCfg). ● Charge-Done: If enabled, the IC blocks charge whenever charge termination is detected until discharging or charger removal is eventually detected. ● Charger-Communication Timeout: If enabled, the IC turns off the charge FET during charging if the host has stopped communicating beyond a timeout configurable from 11s to 3min. In systems which consult the battery for prescribing the charge current or charge voltage (especially to apply JEITA thresholds or step-charging), this feature is useful to protect against operating system crash or shutdown. ● Overcharge-Capacity Fault: If the feature is enabled and the charge session delivers more charge (coulombs) to the battery than the expected full design capacity, charging is blocked. This threshold is programmable as a percentage (see nProtMiscTh.QOvflwTh) beyond the design capacity. Other Faults: ● Nonvolatile CheckSum Failure: If enabled (nNVCfg1.enProtChkSm), the MAX17330 blocks charge and discharge when startup checksum of protector NVM does not match the value stored in nProtCfg2.CheckSum. Other Protection Functionality: ● Zero-Volt Charging: The IC is able to begin charging when the cell has depleted to 2.16V (ZVC disabled) or from 0V (ZVC enabled). See the Zero-Volt Charging section for more details. ● Overdischarge-Removal Detection: Following any overdischarge current fault, the IC tests for load removal by sourcing 30μA into PCKP after turning off the discharge FET. Load removal is detected when PCKP exceeds 1V. This low threshold is intentionally below the startup voltage of most ICs in order to allow active loads by external ICs while rejecting passive loads by resistors (short-circuit, failed components, etc.). ● Charger Removal Detection: Following any charge fault, the IC measures PCKP to detect the removal of the offending charger after turning off the charge FET. Charger removal is detected when PCKP falls below BATT nOVPrtTh.ChgDetTh or whenever discharge current is detected. ● Battery Internal Self-Discharge Detection: The IC measures the internal self-discharge of the battery that might indicate health or safety problems. The IC alerts the system or turns off the charge and discharge FETs when a leakage is detected above the configurable threshold. See the Battery Internal Self-Discharge section for more details. ● Ideal-Diode Control: During any charge fault, the charge FET turns on when a discharge current is detected. See the Ideal Diode section for more details. The discharge FET behaves the same way during discharge faults to block discharging, yet turns on during charging. This ideal diode behavior reduces the heat and voltage drop associated with the body diode during protection faults. Protection Fault Reporting: ● Protection Fault Status: Each charge and discharge fault state is latched in the ProtStatus register. When the fault is cleared, the corresponding bit is cleared. ● Protection Fault Alerts: The ProtAlrt register latches the status of any previous faults detected by the device. Once a fault is detected, the corresponding bit remains set until it is cleared by the host. Additionally, the Status.ProtAlrt bit is set when any ProtAlrt bit is set. ● Protection Fault Logging: The nFaultLog register also indicates which protection events happened during each history log period. Charging Regulation Registers: The ChargingVoltage and ChargingCurrent registers control and display the calculated target charging voltage and current. This includes the following information which is generally associated with a particular battery and can be stored in the battery with the MAX17330: www.analog.com Analog Devices | 39 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector ● Factory Recommended Charging Current and Voltage: This is useful when a system involves multiple battery vendors, swappable batteries, aftermarket batteries, or legacy system support. ● Charging Modifications According to Battery Temperature: Significantly above and below room temperature, most cell manufacturers recommend charging at reduced current and lower termination voltage to assure safety and improve lifespan. The MAX17330 modulates its settings according to TooCold/Cold/Room/Warm/Hot/TooHot programmable temperature regions (see nTPrtTh1/nTPrtTh2/nTPrtTh3). Both charging current and voltage are modulated at Cold/Warm/Hot, targeting lower than Room (see nVChgCfg and nIChgCfg). ● Step-Charging: A common practice to balance lifespan and charge speed is to apply step-charging profiles (see the Step-Charging section). The MAX17330 supports three programmable steps with programmable charge currents and voltages. At a high level, the MAX17330 protector has state machine as shown in Figure 7. Each charge and discharge fault state is latched in the ProtStatus register, where each fault obeys a separate instance of the state machine shown in Figure 7. Any single charge fault opens the charge FET to block charge current (charge faults are OR'd together). All charge faults must be released to allow charge to resume (charge fault release conditions are AND'd together). The behavior is similar for blocking discharge. CHARGE FAULT (OR’D) BLOCK CHARGE CHARGEGOOD = 0 ALLOW CHARGE CHARGEGOOD = 1 CHGEN = CHARGEGOOD OR DISCHARGING CHARGE FAULTS RELEASED (AND’D) DISCHARGE FAULT (OR’D) ALLOW DISCHARGE DISGOOD = 1 BLOCK DISCHARGE DISGOOD = 0 DISEN = DISCHARGEGOOD OR CHARGING DISCHARGE FAULTS RELEASED (AND’D) Figure 7. Simplified Protector State Machine The IC includes a write protection and a permanent locking function. The write protection prevents accidental overwrites of protection parameters. This protection must be cleared before updating any registers and should be set after configuration changes are made. The permanent locks prevent intentional or malicious tampering and should be enabled after development is complete and the battery pack is ready to ship in production. See the Memory Locks and Write Protection section for more details. www.analog.com Analog Devices | 40 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector The protector registers are summarized by their protection function in Table 5 and are graphically shown across the various temperature ranges in Figure 8 and Figure 9. Table 5. Summary of Protector Registers by Function FUNCTION REGISTER VOLTAGE THRESHOLDS Permanent Fail Overvoltage Protection Overvoltage Protection nOVPrtTh nVChgCfg, nOVPrtTh Overvoltage Protection Release nOVPrtTh UnderOCV Protection nUVPrtTh Undervoltage Protection nUVPrtTh Undervoltage Shutdown nUVPrtTh Prequalification Voltage nChgCfg0 CURRENT THRESHOLDS Fast Overcharge Protection nODSCTh, nODSCCfg Slow Overcharge Protection nIPrtTh1 Slow Overdischarge Protection nIPrtTh1 Fast Overdischarge Protection nODSCTh, nODSCCfg Short Circuit Protection nODSCTh, nODSCCfg Charging Detected Discharging Detected Temperature Thresholds Fault Timers nProtMiscTh nProtMiscTh nTPrtTh1, nTPrtTh2, nTPrtTh3, nProtMiscTh nDelayCfg CHARGING REGULATION Charging Voltage nVChgCfg Charging Current nIChgCfg Precharge Current nOVPrtTh Step Charging Protection Status/Configuration www.analog.com nStepChg nProtCfg, ProtStatus, nBattStatus Analog Devices | 41 T4 (TOO HOT) T3 (HOT) T2 (COLD) 4.51V TWARM AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector T1 (TOO COLD) MAX17330 CELL VOLTAGE PERM FAIL OVP STEPV0 TOO COLD COLD 0 ROOM WARM 10 TEMPERATURE (°C) 40 3.7V DESIGN VOLTAGE 3.3V VEMPTY 2.92V UOCV PROTECTION 2.6V UV PROTECTION AND PREQUAL VOLTAGE 2.3V UV SHUTDOWN 4.2V (PACK VOLTAGE) HOT 45 JEITA CHARGING VOLTAGE STEPDV1 STEPV1 STEP-CHARGING STEPDV0 4.2V CHARGING VOLTAGE PERM FAIL OTP TOO HOT DISCHARGE 4.21V OVP RELEASE DIE TEMP HOT 4.25V OVERVOLTAGE PROTECTION STEPV2 STEPV1 STEPV0 TOO HOT 55 75 90 85 COLD ROOM WARM HOT CHARGING VOLTAGE 4.14V 4.2V 4.18V 4.16V STEPV1 4.1V 4.16V 4.14V 4.12V STEPV0 4.06V 4.12V 4.1V 4.08V MINIMUM OPERATING VOLTAGE Figure 8. Programmable Voltage Thresholds www.analog.com Analog Devices | 42 CHARGING CURRENT T3 (HOT) TWARM 3584mA FAST OVERCHARGE PROTECTION T4 (TOO HOT) AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector T2 (COLD) T1 (TOO COLD) MAX17330 STEPCURR1 STEPCURR2 DIE TEMP HOT TOO HOT DISCHARGE 1280mA CHARGING CURRENT PERM FAIL OTP 3000mA SLOW OVERCHARGE PROTECTION STEP-CHARGING CHARGING CURRENT STEPCURR1 STEPCURR2 TOO COLD COLD ROOM WARM HOT TOO HOT 3.5mA COLD ROOM WARM HOT PRECHARGE CHARGING CURRENT DISCHARGING CURRENT 7.5mA CURRDET -10 10 TEMPERATURE (°C) 35 -3000mA 45 60 70 75 80 0.75C 1C 0.88C 0.625C STEPCURR1 0.38C C/2 0.44C 0.31C STEPCURR2 0.19C C/4 0.22C 0.15C SLOW OVERDISCHARGE PROTECTION -4096mA FAST OVERDISCHARGE PROTECTION -5120mA SHORT-CIRCUIT PROTECTION Figure 9. Programmable Current Thresholds www.analog.com Analog Devices | 43 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector Battery Internal Self-Discharge Detection (ISD) A healthy lithium-ion/polymer battery has a very high coulombic-efficiency, typically greater than 99.9% (defined as discharge mAh vs. charge mAh). Some portion of the charge capacity can be lost by internal self-discharge. This includes natural aging, which is exacerbated if the battery stays at a high temperature and/or high state for long periods of time. However, in a damaged battery, additional capacity can be lost (unavailable for discharge), and some portion of this reflects permanent capacity loss. Unusual self-discharge in a lithium-ion/polymer battery might indicate health or safety problems. The MAX17330 internal self-discharge (ISD) detection feature measures battery leakage and provides the following functions: ● Leakage Measurement: The LeakCurrRep register outputs the milliampere leakage measured across several days and multiple charge termination events. • Accurate leakage detection • Low ppm false-positive rate at a 3mA threshold • Detection during normal use • No discharge depth or duration constraints • Requires at least four full events, each separated by 20 hours or more ● Leakage Log: Leakage measurements are recorded in the battery-life-logging data. This reveals leakage versus time for any returned battery or for managing deployed packs. ● Leakage Alert: If enabled, an LDET alert (see ProtAlrt) is asserted when LeakCurrRep exceeds the programmable alert threshold. ● Leakage Fault: If enabled, the protector disconnects the battery when LeakCurrRep exceeds the programmable fault threshold. www.analog.com Analog Devices | 44 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector Example of Internal Self-Discharge Detection Figure 10 shows the current leakage detected by the MAX17330 as a result of placing a 909Ω resistor across a cell to emulate a battery with internal self-discharge over various temperatures. Figure 10. Example of Internal Self-Discharge with Temperature Variation Configuring ISD Contact Maxim Integrated for configuring the ISD Feature. See the Battery Internal Self-Discharge Registers section for configuration details. Protector Thresholds The MAX17330 provides a variety of programmable protector thresholds that are stored in nonvolatile memory. These thresholds include voltage, current, temperature, and timer delays. Voltage Thresholds All voltage thresholds of the MAX17330 are shown graphically in Figure 8 and in table form with details of which bits and registers create the various thresholds in Table 6. The description of each register provides additional guidance for selection of the register value. www.analog.com Analog Devices | 45 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector Table 6. Voltage Thresholds NAME DESCRIPTION Permanent Fail Overvoltage Programmable overvoltage at each JEITA band. Programmable 10mV resolution from 3.9V to 4.88V. Programmable delay. Overvoltage (with 4xJEITA) CONFIGURATION REGISTERS EXAMPLE nOVPrtTh.OVPPermFail 4.4V ChargeVoltage[temp] + nOVPrtTh.dOVP (4.1V/ 4.20V/ 4.18V/ 4.15V) +50mV Overvoltage Release Programmable release hysteresis Overvoltage nOVPrtTh.dOVPR (4.15V/ 4.25V/ 4.23V/ 4.2V) -10mV ChargeVoltage-Room ChargingVoltage() output nVChgCfg.Room 4.20V ChargeVoltage-Hot ChargingVoltage() output nVChgCfg.Hot 4.15V ChargeVoltage-Warm ChargingVoltage() output nVChgCfg.Warm 4.18V ChargeVoltage-Cold ChargingVoltage() output nVChgCfg.Cold 4.10V DesignVoltage For information only, no action nDesignVolt 3.7V EmptyVoltage For fuel gauge only (not related to protection) nVEmpty 3.0V Undervoltage Release Charger applied Under OCV Protection (SmartEmpty) Programmable under-OCV 40mV steps UVP to UVP + 1.28V. nUVPrtTh.UOCVP 3.2V Undervoltage Protection Programmable undervoltage 20mV steps 2.2V to 3.4V. Gauging and communications work until undervoltageshutdown nUVPrtTh.UVP 2.7V Undervoltage Shutdown Gauging and communications work until undervoltageshutdown nUVPrtTh.UVShdn 2.5V Undervoltage Lockout 2.11V typ, 2.16V max Zero-Voltage Charging 0V Current Thresholds All of the current thresholds of the MAX17330 are shown graphically in Figure 9 and in table form with details of each threshold in Table 7. The description of each register provides additional guidance for selection of the register value. Table 7. Current Threshold Summary CURRENT ACTION Overcharge Current (fast) CHG off Overcharge Current (slow with 4xJEITA) CHG off Overdischarge Current (fast) DIS off Overdischarge Current (slow) DIS off Short-Circuit Current DIS off www.analog.com RELEASE Discharging or charger removal detection Charging or load removal detection DETAILS Threshold 5-bit, 1.25mV steps to 38.75mV. Delay programmable 4-bit, 1ms to 15ms in 0.9ms steps. Programmable 0.4mV steps to 51.2mV. Delay programmable 351ms to 45s. Separate thresholds for 4 out of 6 JEITA segments. 5-Bit, 2.5mV steps to 77.5mV. Delay programmable 4-bit, 1ms to 15ms in 0.9ms steps. Programmable 0.4mV steps to 51.2mV. Delay programmable 351ms to 45s. 5-Bit, 5mV steps to 155mV. Delay programmable 4-bit, 70μs steps to 985μs. Analog Devices | 46 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector Table 7. Current Threshold Summary (continued) Charging Detected Discharging Detected Normal Normal — Current > CurrDet or AvgCurrent > AvgCurrDet or PCKP > BATT + 0.15V to release overdischarge protection. — Current < -CurrDet or AvgCurrent < -AvgCurrDet or PCKP < BATT + 0.15V (falling-edge) indicates discharging. When discharging is detected, overcharge current faults release. Other charge faults such as OVP, OTP, and UTP remain set, however the CHG FET turns on to prevent the heat and voltage drop associated with the 0.6V CHG FET body diode. See the Ideal Diode Behavior section for more details. An OVP fault remains remembered (unreleased) until voltage falls and discharging is also detected. Overcurrent Protection The MAX17330 provides three levels of protection for overdischarge current events: fast, medium, and slow as shown in Figure 11. The MAX17330 also provides fast and slow levels of protection for overcharge current protection. The fast and medium levels of protection are provided by comparators and the slow levels are based on the ADC readings. The MAX17330 maintains the protection until the source of the fault has been removed. Overcharge protection fault releases when pack voltage falls below BATT + 0.1V (edge, not level) while the IC tests charger removal by applying a 40kΩ pull down from PCKP to GND (during any charger fault). Overdischarge current (fast or slow) or short-circuit current protection faults release when PCKP rises above 1V, while the IC applies a 30μA source current test to PCKP. SHORT-CIRCUIT THRESHOLD FAST MEDIUM SLOW (MICROSECONDS) (MILLISECONDS) (SECONDS, WITH 1% ACCURACY) OVERDISCHARGE THRESHOLD NODSCTH.ODTH (0-77.5mV) ADC OVERDISCHARGE THRESHOLD NDELAYCFG.OVERCURRTIMER (0.351s to 22.5s) OVERDISCHARGE DELAY NODSCCFG.ODDLY (1.05ms - 14.66ms) ADC OVERCURRENT DELAY NIPRTTH1.ODCP (0-51.2mV) SHORT-CIRCUIT DELAY NODSCCFG.SCDLY (131µs TO 985µs) DISCHARGE CURRENT NODSCTH.SCTH (0-155mV) DEBOUNCE TIME Figure 11. Fast, Medium, and Slow Overdischarge Protection www.analog.com Analog Devices | 47 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector Fast Overcurrent Comparators The MAX17330 contains three programmable fast overcurrent comparators called Overdischarge (OD), Short-Circuit (SC), and Overcharge (OC) that allow control protection for overdischarge current, short-circuit current, and overcharge current. These comparators have programmable threshold levels and programmable debounced delays. See Figure 12. The OD comparator threshold can be programmed from 0mV to -77.5mV with 2.5mV resolution (0A to -7.75A with 0.25A resolution using 10mΩ sense resistor). The OC comparator threshold can be programmed from 0mV to 38.75mV with 1.25mV resolution (0A to 38.75A with 0.125A resolution using a 10mΩ sense resistor). The OD and OC comparators have a programmable delay from 1.05ms to 14.6ms with 0.97ms resolution. The SC comparator threshold can be programmed from 0mV to -155mV with 5mV resolution (0A to -15.5A with 0.5A resolution using a 10mΩ sense resistor) and has a programmable delay from 70μs to 985μs with a 61μs resolution. The nODSCTh register sets the threshold levels where each comparator trips. The nODSCCfg register enables each comparator and sets their debounce delays. The nODSCCfg register also maintains indicator flags of which comparator has been tripped. These register settings are maintained in nonvolatile memory if the nNVCfg1.enODSC bit is set. Slow Overcurrent Protection The MAX17330 provides programmable thresholds for the slow overdischarge current protection (ODCP) and overcharge current protection (OCCP). ODCP and OCCP can be configured to provide different levels of protection across the six temperature zones as shown in Figure 9. Overcurrent Comparator Diagram + SCTH - OCTH + SCDLY - OCDLY OCi SCi ODSCCfg + ODTH OCDLY - ODi CSN CSP RSENSE Figure 12. Overcurrent Comparator Diagram Temperature Thresholds The six temperature zones shown in Figure 8 and Figure 9 can be configured in the nTPrtTh1, nTPrtTh2, and nTPrtTh3 registers. Other Thresholds The MAX17330 also supports additional thresholds for suspending/releasing charge, detecting permanent failures of the charge and discharge FETs, and providing the recommended charging prescription as described in Table 8. www.analog.com Analog Devices | 48 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector Table 8. Other Thresholds THRESHOLD ACTION CONDITIONS Charge Suspend CHG off FullDet Fault—if enabled (nProtCfg.FullEn) and charge termination criteria (see ICHGTerm and charge termination). ChgWDT Fault—if enabled (nProtCfg.ChgWDTEn) and communications timeout. Charge-Suspend Release Normal FullDet Release—Discharge or charger removal detected. ChgWDT Release—Communications or discharge or charger removal detected. Charge FET Failure Blow fuse CHG off yet charge-current persists (programmable). Discharge FET Failure Blow fuse DIS off yet discharge-current persists (programmable). Charge Voltage/Current "Prescription" Six-zone JEITA (four charge currents and voltages). Permanent Failure The IC supports several types of faults which result in a permanent failure. When any enabled permanent failure is detected, both FETs turn off and remain off regardless of power-cycling. Upon permanent failure detection, the IC records the permanent failure status into nonvolatile nBattStatus. Furthermore, the PFAIL output drives high to either drive an external fuse or latch a secondary protector. This action is useful when a FET failure is detected since charge and discharge can not be blocked in any other way. The following permanent failure faults are supported whenever permanent failures are enabled (nProtCfg.PFEn = 1) and the condition persists longer than the Permanent Fail debounce timer (nDelayCfg.permFailTimer). When any permanent failure fault is detected, the nBattStatus.PermFail bit is set in addition to the specific fault bit (also in nBattStatus), and both FET drivers are put in the off state. ● CHG/DIS FET open/short Failures: Enable/disable this feature by configuring nProtCfg.FetPFEn. • DIS FET Shorted: If DIS = Off and discharging is detected, nBattStatus.DFETFs is set and written to NVM. • CHG FET Shorted: If CHG = Off and charging is detected, nBattStatus.CFETFs is set and written to NVM. • FET Open Failure: For either of the following detection methods, the cause of an open can not be distinctly attributed to specifically either the CHG or DIS FET. • Detected By Discharge Fail: If DIS = On and PCKP = Low and discharge current isn't detected, nBattStatus.FETFo is set and written to NVM. • Detected By Charge Fail: If CHG = On and DIS = On and PCKP > BATT + nOVPrtTh.ChgDetTh and charge current isn't detected, nBattStatus.FETFo is set and written to NVM. ● Severe Over-Voltage Failure: If VCell exceeds nVPrtTh2.OVP_PermFail, nBattStatus.OVPF is set and written to NVM. Disable by configuring OVP_PermFail to the maximum value of 5.12V (0xFF__). ● Severe Over-Temperature Failure: If Temp exceeds nTPrtTh3.TpermFailHot, nBattStatus.OTPF is set and written to NVM. Disable by configuring OTP_PermFail to the maximum value of 127degC (0x7F__). ● Nonvolatile Protector Checksum Failure: If enabled (nNVCfg1.enProtChkSum), during startup a checksum of the protector configuration is calculated and compared against the nChkSum register. If the value mismatches, nBattStatus.ChkSumF is set. www.analog.com Analog Devices | 49 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector Disabling FETs by Pin-Control or I2C Command The IC provides FET override control by either I2C command or pin command to the ALRT pin. This functionality can be useful for various types of applications: ● Factory Testing: Disconnecting the battery is useful for testing with a controlled external power supply. ● Battery Selection: In a multiple-battery system, one battery can be disconnected and another connected by operating the FETs. When allowed by nonvolatile configuration, both FETs can be turned off by pin control or either FET can be individually turned off by I2C command. The control operates as follows: ● ALRT Pin Override: Set nProtCfg.OvrdEn = 1 and drive ALRT low to force both FETs into the off state. Releasing the ALRT line recovers the FETs according to the protector's fault state machine. ● I2C Command Override: Set nProtCfg.CmOvrdEn = 1 and write CommStat.CHGOff or CommStat.DISOff to independently disable either the charge or discharge FET. Clearing CHGOff and DISOff recovers the FETs according to the protector's fault state machine. These features can be disabled and locked by nonvolatile memory to prevent malicious code from blocking the FETs. Although disabling FETs does not produce any safety issues, it can be a nuisance if malicious system-side software denies power to the system. Fuel Gauge ModelGauge m5 EZ Algorithm Classical coulomb-counter-based fuel gauges have excellent linearity and short-term performance. However, they suffer from drift due to the accumulation of the offset error in the current-sense measurement. Although the offset error is often very small, it cannot be eliminated, causes the reported capacity error to increase over time, and requires periodic corrections. Corrections are usually performed at full or empty. Some other systems also use the relaxed battery voltage to perform corrections. These systems determine the true state-of-charge (SOC) based on the battery voltage after a long time of no current flow. Both have the same limitation; if the correction condition is not observed over time in the actual application, the error in the system is boundless. The performance of classic coulomb counters is dominated by the accuracy of such corrections. Voltage measurement-based SOC estimation has accuracy limitations due to imperfect cell modeling but does not accumulate offset error over time. The IC includes an advanced voltage fuel gauge (VFG) which estimates OCV even during current flow and simulates the nonlinear internal dynamics of a Li+ battery to determine the SOC with improved accuracy. The model considers the time effects of a battery caused by the chemical reactions and impedance in the battery to determine SOC. This SOC estimation does not accumulate offset error over time. The IC performs a smart empty compensation algorithm that automatically compensates for the effect of temperature condition and load conditions to provide accurate stateof-charge information. The converge-to-empty function eliminates error toward an empty state. The IC learns battery capacity over time automatically to improve long-term performance. The age information of the battery is available in the output registers. The ModelGauge m5 EZ algorithm combines a high-accuracy coulomb counter with a VFG. See Figure 13. The complementary combined result eliminates the weaknesses of both the coulomb counter and the VFG while providing the strengths of both. A mixing algorithm weighs and combines the VFG capacity with the coulomb counter and weighs each result so that both are used optimally to determine the battery state. In this way, the VFG capacity result is used to continuously make small adjustments to the battery state, canceling the coulomb-counter drift. www.analog.com Analog Devices | 50 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector COULOMB COUNTER ModelGauge Δ% SOC VERY SLOW INFLUENCE ΔQ MICROCORRECTIONS CAPACITY FULL, EMPTY, AND STANDBY STATE DETECTION UNNECESSARY Figure 13. Merger of Coulomb Counter and Voltage Based Fuel Gauge The ModelGauge m5 EZ algorithm uses this battery state information and accounts for temperature, battery current, age, and application parameters to determine the remaining capacity available to the system. As the battery approaches the critical region near empty, the ModelGauge m5 EZ algorithm invokes a special error correction mechanism that eliminates any error. The ModelGauge m5 EZ algorithm continually adapts to the cell and application through independent learning routines. As the cell ages, its change in capacity is monitored and updated and the voltage-fuel-gauge dynamics adapt based on cell-voltage behavior in the application. www.analog.com Analog Devices | 51 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector VOLTAGE OCV CALCULATION OCV TEMPERATURE COMPENSATION LEARN RELAXED CELL DETECTION OCV OUTPUT OCV TABLE LOOKUP COULOMB COUNTER % REMAINING OUTPUT mAH OUTPUT CURRENT TIME × CAPACITY LEARN mAh PER PERCENT EMPTY DETECTION MIXING ALGORITHM mAH OUTPUT MIXCAP REGISTER MIXSOC REGISTER EMPTY COMPENSATION LEARNING APPLICATON EMPTY COMPENSATION BASED ON APPLICATION TEMPERATURE AND DISCHARGE RATE + - + END OF CHARGE DETECTION APPLICATION OUTPUTS: REPSOC REGISTER REPCAP REGISTER AVSOC REGISTER AVCAP REGISTER TTE / AtTTE / TTF REGISTERS FULLCAP REGISTER CELL CHEMISTRY OUTPUTS: VFOCV REGISTER CYCLES REGISTER RFAST REGISTER FULLCAPNOM REGISTER AGE REGISTER Figure 14. ModelGauge m5 EZ Block Diagram www.analog.com Analog Devices | 52 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector Wakeup/Shutdown Modes of Operation The MAX17330 supports six power modes (three active modes and three shutdown modes) as shown in Table 9 with descriptions of the features available in each mode, the typical current consumption of each mode, and the method to enter and exit each mode. Table 9. Modes of Operation MODE CONSUMPTION (TYPICAL) (μA) DESCRIPTION 28 Full Functionality. The Protection FETs, charge pump, and ADC are on. Tasks execute every 351ms. 21 FETs, charge pump, and ADC are on. Tasks execute every 1.4s. If enabled, the the device automatically enters and exits this mode depending on current measurements. Entering hibernate mode requires a low-enough current for a long-enough duration. Exiting requires just one high-enough current event. For specific details regarding the thresholds, see nHibCfg register definition. 11 ADC is on. The FETs and charge pump are disabled due to a protection fault, disconnecting the battery from the system. RAM is preserved and the gauge continues to monitor the battery. Firmware remains awake and ready to communicate or enable the battery. Firmware executes every 1.4s. 11 Similar state as "Protected and Awake" except the firmware is responsive to wakeup events such as: charger-connection, communications-wakeup, or pushbutton wakeup (depending on which wakeups are enabled by configuration). Firmware executes every 1.4s. See nHibCfg. 8 Similar state as "Protected and Awake" except the firmware is responsive to wakeup events such as: charger-connection, communications-wakeup, or pushbutton wakeup (depending on which wakeups are enabled by configuration). Firmware executes every 5.625s. See nHibCfg. DeepShip1* 0.5 FETs, charge pumps, ADC, and firmware are all placed into a shutdown state. The only activity alive relates to analog circuits that monitor for wakeup conditions (charger-detection, communications, or pushbutton, depending on which are enabled). DeepShip2* / Undervoltage Shutdown 0.1 FETs, charge pumps, ADC, firmware, and most wakeup circuits are powered down. Only the charger-detection wakeup circuit remains powered in this mode to best conserve the small remaining battery capacity and prevent deep discharge. Active Hibernate (optional) Protected and Awake Ship* *When an I2C SHIP command (setting Config.SHIP = 1) or I2C SCL/SDA lines collapse (and depending on whether COMMSH is enabled), the MAX17330 either enters Ship (if nProtCfg.DeepShpEn = 0) or DeepShip1 (if nProtCfg.DeepShpEn = 1) or DeepShip2 according to the configuration. www.analog.com Analog Devices | 53 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector Table 10. MAX17330 Ship Modes 8μA Ship 0.5μA DeepShip1 0.1μA DeepShip2 0.1μA UVShdn ENTER WAKEUP Config.Ship I2C, Pushbutton, or Charge Source or SDAcollapse FUNCTIONALITY nProtCfg. DeepShipEn nProtCfg. DeepShip2En 5.6s Measurements/ Updates 0 0 1 0 1 1 — — No updates Charge Source Only VCell < UVShdn The MAX17330 can be woken up with a variety of methods depending on the configuration. If pushbutton wakeup is enabled (nConfig.PBen = 1), then consistently pulling the ALRT/PIO pin low, either by pushbutton or system configuration, wakes up the device. A high-to-low transition on any of the communication lines wakes up the device. A consistent connection to a charge source wakes up the device. The MAX17330 prevents accidental wake-up when the system is boxed and shipped. When woken up by any source, it debounces all wake-up sources (button, communications, and charger-detection) to ensure that the wake-up is valid. If no valid wake-up is discovered, the device returns to Ship or DeepShip. The IQ in the active, hibernate, and ship modes are impacted by the configuration of the IC. Table 11 shows the recommended configuration settings for the nConfig register and the impact those settings have on the IQ of each mode. Note that when in hibernate mode, the protection for overtemperature and overvoltage are delayed by the nHibCfg.HibScalar value. It is not recommended to have hibernation enabled with the nHibCfg.HibScalar set to more than 1.4 seconds. Table 11. Recommended nHibCfg Settings and the Impact on IQ FETSOFF FETS-ON MODES nHibCfg SHIP IQ (μA) ACTIVE/ HIBERNATE IQ (μA) ACTIVE (s) SHIP (s) 1.4s Ship 0x0909 11 28/NA 0.351 1.4 1.4s Ship + Hibernate 0x8909 11 28/21 0.351 1.4 5.625s Ship 0x090B 8 28/NA 0.351 5.625 AVAILABLE LOW POWER CONFIGURATION UPDATE RATE NOTES Overtemperature and overvoltage detection is delayed by 1.4s when in hibernate mode. Power Mode Transition State Diagram Figure 15 illustrates how the device transitions in and out of all of the possible power modes of operation of the device. www.analog.com Analog Devices | 54 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector POWER GOOD STARTUP C OR HGD BU ET TTO OR N ( COM IF E NA MS BLE D) WAKEVERIFY: Any of the following confirm legitimate wakeup: 1) ALRT/PIO consistantly low (if feature enabled) 2) Communications (high+low detected) 3) Charger consistently detected NO W AKEU WAKEVERIFY CH OR B GDET O UTT R CO ON (IF E MMS NAB LED ) CH GD ET HW STARTUP PS VE RIFIE D WAKEUP VERIFIED ACTIVE (28µA) OR HIBERNATE (21µA) EITHER FET ON IF (FETS OFF) PROTECT (11µA) SHIP (8µA/11µA) 0 1 DEEPSHIP (0.5µA) HW UVSHDN (0.1µA) UV NPROTCFG.DEEPSHIPEN SHDN COMMITTED ANY SHUTDOWN CONDITION > TMR/2 FETS OFF, PKSINK =1 TIMER & PCKPOK SHUTDOWN CONDITIONS: Command, Comms-drop, or UV SHDNTimer counts upon condition, aborts (clears) upon absense of conditions. At half timer, the timer pauses unless charger is clearly absent (PckpOK = 0) Figure 15. Power Mode Transition State Diagram Pushbutton Wakeup The ALRT/PIO pin can be used to wake up the device by enabling the pushbutton wakeup function by setting the nConfig.PBen. The pushbutton can be implemented in the system to wakeup the device and the system as shown in the Pushbutton Schematic. www.analog.com Analog Devices | 55 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector Applications Information Component Selection MAX17330 has the following fixed components. These must remain the same in all designs. Voltage ratings listed are minimums. Higher ratings can be used, but should minimize derating on capacitors. The subscript denotes the pin name to which the component is connected. See the Typical Application Schematic for reference. Table 12. MAX17330 Standard Components VALUE MINIMUM RATING RBATT 10Ω — Must match RC time with RPCKP. Power rating should be sized with RZVC. If Zero-Volt charging is not used, use 1mA rating. CBATT 0.1μF 5V Must match RC time with CPCKP. RPCKP 1kΩ — Low Current. RC time matching is helpful for supplement mode detection. CPCKP 1nF 10V CCP 0.1μF 10V CREG2 0.47μF 5V RCHG 100Ω — CCHG 22nF — RDIS 1kΩ — COMPONENT NOTES This node can be exposed to higher voltage. Higher voltage capacitor can be used. Lower resistance can be used for faster DIS response. 0Ω is acceptable. Higher resistance increases FET Turn Off switching time. Sense Resistor Sense resistor selection is critical to MAX17330 operation. The charging and protection current range and resolution are defined by the sense resistor, as are the capacity range and resolution. Table 13 provides guidance for regulation current ranges based on the sense resistor. A current range should be selected for the Constant Current regulation. Termination Current can be below the charge current range. For managed DC-DC applications, the heat generated in the CHG/DIS FETs is significantly less, and smaller sense resistors and larger currents are allowed. For applications with fixed DC voltage input, larger thermal budget, and larger currents than the listed range are allowed, see Table 22 for maximum current range. For fixed DC applications, at low cell voltage, the MAX17330 might regulate in Constant Power mode until the cell voltage is high enough to enter CC mode. See Table 18 for heat limits. Table 13. Sense Resistor Selection CHARGE SOURCE RSENSE (mΩ) CHARGE CURRENT RANGE (mA) 2 1750 to 5712 Managed DC-DC or Switching Charger 5 700 to 5120 Managed DC-DC or Switching Charger 10 350 to 2560 5V or USB 10 350 to 1129 5V or USB 20 175 to 565 5V or USB 50 70 to 226 5V or USB 100 35 to 113 5V or USB 200 17.5 to 56 5V or USB 500 7 to 23 Managed DC-DC or Switching Charger www.analog.com Analog Devices | 56 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector Charging and Protection FETs After sense resistor selection, FET selection is the the next critical component choice for system design. The MAX17330 uses a voltage doubler charge pump as the input to the FET drivers. With this design, VGS for the CHG FET is always equal to VCell. The FET VTH must be low to allow it to turn on and regulate the FET from a low battery. VTH < 2V is recommended. VDS for the CHG FET (or VSS for dual FETs) must be set based on the application requirements. For pack side applicaiton with removable batteries, 12V is recommended and 20V is optional. For implementations where the battery is captive, or MAX17330 is installed on the system board, lower VDS (or VSS) is allowed but must meet the maximum charge source voltage. Power Dissipation is a critical function since the MAX17330 operates the FET in the Ohmic/Linear region. For FETs with lower power dissipation, the HeatLim of MAX17330 reduces charging current to keep the FET in the safe operating range. Good thermal rated FETs and PCB design is needed for maximum charging current. RDSON and package size can be other considerations for application purposes. They are not critical for MAX17330 operation. ESD and Optional Components Thermistors are optional, but recommended components on the MAX17330. See the nPackCFG.THCfg register subfield for details on how thermistors are used by the MAX17330. Table 97 lists common NTC thermistors with their associated Beta value and the nThermCfg value. Other thermistors can be used with the formula listed in Table 97, or by contacting Maxim Integrated. The Typical Application Schematic shows series resistors and Zener diodes on the ALRT, SDA, and SCL pins. For applications where these pins are exposed, adding some ESD protection is necessary. TVS diodes can be used instead of Zener diodes for stronger protection. 150Ω resistors have been tested with 4.7V Zener diodes to withstand ±8kV contact and ±16kV air discharge without damage to the IC. These components can be omitted for applications where the MAX17330 is installed on the system board. In application using multiple protection ICs where the secondary protector is connected between MAX17330 and the cell, RZVC must be populated. If the secondary protector blocks Zero-Volt charging, RZVC doesn't need an exact calculation and only provides current to wake the secondary protector if it is in a protected or shutdown state (use 100Ω for this application). For Zero-Volt charging, RZVC is calculated with the formula in the Zero-Volt Charging section. For applications with only the MAX17330 as the protector and no Zero-Volt charging, do not connect RZVC. Register Description Conventions The following sections define standard conventions used throughout the data sheet to describe register functions and device behavior. Any register that does not match one of the following data formats is described as a special register. Standard Register Formats Unless otherwise stated during a given register's description, all IC registers follow the same format depending on the type of register. See Table 14 for the resolution and range of any register described hereafter. Note that current and capacity values are displayed as a voltage and must be divided by the sense resistor to determine amps or amp-hours. It is strongly recommended to use the lower byte of nRSense (19Ch) register to store the sense resistor value for use by the host software. Table 14. ModelGauge Register Standard Resolutions REGISTER TYPE LSB SIZE MINIMUM VALUE MAXIMUM VALUE Capacity 5.0μVh/ RSENSE 0μVh 327.675mVh/ RSENSE Percentage 1/256% 0% 255.9961% 78.125μV 0V 5.11992V Voltage www.analog.com NOTES Equivalent to 0.5mAh with a 10mΩ sense resistor. 1% LSb when reading only the upper byte. — Analog Devices | 57 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector Table 14. ModelGauge Register Standard Resolutions (continued) REGISTER TYPE LSB SIZE MINIMUM VALUE MAXIMUM VALUE NOTES 1.5625μV/ RSENSE -51.2mV/ RSENSE 51.1984mV/ RSENSE Signed 2's complement format. Equivalent to 156.25μA with a 10mΩ sense resistor. Temperature 1/256°C -128°C 127.996°C Signed 2's complement format. 1°C LSb when reading only the upper byte. Resistance 1/4096Ω 0Ω 15.99976Ω — 5.625s 0s 102.3984hr — Power 8mW/RSENSE -262W/RSENSE 262W/RSENSE Special — — — Current Time Signed 2's complement format. Equivalent to 0.8mW with a 10mΩ sense resistor. Format details are included with the register description. Device Reset Device reset refers to any condition that would cause the IC to recall nonvolatile memory into RAM locations and restart operation of the fuel gauge. Device reset refers to initial power up of the IC, temporary power loss, or reset through the software power-on-reset command. Nonvolatile Backup and Initial Value All configuration register locations have nonvolatile memory backup that can be enabled with control bits in the nNVCfg0, nNVCfg1, and nNVCfg2 registers. If enabled, these registers are initialized to their corresponding nonvolatile register value after device reset. If nonvolatile backup is disabled, the register restores to an alternate initial value instead. See each register description for details. Register Naming Conventions Register addresses are described throughout the document as 9-bit internal values from 000h to 1FFh. These addresses must be translated to 8-bit external slave address and 8-bit register address. A leading '0' indicates the primary slave address (0x6C by default) should be used to read this register and a leading '1' indicates the secondary slave address (default 0x16) should be used to read this register. See the Memory section for details. Register names that start with a lowercase 'n', such as nPackCfg for example, indicate that the register is a nonvolatile memory location. Register names that start with a lower case 's' indicate the register is part of the SBS compliant register block. www.analog.com Analog Devices | 58 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector Charging Registers Charging Status and Configuration Registers ChgStat Register (0A3h) Register Type: Special The ChgStat register shown in Table 15 indicates the charger control mode. Table 15. ChgStat (0A3h) Format D15 D14 D13 D12 D11 D10 D9 D8 Dropout x x x x x x x D7 D6 x D5 D4 D3 D2 D1 D0 x x CP CT CC CV CC: Constant Current mode. Charging is controlled by ChargingCurrent register. CV: Constant Voltage mode. Charging is controlled by ChargingVoltage register. CP: Heat Limit. If the Pack+ voltage is adjustable, decrease the voltage to exit CP mode to increase charging speed. CT: FET Temperature limit. If the Pack+ voltage is adjustable, decrease the voltage to decrease FET temperature and increase charging speed. Dropout: Dropout Saturation Prevention. An alert is also generated on Status.CA whenever dropout is detected. If PACK+ voltage is adjustable, the application processor should increase the voltage to increase charging speed. When charging directly from USB, the MAX17330 attempts to charge at the current indicated in ChargingCurrent. If this exceeds the current limit of the USB charger, the USB output voltage drops and the MAX17330 enters Dropout mode. The USB output voltage increases as a function of the cell voltage and the dropout voltage until the battery reaches CV mode. The USB output voltage returns back to regulation as the battery current tapers closer to the termination current. nChgCfg0 Register (1C2h) Type: Special The nChgCfg0 register is shown in Table 16 and sets the Prequal voltage and current as well as Minimum System Voltage. Table 16. nChgCfg0 Register (1C2h) Format D15 0 D14 D13 D12 D11 nOCMargin D10 D9 D8 D7 PreQualVolt D6 D5 D4 D3 VSysMin D2 D1 D0 PreChgCurr PreQualVolt: Sets the Prequal voltage. Prequal Voltage = UVP + PreQualVolt x 20mV, PreQualVolt is a signed 2's compliment value with range of UVP - 320mV to UVP + 300mV. PreChgCurr: Sets the precharging current for the ChargingCurrent register. Precharge current is calculated as: PreChargeCurrent = nIChgCfg.RoomChargingCurrent x PreChgCurr / 128 with a range from RoomChargingCurrent / 128 to RoomChargingCurrent / 4. VSysMin: If the charge source is overloaded and is not able to hold the output voltage, Minimum System Voltage increases PACK+ voltage by keeping the DIS FET Off until cell voltage reaches VSysMin. The system minimum voltage is relative to nVempty and can be configured from nVempty to nVempty - 0.7V in 100mV steps. The recommended setting for VSysMin is 3.4V or lower, as this generates extra heat during charging. Set to 0 to disable this feature. nChgCfg1 Register (1CBh) Type: Special The nChgCfg1 register is shown in Table 17 and sets the heat and temperature parameters for the charger. Table 17. nChgCfg1 (1CBh) Format D15 D14 www.analog.com D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Analog Devices | 59 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector Table 17. nChgCfg1 (1CBh) Format (continued) 0 0 HeatLim 0 FETLim FetTheta HeatLim: Set HeatLim to limit the thermal dissipation in the protection FETs during prequal regulation. Set HeatLim from 51mW to 1581mW in 51mW steps with to 10mΩ RSENSE (Heat = I x V). The effective power-dissipation limit is (HeatLim) x 51mW. See Table 18 for other sense resistors. Table 18. HeatLim Range and Resolution for Different Sense Resistors SENSE RESISTOR (mΩ) MIN (mW) MAX (mW) STEP (mW) 102 5 102 3162 10 51 1581 51 20 25.5 790.5 25.5 50 10.2 316.2 10.2 100 5.1 158.1 5.1 200 2.55 79.05 2.55 FetTheta: FetTheta is used to calculate actual Junction temp with only observing DieTemp and Thermistor 2 during charging. FET Junction temperature is calculated with the following equation: FETTemp = TH2_Temp+ (TH2_Temp - DieTemp) x FetTheta. The FetTheta configuration range is 0 to 4.0 with 0.125 steps. If Zero-Volt charging is used, or Thermistor 2 is not used, DieTemp is used as FET temperature. FETLim: Set FET Lim to limit FET temperature during charging. The range is 75°C to 103°C with a 4°C lsb. nMiscCfg2 Register (1E4h) Type: Special The nMiscCfg2 register is shown in Table 19 and sets the charger restart threshold voltage. Table 19. nMiscCfg2 Register (1E4h) Format D15 D14 D13 D12 D11 D10 D9 0 0 0 0 0 0 0 D8 D7 D6 D5 dFullOCV D4 D3 D2 D1 D0 0 0 dFullOCV: Sets the charger restart open circuit voltage threshold. The charger restarts if the open circuit voltage falls below ChargingVoltage - dFullOCV - 10mV. dFullOCV has a LSB of 0.625mV, with a range of 80mV. The recommended value for this is 50mV for a total of 60mV below ChargingVoltage for the restart threshold. Set dFullOCV to 0 to disable this function. This function is disabled by default. www.analog.com Analog Devices | 60 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector Charging Configuration Registers The ChargingVoltage and ChargingCurrent display the calculated target charge voltage and current. This includes the programmed charging voltage and current, charging modifications according to battery temperature, and step-charging. ChargingVoltage Register (02Ah) Register Type: Voltage Nonvolatile Backup: None The ChargingVoltage register reports the target charging voltage. ChargingCurrent Register (028h) Register Type: Current Nonvolatile Backup: None The ChargingCurrent register reports the target charging current. nIChgTerm Register (19Ch) Register Type: Current Nonvolatile Restore: IChgTerm (01Eh) if nNVCfg0.enICT is set Alternate Initial Value: 1/3rd the value of the nFullCapNom register (corresponds to C/9.6) The nIChgTerm register allows the device to detect when a charge cycle of the cell has completed. nIChgTerm should be programmed to the exact charge termination current used in the application. The device detects end-of-charge if both of the following conditions are met: • VFSOC Register > FullSOCThr Register • Current Register < IChgTerm See the End-of-Charge section for more details. nVChgCfg Register (1D9h) The nVChgCfg register, shown in Table 20, sets the JEITA charge voltage configuration for the MAX17330. The JEITA charge voltage is used to calculate the Charging Voltage register and is used to determine the overvoltage-protection threshold. Each charge voltage register is a signed offset with 5mV or 20mV resolution. The RoomChargeV offset is defined relative to a normal standard charge setting of 4.2V. The additional charge voltages are relative to RoomChargeV based on the temperature. To disable the temperature dependence and create a flat charging voltage across the temperature range, set dWarmChargeV, dColdChargeV, and dHotChargeV to a value of 0x00. Table 20. nVChgCfg Register (1D9h) Format D15 D14 D13 D12 D11 RoomChargeV D10 D9 D8 D7 D6 dWarmChargeV D5 D4 D3 dColdChargeV D2 D1 D0 dHotChargeV RoomChargeV: RoomChargeV defines the charge voltage between temperatures T2 and T3 relative to a standard 4.2V setting, providing a range of 3.56V to 4.835V in 5mV steps. RoomChargeV is a signed configuration. Set to 0x00 to configure for standard 4.2V. dColdChargeV: ColdChargeV defines the delta charge voltage (relative to room) between temperatures T1 and T2 relative to the room setting, providing a range of RoomChargeV (RoomChargeV - 140mV) in -20mV steps. dColdChargeV configuration is unsigned. dWarmChargeV: WarmChargeV defines the delta charge voltage (relative to room) between temperatures TWarm and T3 relative to the room setting, providing a range of RoomChargeV (RoomChargeV - 60mV) in -20mV steps. dColdChargeV configuration is unsigned. www.analog.com Analog Devices | 61 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector dHotChargeV: HotChargeV defines the delta charge voltage (relative to room) between temperatures T3 and T4 relative to the room setting, providing a range of WarmChargeV (WarmChargeV - 140mV) in -20mV steps. dHotChargeV configuration is unsigned. nIChgCfg Register (1D8h) The nIChgCfg register shown in Table 21 sets the nominal room temperature charging current and the coefficients to scale the charging current across the temperature zones shown in Figure 9. The WarmCOEF, ColdCOEF, and HotCOEF coefficients impact the charging current as well as OCCP and ODCP (See nIPrtTh1). To disable the temperature dependence and create a flat charging current across the temperature range, set the lower byte of nIChgCfg to a value of 0xFF. Table 21. nIChgCfg Register (1D8h) Format D15 D14 D13 D12 D11 D10 D9 D8 D7 RoomChargingCurrent D6 D5 WarmCOEF D4 D3 D2 ColdCOEF D1 D0 HotCOEF RoomChargingCurrent: Sets the nominal room-temperature charging current. The LSB is 100μV. The ChargingCurrent of MAX17330 is configurable from 10mA (0x00) to 2560mA (0xFF) with a 10mΩ sense resistor. See Table 22 for other sense resistors. Table 22. Charging Current for Different Sense Resistors SENSE RESISTOR (mΩ) STEP SIZE (mA) MAX CURRENT (mA) 2 50 12800 5 20 5120 10 10 2560 50 2 512 100 1 256 200 0.5 128 In addition to the range and resolution tradeoff, optimum sense resistor selection requires considering power dissipation and the analog accuracy of the MAX17330. See the Component Selection section for more details. HotCOEF: Coefficient 12.5% to 100% relative to ChargingCurrent for controlling the charge current at hot. HotCOEF has a 12.5% LSB resolution. The resulting HotChargingCurrent is controlled by the following equation: HotChargingCurrent = RoomChargingCurrent x (HotCOEF + 1)/8 WarmCOEF: Coefficient 62.5% to 100% relative to ChargingCurrent for controlling the charge current at warm. WarmCOEF has a 12.5% LSB resolution. The resulting WarmChargingCurrent is controlled by the following equation: WarmChargingCurrent = RoomChargingCurrent x (WarmCOEF + 5)/8 ColdCOEF: Coefficient 12.5% to 100% relative to ChargingCurrent for controlling the charge current at cold. ColdCOEF has a 12.5% LSB resolution. The resulting ColdChargingCurrent is controlled by the following equation: ColdChargingCurrent = RoomChargingCurrent x (ColdCOEF + 1)/8 HotCOEF, WarmCOEF, and ColdCOEF also rescale nIPrtTh1.OCCP. nStepChg Register (1DBh) The nStepChg register defines the step-charging prescription as shown in Figure 2. To disable step-charging, set nStepChg = 0xFF00. Table 23. nStepChg Register (1DBh) Format D15 D14 D13 StepCurr1 www.analog.com D12 D11 D10 D9 StepCurr2 D8 D7 D6 D5 StepdV0 D4 D3 D2 D1 D0 StepdV1 Analog Devices | 62 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector StepCurr1 and StepCurr2: Both of these register bit-fields scale the JEITA charge current down by a 4-bit ratio from 1/ 16 to 16/16. StepdV0 and StepdV1: These register bit-fields configure StepVolt0 and StepVolt1 relative to the JEITA charge voltage. Both registers are negative offsets relative to JEITA ChargeVoltage and support 10mV LSB. Protection Registers Voltage Protection Registers nUVPrtTh Register (1D0h) Register Type: Special The nUVPrtTh register shown in Table 24 sets undervoltage protection, deep-discharge-state protection, and undervoltage-shutdown thresholds. Table 24. nUVPrtTh Register (1D0h) Format D15 D14 D13 D12 D11 D10 D9 D8 D7 UVP D6 D5 D4 D3 UOCVP D2 D1 D0 UVShdn UVP: Undervoltage Protection Threshold. The MAX17330 opens the discharge FET when VCell < UVP. UVP can be configured from 2.2V to 3.46V in 20mV steps. UVP is unsigned. UOCVP: Under Open Circuit Voltage Protection Threshold (also referred to as SmartEmpty). The MAX17330 opens the discharge FET when VFOCV < UOCVP. UOCVP is relative to UVP and can be configured from UVP to UVP + 1.28V in 40mV steps. UVShdn: Undervoltage Shutdown Threshold. The MAX17330 shutdowns when VCell < UVShdn. UVShdn is relative to UVP and can be configured from UVP - 0.32V to UVP + 0.28V in 40mV steps. Note that this is a signed value and UVShdn should be configured as a 2's compliment negative value so that UVShdn < UVP. nOVPrtTh Register (1DAh) Factory Default Value: B354h The nOVPrtTh register shown in Table 25 sets the permanent overvoltage protection threshold, the charge-detection threshold, the overvoltage-protection threshold, and the overvoltage-protection-release threshold. dOVP and dOVPR are relative to the Charge Voltage that is set in the nVChgCfg register and have a 10mV resolution. Table 25. nOVPrtTh Register (1DAh) Format D15 D14 D13 OVPPermFail D12 D11 0 D10 D9 ChgDetTh D8 D7 D6 D5 D4 D3 dOVP D2 D1 D0 dOVPR dOVP: Delta from ChargeVoltage to Overvoltage Protection. dOVP sets JEITA overvoltage protection relative to ChargeVoltage (see nVChgCfg). If nNVCfg1.enJP is disabled, then OVP voltage is calculated from RoomChargeV across all temperature zones. This is a positive number with 10mV resolution and 150mV range. Overvoltage protection is calculated as: OVP = ChargeVoltage + dOVP x 10mV dOVPR: Delta from Overvoltage Protection to the Overvoltage-Release Threshold. dOVPR sets overvoltage-protection release relative to the overvoltage-protection setting. This is a positive number with 10mV resolution and is translated to a negative offset relative to OVP. Overvoltage-protection release is calculated as: OVPR = OVP - dOVPR x 10mV OVPPermFail: Permanent Failure OVP (permanent overvoltage protection) Threshold. Permanent failure overvoltage protection occurs when any cell voltage register reading exceeds this value. The OVPPermFail range is OVP_thresholdRoom + 40mV to OVP_thresholdRoom + 340mV with a 20mV LSB. OVP_PermFail_Threshold = OVPRoom + 40mV + (OVPPermFail x 20mV) www.analog.com Analog Devices | 63 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector ChgDetTh: Charger Detection Threshold. The IC determines that a charger is connected when PCKP > (BATT + ChgDetTh). ChgDetTh has a range of 10mV to 80mV with a 10mV LSB. Current Protection Registers nODSCTh Register (1DDh) Factory Default Value: 0EAFh The nODSCTh register sets the current thresholds for each overcurrent alert. The format of the registers is shown in Table 26. Table 26. nODSCTh Register (1DDh) Format D15 D14 D13 D12 D11 D10 D9 D8 OCTH D7 D6 D5 D4 D3 SCTH D2 D1 D0 ODTH X: Don't Care. SCTH: Short-Circuit Threshold Setting. Sets the short-circuit threshold to a value between 0mV and -158.72mV with a step size of -5.12mV. The SCTH bits are stored such that 0x1F = 0mV and 0x00 = -158.72mV. The short-circuit threshold is calculated as -158.72mV + (SCTH x 5.12mV). ODTH: Overdischarge Threshold Setting. Sets the overdischarge threshold to a value between 0mV and -79.36mV with a step size of -2.56mV. The ODTH bits are stored such that 0x1F = 0mV and 0x00 = -79.36mV. The overdischarge threshold is calculated as -79.36mV + (ODTH x 2.56mV). OCTH: Overcharge Threshold Setting. Sets the overcharge threshold to a value between 0mV and 39.375mV with a step size of 0.625mV. The OCTH bits are stored such that 0x3F = 0mV and 0x00 = 39.375mV. The overcharge threshold is calculated as 39.375mV - (OCTH x 0.625mV). Table 27 shows sample values of calculated thresholds in millivolts for OCTH, SCTh, and ODTH. Equivalent current thresholds are shown assuming a 10mΩ sense resistor. Table 27. OCTH, SCTh, and ODTH Sample Values OCTH SCTH ODTH 0x00 39.375mV 3.9375A -158.72mV -15.872A -79.36mV -7.936A 0x01 38.75mV 3.875A -153.6mV -15.36A -76.8mV -7.68A 0x02 38.125mV 3.8125A -148.8mV -14.848A -74.24mV -7.424A 0x04 36.875mV 3.6875A -138.24mV -13.824A -69.12mV -6.912A 0x08 34.735mV 3.4735A -117.76mV -11.776A -58.88mV -5.888A 0x10 29.375mV 2.9375A -76.8mV -7.68A -38.4mV -3.84A 0x14 26.875mV 2.6875A -56.32mV -5.632A -28.16mV -2.816A 0x18 24.375mV 2.4375A -35.84mV -3.584A -17.92mV -1.792A 0x1E 20.625mV 2.0625A -5.12mV -0.512A -2.56mV 0.256A 0x1F 20mV 2A 0mV 0.00A 0.0mV 0.00A 0x2F 10mV 1A — — — — 0x3F 0mV 0A — — — — nODSCCfg Register (1DEh) Factory Default Value: 0x4355 The nODSCCfg register configures the delay behavior for the short-circuit, over-discharge-current, and over-chargecurrent comparators. The format of the register is shown in Table 28. Table 28. nODSCCfg Register (1DEh) Format D15 D14 www.analog.com D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Analog Devices | 64 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector Table 28. nODSCCfg Register (1DEh) Format (continued) X 1 X X SCDLY X 1 X 1 OCDLY X: Don't Care. SCDLY: Short-Circuit Delay. Configure from 0x0 to 0xF to set short-circuit detection debouncing delay between 70μs and 985μs (70μs + 61μs x SCDLY). There can be up to 31μs of additional delay before the short-circuit's alert affects the discharge FET. OCDLY: Overdischarge and Overcharge Current Delay. Configure from 0x1 to 0xF to set overdischarge/overcharge detection debouncing delay between 70μs and 14.66ms (70μs + 977μs x OCDLY). nIPrtTh1 Register (1D3h)—Overcurrent Protection Thresholds Register Type: Special The nIPrtTh1 register shown in Table 29 sets the upper and lower limits for overcurrent protection when current exceeds the configuration threshold. The upper 8-bits set the overcharge current protection threshold and the lower 8-bits set the overdischarge current protection threshold. Protection threshold limits are configurable with 400μV resolution over the full operating range of the current register. Table 29. nIPrtTh1 Register (1D3h) Format D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 OCCP D4 D3 D2 D1 D0 ODCP OCCP: Overcharge current-protection threshold in room temperature. Overcharge current-protection occurs when the current register reading exceeds this value. This field is signed 2's complement with 400μV LSb resolution to match the upper byte of the current register. HotCOEF, WarmCOEF, and ColdCOEF rescales nIPrtTh1.OCCP in hot, warm, and cold regions. For example, in warm regions, the overcharge current protection threshold updates to OCCP x WarmCOEF. See the nIChgCfg register for HotCOEF, WarmCOEF, and ColdCOEF definitions and the nTPrtTh2 and nTPrtTh3 registers for temperature region definition. ODCP: Overdischarge current-protection threshold. Overdischarge current-protection occurs when current register reading exceeds this value. This field is signed 2's complement with 400μV LSb resolution to match the upper byte of the current register. The fault delay for OCCP and ODCP is configured in nDelayCfg.OverCurrTimer. Temperature Protection Registers The IC has five thresholds for charging protection as well as overdischarge temperature protection and overtemperature permanent failure protection. The standard register format for each of these thresholds is a signed 2's compliment number with 1°C resolution. The IC has 2°C of hysterisis for releasing temperature faults. nTPrtTh1 Register (1D1h) Register Type: Special The nTPrtTh1 register shown in Table 30 sets T1 "Too-Cold" and T4 "Too-Hot" thresholds which control JEITA and provide charging (Too-Hot or Too-Cold) protection. nProtMiscTh.TooHotDischarge provides discharging (Too-Hot only) protection. Threshold limits are configurable with 1°C resolution over the full operating range Temp register. Table 30. nTPrtTh1 Register (1D1h) Format D15 D14 D13 D12 D11 D10 D9 D8 T4 ("Too-Hot") D7 D6 D5 D4 D3 D2 D1 D0 T1 ("Too-Cold") T1-T4 follow JEITA's naming convention for temperature ranges. T1: JEITA "Too-Cold" temperature threshold. When Temp < T1, charging is considered unsafe and can damage the battery so the MAX17330 blocks charging. www.analog.com Analog Devices | 65 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector T4: JEITA "Too-Hot" temperature threshold. When Temp > T4, charging is blocked by the MAX17330. nTPrtTh2 Register (1D5h) Register Type: Special The nTPrtTh2 register shown in Table 31 sets T2 "Cold" and T3 "Hot" thresholds which control JEITA and modulate charging (Hot or Cold) guidance and protection. Threshold limits are configurable with 1°C resolution over the full operating range Temp register. Table 31. nTPrtTh2 (1D5h) Format D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 T3 ("Hot") D3 D2 D1 D0 T2 ("Cold") T1-T4 follow JEITA's naming convention for temperature ranges. T2: JEITA "Cold" temperature threshold. When Temp < T2, charging current/voltage should be reduced and the chargeprotection thresholds are adjusted accordingly. T3: JEITA "Hot" temperature threshold. When Temp > T3, charging current/voltage should be reduced and the chargeprotection thresholds are adjusted accordingly. nTPrtTh3 Register (1D2h) (beyond JEITA) Register Type: Special The nTPrtTh3 register shown in Table 32 sets Twarm and TpermFailHot thresholds which control JEITA and modulate charging (Warm) guidance and protection. Threshold limits are configurable with 1°C resolution over the full operating range Temp register. Table 32. nTPrtTh3 Register (1D2h) Format D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 TpermFailHot D3 D2 D1 D0 Twarm nTPrtTh3 defines protection thresholds beyond standard JEITA definition. Twarm: Warm temperature threshold (between 'normal' and THot), giving an extra temperature region for changing charging current and charging voltage control. TpermFailHot: If enabled, the MAX17330 goes into permanent failure mode and permanently disables the charge FET as well as trips the secondary protector (if installed) or blows the fuse (if installed). Fault Timer Registers nDelayCfg Register (1DCh) Factory Default Value: 0x9B3D Set nDelayCfg to configure debounce timers for various protection faults. A fault state is concluded only if the condition persists throughout the duration of the timer. All delay times start when the ADC first measures the value to exceed the protection threshold which could be up to an additional 351ms of delay between the time the fault is observed externally and the time the ADC first measures the fault. Charging faults can have an additional delay at the conclusion of the timer before the current completely drops 0mA.There is a capacitor from the gate to source of the CHG FET that is needed for charge regulation, which also slows down the ability to completely stop charge current for any charging faults. The current is immediately reduced at the end of the protection timer setting and is completely reduced to 0mA when the capacitor voltage decays to 0V. Table 33. nDelayCfg (1DCh) Format D15 D14 CHGWDT D13 D12 FullTimer D11 D10 D9 OVPTimer D8 D7 D6 OverCurrTimer D5 D4 PermFailTimer D3 D2 TempTimer D1 D0 UVPTimer UVPTimer: Set UVPTimer to configure the Undervoltage-Protection timer. www.analog.com Analog Devices | 66 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector Shutdown Timer: Set UVPTimer to configure the Shutdown timer which controls the timing for entering Ship, DeepShip, and DeepShip2/UVShutdown. When the IC begins to enter a low-power mode, it is important to let the Shutdown Timer expire for the IC to fully enter the low-power mode before returning to active mode. Table 34. UVPTimer Settings UVPTimer SETTING 0 1 2 3 UVPTimer Configuration 0ms to 351ms 351ms to 0.7s 0.7s to 1.4s 1.4s to 2.8s Shutdown Timer Configuration 22.5s to 45s 45s to 90s 90s to 180s 3min to 6min TempTimer: Set TempTimer to configure the fault-timing for the following faults: Too-Cold-Charging (TooColdC), TooHot-Charging (TooHotC), Die-Hot (DieHot), and Too-Hot-Discharging (TooHotD). Table 35. TempTimer Setting TempTimer SETTING 0 1 2 3 Configuration 0ms to 351ms 351ms to 0.7s 0.7s to 1.4s 1.4s to 2.8s The TempTimer setting also controls the temperature transition delay. If the MAX17330 detects a change in temperature that results in a lower OVP threshold, the MAX17330 applies a delay equal to the TempTrans configuration before the new lower OVP threshold goes into effect. There is a delay equal to the TempTrans configuration before the new lower OVP threshold goes into effect. Table 36. TempTrans Configuration Settings TempTimer SETTING 0 1 2 3 TempTrans Configuration 3.151s to 4.55s 5.951s to 8.75s 11.55s to 17.15s 23.351s to 34.851s PermFailTimer: Set PermFailTimer to configure the fault timing for permanent failure detection. Generally, larger configurations are preferred to prevent permanent failure unless some severe condition persists. Table 37. PermFailTimer Settings PermFailTimer SETTING 0 (NOT RECOMMENDED) 1 2 3 Configuration 0ms to 351ms 351ms to 0.7s 0.7s to 1.4s 1.4s to 2.8s OverCurrTimer: Set OverCurrTimer to configure the slower overcurrent protection (the additional fast hardware protection thresholds are described in nODSCCfg and nODSCTh). OverCurrTimer configures the fault timing for the slow overcharge-current detection (OCCP) as well as overdischarge-current detection (ODCP). Table 38. OverCurrTimer Settings OverCurrTimer SETTING 0 1 2 3 4 5 6 7 Configuration 0ms to 351ms 0.351s to 0.7s 0.7s to 1.4s 1.4s to 2.8s 2.8s to 5.6s 5.6s to 11.25s 11.25s to 22.5s 22.5s to 45s OVPTimer: Set OVPTimer to configure the fault timing for overvoltage protection. Table 39. OVPTimer Settings OVPTimer SETTING 0 1 2 3 Configuration 0ms to 351ms 351ms to 0.7s 0.7s to 1.4s 1.4s to 2.8s FullTimer: Set FullTimer to configure the timing for full detection. When charge-termination conditions are detected after the timeout, the CHG FET turns off (if feature is enabled). Prequal Timer: Set FullTimer to configure the timing for prequal charging. Prequal Timer and FullTimer share the same bits in the nDelayCfg register. Table 40. FullTimer Settings FullTimer SETTING www.analog.com 0 1 2 3 4 5 6 7 Analog Devices | 67 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector Table 40. FullTimer Settings (continued) FullTimer Configuration 33s to 44s 67s to 90s 2.25min to 3min 4.5min to 6min 9min to 12min 18min to 24min 36min to 48min 72min to 96min Prequal Timer Configuration 16.875s to 22.5s 33s to 44s 67s to 90s 2.25min to 3min 4.5min to 6min 9min to 12min 18min to 24min 36min to 48min CHGWDT: Set CHGWDT to configure the charger communication watchdog timer. If enabled, the MAX17330 chargeprotects whenever the host has stopped communicating and the SDA/SCL lines idle high for longer than this timeout. ChgRm: Charger removal debounce (1/4 ChgWDT debounce setting) Table 41. ChgWDT/ChgRm Settings ChgWDT/ChgRm SETTINGS 0 1 2 3 CHGWDT Timer 11.2s to 22.5s 22.5s to 45s 45s to 90s 90s to 3min ChgRm Timer 2.8s to 5.6s 5.6s to 11.2s 11.2s to 22.4s 22.4s to 44.8s Battery Internal Self-Discharge Detection Registers Factory Default nProtCfg2 Value: 1006h To enable the ISD feature using the coulombic-efficiency (CE) method, configure LeakFaultCfg, LeakCurrTh, and CEEn as shown in Table 42. Choose the alert and fault mode with LeakFaultCfg and configure the thresholds with LeakCurrTh, as shown in Table 43. When the ISD alerts are enabled, any leakage current detected beyond the threshold is indicated by the ProtAlrt.LDET bit and Status.PA bit (if nConfig.ProtAlrtEn = 1). If the ALRT pin is enabled for alerts (nConfig.Aen = 1 and nConfig.ProtAlrtEn = 1), then the pin indicates the ISD alert. To service the alert, first clear the ProtAlrt register and then clear Status.PA. The event is also indicated in nBattStatus.LDET, which is recorded in the permanent lifelog. The reported leakage-current measurement can be read from two different registers: ● LeakCurrRep = 15-bit unsigned left-justified value with an LSB of 1.5625μV/16 (or 0.15625mA/16 with 10mΩ sense resistor). ● nBattStatus.LeakCurr = 8-bit unsigned value with an LSB of 3.125μV (or 0.3125mA with 10mΩ sense resistor). Contact Analog Devices for configuring the ISD feature. Table 42. nProtCfg2 Register (1DFh) Format D15 D14 LeakFaultCfg D13 D12 D11 CEEn D10 D9 D8 D7 LeakCurrTh D6 D5 D4 D3 D2 D1 D0 CheckSum Table 43. Alert and Fault Mode Settings LeakFaultCfg SETTING DESCRIPTION LeakCurrTh RESOLUTION ALERT RANGE FAULT RANGE Note: Leakage current above LeakCurrTh triggers an alert/fault. Currents refer to the 10mΩ RSENSE. 000 Disabled 001 Alert Only 010 Fault = Alert + 2.5mA 011 Fault = Alert + 5mA 100 Fault Only (+2.5mA offset) 101 Alert Only 110 Fault = Alert + 2.5mA 111 Fault = Alert + 10mA 0.3125mA 0.3125mA to 5mA 2.8125mA to 7.5mA 5.3125mA to 10mA 3.125mA to 12.5mA 0.625mA 0.625mA to 10mA 3.125mA to 12.5mA 10.625mA to 20mA X: Don't Care CEEn: Coulombic-efficiency (CE) method enable. Set to 1 to enable self-discharge detection. www.analog.com Analog Devices | 68 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector LeakFaultCfg: Leakage Fault Configuration. Set LeakFaultCfg to configure the alert and fault behavior as shown in Table 43. LeakCurrTh: Leakage Current Threshold is an unsigned 4-bit threshold for leakage current alert and fault generation. The LSB resolution is either 0.625mA or 1.25mA based on the LeakCurrCfg setting as shown in Table 43. When alerts and faults are both enabled, the fault threshold is either 5mA, 10mA, or 20mA above the alert threshold as shown in the Description column of Table 43. CheckSum: Protector NVM CheckSum. CheckSum is the checksum value of the protection registers for validating NVM at startup when nNVCfg1.enProtChksm = 1. LeakCurrRep Register (0x16F) The LeakCurrRep register contains the reported leak current when it is enabled with nCheckSum.CEEn as shown in Table 44. Table 44. LeakCurrRep Register (0x16F) Format D15 D14 D13 D12 D11 D10 0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Reported LeakCurrent Reported LeakCurrent: Reported Leak Current is an unsigned 15-bit leakage current. This register stores the reported leakage current with an LSB of 1.5625μV/16 (or 0.15625mA/16 with a 10mΩ sense resistor). The range is 0mA to 319.99mA. Status/Configuration Protection Registers nProtCfg Register (1D7h) The Protection Configuration register contains enable bits for various protection functions. Table 45. nProtCfg Register (1D7h) Format D15 D14 D13 ChgWDTEn nChgAutoCtrl FullEn D12 D11 SCTest D10 D9 D8 CmOvrdEn ChgTestEn PrequalEn D7 D6 D5 D4 D3 D2 D1 D0 Reserved PFEn DeepShpEn OvrdEn UVRdy FetPFEn BlockDisCEn DeepShp2En BlockDisCEn: Block Discharge FET at too Cold (nTPrtTh1). PFEn: PermFail Enable. Set PFEn = 1 to enable the detection of a permanent failure to permanently turn the FETs off. All types of permanent failures operate only if PFEn = 1 and are all disabled if PFEn = 0. PFEn must be enabled for the PFAIL pin to be operational. See the Permanent Failure section for more details. FetPFEn: FET PermFail Enable. Set to 1 to enable Charge FET and Discharge FET open or short detection, which registers a permanent failure, permanently turns the FETs off, and drives the PFAIL pin high. PFEn must also be set for the FET PermFail Enable to operate. UVRdy: Undervoltage Ready. Only use with Legacy Mode, set to 1 to use MAX17330 charging. In the undervoltage protected state (but higher than undervoltage shutdown), this bit chooses whether or not the CHG FET remains enabled. Configure UVRdy = 0 to keep the CHG FET and corresponding charge pumps powered during undervoltage protection. In this state, the pack is quickly responsive to charger connection. Configure UVRdy = 1 to disable the CHG FET and corresponding charge pumps during undervoltage protection. In this state, the consumption drops to 11μA but there is a hibernate latency (set by nHibCfg.HibScalar) between when the charge source is applied and when the battery begins charging. OvrdEn: Override Enable. Set OvrdEn = 1 to enable the Alert pin to be an input to disable the protection FETs. CmOvrdEn: Comm Override Enable. This bit when set to 1 allows the ChgOff and DisOff bits in CommStat to be set by I2C communication to turn off the protection FETs. See Disabling FETs by Pin-Control or I2C Command section for more details about OvrdEn and CmOvrdEn. DeepShpEn: Set DeepShpEn = 1 to associate shutdown actions (I2C shutdown command or communication removal) www.analog.com Analog Devices | 69 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector with 0.5μA shutdown. All registers power down in this mode. Set DeepShpEn = 0 to continue full calculations but with protector disabled (CHGEn = 0, DISEn = 0, pump off), operating at the 11μA consumption rate. DeepShp2En: Set DeepShp2En = 1 to associate shutdown actions (I2C shutdown command or communication removal) with 0.1μA shutdown. All registers power down in this mode. Set DeepShp2En = 0 to use DeepShip 1 (0.5μA or 11μA modes). Wake up DeepShip2 by connecting a charge source. SCTest: Set SCTest = 01 to source 30μA from BATT to PCKP to test for the presence/removal of any overload/shortcircuit at PCKP. SCTest is only used during special circumstances when DIS = off. Particularly if an overdischarge current fault has been tripped. Because of this, the PCKP resistor must be 10kΩ or less for proper short-circuit removal detection. Set SCTest = 00b to disable. BlockChgEn: Enable block Chg FET from I2C for parallel charging application. Protstatus.D7 is set to 1 or 0 according to Config.D0. nChgAutoCtrl: CHG FET is controlled ON/OFF only. Normal applications should set nProtCfg.nChgAutoCtrl and config.ChgAutoCtrl to 0. Set nProtCfg.nChgAutoCtrl and config.Legacy to 1 to use this function. Charge control is not used. Ideal Diode mode is not used. nPreQualEn: Charge the battery at prequal until Cell voltage is greater than Undervoltage Protection level. FullEn: Full Charge Protection Enable. If the full charge protection feature is enabled, the charge FET opens when the battery is fully charged (RepSOC reaches 100%). ChgWDTEn: Charger WatchDog Enable. If the charger watchdog feature is enabled, the protector disallows charging unless communication has not been detected for more than the Charger WatchDog delay that is configured in nDelayCfg.ChgWdg. nBattStatus Register (1A8h) Battery Status Nonvolatile Register The Battery Status register contains the permanent battery status information. If nProtCfg.PFen = 1, then a permanent fail results in permanently turning the FETs off to ensure the safety of the battery. Table 46. nBattStatus Register (1A8h) Format D15 D14 D13 D12 D11 D10 D9 D8 PermFail OVPF OTPF CFETFs DFETFs FETFo BattHlth ChksumF D7 D6 D5 D4 D3 D2 D1 D0 Reserved PermFail: Permanent Failure. This bit is set if any permanent failure is detected. CFETFs: ChargeFET Failure-Short Detected. If the MAX17330 detects that the charge FET is shorted and cannot be opened, it sets the CFETFs bit and the PermFail bit. This function is enabled with nProtCfg.FetPFEn. DFETFs: DischargeFET Failure-Short Detected. If the MAX17330 detects that the discharge FET is shorted and cannot be opened, it sets the DFETFs and the PermFail bit. This function is enabled with nProtCfg.FetPFEn. FETFo: FET Failure Open. If the MAX17330 detects an open FET failure on either FET, it sets FETFo. This function is enabled with nProtCfg.FetPFEn. ChksumF: Checksum Failure. ChksumF protection related NVM configuration registers checksum failure. In the case of a checksum failure, the device sets the PermFail bit but does not write it to NVM to prevent using an additional NVM write. This allows the PermFail bit to be cleared by the host so that the INI file can be reloaded. ProtStatus Register (0D9h) The Protection Status register contains the Fault States of the Protection State Machine. Table 47. ProtStatus Register (0D9h) Format D15 D14 D13 D12 D11 D10 D9 D8 ChgWDT TooHotC Full TooColdC OVP OCCP Qovflw PreqF/LDet www.analog.com Analog Devices | 70 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector Table 47. ProtStatus Register (0D9h) Format (continued) D7 D6 D5 D4 D3 D2 D1 D0 BlockChg PermFail DieHot TooHotD UVP ODCP BlockDis/TooColdD Shdn BlockChg: Blocks charging from either communication timeout or absence of recurring Status.BlockChg = 0 command. BlockDis: Blocks discharging by direct I2C command (Config2.BlockDis); BlockDis auto-releases when BlockChg begins. TooColdD: Same threshold with TooColdC. Enable this function by setting BlockDisCEn in nProtCfg register. Shdn: A flag to indicate the Shutdown Event status to Protector module for further action on Charging/Discharging FETs, Charge Pump, and PkSink. PermFail: Permanent Failure Detected. See nBattStatus for details of the Permanent Failure. Discharging Faults: ODCP—Overdischarge current protection UVP—Undervoltage Protection TooHotD—Overtemperature for Discharging DieHot—Overtemperature for die temperature Charging Faults: TooHotC—Overtemperature for Charging OVP—Overvoltage OCCP—Overcharge Current Protection Qovrflw—Q Overflow TooColdC—Undertemperature Full—Full Detection ChgWDT—Charge Watchdog Timer DieHot—Overtemperature for Die Temperature PreqF—Prequal timeout was detected LDet—Leakage fault was detected ProtAlrt Register (0AFh) The Protection Alerts register contains a history of any protection events that have been logged by the device and is formatted as shown in Table 48. If any bit of ProtAlrt is 1, then the Status.PA bit is also 1 if Config.PAEn = 1. Once a bit is set, it remains set until cleared by the host. The Alert pin is driven low if Config.ProtAlrtEn = 1. Table 48. ProtAlrt Register (0AFh) Format D15 D14 D13 D12 D11 D10 D9 D8 ChgWDT/LDet TooHotC Full TooColdC OVP OCCP Qovflw Reserved D7 D6 D5 D4 D3 D2 D1 D0 Reserved TempRegionChange DieHot TooHotD UVP ODCP Reserved Reserved TempRegionChange: Temperature Region Change. A change in the JEITA temperature region creates this alert so that the host is alerted to a reduction in JEITA charging voltage that can impact the charging or protection parameters. HProtCfg2 Register (0F1h) Register Type: Special Nonvolatile Backup: None The status of the discharge FET and charge FET can be monitored in the HProtCfg2 register as shown in Table 49. www.analog.com Analog Devices | 71 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector Table 49. HProtCfg2 (0F1h) Format D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 x x x x x x x x x x x x x x DISs CHGs DISs: Discharge FET Status. DISs = 1 indicates the discharge FET is on and allows discharge current. DISs = 0 indicates the discharge FET is off and blocks discharge current. CHGs: Charge FET Status. CHGs = 1 indicates the charge FET is on and allows charge current. CHGs = 0 indicates the charge FET is off and blocks charge current. X: Reserved. FProtStat Register (0DAh) Table 50. FProtStat Register (0DAh) format D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 X D5 D4 IsDis D3 X D2 D1 D0 Hot Cold Warm X: Don't Care IsDis: Battery is in Discharging state. Cleared when charging signal is detected. Hot: Operating in Hot JEITA region. Cold: Operating in Cold JEITA region. Warm: Operating in Warm JEITA region. Other Protection Registers nProtMiscTh Register (1D6h) Register Type: Special The nProtMiscTh register is shown in Table 51 and sets a few miscellaneous protection thresholds. Table 51. nProtMiscTh Register (1D6h) Format D15 D14 D13 QovflwTh D12 D11 D10 D9 TooHotDischarge D8 D7 D6 D5 CurrDet D4 D3 D2 D1 D0 DieTempTh DieTempTh: Sets the dietemp overtemperature protection threshold relative to 50°C and has an LSB of 5°C. DieTempTh defines the delta between 50°C and the dietemp protection threshold. The range is 50°C and 125°C. CurrDet: CurrDet is configurable from 25μV/RSENSE to 400μV/RSENSE in 25μV/RSENSE steps (equivalent to 2.5mA to 40mA in 2.5mA steps with a 10mΩ sense resistor). It is a threshold to detect discharging and charging events from the device perspective. (current > CurrDet) indicates charging, (current < -CurrDet) indicates discharging. TooHotDischarge: Sets the over-temperature protection threshold associated with discharge. TooHotDischarge has 2°C LSB's and defines the delta between Over-Temp-Charge (nTPrtTh1.T4) and Over-Temp-Discharge. The range is nTPrtTh1.T4(TooHot) to nTPrtTh1.T4(TooHot) + 30°C. QovflwTh: QovflwTh sets the coefficient for the Qoverflow alert threshold. Qoverflow alert threshold = designCap x coefficient. The MAX17330 monitors the delta Q between the Q at the start of charge and the current Q. If the delta Q exceeds the Qoverflow alert threshold, indicating that the charger has charged more than the expected capacity of the battery, then a ProtStatus.Qovrflw fault is generated and the charge is briefly interrupted. The ProtAlrt.QOverflow bit remains set until the host clears the bit. The coefficient is calculated as: coefficient = 1.0625 + (QovflwTh x 0.0625). www.analog.com Analog Devices | 72 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector ModelGauge m5 Algorithm ModelGauge m5 EZ Registers AVCAP/AVSOC REPCAP/REPSOC TEMPERATURE MIXCAP/MIXSOC AVGVCELL FULLCAP AVGCURRENT FULLCAPREP AVGTEMPERATURE FULLCAPNOM NDESIGNVOLT VFOCV/VFSOC NDESIGNCAP VRIPPLE NICHGTERM Characterization Table CHARACTERIZATION Characterization Table TABLES NQRTABLES00,10,20,30 NFULLSOCTHR NRCOMP0 NFULLCAPNOM NVEMPTY NTEMPCO NIAVGEMPTY ModelGauge m5 ALGORITHM AGE AGEFORECAST CYCLES NRIPPLECFG NCONVGCFG NCVCFG NAGEFCCFC NLEARNCFG NFLITERCFG NRELAXCFG NMISCCFG ATRATE FULLCAPNOM ALGORITHM CONFIGURATION CELL CHARACTERIZATION INFORMATION APPLICATION SPECIFIC RSLOW TTE/TTF/AtTTE ModelGauge ALGORITHM OUTPUTS VCELL CURRENT CYCLES TIMERH NQRTABLES00,10,20,30 NIAVGEMPTY RCOMP0 TEMPCO FULLCAPREP LEARNED INFORMATION ANALOG INPUTS For accurate results, the ModelGauge m5 EZ uses information about the cell and the application as well as the realtime information measured by the IC. Figure 16 shows inputs and outputs to the algorithm grouped by category. Analog input registers are the real-time measurements of voltage, temperature, and current performed by the IC. Applicationspecific registers are programmed by the customer to reflect the operation of the application. The Cell Characterization Information registers hold characterization data that models the behavior of the cell over the operating range of the application. The Algorithm Configuration registers allow the host to adjust the performance of the IC for its application. The Learned Information registers allow an application to maintain the accuracy of the fuel gauge as the cell ages. The register description sections describe each register function in detail. Figure 16. ModelGauge m5 EZ Registers ModelGauge m5 EZ Algorithm Output Registers The following registers are outputs from the ModelGauge m5 EZ algorithm. The values in these registers become valid 480ms after the IC is reset. www.analog.com Analog Devices | 73 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector RepCap Register (005h) Register Type: Capacity Nonvolatile Backup: None RepCap or Reported Capacity is a filtered version of the AvCap register that prevents large jumps in the reported value caused by changes in the application such as abrupt changes in temperature or load current. See the Fuel-Gauge Empty Compensation section for details. RepSOC Register (006h) Register Type: Percentage Nonvolatile Backup: None RepSOC is a filtered version of the AvSOC register that prevents large jumps in the reported value caused by changes in the application such as abrupt changes in load current. RepSOC corresponds to RepCap and FullCapRep. RepSOC is intended to be the final state of charge percentage output for use by the application. See the Fuel-Gauge Empty Compensation section for details. FullCapRep Register (010h) Register Type: Capacity Nonvolatile Backup and Restore: nFullCapRep (1A9h) or nFullCapNom (1A5h) This register reports the full capacity that goes with RepCap, generally used for reporting to the user. A new full-capacity value is calculated at the end of every charge cycle in the application. TTE Register (011h) Register Type: Time Nonvolatile Backup: None The TTE register holds the estimated time-to-empty for the application under present temperature and load conditions. The TTE value is determined by dividing the AvCap register by the AvgCurrent register. The corresponding AvgCurrent filtering gives a delay in TTE empty, but provides more stable results. TTF Register (020h) Register Type: Time Nonvolatile Backup: None The TTF register holds the estimated time-to-full for the application under present conditions. The TTF value is determined by learning the constant current and constant voltage portions of the charge cycle based on experience of prior charge cycles. Time-to-full is then estimated by comparing the present charge current to the charge termination current. Operation of the TTF register assumes all charge profiles are consistent in the application. See the Typical Operating Characteristics for sample performance. Age Register (007h) Register Type: Percentage Nonvolatile Backup: None The Age register contains a calculated percentage value of the application’s present cell capacity compared to its expected capacity. The result can be used by the host to gauge the battery pack health as compared to a new pack of the same type. The equation for the register output is: Age Register = 100% x (FullCapNom register/DesignCap register) Cycles Register (017h) and nCycles (1A4h) Register Type: Special Nonvolatile Backup and Restore: nCycles (1A4h) www.analog.com Analog Devices | 74 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector The Cycles register maintains a total count of the number of charge/discharge cycles of the cell that have occurred. The result is stored as a percentage of a full cycle. For example, a full charge/discharge cycle results in the Cycles register incrementing by 100%. The Cycles register has a full range of 0 to 16383 cycles with a 25% LSb. Cycles is periodically saved to nCycles to provide a long-term nonvolatile cycle count. Table 52. nCycles Register (1A4h) Format D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 CycleCount (Cycles register 4000 > 2000 CAPACITY RESOLUTION (mAh) MAXIMUM CAPACITY (mAh) 1 0064h 1562.5 2 00C8h 781.25 ±51.2 5 144360 ±25.6 2.5 71680 > 800 5 01F4h 312.5 ±10.24 1 28672 > 400 10 03E8h 156.25 ±5.12 0.5 14336 > 200 20 07D0h 78.125 ±2.56 0.25 7168 > 80 50 1388h 31.25 ±1.02 0.1 2867 > 40 100 2710h 15.625 ±0.51 0.05 1433 AvgCurrent Register (01Dh) Register Type: Current www.analog.com Analog Devices | 115 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector Nonvolatile Backup: None The AvgCurrent register reports an average of Current register readings over a configurable 0.7 second to 6.4 hour time period. See the FilterCfg register description for details on setting the time filter. The first Current register reading after returning to active mode sets the starting point of the AvgCurrent filter. MaxMinCurr Register (00Ah) Register Type: Special Nonvolatile Backup: Periodically saves to nMaxMinCurr (1ABh) if nNVCfg2.enMMC is set, but does not restore from nonvolatile memory. Alternate Initial Value: 0x807F The MaxMinCurr register maintains the maximum and minimum Current register values since the last IC reset or until cleared by host software. Each time the Current register updates, it is compared against these values. If the reading is larger than the maximum or less than the minimum, the corresponding value is replaced with the new reading. At powerup, the maximum current value is set to 80h (the minimum) and the minimum current value is set to 7Fh (the maximum). Therefore, both values are changed to the Current register reading after the first update. The host software can reset this register by writing it to its power-up value of 0x807F. The maximum and minimum voltages are each stored as two’s complement 8-bit values with 0.4mV/RSENSE resolution. Table 92 shows the register format. Table 92. MaxMinCurr (00Ah)/nMaxMinCurr (1ABh) Register Format D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 MaxCurrent D4 D3 D2 D1 D0 MinCurrent MaxCurrent: Maximum Current register reading (0.40mV/RSENSE resolution) MinCurrent: Minimum Current register reading (0.40mV/RSENSE resolution) MaxMinCurr is not cumulative across the entire battery lifetime. After each periodic nonvolatile-memory save, MaxMinCurr resets to 0x807F to find the next maximum and minimum current across the next segment of battery life. This behavior helps provide a useful log across the battery lifetime where each log segment shows the maximum and minimum current experienced across only that segment. nCGain Register (1C8h) Register Type: Special The nCGain register adjusts the gain and offset of the current measurement result. The current measurement A/D is factory trimmed to data sheet accuracy without the need for the user to make further adjustments. The recommended default for the nCGain register is 0x4000 which applies no adjustments to the Current register reading. For specific application requirements, the CGain and COff values can be used to adjust readings as follows: Current register = (current A/D reading × (CGain / 256)) + COff CGain and COff are combined into a single register formatted as shown in Table 93. Table 93. nCGain Register (1C8h) Format D15 D14 D13 D12 D11 D10 D9 CGain D8 D7 D6 D5 D4 D3 D2 D1 D0 COff COff: COff has a range of -32 to +31 LSbs. However, it is normally not recommended to calibrate COff. COff = 0 is recommended for most applications. CGain: The recommended default value of CGain = 0x100 corresponds to a gain of 1. CGain can be calculated as follows: CGain = ((MeasuredCurrent/ReportedCurrent) x 0x0100). CGain is a signed value and can be negative. CGTempCo (0B8h)/nCGTempCo (0x1C9) Register Register Type: Special Alternate Initial Value: 0x20C8 www.analog.com Analog Devices | 116 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector If Config.FastADCen= 0 and nNVCfg1.enMet = 1, then CGTempCo is used to adjust current measurements for temperature. CGTempCo has a range of 0% to 3.1224% per °C with a step size of 3.1224/0x10000 percent per °C. If the nNVCfg1.enMtl bit is clear, CGTempCo defaults to a value of 0x20C8 or 0.4% per °C which is the approximate temperature coefficient of a copper trace. If the nNVCfg1.enMtl bit is set, CGTempCo restores from nCGTempCo (1C9h) after IC reset allowing a custom sense resistor temperature coefficient to be used. Note that Config.FastADCen and nNVCfg1.enMet cannot be enabled simultaneously. Copper Trace Current Sensing The MAX17330 can measure current using a copper board trace instead of a traditional sense resistor, the main difference being the ability to adjust to the change in sense resistance over temperature. To enable copper trace current sensing, set the following configuration bits nNVCfg1.enADCCfg = 0 and nNVCfg2.enMet = 1. The IC's default temperature adjustment is 0.4% per °C but can be adjusted using the nCGTempCo/nADCCfg register if nNVCfg1.enMtl = 1. Note that copper trace current sensing cannot be enabled at the same time as custom ADC Configuration. For 1-ounce copper, a length-to-width ratio of 6:1 creates a 0.0035Ω sense resistor which is suitable for most applications. Table 94 summarizes the IC setting for copper trace sensing. Table 94. Copper Trace Sensing PARAMETER SETTING nNVCfg1.enADCCfg 0 ADC Configuration defaulted. RESULT nNVCfg1.enMet 1 Sense resistor temperature compensation enabled. nNVCfg2.enMlt 0 Sense resistor temperature compensation set to default of 0.4% per °C (typical copper). nRense 0x012C RSENSE Size 6:1 Sense resistor indicator to host software set to 3.5mΩ. A 6:1 length-to-width ratio of 1oz copper gives a resistance of 3.5mΩ. MinCurr Register (0AEh) Register Type: Current Nonvolatile Backup: None The MinCurr register maintains the minimum discharge Current register value within a 45-second period or until cleared by the host software. Each time the Current register updates, it is compared against its value. If the reading is less than the minimum, the corresponding value is replaced with the new reading. At power-up, MinCurr value is set to 0 (maximum discharge current). Therefore, the value is changed to the Current register reading after the first update during discharge. The host software can reset this register by writing it to its power-up value of 0. LSB is 1.5625μV/RSENSE. Temperature Measurement The IC can be configured to measure its own internal die temperature and an external NTC thermistor. See the nPackCfg register for details. Every 1.4s the IC biases the external thermistor with an internal trimmed pullup. After the pullup is enabled, the IC waits for a settling period of tPRE before making measurements on the TH pin. Measurement results are converted to a ratiometric value from 0% to 100%. The active pullup is disabled when temperature measurements are complete. This feature limits the time the external resistor-divider network is active and lowers the total amount of energy used by the system. The ratiometric results are converted to temperature using logarithmic thermistor resistance translation each time the TH pin is measured. Internal die temperature measurements are factory calibrated and are not affected by nThermCfg register settings. Proper nThermCfg configuration is needed to achieve thermistor accuracy from -40ºC to +85ºC. Additionally, the IC maintains a record of the minimum and maximum temperature measured and an average temperature over a time period defined by the host. Temperature Measurement Timing Temperature measurement channels are individually enabled using the nPackCfg register. A/D measurement order and firmware post-processing determine when a valid reading becomes available to the user. In addition, not all channels are measured each time through the firmware task loop. Selection options for enabled channels create a large number of www.analog.com Analog Devices | 117 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector possible timing options. Table 95 shows the timing for all temperature measurements made by the IC for some typical pack configurations. All times in this table are considered typical. Table 95. Temperature Measurement Timing nPackCfg SETTING APPLICATION Die Temperature Only Die Temperature and Thermistor nPackCfg.A1En =0 nPackCfg.A1En =1 FIRST UPDATE AFTER RESET REGISTER Temp, IntTemp, AvgIntTemp UPDATE RATE IN ACTIVE MODE1 UPDATE RATE IN HIBERNATE MODE2 351ms 550ms AvgTA 1.4s 351ms IntTemp, Temp1, Temp, AvgIntTemp, AvgTemp1 550ms AvgTA 1406ms 5.625s 351ms 1.4s 1. Not all registers update at the same time. Updates are staggered to one channel per task period. Update order is IntTemp and Temp. 2. Hibernate mode update times assume the recommended nHibCfg.HibScalar setting of four task periods. Temp Register (01Bh) Register Type: Temperature Nonvolatile Backup: None The Temp register is the input to the fuel gauge algorithm. The Temp register reflects the thermistor or die temperature as configured in nPackCfg. AvgTA Register (016h) Register Type: Temperature Nonvolatile Backup: None The AvgTA register reports an average of the readings from the Temp register. Averaging period is configurable from 6 minutes up to 12 hours as set by the FilterCfg register. The first Temp register reading after returning to active mode sets the starting point of the averaging filters. MaxMinTemp Register (009h) Register Type: Special Nonvolatile Backup: Periodically saves to nMaxMinTemp (1ADh) if nNVCfg2.enMMT is set, but does not restore from nonvolatile memory. Alternate Initial Value: 0x807F The MaxMinTemp register maintains the maximum and minimum Temp register (008h) values since the last fuel-gauge reset or until cleared by host software. It is compared against these values each time the Temp register updates. If the reading is larger than the maximum or less than the minimum, the corresponding values are replaced with the new reading. At power-up, the maximum value is set to 80h (minimum) and the minimum value is set to 7Fh (maximum). Therefore, both values are changed to the Temp register reading after the first update. Host software can reset this register by writing it to its power-up value of 0x807F. The maximum and minimum temperatures are each stored as two’s complement 8-bit values with 1°C resolution. Table 96 shows the format of the register. Table 96. MaxMinTemp (009h)/nMaxMinTemp (1ADh) Register Format D15 D14 D13 D12 D11 D10 D9 D8 D7 MaxTemperature D6 D5 D4 D3 D2 D1 D0 MinTemperature MaxTemperature: Maximum Temp register reading (1ºC resolution) MinTemperature: Minimum Temp register reading (1ºC resolution) www.analog.com Analog Devices | 118 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector MaxMinTemp is not cumulative across the entire battery lifetime. After each periodic nonvolatile memory save, MaxMinTemp resets to 0x807F to find the next maximum and minimum temperatures across the next segment of battery life. This behavior helps provide a useful log across the battery lifetime where each log segment shows the maximum and minimum temperature experienced across only that segment. nThermCfg Register (1CAh) Factory Default Value: 71BEh External NTC thermistors generate a temperature-related voltage measured at the TH/TH2 pins. Set nThermCfg register to compensate the thermistor for accurate translation of temperature. Table 97 lists common NTC thermistors with their associated Beta value and the nThermCfg value. The thermistors in the table translate within ±1°C from -40°C to +85°C. For other thermistors, use the equation in Table 97 to translate within ±2.5°C. Table 97. Register Settings for Common Thermistor Types R25C(kΩ) BETA at 25°C to 85°C nThermCfg Murata NCP15XH103F03RC 10 3435 71E8h Semitec 103AT-2 10 3435 91C3h TDK B57560G1103 7003 10 3610 5183h Murata NCU15WF104F6SRC 100 4250 48EBh NTC TH11-4H104F 100 4510 08D9h TDK NTCG064EF104FTBX 100 4225 58EFh THERMISTOR Other 10K 10 nThermCfg = 7000h + (3245919/Beta1 - 512) Other 100K 100 nThermCfg = 3000h + (3245919/Beta1 - 512) 1. Use Beta 25°C to 85°C. DieTemp (034h) Register Register Type: Temperature Nonvolatile Backup: None This register displays temperature in degrees Celsius, ±128ºC, or 1ºC in the high-byte, or 1/256ºC LSB. AvgDieTemp (040h) Register Register Type: Temperature Nonvolatile Backup: None The AvgDieTemp register reports a 4-sample filtered average of the DieTemp register. FETTemp (015h) Register Register Type: Temperature Nonvolatile Backup: None This register displays FET temperature in degrees Celsius, ±128ºC, or 1ºC in the high-byte, or 1/256ºC LSB. FETTemp is used during charge regulation to regulate/limit the FET temperature during charging. When a second thermistor is not installed and enabled, FETTemp simply equals DieTemp, and DieTemp is used as an approximation for FET temperature. When a second thermistor is installed, FETTemp is calculated by the temperature measured at TH2 and exaggerated according to the thermal gradient observed between TH2 and DieTemp. The gradient helps estimate the "unseen temperature" inside the FET (which is always hotter than any directly measurable temperature) according to the following equation: FETTemp = TH2_Temp + (TH2_Temp - DieTemp) x FetTheta www.analog.com Analog Devices | 119 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector The FetTheta range is 0 to 4.0 with 0.125 steps. See also the nChgCfg1 and nPackCfg for more details to enable and configure the FET thermistor. Power Power Register (0B1h) Instant power calculation from immediate current and voltage. LSB is 0.8mW with a 10mΩ sense resistor. AvgPower Register (0B3h) Filtered Average Power from the power register. LSB is 0.8mW with a 10mΩ sense resistor. Filter bits located in Config2.POWR. nADCCfg Register (1C9h) Register Type: Special Nonvolatile Restore: There is no associated restore location for this register. Set Config.FastADCen = 1 and nNVCfg2.enMet = 0, to use nADCCfg to set the the ADC for longer samples which reduce sample noise at the expense of quiescent current. Table 98. nADCCfg (0x1C9) Format D15 D14 D13 D12 D11 D10 TermEn ChgTermEn 0 1 0 0 D9 D8 D7 nTerm D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 Default value: 0x5188 Standard configuration for ADC averaging count select is fixed 4ms. With nADCCfg settings, longer than 4ms ADC conversions are possible and result in less noisy ADC readings. Default value for nADCCfg reduces VCell noise by 4x (64ms), PCKP/Temp noise by 3x (32ms) ChgTermEn: ADC Changes are only enabled during charging. Current consumption is not sensitive while the charge source is present. ADC behavior is returned back to 4ms sampling when the charge source is removed. TermEn: ADC Changes are always on. This has significant current consumption impact and is not recommended. nTerm: ADC averaging count select. (0, 1, 2, 3, 4, 5, 6, or 7) setting of nMaxTerm/nTerm corresponds to (4, 8, 16, 32, 64, 128, 256, or 512)ms per ADC channel conversion, respectively. 256ms, 512ms choices are not recommended to avoid timekeeping issues. Status and Configuration Registers The following registers control IC operation not related to the fuel gauge such as power-saving modes, nonvolatile backup, and ALRT pin functionality. DevName Register (021h) Register Type: Special Nonvolatile Backup: None The DevName register holds firmware revision information. This allows the host software to easily identify the type of IC being communicated with. Table 99 shows the DevName register format. Table 99. DevName Register (021h) Format D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Revision The DevName for the IC is 0x40B0 or 0x40B1. www.analog.com Analog Devices | 120 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector nROMID0 (1BCh)/nROMID1 (1BDh)/nROMID2 (1BEh)/nROMID3 (1BFh) Registers Register Type: Special Nonvolatile Restore: There are no associated restore locations for these registers. Each MAX17330 IC contains a unique 64-bit identification value that is contained in the nROMID registers. The unique ID can be reconstructed from the nROMID registers as shown in Table 100. Table 100. nROMID Registers (1BCh to 1BFh) Format NROMID3[15:0] NROMID2[15:0] NROMID1[15:0] NROMID0[15:0] ROM ID [63:48] ROM ID [47:32] ROM ID [31:16] ROM ID [15:0] Status Register (000h) Register Type: Special Nonvolatile Backup: None Initial Value: 0x0002 The Status register maintains all flags related to alert thresholds. Table 101 shows the Status register format. Table 101. Status Register (000h) Format D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 PA Smx Tmx Vmx CA Smn Tmn Vmn dSOCi Imx AllowChgB X Bst Imn POR X POR: Power-On Reset. This bit is set to 1 when the device detects that a software or hardware POR event has occurred. This bit must be cleared by the system software to detect the next POR event. POR is set to 1 at power-up. Imn: Minimum Current Alert Threshold Exceeded. This bit is set to 1 whenever a Current register reading is below the minimum IAlrtTh value. This bit is cleared automatically when Current rises above minimum IAlrtTh value. Imn is set to 0 at power-up. Bst: Battery Status. Useful when the IC is used in a host-side application. This bit is set to 0 when a battery is present in the system and set to 1 when the battery is absent. Bst is set to 0 at power-up. Imx: Maximum Current Alert Threshold Exceeded. This bit is set to 1 whenever a Current register reading is above the maximum IAlrtTh value. This bit is cleared automatically when Current falls below the maximum IAlrtTh value. Imx is set to 0 at power-up. dSOCi: State of Charge 1% Change Alert. This is set to 1 whenever the RepSOC register crosses an integer percentage boundary such as 50%, 51%, etc. Must be cleared by the host software. dSOCi is set to 0 at power-up. Vmn: Minimum Voltage Alert Threshold Exceeded. This bit is set to 1 whenever a VCell register reading is below the minimum VAlrtTh value. This bit may or may not need to be cleared by system software to detect the next event. See the Config.VS bit description. Vmn is set to 0 at power-up. Tmn: Minimum Temperature Alert Threshold Exceeded. This bit is set to 1 whenever a Temperature register reading is below the minimum TAlrtTh value. This bit may or may not need to be cleared by system software to detect the next event. See the Config.TS bit description. Tmn is set to 0 at power-up. Smn: Minimum SOC Alert Threshold Exceeded. This bit is set to 1 whenever SOC falls below the minimum SAlrtTh value. This bit may or may not need to be cleared by system software to detect the next event. See the Config.SS and MiscCFG.SACFG bit descriptions. Smn is set to 0 at power-up. Vmx: Maximum Voltage Alert Threshold Exceeded. This bit is set to 1 whenever a VCell register reading is above the maximum VAlrtTh value. This bit may or may not need to be cleared by the system software to detect the next event. See the Config.VS bit description. Vmx is set to 0 at power-up. Tmx: Maximum Temperature Alert Threshold Exceeded. This bit is set to 1 whenever a Temperature register reading is above the maximum TAlrtTh value. This bit may or may not need to be cleared by the system software to detect the next event. See the Config.TS bit description. Tmx is set to 0 at power-up. Smx: Maximum SOC Alert Threshold Exceeded. This bit is set to 1 whenever SOC rises above the maximum SAlrtTh value. This bit may or may not need to be cleared by the system software to detect the next event. See the Config.SS www.analog.com Analog Devices | 121 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector and MiscCFG.SACFG bit descriptions. Smx is set to 0 at power-up. PA: Protection Alert. This bit is set to a 1 when there is a protection event. The details of each protection event can be found in the ProtAlrt register. This bit must be cleared by the system software to detect the next protection event. However, before clearing this bit, the ProtAlrt register must first be written to 0x0000. ProtAlrt is set to 0 at power-up. CA: Charging Alert. This bit is set to a 1 when there is a CP or CT or Dropout event. The details of each charging event can be found in the Chgstat register. This bit must be cleared by the system software to detect the next event. Chgstat updates every 351ms and does not require interaction from the system software to clear it. AllowChgB: Allow Charge Bar. The AllowChgB bit is used for managing the charging or discharging of multiple batteries in parallel and is enabled by setting nPackCfg.ParEn = 1. Clear this bit to 0 to allow charging as well as block discharging when Config2.BlockDis = 1. This bit must be cleared every 1.4 seconds for continuous charging or continuous discharge blocking. X: Don’t Care. This bit is undefined and can be logic 0 or 1. Status2 Register (0B0h) Register Type: Special Nonvolatile Backup: None Initial Value: 0x0000 The Status2 register maintains status of hibernate mode. Table 102 shows the Status register format. Table 102. Status2 Register (0B0h) Format D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X X X X X X X X X Hib x Hib: Hibernate Status. This bit is set to 1 when the device is in hibernate mode or 0 when the device is in active mode. Hib is set to 0 at power-up. X: Don’t Care. This bit is undefined and can be logic 0 or 1. nI2CCfg Register (1B4h) Register Type: Special Nonvolatile Restore: There is no associated restore location for this register. The nI2CCfg register manages settings for I2C and SBS mode operation of the IC. Table 103 shows the register format. Table 103. nI2CCfg Register (1B4h) Format D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 CapMd X X X X X X X X X SDA_OUT DIS_SLT WPen D1 MECfg D0 X X: Don’t Care. This bit is undefined and can be logic 0 or 1. WPen: Write Protection Enable. WPen = 0 (Default) to enable write protection. DIS_SLT: Disable Slave Timeout. DIS_SLT = 0 to enable slave timeout where slave stops communicating and drops off the bus after 30mS of SCL low duration. DIS_SLT = 1 (Default) to disable the slave timeout. SDA_OUT: Enable SDA output to PFail pin. Set SDA_OUT = 1 to enable PFAIL pin to become open-drain for SDA and SDA pin is input only. SDA pin is bi-drectional when SDA_OUT is 0 (Default). MECfg: Configures sMaxError register output when operating in SBS mode. 00: Always report 0% error 01: Always report 1% error 10: Report actual experienced error 11: Always report 3% error CapMd: Selects sBatteryMode.CapMd bit default setting when operating in SBS mode. CapMd resets to 0 every time a www.analog.com Analog Devices | 122 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector pack removal occurs as detected by floating communication lines. nPackCfg Register(1B5h) Register Type: Special The nPackCfg register configures the voltage and temperature inputs to the A/D and also to the fuel gauge. nPackCfg configuration must match the pack hardware for proper operation of the IC. Table 104 shows the register format. The factory default for nPackCfg is 0x1000. Table 104. nPackCfg (1B5h) Register Format D15 D14 0 S_Hib D13 D12 THCfg D11 D10 THType D9 D8 000 D7 D6 0 ParEn D5 D4 D3 D2 I2CSid D1 D0 0001 I2CSid Configure the I2C address and SMBus address with this bit field. For dynamic changes to the I2C address, see I2CCmd Register. Table 105. I2C Address Configuration I2CSID PRIMARY ADDRESS SECONDARY ADDRESS 0b00 6Ch 16h 0b01 ECh 96h 0b10 64h 1Eh 0b11 E4h 9Eh ParEn: Enable parallel charging feature. See Parallel Battery Management section for details. THType: If using a 10kΩ NTC thermistor, set THType = 0. If using a 100kΩ NTC thermistor, set THType = 1. See nThermCfg for additional details. THCfg: THCfg sets the Thermistor behavior. Note TH2 is only available when ZVC is not used. Table 106. Thermistor Configuration THCFG BEHAVIOR 0b00 Both thermistors channels disabled. Temp and FETTemp are measured from DieTemp. 0b01 Thermistor 1 is used as battery temperature, Thermistor 2 is used with DieTemp for calculating FETTemp. 0b10 Thermistor 1 is enabled. FETTemp is copied from DieTemp. 0b11 Invalid. Do not set. S_Hib: Ship-Mode Hibernate. Set S_Hib = 1 to use hibernate operation during ship-mode. Set S_Hib = 0 for full-shutdown during ship-mode (0.5μA or 0.1μA, see nProtCfg). In Hibernate mode, the fuel gauge functionality is active and the battery state is continually updated. I2CCmd Register(12Bh) Register Type: Special The I2CCmd register changes the primary and secondary slave addresses of MAX17330. To change the slave ID, configure the Alert pin to a logic HIGH or LOW, write the target GoToSID and IncSID bits, and wait 1.4s. Table 107 shows the register format. If the Alert pin is logic HIGH, the I2C addresses of the device change to the addresses listed in the ALERT HIGH column of Table 108. If the Alert pin is logic LOW, the I2C addresses of the device change to the addresses listed in the ALERT LOW column of Table 108. If multiple MAX17330 devices are sharing the same I2C bus, the Alert pin on one device should be set to logic LOW and the others set to logic HIGH, allowing the devices to move to different I2C slave addresses. Table 107. I2CCmd (12Bh) Register Format D15 D14 D13 D12 D11 0 www.analog.com D10 D9 D8 D7 D6 D5 D4 GoToSID D3 D2 0 D1 D0 IncSID Analog Devices | 123 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector GoToSID: Configure the primary I2C slave address and secondary slave address with this bit field. The primary slave address applies to all registers with a leading "0" in the register address, for example, 022h. The secondary slave address applies to all registers with a leading "1" in the register address, for example, 1AAh. Note: The addresses shown in Table 108 are 8-bit slave addresses. Table 108. GoToSID Address Configuration GoToSID ALERT HIGH ALERT LOW — Primary/Secondary Address Primary/Secondary Address 0b00 ECh/96h 6Ch/16h 0b01 64h/1Eh ECh/96h 0b10 E4h/9Eh 64h/1Eh 0b11 6Ch/16h E4h/9Eh IncSID: Set to 1 to incremement the Slave ID as defined in the GoTOSID bitfield. nConfig Register (1B0h) Register Type: Special Nonvolatile Restore: Config (00Bh) and Config2 (0ABh) if nNVCfg0.enCfg is set. Alternate Initial Value: 0x2214 for Config, 0x2058 for Config2 The nConfig register holds all shutdown enable, alert enable, and temperature enable control bits. Writing a bit location enables the corresponding function within one task period. Table 109, Table 110, and Table 111 show the register formats. Table 109. nConfig Register (1B0h) Format D15 D14 D13 D12 D11 D10 D9 D8 PAen SS TS VS 0 PBen DisBlockRead 0 D7 D6 D5 D4 D3 D2 D1 D0 AtRateEn COMMSH FastADCen 1 FTHRM Aen dSOCen TAlrtEn Table 110. Config Register (00Bh) Format D15 D14 D13 D12 D11 D10 D9 D8 0 SS TS VS 0 PBen DisBlockRead ChgAutoCtrl D7 D6 D5 D4 D3 D2 D1 D0 SHIP COMMSH FastADCen ETHRM FTHRM Aen CAen PAen Table 111. Config2 Register (0ABh) Format D15 D14 D13 D12 POR_CMD 0 AtRtEn 0 D7 D6 D5 D4 dSOCen TAlrtEn 0 1 D11 D10 D9 D8 POWR D3 D2 DRCfg D1 D0 CPMode BlockDis 0: Bit must be written 0. Do not write 1. 1: Bit must be written 1. Do not write 0. BlockDis: Block Discharge. The BlockDis bit is used for managing the discharging of multiple batteries in parallel and is enabled by setting nPackCfg.ParEn = 1. Set to 1 and clear Status.BlockChg to enable blocking of discharge current. See Parallel management for more detail. PAen: Protection Alert Enable. Set PAen = 1 to enable this feature that saves the protector faults (TooHotC, TooColdC, OVP, OCCP, DieHot, TooHotD, UVP, ODCP, and LDet) into the low byte of the nBattStatus register. After each life logging write to NVM, the low byte of nBattStatus is cleared. www.analog.com Analog Devices | 124 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector CAen: Charge alerts enable. Set CAen = 1 to drive the ALRT pin low on dropout or heat limit alerts. Config.Aen must be set to 1 to allow this function. PBEn: PushButton enable. Set PBEn = 1 to enable wakeup by pushbutton. This application allows a gadget to be completely sealed with the battery disconnected until a shared system button is pressed. DisBlockRead: Disable SBS Block Read. Set DisBlockRead to 1 for normal read access in the 16h memory space. Clear DisBlockRead to 0 to enable SBS block reads when SBS Mode is enabled with nNVCfg0.SBSen. The default setting for DisBlockRead is 1. Aen: Enable alert on fuel-gauge outputs. When Aen = 1, violation of any of the alert threshold register values by temperature, voltage, or SOC triggers an alert. This bit affects the ALRT pin operation only. The Smx, Smn, Tmx, Tmn, Vmx, Vmn, Imx, and Imn bits of the Status register (000h) are not disabled. Note that if this bit is set to 1, the ALSH bit should be set to 0 to prevent an alert condition from causing the device to enter shutdown mode. FTHRM: Force Thermistor Bias Switch. This allows the host to control the bias of the thermistor switch or enable fast detection of battery removal. Set FTHRM = 1 to always enable the thermistor bias switch. With a standard 10kΩ thermistor, this adds an additional ~200μA to the current drain of the circuit. ETHRM: Enable Thermistor. Set to logic 1 to enable the automatic TH output bias and TH measurement. FastADCen: Enable FastADC. Set to logic 1 to enable the FastADC feature. COMMSH: Communication Shutdown. Set to logic 1 to force the device to enter shutdown mode if both SDA and SCL are held low. This also configures the device to wake up on a rising edge of any communication. See Table 9. SHIP: Ship or Deepship Command. Write this bit to logic 1 to force into ship or deepship mode based on nProtCfg.DeepShpEn after timeout of the Shutdown Timer register, which is configured in nDelayCfg.UVPTimer. SHIP is reset to 0 at power-up and upon exiting ship or deepship mode. VS: Voltage ALRT Sticky. When VS = 1, voltage alerts can only be cleared through software. When VS = 0, voltage alerts are cleared automatically when the threshold is no longer exceeded. TS: Temperature ALRT Sticky. When TS = 1, temperature alerts can only be cleared through software. When TS = 0, temperature alerts are cleared automatically when the threshold is no longer exceeded. SS: SOC ALRT Sticky. When SS = 1, SOC alerts can only be cleared through software. When SS = 0, SOC alerts are cleared automatically when the threshold is no longer exceeded. ChgAutoCtrl: CHG FET is controlled ON/OFF only. Normal applications should set nProtCfg.nChgAutoCtrl and config.Legacy to 0. Set nProtCfg.nChgAutoCtrl and config.ChgAutoCtrl to 1 to use this function. Charge control is not used. Ideal diode mode is not used. POR_CMD: Firmware Restart. Set this bit to 1 to restart IC firmware operation without performing a recall of nonvolatile memory into RAM. This allows different IC configurations to be tested without changing nonvolatile memory settings. This bit is set to 0 at power-up and automatically clears itself after firmware restart. TAlrten: Temperature Alert Enable. Set this bit to 1 to enable temperature based alerts. Write this bit to 0 to disable temperature alerts. This bit is set to 1 at power-up. dSOCen: SOC Change Alert Enable. Set this bit to 1 to enable the Status.dSOCi bit function. Write this bit to 0 to disable the Status.dSOCi bit. This bit is set to 0 at power-up. CPMode: Constant-power mode. Set to 1 to enable constant-power mode. DRCfg: Deep Relax Time Configuration. 0b00 for 0.8 hours to 1.6 hours, 0b01 for 1.6 hours to 3.2 hours, 0b10 hours for 3.2 hours to 6.4 hours, and 0b11 hours for 6.4 hours to 12.8 hours. POWR: Sets the time constant for the AvgPower register. The default POR value of 0000b gives a time constant of 0.7s. The equation setting the period is: AvgPower time constant = 45s x 2(POWR-6) nHibCfg Register (1BBh) Register Type: Special Nonvolatile Restore: None www.analog.com Analog Devices | 125 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector The nHibCfg register controls hibernate mode functionality. The IC enters hibernate mode if the measured system current falls below the HibThreshold setting for longer than the HibEnterTime delay. While in hibernate mode, the IC reduces its operating current by slowing down its task period as defined by the HibScalar setting. The IC automatically returns to active mode of operation if current readings go above the HibThreshold setting for longer than the HibExitTime delay. Table 112 shows the register format. Table 112. nHibCfg Register (1BBh) Format D15 D14 EnHib D13 D12 D11 HibEnterTime D10 D9 D8 HibThreshold D7 D6 D5 0 0 0 D4 D3 D2 HibExitTime D1 D0 HibScalar 0: Bit must be written 0. Do not write 1. HibScalar: Sets the task period while in hibernate mode based on the following equation: Hibernate Mode Task Period(s) = 702ms x 2(HibScalar) HibExitTime: Sets the required time period of consecutive current readings above the HibThreshold value before the IC exits hibernate mode and returns to active mode of operation. Hibernate Mode Exit Time(s) = (HibExitTime + 1) x 702ms x 2(HibScalar) HibThreshold: Sets the threshold level for entering or exiting hibernate mode. The threshold is calculated as a fraction of the full capacity of the cell using the following equation: Hibernate Mode Threshold(mA) = ( FullCap(mAh)/0.8 hours )/2(HibThreshold) HibEnterTime: Sets the time period that consecutive current readings must remain below the HibThreshold value before the IC enters hibernate mode as defined by the following equation. The default HibEnterTime value of 000b causes the IC to enter hibernate mode if all current readings are below the HibThreshold for a period of 5.625 seconds, but the IC could enter hibernate mode as quickly as 2.812 seconds. 2.812s x 2(HibEnterTime) < Hibernate Mode Entry Time < 2.812s x 2(HibEnterTime + 1) EnHib: Enable Hibernate Mode. When set to 1, the IC enters hibernate mode if conditions are met. When set to 0, the IC always remains in active mode of operation. nRSense Register (1CFh) Register Type: Special Nonvolatile Restore: There is no associated restore location for this register. The nRSense register is the designated location to store the sense resistor value used by the application. This value is not used by the IC as all current and capacity information is reported in terms of μV and μVh. Host software can use the nRSense register value to convert current and capacity information into mA and mAh. It is recommended that the sense resistor value be stored with a LSb weight of 10μΩ, which gives a range of 10μΩ to 655.35mΩ. Table 113 shows recommended register settings based on common sense resistor values. Table 113. Recommended nRSense Register Values for Common Sense Resistors SENSE RESISTOR (Ω) nRSENSE REGISTER 0.005 0x01F4 0.010 0x03E8 0.020 0x07D0 nDesignVoltage Register (1E3h) Register Type: Special Nonvolatile Restore: There is no associated restore location for this register. Table 114. nDesignVoltage Register (1E3h) Format D15 D14 D13 D12 Vminsys www.analog.com D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Vdesign Analog Devices | 126 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector Vminsys: (unsigned byte) = Minimum system voltage specification for the design. Generates MinSysVoltage value. Vdesign: (unsigned byte) = Design voltage specification for the design. Each byte has a LSB = 20mV (resolution) giving a full-scale range between 0V and 5.12V. These values are used in Dynamic Power Calculations when enDP = 1. AtRate Functionality The AtRate function allows the host software to see theoretical remaining time or capacity for any given load current. AtRate can be used for power management by limiting system loads depending on the present conditions of the cell pack. Whenever the AtRate register is programmed to a negative value indicating a hypothetical discharge current, the AtQResidual, AtTTE, AtAvSOC, and AtAvCap registers display theoretical residual capacity, time-to-empty, stateof-charge, and available capacity respectively. The host software should wait two full task periods (703ms minimum in active mode) after writing the AtRate register before reading any of the result registers. AtRate Register (004h) Register Type: Current Nonvolatile Backup: None The host software should write the AtRate register with a negative two’s-complement 16-bit value of a theoretical load current prior to reading any of the AtRate output registers. AtQResidual Register (0DCh) Register Type: Capacity Nonvolatile Backup: None The AtQResidual register displays the residual charge held by the cell at the theoretical load current level entered into the AtRate register. AtTTE Register (0DDh) Register Type: Time Nonvolatile Backup: None The AtTTE register can be used to estimate time-to-empty for any theoretical current load entered into the AtRate register. The AtTTE register displays the estimated time-to-empty for the application by dividing AtAvCap by the AtRate register value. AtAvSOC Register (0CEh) Register Type: Percentage Nonvolatile Backup: None The AtAvSOC register holds the theoretical state-of-charge of the cell based on the theoretical current load of the AtRate register. The register value is stored as a percentage with a resolution of 0.0039% per LSB. If a 1% resolution state-ofcharge value is desired, the host can read only the upper byte of the register instead. AtAvCap Register (0DFh) Register Type: Capacity Nonvolatile Backup: None The AtAvCap register holds the estimated remaining capacity of the cell based on the theoretical load current value of the AtRate register. The value is stored in terms of µVh and must be divided by the application sense-resistor value in terms of mΩ to determine the remaining capacity in mAh. Alert Function The Alert Threshold registers allow interrupts to be generated by detecting a high or low voltage, current, temperature, or state-of-charge. Interrupts are generated on the ALRT pin open-drain output driver. An external pullup resistor is required www.analog.com Analog Devices | 127 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector to generate a logic-high signal. Alerts can be triggered by any of the following conditions: • Over/undervoltage—VAlrtTr register threshold violation (upper or lower) and alerts enabled (Aen = 1). • Over/undertemperature—TAlrtTr register threshold violation (upper or lower) and alerts enabled (Aen = 1). • Over/under current—IAlrtTr register threshold violation (upper or lower) and alerts enabled (Aen = 1). • Over/under SOC—SAlrtTr register threshold violation (upper or lower) and alerts enabled (Aen = 1). To prevent false interrupts, the threshold registers should be initialized before setting the Aen bit. Alerts generated by battery insertion or removal can only be reset by clearing the corresponding bit in the Status (000h) register. Alerts generated by a threshold-level violation can be configured to be cleared only by the host software or cleared automatically when the threshold level is no longer violated. See the Config register description for details of the alert function configuration. nVAlrtTh Register (18Ch) Register Type: Special Nonvolatile Restore: VAlrtTh (001h) if nNVCfg1.enAT is set. Alternate Initial Value: 0xFF00 (Disabled) The nVAlrtTh register shown in Table 115 sets upper and lower limits that generate an ALRT pin interrupt if exceeded by the VCell register value. The upper 8 bits set the maximum value and the lower 8 bits set the minimum value. Interrupt threshold limits are selectable with 20mV resolution over the full operating range of the VCell register. At power-up, the thresholds default to their maximum settings unless they are configured to be restored from nonvolatile memory instead by setting the nNVCfg1.enAT bit. Table 115. VAlrtTh (001h)/nVAlrtTh (18Ch) Register Format D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 VMAX D4 D3 D2 D1 D0 VMIN VMAX: Maximum voltage reading. An alert is generated if the VCell register reading exceeds this value. This field has 20mV LSb resolution. VMIN: Minimum voltage reading. An alert is generated if the VCell register reading falls below this value. This field has 20mV LSb resolution. nTAlrtTh Register (18Dh) Register Type: Special Nonvolatile Restore: TAlrtTh (002h) if nNVCfg1.enAT is set. Alternate Initial Value: 0x7F80 (Disabled) The nTAlrtTh register shown in Table 116 sets upper and lower limits that generate an ALRT pin interrupt if exceeded by the Temp register value. The upper 8 bits set the maximum value and the lower 8 bits set the minimum value. Interrupt threshold limits are stored in 2’s-complement format with 1ºC resolution over the full operating range of the Temp register. At power-up, the thresholds default to their maximum settings unless they are configured to be restored from nonvolatile memory instead by setting the nNVCfg1.enAT bit. Table 116. TAlrtTh (002h)/nTAlrtTh (18Dh) Register Format D15 D14 D13 D12 TMAX D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TMIN TMAX: Maximum temperature reading. An alert is generated if the Temp register reading exceeds this value. This field is signed 2's-complement format with 1ºC LSb resolution. TMIN: Minimum temperature reading. An alert is generated if the Temp register reading falls below this value. This field is signed 2's-complement format with 1ºC LSb resolution. www.analog.com Analog Devices | 128 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector nSAlrtTh Register (18Fh) Register Type: Special Nonvolatile Restore: SAlrtTh (003h) if nNVCfg1.enAT is set. Alternate Initial Value: 0xFF00 (Disabled) The nSAlrtTh register shown in Table 117 sets upper and lower limits that generate an ALRT pin interrupt if exceeded by the selected RepSOC, AvSOC, MixSOC, or VFSOC register values. See the MiscCFG.SACFG setting for details. The upper 8 bits set the maximum value and the lower 8 bits set the minimum value. Interrupt threshold limits are selectable with 1% resolution over the full operating range of the selected SOC register. At power-up, the thresholds default to their maximum settings unless they are configured to be restored from nonvolatile memory instead by setting the nNVCfg1.enAT bit. Table 117. SAlrtTh (003h)/nSAlrtTh (18Fh) Register Format D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 SMAX D4 D3 D2 D1 D0 SMIN SMAX: Maximum state-of-charge reading. An alert is generated if the selected SOC register reading exceeds this value. This field has 1% LSb resolution. SMIN: Minimum state-of-charge reading. An alert is generated if the selected SOC register reading falls below this value. This field has 1% LSb resolution. nIAlrtTh Register (0ACh) Register Type: Special Nonvolatile Restore: IAlrtTh (1ACh) if nNVCfg1.enAT is set. Alternate Initial Value: 0x7F80 (Disabled) The nIAlrtTh register shown in Table 118 sets upper and lower limits that generate an ALRT pin interrupt if exceeded by the Current register value. The upper 8 bits set the maximum value and the lower 8 bits set the minimum vaue. Interrupt threshold limits are selectable with 400μV resolution over the full operating range of the Current register. At power-up, the thresholds default to their maximum settings unless they are configured to be restored from nonvolatile memory instead by setting the nNVCfg1.enAT bit. Table 118. IAlrtTh (0ACh)/nIAlrtTh (18Eh) Register Format D15 D14 D13 D12 D11 D10 D9 CURRMAX D8 D7 D6 D5 D4 D3 D2 D1 D0 CURRMIN CURRMAX: Maximum Current Threshold. An alert is generated if the current register reading exceeds this value. This field is signed 2's-complement with 400μV LSb resolution to match the upper byte of the Current register. CURRMIN: Minimum Current Threshold. An alert is generated if the current register reading falls below this value. This field is signed 2's-complement with 400μV LSb resolution to match the upper byte of the Current register. Smart Battery Compliant Operation The is compliant to the Smart Battery Specification v1.1 when nNVCfg0.enSBS = 1. Enabling SBS operation does not interfere with normal operation of the IC. SBS formatted registers are accessed at slave address 16h and memory addresses 100h to 17Fh using SBS protocols. SBS functionality can be configured using the nSBSCfg and nDesignVoltage registers. SBS Compliant Memory Space (I2C Interface Only) The MAX17330 contains an SBS v1.1 Compliant memory space on pages 10h to 17h that can be accessed using the Read Word, Write Word, and Read Block commands at 2-Wire slave address 16h. Table 119 lists the SBS compliant registers. Refer to the SBS 1.1 Specification for details of registers at addresses 100h to 12Fh. Registers marked with Note 3 in the table are shared between SBS and normal IC functions and are always readable regardless of IC settings. Their format is described in the Analog Measurements section of the data sheet. All other registers on pages 13h to 17h are described in this section. Greyed locations are reserved and should not be written to. www.analog.com Analog Devices | 129 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector Table 119. SBS Register Space Memory Map PAGE/ 10XH 11XH 12XH 13XH 14XH 15XH 16XH 17XH 0h sManfctAccess sFullCap sManfctrName1 — — — — — 1h sRemCapAlarm sRunTTE sDeviceName1 — — — — — WORD 2h sRemTimeAlarm sAvgTTE sDevChemistry1 — — — — — 3h sBatteryMode sAvgTTF sManfctData2 — — — — — 4h sAtRate sChargingCurrent — Temp13 — — — — 5h — sChargingVoltage — IntTemp3 — — — — 6h sAtTTE sBatteryStatus — sFirstUsed — — — — 7h sAtRateOK sCycles — AvgTemp13 — — sAvCap — 8h sTemperature sDesignCap — AvgIntTemp3 — — sMixCap — 9h sPackVoltage sDesignVolt — — — — — — Ah sCurrent sSpecInfo — — — — — — Bh sAvgCurrent sManfctDate — — — — — — Ch sMaxError sSerialNumber2 — — — — — — Dh sRelSOC — — — — — CGTempCo3 — Eh sAbsSOC — — — — — — — Fh sRemCap — — sCell1 sAvgCell1 — — — 1. Location is read as ASCII data using the Read Block command. 2. Location is read as Hexadecimal data using the Read Block command. 3. Location is shared between SBS and normal IC functions and is always readable regardless of IC settings. sRemCapAlarm/sRemTimeAlarm Registers (101h/102h) Register Type: Capacity/Time Nonvolatile Restore: None sRemCapAlarm: sRemCapAlarm defaults to DesignCap/10 at startup. sRemTimeAlarm: sRemTimeAlarm defaults to 10min at startup. At-Rate Functionality sAtRate Register (104h) Register Type: Current Nonvolatile Backup: None The host software should write the sAtRate register with a negative two’s-complement 16-bit value of a theoretical load current prior to reading any of the at-rate output registers. AtRate calculations are performed using sAtRate (0x104) if enSBS = 1 or AtRate(0x004) if enSBS = 0. sAtTTF Register (105h) Register Type: Time Nonvolatile Backup: None The sAtTTF register can be used to estimate time to full for any theoretical current load entered into the sAtRate register. AtRate calculations are performed using either sAtRate (0x104) if enSBS = 1 or AtRate(0x004) if enSBS = 0. www.analog.com Analog Devices | 130 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector sAtTTE Register (105h) Register Type: Time Nonvolatile Backup: None The sAtTTE register can be used to estimate time-to-empty for any theoretical current load entered into the sAtRate register. The AtTTE register displays the estimated time-to-empty for the application by dividing AtAvCap by the sAtRate register value. sAtTTE is translated from AtTTE for conversion into minutes. AtRate calculations are performed using either sAtRate (0x104) if enSBS = 1 or AtRate(0x004) if enSBS = 0. sAtRateOK Register (107h) Register Type: Special Nonvolatile Restore: None From SBS spec AtRateOK(): Description: Returns a boolean value that indicates whether or not the battery can deliver the previously written AtRate value of additional energy for 10 seconds (boolean). If the AtRate value is zero or positive, the AtRateOK() function ALWAYS returns true. The result can depend on the setting of CAPACITY_MODE bit. Purpose: The AtRateOK() function is part of a two-function call-set used by power management systems to determine if the battery can safely supply enough energy for an additional load. It is used immediately after the SMBus host sets the AtRate value. sTemperature Register (108h) Register Type: Temperature Nonvolatile Restore: None Temperature is translated from AvgTA register. sPackVoltage Register (109h) Register Type: Voltage Nonvolatile Restore: None Voltage is translated from sCELL1. sChargingCurrent Register (114h) Register Type: Current Nonvolatile Restore: None As for the SBS, this register returns the smart battery's desired charging rate in mA. sDesignVolt Register (119h) Register Type: Voltage Nonvolatile Restore: None sDesignVolt is represented per cell. sSpecInfo Register (11Ah) Register Type: Special Nonvolatile Backup: None Table 120. SpecInfo (11Ah) Format D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 0 0 1 1 (PEC) 0 0 0 1 www.analog.com Analog Devices | 131 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector PEC: PEC indicates whether the pack is configured to support SMBus PEC correction. PEC is always enabled on the MAX17330 in SBS Mode. sSerialNumber Register (11Ch to 11Eh) Register Type: Special Nonvolatile Restore: None SerialNumber indicates the 16-bit serial number as stored in nSerialNumber MTP. SerialNumber2 and SerialNumber3 provide extended data for the serial number as stored in nSerialNumber2 and nSerialNumber3. By using 6-bytes total, a serial number can provide a very unique ID for 281 trillion devices. A 4-byte serial number can support 4.3 billion devices. Some of the bits can be fixed to indicate the platform or other information. sManfctrName Register (120h) Register Type: Special Nonvolatile Restore: nManfctrName A block SMBus/I2C read of 0x20 on I2C slave 0x16 (SBS) reports RAM addresses 0x120 sequenced with 0x146-0x14A, for a total of 6-words of data. The first byte indicates the byte length and the following bytes are ASCII characters representing the brand name of the pack. This data is taken from nManfctrName MTP, except that the byte count is set by firmware instead of saved in MTP. sDeviceName Register (121h) Register Type: Special Nonvolatile Restore: nDeviceName A block SMBus/I2C read of 0x21 on I2C slave 0x16 (SBS) reports RAM addresses 0x121 sequenced with 0x140 to 0x143, for a total of 5-words of data. The first byte indicates the byte length and the following bytes are ASCII characters representing the device name. This data is taken from nDeviceName MTP, except that the byte-count is set by firmware instead of saved in MTP. sDevChemistry Register (122h) Register Type: Special Nonvolatile Restore: None A block SMBus/I2C read of 0x22 on I2C slave 0x16 (SBS) reports RAM addresses 0x122 sequenced with 0x156 to 0x158, for a total of 4-words of data. The first byte indicates the byte length and the following bytes are ASCII characters representing the device chemistry. This string is always “LION” for the MAX17330, which is standard for all SBS packs. sManfctData Registers (123h to 12Fh) Register Type: Various Nonvolatile Restore: None The bytes of this read-block command are defined as follows: Byte 0: Cell count. Copy from NCELLS information. Byte 1: High-Byte of eep_MEM_VER Byte 2: Low-byte of eep_MEM_VER Byte 3: High-Byte of Version Byte 4: Low-Byte of Version Byte 5: HCONFIG Byte 6: HCONFIG2 Byte 7: Q Byte 8: QH www.analog.com Analog Devices | 132 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector sFirstUsed Register (136h) This register contains a mirror of the value stored in nonvolatile memory address 1D7h. sCell1 Register (13Fh) This register contains the same cell voltage information displayed in Cell1 (0D8h) respectively with SBS compliant formatting. 1 LSb = 1mV, which gives a full scale range of 0V to 65.535V. sAvgCell1 Register (14Fh) This register contains the same average cell voltage information displayed in AvgCell1 (0D4h) with SBS compliant formatting. 1 LSb = 1mV, which gives a full scale range of 0V to 65.535V. sAvCap Register (167h) This register contains the same information as the AvCap (01Fh) register. It is formatted for SBS compliance where 1 LSb = 1mAh, which gives a full scale range of 0mAh to 65535mAh. sMixCap Register (168h) This register contains the same information as the MixCap (00Fh) register. It is formatted for SBS compliance where 1 LSb = 1mAh, which gives a full scale range of 0mAh to 65535mAh. sManfctInfo Register (170h) The sManfctInfo register is accessed using the SBS protocol read block command. This register function is not supported in the MAX17330. Nonvolatile SBS Register Back-Up When SBS mode operation is enabled by setting nNVCfg0.enSBS = 1, data from several nonvolatile memory locations are translated into SBS memory space. Table 121 lists these translations. Note that when performing an SBS Read Block command, the IC automatically generates the size data byte by counting the number of sequential non-zero data bytes stored in the corresponding nonvolatile memory locations. The nonvolatile memory only needs to store the actual data to be read by an SBS Read Block command. If the SBS mode of operation is disabled, these locations become available for general purpose nonvolatile data storage. Table 121. SBS to Nonvolatile Memory Mapping NONVOLATILE MEMORY ADDRESS NONVOLATILE MEMORY REGISTER NAME SBS MEMORY ADDRESS S REGISTER NAME 1D6h nManfctrDate 1Bh sManfctrDate 1D7h nFirstUsed 36h sFirstUsed 1CCh-1CEh nManfctrName[2:0] 1D8h-1DAh nSerialNumber[2:0] 1DBh-1DFh nDeviceName[4:0] 20h (Read Block Command) 1Ch (Read Block Command) 21h (Read Block Command) sManfctrName sSerialNumber sDeviceName nCGain and Sense Resistor Relationship To meet SBS compliance, current and capacity registers in the SBS memory space must have an LSb bit weight of 1mA or 1mAh. The current gain must be adjusted based on the application sense resistor value to set the proper bit weight. Table 122 shows the proper nCGain value to use for the most common sense resistor values. This is the default register value only, it does not include any offset trim or custom gain adjustment. Note that changing the nCGain register affects the gain reported by the standard ModelGauge current and capacity registers. www.analog.com Analog Devices | 133 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector Table 122. nCGain Register Settings to Meet SBS Compliance SENSE RESISTOR VALUE (mΩ) NCGAIN REGISTER VALUE CORRESPONDING CGAIN REGISTER VALUE 2.5 0x4000 0x0400 5 0x2000 0x0200 10 0x1000 0x0100 Dynamic Battery Power Technology (DBPT) Registers Many mobile systems with high-performance CPUs, GPUs, motors, radios, etc., require the battery to deliver short pulses of high power without the battery voltage falling below critical system undervoltage levels. Managing these pulse loads optimally without sacrificing performance is quite challenging without appropriate battery capability information being available to the system. To achieve better run-time and to help the system run at optimal performance, Analog Devices has developed Dynamic Battery Power Technology (DBPT). The MAX17330 supports this DBPT feature, which provides the on-demand battery capability to be used for managing pulse loads. To support these high pulses without the battery voltage falling below critical system undervoltage levels, the MAX17330 indicates the instantaneous peak and sustained power levels that can be extracted safely from the battery. The system can use this information to set its maximum current in accordance with battery power capability. For example, in many applications, the system requires at least 3.3V to operate correctly. By configuring the MAX17330 for DBPT, the system's loads can be controlled or limited to stay within the battery's capability and ensure that a minimum system voltage (MinSysVolt) is not crossed until the battery is in a very low state. The implementation of DBPT in the MAX17330 hews closely to Intel's Dynamic Battery Power Technology v2.0 standard and relies on specific functions and corresponding registers. This section defines those functions. The implementation in the MAX17330 includes all the same registers as the Intel spec. However, the MAX17330 register set uses different LSBs and addresses from the Intel standard. The following registers are used for DBPT. The MAX17330 uses the standard current register format (0.15625µV/Sense Resistor) for current, 0.8mW for power, and 0.2441mΩ (precisely 1/4.096) for resistance. MaxPeakPower Register (0A4h) Specification Description: The fuel gauge computes and returns the maximum instantaneous peak output power of the battery pack in cW, which is available for up to 10ms, given the external resistance and required minimum system voltage. The MaxPeakPower value is expected to be negative and is updated every 351mS. MaxPeakPower is initialized to the present value of MaxPeakPower on reset or power-up. The system designer should limit the actual maximum peak power to account for various system limitations, such as limiting the cell discharge current to the 2C rate and allowing for the safe operating area specifications for devices in the power path, such as MOSFETs. LSB is 0.8mW. Actual Calculation: MaxPeakPower = MPPCurrent x AvgVCell SusPeakPower Register (0A5h) Specification Description: The fuel gauge computes and returns the sustained peak output power of the battery pack in cW, which is available for up to 10s, given the external resistance and required minimum voltage of the voltage regulator. The SusPeakPower value is expected to be negative and is updated every 351mS. SusPeakPower is initialized to the present value of SusPeakPower on reset or power-up. The system designer should limit the actual sustained peak power to account for various system limitations, such as limiting the cell discharge current to the 2C rate and allowing for the safe operating area specifications for devices in the power path, such as MOSFETs. LSB is 0.8mW. www.analog.com Analog Devices | 134 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector Actual Calculation: SusPeakPower = SPPCurrent x AvgVCell sPackResistance (0A6h) and nPackResistance (1C5h) Specification Description: This function reports the total noncell pack resistance value to account for the resistances due to cell interconnect, sense resistor, FET, fuse, connector, and other impedances between the cells and output of the battery pack. The cell internal resistance should NOT be included. PackResistance is set at time of pack manufacture. Writes to this value do not affect the value during normal operation. This value is usually determined by the battery pack manufacturer and set at time of pack manufacture. The pack-maker can configure PackResistance by programming the nonvolatile nPackResistance during production. LSB of 1mΩ per LSB. SysResistance (0A7h) Specification Description: The SysResitance register configures the total resistance value into fuel gauge to account for the resistances due to the resistance of power/ground metal, sense resistor, FET, and other parasitic resistance on the system main board. SysResistance is initialized to a default value of 0mΩ. The system designer is expected to overwrite the default value with the value from the system in question. This allows a single pack to be used in multiple systems which can have various values for SysResistance. LSB of 0.2441mΩ per LSB MinSysVoltage() (0A8h) Specification Description: The MinSysVoltage register configures the required minimum system input voltage in mV into the fuel gauge. The system regulator still operates normally if its input voltage is at this level. MinSysVoltage is initialized to a default value from the upper byte of the nDesignVoltage register at power up. Table 114 shows the register format for nDesignVoltage. The system designer can write the MinSysVoltage register directly during normal operation to change from the default setting. This allows a single pack to be used in multiple systems, which may have various values for MinSysVoltage. Writing MinSysVoltage above or below the empty point should not change the empty point. However, calculations for MPPCurrent, SPPCurrent, MaxPeakPower, and SusPeakPower reports 0x0000 when VCell is less than the MinSysVoltage. For accurate performance, the system should normally update MinSysVoltage according to its requirements. MPPCurrent (0A9h) Register Type: Current Specification Description: The fuel gauge computes and returns the maximum instantaneous peak current of the battery pack in the standard current register format, which is available for up to 10ms, given the external resistance and required minimum voltage of the voltage regulator. The MPPCurrent value is expected to be negative and has to be updated at least once every second. MPPCurrent is initialized to the present value of MPPCurrent on reset or power-up. Actual Calculation: MPPCurrent = (AvgVCell - MinSySVoltage) / [(PackResistance + SysResistance) x Rgain1] SPPCurrent (0AAh) Register Type: Current Specification Description: The fuel gauge computes and returns the sustained peak current of the battery pack in the standard current register www.analog.com Analog Devices | 135 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector format, which is available for up to 10s, given the external resistance and required minimum system voltage. The SPPCurrent value is expected to be negative and has to be updated at least once every second. SPPCurrent is initialized to the present value of SPPCurrent on reset or power-up. Actual Calculation: SPPCurrent = (AvgVCell - MinSySVoltage) / (RCell x Rgain2) SHA-256 Authentication The MAX17330 supports authentication which is performed using a FIPS 180-4 compliant SHA-256 one-way hash algorithm on a 512-bit message block. The message block consists of a 160-bit secret, a 160-bit challenge, and 192 bits of constant data. Optionally, the 64-bit ROM ID replaces 64 of the 192 bits of constant data used in the hash operation. Contact Analog Devices for details of the message block organization. The host and the IC both calculate the result based on the mutually known secret. The result of the hash operation is known as the message authentication code (MAC) or message digest. The MAC is returned by the IC for comparison to the host’s MAC. Note that the secret is never transmitted on the bus and thus cannot be captured by observing bus traffic. Each authentication attempt is initiated by the host system by writing a 160-bit random challenge into the SHA memory address space 0C0h to 0C9h. The host then issues the compute MAC or compute MAC with ROM ID command. The MAC is computed per FIPS 180-4 and stored in address space 0C0h to 0CFh, overwriting the challenge value. The MAX17330 also provides a 2-stage authentication scheme that utilizes a temporary secret. Note that the results of the authentication attempt are determined by host verification. Operation of the IC is not affected by authentication success or failure. Authentication Procedure Figure 27 shows how a host system verifies the authenticity of a connected battery. The host first generates a random 160-bit challenge value and writes the challenge to IC memory space 0C0h to 0C9h. The host then sends the Compute MAC with ROM ID (3500h) or Compute MAC without ROM ID (3600h) to the Command register 060h and waits tSHA for computation to complete. Finally, the host reads the MAC from memory space 0C0h to 0CFh to verify the result. This procedure requires the secret to be maintained on the host side as well as in the battery. The host must perform the same calculations in parallel to verify that the battery is authentic. www.analog.com Analog Devices | 136 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector Procedure to Verify a Battery RANDOM CHALLENGE GENERATION SECRET SECRET PARALLEL COMPUTATION VERIFICATION MACs MATCH ACCEPT BATTERY MAC COMPUTATION BATTERY MACs DO NOT MATCH REJECT BATTERY HOST Figure 27. Procedure to Verify a Battery Alternate Authentication Procedure Figure 28 shows an alternative method of battery authentication that does not require the host to know the secret. In this method, each host device knows a challenge and MAC pair that matches the secret stored in an authentic battery, but each host device uses a different pair. This eliminates the need for special hardware on the host side to protect the secret from hardware intrusion. A battery could be cloned for a single host device, but creating a clone battery that works with any host would not be possible without knowing the secret. The authentication process for this method is less complex. The host simply writes the challenge to IC memory space 0C0h to 0C9h. The host then sends the Compute MAC without ROM ID (3600h) command to the Command register 060h. Note that the Compute MAC with ROM ID command is not valid for this authentication method. The host then waits tSHA for the computation to complete and reads the MAC from memory space 0C0h to 0CFh to verify the result. www.analog.com Analog Devices | 137 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector Battery Authentication without a Host Side Secret CHALLENGE 1 MAC COMPUTATION MAC 1 VERIFICATION PASS FAIL SECRET VALID BATTERY HOST 1 CHALLENGE 2 MAC COMPUTATION MAC 2 VERIFICATION PASS FAIL SECRET VALID BATTERY HOST 2 CHALLENGE N MAC COMPUTATION MAC N VERIFICATION PASS FAIL SECRET VALID BATTERY HOST N Figure 28. Battery Authentication without a Host Side Secret Secret Management The secret value must be programmed to a known value before performing authentication in the application. The secret cannot be written directly. Instead, the user must generate a new internal secret by performing a SHA computation with the old internal secret and a seed value sent as a challenge. To prevent any one entity from knowing the complete secret value, the process can be repeated multiple times by sending additional challenge seeds and performing additional computations. www.analog.com Analog Devices | 138 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector Note that programming the Secret should be done at the factory before connecting the battery as 5.5V is required at the BATT pin of the IC to update the Secret in NVM. Note that secret memory can only be changed a maximum of nSECRET times including erase operations, and nonvolatile memory updates are not guaranteed. See the nSECRET write limit in the Electrical Characteristics table. Any secret update operation that fails does not change the secret value stored in the IC but consumes one of the available limited updates. Be careful not to use up all secret memory during the generation process. Maxim Integrated strongly recommends permanently locking the secret after it has been generated. Single-Step Secret Generation The single-step secret generation procedure should be used in production environments where the challenge seed value can be kept confidential, for example when there are no OEM manufacturing steps or situations where an outside individual or organization would need to know the challenge seed. Use the following sequence to program the IC. Since the secret cannot be read from the IC, a parallel computation must be performed externally to calculate the stored secret. Figure 29 shows an example of a single-step secret generation operation. Note that new units have their secret value already cleared to all 0s. Also note that programming the Secret should be done at the factory before connecting the battery as 5.5V is required at the BATT pin of the IC to update the Secret in NVM. 1. Clear the CommStat.NVError bit. 2. Write a challenge seed value to the SHA memory space 0C0h to 0C9h. 3. Write Compute Next Secret with ROM ID 3300h or Compute Next Secret without ROM ID 3000h to the Command register 060h. 4. Wait tSHA + tUPDATE for the computation to complete and the new secret to be stored. 5. If CommStat.NVError is set, return to step 1; otherwise, continue. 6. Verify that the secret has been generated correctly with a test challenge at this time. If verification fails, return to step 1. See the Determining Number of Remaining Updates section to verify that enough nonvolatile memory writes remain to repeat the process. 7. Write Lock Secret 6000h to the Command register 060h. Note that this operation cannot be reversed. 8. Wait tUPDATE for the secret to lock permanently. Single-Step Secret Generation Example SEED COMPUTE NEXT PARALLEL COMPUTATION STARTING SECRET CLEARED TO ALL 0s FINAL SECRET BATTERY FINAL SECRET Figure 29. Single-Step Secret Generation Example www.analog.com Analog Devices | 139 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector Multi-Step Secret Generation Procedure The multi-step secret generation procedure should be used in environments where an outside individual or organization would need to know the challenge seed such as OEM manufacturing. The multi-step procedure is more complicated but allows a secret to be stored inside the IC without providing any information to an OEM that could jeopardize secret integrity. Figure 30 shows an example where three OEMs are each provided with a seed value for a Compute Next operation. The final secret value stored inside the IC is known only to the top-level manager who knows all seed values and has performed the computation separately. Use the following procedures when generating a multi-step secret. Note that the secret can only be updated or cleared nSECRET times total. New units have their secret value already cleared to all 0s. Also, note that programming the Secret should be done at the factory before connecting the battery as 5.5V is required at the BATT pin of the IC to update the Secret in NVM. All OEMs: 1. Clear the CommStat.NVError bit. 2. Write challenge seed value to the SHA memory space 0C0h to 0C9h. 3. Write Compute Next Secret with ROM ID 3300h or Compute Next Secret without ROM ID 3000h to the Command register 060h. 4. Wait tSHA + tUPDATE for the computation to complete and the new secret to be stored. 5. If CommStat.NVError is set, return to step 1; otherwise, continue. 6. Verify that the secret has been generated correctly with a test challenge at this time. If verification fails, return to step 1. See the Determining Number of Remaining Updates section to verify that enough nonvolatile memory writes remain to repeat the process. Last OEM: 1. Follow the previous procedure for the final secret update. 2. Write Lock Secret 6000h to the Command register 060h. Note that this operation cannot be reversed. 3. Wait tUPDATE for the secret to lock permanently. Top Level: 1. Generate all seed values to provide to OEMs. 2. Perform SHA calculations separately to determine what the final secret is after all manufacturing steps. 3. Keep the final secret value secure. www.analog.com Analog Devices | 140 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector Multi-Step Secret Generation Example SEED 1 GENERATION SEED 1 MIDDLE SECRET 1 COMPUTATION CHALLENGE 1 AND MAC 1 FOR VERIFICATION COMPUTE NEXT STARTING SECRET CLEARED TO ALL 0s MIDDLE SECRET 1 TOP LEVEL PROJECT MANAGER OEM 1 BATTERY SEED 3 GENERATION SEED 2 MIDDLE SECRET 2 COMPUTATION CHALLENGE 2 AND MAC 2 FOR VERIFICATION COMPUTE NEXT MIDDLE SECRET 1 MIDDLE SECRET 2 OEM 2 BATTERY SEED 3 GENERATION SEED 3 FINAL SECRET CHALLENGE 3 AND MAC 3 FOR VERIFICATION OEM 3 COMPUTE NEXT MIDDLE SECRET 2 FINAL SECRET BATTERY Figure 30. Multi-Step Secret Generation Example 2-Stage Authentication Scheme The MAX17330 provides a 2-stage authentication scheme that utilizes a temporary secret for an added layer of security. Figure 31 illustrates how to create a unique intermediate secret that can be stored in the host at the factory. Figure 32 outlines the procedure to complete the 2-stage authentication. The following procedure implements the 2-stage authentication scheme: 1. Write Copy Temporary Secret from NVM command 3800h to the Command register 060h. 2. Write unique challenge seed value to the SHA memory space 0C0h to 0C9h to be used to compute the next temporary secret. 3. Write Compute Next Temporary Secret with ROM ID 3900h or Compute Next Temporary Secret without ROM ID 3A00h to the Command register 060h. 4. Wait tSHA for the computation to complete. www.analog.com Analog Devices | 141 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector 5. Write challenge seed value to the SHA memory space 0C0h to 0C9h to be used to compute the MAC using the temporary secret. 6. Write Compute MAC From Temporary Secret with ROM ID 3D00h or Compute MAC From Temporary Secret without ROM ID 3C00h to the Command register 060h. 7. Wait tSHA for the computation to complete. 8. Read the MAC from SHA memory space 0C0h to 0CFh to verify the result. Because the temporary secret is stored in the same RAM location used for SHA calculation, executing some commands overwrites the temporary secret. The functional impact is summarized as follows. ● Compute MAC and Compute Next Secret commands overwrite the temporary secret. ● Copy temporary secret from NVM overwrites the temporary secret (as expected). ● Compute MAC from temporary secret also overwrites the temporary secret. If a temporary secret is used for multiple MAC calculations, the temporary secret needs to be reconstructed after each MAC computation. Create a Unique Intermediate Secret SECRET UNIQUE CHALLENGE COMPUTE NEXT SECRET UNIQUE INTERMEDIATE SECRET FACTORY (ONCE PER HOST) Figure 31. Create a Unique Intermediate Secret www.analog.com Analog Devices | 142 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector Procedure for 2-Stage Authentication UNIQUE INTERMEDIATE SECRET UNIQUE CHALLENGE STEP 1 COMPUTE NEXT TEMPORARY SECRET SECRET UNIQUE INTERMEDIATE SECRET RANDOM CHALLENGE GENERATION STEP 2 PARALLEL COMPUTATION STEP 3 VERIFICATION MACs MATCH ACCEPT BATTERY MAC COMPUTATION FROM TEMPORARY SECRET BATTERY MACs DO NOT MATCH REJECT BATTERY HOST Figure 32. Procedure for 2-Stage Authentication Determining Number of Remaining Updates The internal secret can only be updated or cleared nSECRET times total. The number of remaining updates can be calculated using the following procedure: 1. Write 0xE29D to the Command register (060h). 2. Wait tRECALL. 3. Read memory address 1FDh. 4. Decode address 1FDh data as shown in Table 123. Each secret update has redundant indicator flags for reliability. www.analog.com Analog Devices | 143 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector Logically OR the upper and lower bytes together, then count the number of 1s to determine how many updates have already been used. The first update occurs in a manufacturing test to clear the secret memory before shipping to the user. Table 123. Number of Remaining Secret Updates ADDRESS 0E6H DATA LOGICAL OR OF UPPER AND LOWER BYTES NUMBER OF UPDATES USED NUMBER OF UPDATES REMAINING 0000000x00000001b or 00000001b 1 5 00000011b 2 4 00000111b 3 3 00001111b 4 2 00011111b 5 1 00111111b 6 0 000000010000000xb 000000xx0000001xb or 0000001x000000xxb 00000xxx000001xxb or 000001xx00000xxxb 0000xxxx00001xxxb or 00001xxx0000xxxxb 000xxxxx0001xxxxb or 0001xxxx000xxxxxb 00xxxxxx001xxxxxb or 001xxxxx00xxxxxxb Authentication Commands All SHA authentication commands are written to memory address 060h to perform the desired operation. Writing the challenge or reading the MAC is handled by accessing the SHA memory space on page 0Ch through direct read and write operations. COMPUTE MAC WITHOUT ROM ID [3600h] The challenge value must be written to the SHA memory space before performing a Compute MAC command. This command initiates a SHA-256 computation without including the ROM ID in the message block. Instead, the ROM ID portion of the message block is replaced with a value of all 1s. Since the ROM ID is not used, this command allows the use of a master secret and MAC response independent of the ROM ID. The IC computes the MAC in tSHA after receiving the last bit of this command. After the MAC computation is complete, the host can read the MAC from the SHA memory space. COMPUTE MAC WITH ROM ID [3500h] The challenge value must be written to the SHA memory space before performing a Compute MAC command. This command is structured the same as the compute MAC without ROM ID, except that the ROM ID is included in the message block. With the unique ROM ID included in the MAC computation, the MAC is unique to each unit. After the MAC computation is complete, the host can read the MAC from the SHA memory space. COMPUTE NEXT SECRET WITHOUT ROM ID [3000h] This command initiates a SHA-256 computation and uses the resulting MAC as the next or new secret. The hash operation is performed with the current 160-bit secret and the new 160-bit challenge. Logical 1s are loaded in place of the ROM ID. The last 160 bits of the MAC are used as the new secret value. The host must allow tSHA after issuing this command for the SHA calculation to complete, then wait tUPDATE for the new secret value to be stored in nonvolatile memory. During this operation, the SHA memory space is not updated. Note that the old secret value must be known before executing this command to calculate what the new secret value is. Also, note that programming the Secret should www.analog.com Analog Devices | 144 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector be done at the factory before connecting the battery as 5.5V is required at the BATT pin of the IC to update the Secret in NVM. COMPUTE NEXT SECRET WITH ROM ID [3300h] This command initiates a SHA-256 computation and uses the resulting MAC as the next or new secret. The hash operation is performed with the current 160-bit secret, the 64-bit ROM ID, and the new 160-bit challenge. The last 160 bits of the output MAC are used as the new secret value. The host must allow tSHA after issuing this command for the SHA calculation to complete, then wait tUPDATE for the new secret value to be stored in nonvolatile memory. During this operation, the SHA memory space is not updated. Note that the old secret value must be known before executing this command to calculate what the new secret value is. Also, note that programming the Secret should be done at the factory before connecting the battery as 5.5V is required at the BATT pin of the IC to update the Secret in NVM. CLEAR SECRET [5A00h] This command sets the 160-bit secret to all 0s. The host must wait tUPDATE for the IC to write the new secret value to nonvolatile memory. This command uses up one of the secret write cycles. LOCK SECRET [6000h] This command write protects the secret preventing accidental or malicious overwrite of the secret value. The secret value stored in nonvolatile memory becomes permanent. The host must wait tUPDATE for the lock operation to complete. SHA-256 Lock state is not shown in the Lock register. The lock state can be verified by reading nonvolatile memory history using the following sequence: 1. Send 0xE29B to the Command register (060h). 2. Wait for tRECALL. 3. Read memory address 1FCh. If address 1FCh is 0x0000, then the secret is not locked. If address 1FCh is anything other than 0x0000, then the secret is permanently locked. COPY TEMPORARY SECRET FROM NVM [3800] This command copies the secret from NVM and places it in RAM to allow the secret to be used by the other commands. COMPUTE NEXT TEMPORARY SECRET WITH ROMID [3900] This command is similar to COMPUTE NEXT SECRET WITH ROMID except the secret used in the computation comes from the previously executed COPY TEMPORARY SECRET FROM NVM or COMPUTE NEXT TEMPORARY SECRET WITH/WITHOUT ROMID and the next secret is placed in RAM so it can be used in subsequent commands. COMPUTE NEXT TEMPORARY SECRET WITHOUT ROMID [3A00] This command is similar to COMPUTE NEXT SECRET WITHOUT ROMID except the secret used in the computation comes from the previously executed COPY TEMPORARY SECRET FROM NVM or COMPUTE NEXT TEMPORARY SECRET WITH/WITHOUT ROMID and the next secret is placed in RAM so it can be used in subsequent commands. COMPUTE MAC FROM TEMPORARY SECRET WITHOUT ROMID [3C00] This command is the same as COMPUTE MAC WITHOUT ROMID except the secret used in the computation comes from the previously executed COPY TEMPORARY SECRET FROM NVM or COMPUTE NEXT TEMPORARY SECRET WITH/WITHOUT ROMID. COMPUTE MAC FROM TEMPORARY SECRET WITH ROMID [3D00] This command is the same as COMPUTE MAC WITH ROMID except the secret used in the computation comes from the previously executed COPY TEMPORARY SECRET FROM NVM or COMPUTE NEXT TEMPORARY SECRET WITH/ WITHOUT ROMID. Device Reset There are two different levels of reset for the IC; a full reset restores the IC to its power-up state (the same as if power had www.analog.com Analog Devices | 145 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector been cycled) and a fuel-gauge reset resets only the fuel gauge operation without resetting IC hardware. This is useful for testing different configurations without writing to nonvolatile memory. Use the following sequences to reset the IC. FULL RESET 1. Reset IC hardware by writing 000Fh to the Command register at 060h. 2. Wait 10ms. 3. Reset IC fuel gauge operation by writing 8000h to the Config2 register at 0ABh. This command does not disturb the state of the protection FETs. 4. Wait for the POR_CMD bit (bit 15) of the Config2 register to be cleared to indicate that the POR sequence is complete. FUEL-GAUGE RESET 1. Reset IC fuel gauge operation by writing 8000h to the Config2 register at 0ABh. This command does not disturb the state of the protection FETs. 2. Wait for the POR_CMD bit (bit 15) of the Config2 register to be cleared to indicate that the POR sequence is complete. Reset Commands There are two commands that can be used to reset either the entire IC or just the operation of the fuel gauge, protection, and charging configuration without interrupting the hardware (CHG, DIS FETs, or Non-Volatile Shadow Memory). Note that the configuration reset command is written to Config2 instead of the Command register. HARDWARE RESET [000Fh to address 060h] Send the hardware reset command to the Command register to recall all nonvolatile memory into shadow RAM and reset all hardware-based operations of the IC. This command should always be followed by the reset fuel gauge command to fully reset operation of the IC. CONFIGURATION RESET [8000h to address 0ABh] The Configuration Reset command resets operation of the IC without restoring nonvolatile memory values into shadow RAM or resetting the FET Control. This command allows different configurations to be tested without using one of the limited numbers of nonvolatile memory writes. This command does not disturb the state of the protection FETs. Summary of Commands Any operation other than reading or writing a memory location is executed by writing the appropriate command to the Command or Config2 registers. Table 124 lists all function commands understood by the MAX17330. The function command must be written to the Command (060h) or Config2 (0ABh) registers. Device commands are described in detail in the Authentication, Nonvolatile Memory, Reset, and Power Up sections of the data sheet. Table 124. All Function Commands COMMAND TYPE HEX DESCRIPTION 060h 3600h Computes hash operation of the message block with logical 1s in place of the ROM ID. SHA 060h 3500h Computes hash operation of the message block including the ROM ID. Compute Next Secret Without ROM ID SHA 060h 3000h Computes hash operation of the message block with logical 1s in place of the ROM ID. The result is then stored as the new secret. Compute Next Secret With ROM ID SHA 060h 3300h Computes hash operation of the message block including the ROM ID. The result is then stored as the new secret. Clear Secret SHA 060h 5A00h Resets the SHA-256 secret to a value of all 0s. Compute MAC Without ROM ID SHA Compute MAC With ROM ID Lock Secret REGISTER SHA 060h 6000h Permanently locks the SHA-256 secret. Copy NV Block Memory 060h E904h Copies all shadow RAM locations to nonvolatile memory at the same time. NV Recall Memory 060h E001h Recalls all nonvolatile memory to RAM. www.analog.com Analog Devices | 146 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector Table 124. All Function Commands (continued) COMMAND TYPE REGISTER HEX DESCRIPTION History Recall Memory 060h E2XXh Recalls a page of nonvolatile memory history into RAM page 1Eh. NV Lock Memory 060h 6AXXh Permanently locks an area of memory. See the Memory Locks section for details. Hardware Reset Reset 060h 000Fh Recalls nonvolatile memory into RAM and resets the IC hardware. Fuel gauge operation is not reset. Fuel Gauge Reset Reset 0ABh 8000h Restarts the fuel gauge operation without affecting nonvolatile shadow RAM settings. Communication 2-Wire Bus System The uses a 2-Wire bus system to communicate by both standard I2C protocol or by SBS smart battery protocol. The slave address used by the host to access the IC determines which protocol is used and what memory locations are available to read or write. The following description applies to both protocols. See the I2C and SBS Bus System descriptions for specific protocol details. Hardware Configuration The 2-Wire bus system supports operation as a slave-only device in a single or multi-slave, and single or multi-master system. Up to 128 slave devices can share the bus using 7-bit slave addresses. The 2-Wire interface consists of a serial data line (SDA) and serial clock line (SCL). SDA and SCL provide bidirectional communication between the IC and a master device at speeds up to 400kHz. The IC's SDA pin operates bidirectionally. When the IC receives data, the SDA operates as an input. When the IC returns data, the SDA operates as an open-drain output with the host system providing a resistive pullup. See Figure 33. The IC always operates as a slave device, receiving and transmitting data under the control of a master device. The master initiates all transactions on the bus and generates the SCL signal, as well as the START and STOP bits which begin and end each transaction. 2-Wire Bus Interface Circuitry VPULLUP BUS MASTER RPULLUP DEVICE 2-WIRE PORT DQ/SDA Rx DATA Rx DATA Tx DATA WEAK PULLDOWN Tx DATA Rx = RECEIVE Tx = TRANSMIT OD/SCL Tx CLOCK Rx CLOCK WEAK PULLDOWN Figure 33. 2-Wire Bus Interface Circuitry www.analog.com Analog Devices | 147 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector I/O Signaling The following individual signals are used to build byte level 2-Wire communication sequences. Bit Transfer One data bit is transferred during each SCL clock cycle, with the cycle defined by SCL transitioning low to high and then high to low. The SDA logic level must remain stable during the high period of the SCL clock pulse. Any change in SDA when SCL is high is interpreted as a START or STOP control signal. Bus Idle The bus is defined to be idle (i.e., not busy) when no master device has control. Both SDA and SCL remain high when the bus is idle. The STOP condition is the proper method to return the bus to the idle state. START and STOP Conditions The master initiates transactions with a START condition by forcing a high-to-low transition on SDA while SCL is high. The master terminates a transaction with a STOP condition by a low-to-high transition on SDA while SCL is high. A Repeated START condition can be used in place of a STOP then START sequence to terminate one transaction and begin another without returning the bus to the idle state. In multi-master systems, a Repeated START allows the master to retain control of the bus. The START and STOP conditions are the only bus activities in which the SDA transitions when SCL is high. Acknowledge Bits Each byte of a data transfer is acknowledged with an Acknowledge bit (ACK) or a No Acknowledge bit (NACK). Both the master and the IC slave generate acknowledge bits. To generate an Acknowledge, the receiving device must pull SDA low before the rising edge of the acknowledge-related clock pulse (ninth pulse) and keep it low until SCL returns low. To generate a No Acknowledge, the receiver releases SDA before the rising edge of the acknowledge-related clock pulse and leaves SDA high until SCL returns low. Monitoring the acknowledge bits allows for the detection of unsuccessful data transfers. An unsuccessful data transfer can occur if a receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master should reattempt communication. If a transaction is aborted midbyte, the master should send additional clock pulses to force the slave IC to free the bus before restarting communication. Data Order With 2-Wire communication, a byte of data consists of 8 bits ordered most significant bit (MSb) first. The least significant bit (LSb) of each byte is followed by the Acknowledge bit. IC registers composed of multibyte values are ordered least significant byte (LSB) first. Slave Address A bus master initiates communication with a slave device by issuing a START condition followed by a Slave Address and the read/write (R/W) bit. When the bus is idle, the IC continuously monitors for a START condition followed by its slave address. When the IC receives a slave address that matches its Slave Address, it responds with an Acknowledge bit during the clock period following the R/W bit. The supports the slave addresses shown in Table 125. Note: The addresses shown in Table 125 are 8-bit slave addresses. Table 125. 2-Wire Slave Addresses SLAVE ADDRESS PROTOCOL ADDRESS BYTE RANGE INTERNAL MEMORY RANGE ACCESSED 6Ch I 2C 00h to FFh 000h to 0FFh SMBUSTM 00h to 7Fh 100h to 17Fh I 2C 80h to FFh 180h to 1FFh 16h Read/Write Bit The R/W bit following the slave address determines the data direction of subsequent bytes in the transfer. R/W = 0 selects a write transaction, with the following bytes being written by the master to the slave. R/W = 1 selects a read transaction, with the following bytes being read from the slave by the master. www.analog.com Analog Devices | 148 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector Bus Timing The IC is compatible with any bus timing up to 400kHz. See the Electrical Characteristics table for timing details. No special configuration is required to operate at any speed. Figure 34 shows an example of standard 2-Wire bus timing. 2-Wire Bus Timing Diagram SDA tF tLOW tSU;DAT tR tF tHD;STA tSP tBUF tR SCL tHD;STA S tHD;DAT tSU;STA tSU;STO SR P S Figure 34. 2-Wire Bus Timing Diagram I2C Protocols The following 2-Wire communication protocols must be used by the bus master to access memory locations 000h to 1FFh. Addresses 000h to 0FFh and from 180h to 1FFh can be read continuously. Addresses 100h to 17Fh must be read one word at a time. These protocols follow the standard I2C specification for communication. I2C Write Data Protocol The Write Data protocol is used to transmit data to the IC at memory addresses from 000h to 1FFh. Addresses 000h to 0FFh and 180h to 1FFh can be written as a block. Addesses 100h to 17Fh must be written one word at a time. The memory address is sent by the bus master as a single byte value immediately after the slave address, followed by an ACK from the IC. The LSB of the data to be stored is written immediately after the memory address byte, followed by an ACK from the IC. The MSB of the data to be stored is written next, followed by an ACK from the IC. Because the address is automatically incremented after the least significant bit (LSb) of the MSB of each word received by the IC, the LSB of the data at the next memory address can be written immediately after the acknowledgment of the MSB of data at the previous address. The master indicates the end of a write transaction by sending a STOP or Repeated START after receiving the last acknowledge bit. If the bus master continues an auto-incremented write transaction beyond address 0FFh or 1FFh, the IC ignores the data. Data is also ignored on writes to read-only addresses but not reserved addresses. Do not write to reserved address locations. See Figure 35 for an example Write Data communication sequence. www.analog.com Analog Devices | 149 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector ACK DATA N MSB STOP DATA1 LSB ACK DATA0 MSB ACK DATA0 LSB ACK ACK MEMORY ADDRESS ACK SLAVE ADDRESS W/R =0 START WRITE DATA COMMUNICATION PROTOCOL = SLAVE TRANSMISSION ACK COMMAND MSB STOP COMMAND LSB ACK 60h (MEMORY ADDRESS) ACK 6Ch (SLAVE ADDRESS) ACK START EXAMPLE WORD WRITE TO I2C COMMAND REGISTER ADDRESS 060h = HOST TRANSMISSION Figure 35. Example I2C Write Data Communication Sequence I2C Read Data Protocol The Read Data protocol is used to transmit data from IC memory locations 000h to 1FFh. Addresses 000h to 0FFh and 180h to 1FFh can be read as a block. Addresses 100h to 17Fh must be read as individual words. The memory address is sent by the bus master as a single-byte value immediately after the slave address. Immediately following the memory address, the bus master issues a REPEATED START followed by the slave address. The MAX17330 ACKs the address and begins transmitting data. A word of data is read as two separate bytes that the master must ACK. The LSB is read first, followed by an ACK from the master. The MSB is read next, followed by an ACK from the master. Because the address is automatically incremented after the least significant bit (LSb) of the MSB of each word transmitted by the IC, the LSB of the data at the next memory address can be read immediately after the acknowledgment of the MSB of data at the previous address. The master indicates the end of a read transaction by sending a NACK followed by a STOP. If the bus master continues an auto-incremented read transaction beyond memory address 0FFh or 1FFh, the IC transmits all 1s until a NACK or STOP is received. Data from reserved address locations is undefined. See Figure 36 for an example Read Data communication sequence. STOP IntTemp MSB DATA N MSB NACK ACK AvgCurrent LSB NACK DATA0 MSB ACK ACK Current MSB ACK DATA1 LSB ACK DATA0 LSB ACK ACK SLAVE ADDRESS W/R =1 (REPEATED) ACK MEMORY ADDRESS START ACK SLAVE ADDRESS W/R =0 START I2C READ DATA COMMUNICATION PROTOCOL STOP AvgCurrent MSB NACK Current LSB ACK 6Dh (SLAVE READ ADDRESS) ACK (REPEATED) ACK 1Ch (MEMORY ADDRESS) START 6Ch (SLAVE WRITE ADDRESS) ACK START EXAMPLE READ DATA OF CURRENT AND AVGCURRENT REGISTERS ADDRESS 01Ch-01Dh = SLAVE TRANSMISSION IntTemp LSB STOP 17h (SLAVE READ ADDRESS) ACK (REPEATED) ACK 35h (MEMORY ADDRESS) START 16h (SLAVE WRITE ADDRESS) ACK START EXAMPLE READ DATA OF INTTEMP REGISTER ADDRESS 135h = HOST TRANSMISSION Figure 36. Example I2C Read Data Communication Sequence www.analog.com Analog Devices | 150 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector SBS Protocols The following 2-Wire communication protocols must be used by the bus master to access memory locations 100h to 17Fh. These protocols follow the smart battery specification for communication. SBS Write Word Protocol The Write Word protocol is used to transmit data to IC memory addresses between 100h and 17Fh that do not require the Write Block protocol. The memory address is sent by the bus master as a single byte LSB value immediately after the slave address and the MSb of the address is omitted. The LSB of the data to be stored is written immediately after the memory address byte is acknowledged, followed by the MSB. A PEC byte can follow the data word, but the data word is written without checking the validity of the PEC. The master indicates the end of a write transaction by sending a STOP or Repeated START after receiving the last acknowledge bit. Data is ignored on writes to read-only addresses but not reserved addresses. Do not write to reserved address locations. The Write Word protocol should not be used to write to addresses supported by the Write Block protocol, use Write Block at these locations instead. See Figure 37 for an example Write Word communication sequence. Example SBS Write Word Communication Sequence ACK STOP ACK PEC (OPTIONAL) STOP DATA MSB ACK DATA LSB ACK MEMORY ADDRESS ACK ACK SLAVE ADDRESS W/R =1 START SBS WRITE WORD COMMUNICATION PROTOCOL = SLAVE TRANSMISSION DATA MSB ACK DATA LSB ACK 04h (MEMORY ADDRESS) ACK 16h (SLAVE ADDRESS) ACK START EXAMPLE WORD WRITE TO SBS ATRATE REGISTER AT REGISTER ADDRESS 104h PEC (OPTIONAL) = HOST TRANSMISSION Figure 37. Example SBS Write Word Communication Sequence SBS Read Word Protocol The Read Word protocol is used to read data from the IC at memory addresses between 100h and 17Fh. The memory address is sent by the bus master as a single byte LSB value immediately after the slave address and the MSb of the address is ignored. The LSB of the data is read immediately after the memory address byte is acknowledged, followed by the MSB. A PEC byte follows the data word. The master indicates the end of a write transaction by sending a STOP or Repeated START after not acknowledging the last received byte. Data from reserved address locations is undefined. The Read Word protocol should not be used to read from addresses supported by the Read Block protocol, use Read Block at these locations instead. See Figure 38 for an example Read Word communication sequence. www.analog.com Analog Devices | 151 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector Example SBS Read Word Communication Sequence STOP ACK (OPTIONAL) NACK sTEMPERATURE LSB PEC STOP ACK (OPTIONAL) NACK ACK DATA MSB ACK DATA LSB ACK SLAVE ADDRESS W/R =0 (REPEATED) START MEMORY ADDRESS ACK ACK SLAVE ADDRESS W/R =1 START SBS READ WORD COMMUNICATION PROTOCOL = SLAVE TRANSMISSION 17h ACK (REPEATED) 08h (MEMORY ADDRESS) START (SLAVE WRITE ADDRESS) ACK 16h ACK START EXAMPLE READ WORD OF SBS sTEMPERATURE REGISTER ADDRESS 108h (SLAVE READ ADDRESS) sTEMPERATURE LSB PEC = HOST TRANSMISSION Figure 38. Example SBS Read Word Communication Sequence SBS Write Block Protocol The SBS Write Block protocol is not supported by the MAX17330. Use the Write Data command sequence to the corresponding nonvolatile memory locations to update Write/Read Block register locations. See Table 119. SBS Read Block Protocol The Read Block protocol is similar to the Read Word protocol except that the master reads multiple words of data at once. A data size byte is transmitted by the IC immediately after the memory address byte and before the first byte of data to be read. The Read Block protocol is only supported at the register locations shown in Table 126. PEC error checking is provided by the Read Block protocol if nNVCfg0.enSBS = 1. Figure 39 shows an example Read Block communication sequence. Example SBS Read Block Communication Sequence STOP (Optional) NACK DATA3 STOP ACK (Optional) NACK DATA (size-2) ACK DATA0 PEC ACK DATA0 ACK 05h ACK SIZE ACK ACK SLAVE ADDRESS W/R =0 (REPEATED) ACK MEMORY ADDRESS START ACK SLAVE ADDRESS W/R =1 START SBS READ BLOCK COMMUNICATION PROTOCOL = SLAVE TRANSMISSION 17h (SLAVE READ ADDRESS) ACK (REPEATED) ACK 22h (MEMORY ADDRESS) START 16h (SLAVE WRITE ADDRESS) ACK START Example Block Read of SBS DevChemistry Register Address 122h (Size) PEC = HOST TRANSMISSION Figure 39. Example SBS Read Block Communication Sequence www.analog.com Analog Devices | 152 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector Valid SBS Read Block Registers Table 126. Valid SBS Read Block Registers ADDRESS REGISTER SIZE BYTE MAX VALUE FORMAT 0120h sManfctName 0Ah ASCII String 0121h sDeviceName 0Ch ASCII String 0122h sDevChemistry 05h ASCII String 0123h sManfctData 1Ah Hexadecimal 011Ch sSerialNumber 08h Hexadecimal 0170h sManfctInfo 18h Hexadecimal Packet Error Checking SBS read functions support packet error checking (PEC) if nNVCfg0.enSBS is enabled. The host system is responsible for verifying the CRC value it receives and then taking action as a result. SBS write functions accept a PEC byte but complete the write function regardless of the value of the PEC. The CRC can be generated by the host using a circuit consisting of a shift register and XOR gates as shown in Figure 40, or it can be generated with software using the polynomial X8 + X2 + X1 + 1. Refer to the Smart Battery Data Specification for more information. PEC CRC Generation Block Diagram INPUT MSb XOR XOR LSb XOR Figure 40. PEC CRC Generation Block Diagram www.analog.com Analog Devices | 153 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector Appendix A: Reading History Data Pseudo-Code Example The following pseudo-code can be used as a reference for reading history data from the IC. The code first reads and tests all flag information, then reads all valid history data into a two-dimensional array. Afterwards, the HistoryLength variable indicates the depth of the history array data. Int WriteFlags[26]; Int ValidFlags[26]; Boolean PageGood[100]; Int HistoryData[100][16]; Int HistoryLength; Int word, position, flag1, flag2, flag3, flag4; //Read all flag information from the IC WriteCommand(0xE29C); Wait(tRECALL); WriteFlags[0] = ReadData(0x1F2); WriteFlags[1] = ReadData(0x1F3); WriteFlags[2] = ReadData(0x1F4); WriteFlags[3] = ReadData(0x1F5); WriteFlags[4] = ReadData(0x1F6); WriteFlags[5] = ReadData(0x1F7); WriteFlags[6] = ReadData(0x1F8); WriteFlags[7] = ReadData(0x1F9); WriteFlags[8] = ReadData(0x1FA); WriteFlags[9] = ReadData(0x1FB); WriteFlags[10] = ReadData(0x1FC); WriteFlags[11] = ReadData(0x1FD); WriteFlags[12] = ReadData(0x1FE); ValidFlags[0] = ReadData(0x1FF); WriteCommand(0xE29D); Wait(tRECALL); ValidFlags[1] = ReadData(0x1F0); ValidFlags[2] = ReadData(0x1F1); ValidFlags[3] = ReadData(0x1F2); ValidFlags[4] = ReadData(0x1F3); ValidFlags[5] = ReadData(0x1F4); ValidFlags[6] = ReadData(0x1F5); ValidFlags[7] = ReadData(0x1F6); ValidFlags[8] = ReadData(0x1F7); ValidFlags[9] = ReadData(0x1F8); ValidFlags[10] = ReadData(0x1F9); ValidFlags[11] = ReadData(0x1FA); www.analog.com Analog Devices | 154 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector ValidFlags[12] = ReadData(0x1FB); //Determine which history pages contain valid data For loop = 0 to 99 { word = (int)( loop / 8 ); position = loop % 8 ; //remainder flag1 = (WriteFlags[word] >> position) & 0x0001; flag2 = (WriteFlags[word] >> (position+8)) & 0x0001; flag3 = (ValidFlags[word] >> position) & 0x0001; flag4 = (ValidFlags[word] >> (position+8)) & 0x0001; if (flag1 || flag2) && (flag3 || flag4) PageGood[loop] = True; else PageGood[loop] = False; } //Read all the history data from the IC HistoryLength = 0; For loop = 0 to 99 { if(PageGood[loop]) == TRUE { SendCommand(0xE22E + loop); Wait(tRECALL); HistoryData[HistoryLength][0] = ReadData(0x1F0); ... HistoryData[HistoryLength][15] = ReadData(0x1FF); HistoryLength++; } } Appendix B: Parallel Cell Management Example The following pseudo-code can be used as a reference for managing parallel batteries. HOST PSEUDOCODE (on 500ms timer): def on_500ms_timer(): if(all(AllBatts.FProtStat.IsDis==0)): VMax = max(AllBatts.VCell) VMin = min(AllBatts.VCell) stepDown=stepUp=CrossCharge=False if(VMinVMin+400mV and !CrossCharge): Batt.Config2.BlockDis=1 www.analog.com #1 #2 #3 Analog Devices | 155 MAX17330 else: Batt.Config2.BlockDis=0 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector #4 if (Status.CA): if (Batt.ChgStat.[CP,CT]): stepDown=True elif(Batt.ChgStat.Dropout): stepUp =True Status=0xF7FF #7 if(stepDown): step DC-DC down elif(stepUp): step DC-DC up #5 #6 #8 Notes: 1) Evaluate the minimum voltage battery for the ability to support system discharge. When the cell is too low, unplugging the charge source would result in a crash except if cross-charging is allowed 2) Indicate charger presense to all batteries (even blocked batteries) 3) Determine which batteries to block-discharge, to avoid cross-charging 4) Allow discharging if the low battery is much lower than the full battery or the low battery is below VSys_Min 5) Consider FET heat: (DC-DC voltage down) 6) Consider dropout: (DC-DC voltage up) 7) Clear Charge Alert bit 8) Optional: apply DC-DC update Applications: 1) Low-Power Parallel Charging (500mA total). The application must have a programmable DC-DC converter supplying power to the MAX17330 ICs. www.analog.com Analog Devices | 156 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector Typical Application Circuits Typical Application Schematic N N CSN CSP 100Ω CHG 1kΩ DIS 1kΩ PFAIL 100Ω PCKP 0.1µF OPTIONAL ZVC 22nF SYS+ 1nF CP OPTIONAL TH2 10Ω ZVC/TH2 BATT 0.1µF MAX17330 150Ω ALRT 4.7V SDA/DQ TH1 REG2 GND 1.8V SCL 150Ω 4.7V 4.7V 150Ω 0.47µF SYS– www.analog.com Analog Devices | 157 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector Typical Application Circuits (continued) Typical Application Schematic with Fuse N CSN N CSP 100Ω CHG 1kΩ DIS 1kΩ PFAIL 100Ω PCKP 0.1µF 1nF CP OPTIONAL TH2 10Ω ZVC/TH2 BATT 0.1µF MAX17330 150Ω ALRT SDA/DQ TH1 REG2 GND 1.8V OPTIONAL ZVC 22nF SYS+ N 3 TERM FUSE SCL 4.7V 150Ω 4.7V 4.7V 150Ω 0.47µF SYS– www.analog.com Analog Devices | 158 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector Typical Application Circuits (continued) N Pushbutton Schematic N CHG DIS ALRT/PIO SYSPWR SYSTEM PMIC MAX1733x BUTTON PUSH BUTTON 1.8V (VIO) OPTIONAL PULLUP SYSTEM AP N A pushbutton can be shared by the MAX17330 and the system to wake up both the system and the MAX17330. The diode on the system interface PMIC blocks the pulldown when there is no supply, which prevents the wakeup for the MAX17330 when the system interface PMIC loses power in ship mode. The diode on the ALRT/PIO pin prevents the alert pulldown from triggering a button action on the PMIC, which prevents accidental shutdown in the event of an alert being uncleared for greater than ten seconds. The FET between MAX17330 and System AP blocks the System AP pulldown from triggering the wakeup when the AP doesn’t have power. The FET acts as a level shifter and passes the pulldown alert signal in both directions when 1.8V of voltage is present. www.analog.com Analog Devices | 159 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector Typical Application Circuits (continued) Typical Application Schematic for System Side Implementaiton N N CSN CSP 100Ω CHG 1kΩ DIS 1kΩ PFAIL PCKP 0.1µF 100Ω OPTIONAL ZVC 22nF SYS+ 1nF CP ZVC/TH2 BATT 0.1µF MAX17330 OPTIONAL TH2 10Ω ALRT SDA/DQ TH1 SCL REG2 GND 1.8V 0.47µF SYS– Ordering Information INTERFACE PIN-PACKAGE MAX17330X22+ PART I 2C 15 WLP MAX17330X22+T I 2C 15 WLP +Denotes a lead(Pb)-free/RoHS-compliant package. T = Tape and reel. www.analog.com Analog Devices | 160 MAX17330 AccuCharge + ModelGauge m5 EZ 1-Cell Charger, Fuel Gauge, and Protector Revision History REVISION NUMBER REVISION DATE 0 5/21 Initial release — 4/23 Updated title, General Description, Table 6, and Table 83, added Zero-Volt Charge Recovery Diagram, HProtCfg2 Register, removed HConfig2 register, updated Charge Control, Parallel Battery Management, Permanent Failure, Status Register (000h), Config2 Register (0ABh), ProtAlrt Register (0AFh), nI2CCfg Register (1B4h), nProtMiscTh Register (1D6h), nDPLimit Register (1E0h), nOVPrtTh Register (1DAh), nDesignVoltage Register (1E3h), sMPPCurrent (15Eh), RCell Register (014h), nChgCfg1 Register (1CBh), Power, Enabling and Freeing Nonvolatile vs. Defaults, Nonvolatile Memory Configuration Options, Nonvolatile Block Programming, Secret Management, Single Step Secret Generation, MultiStep Secret Generation Procedure, COMPUTE NEXT SECRET WITHOUT ROM ID [3000h], COMPUTE NEXT SECRET WITH ROM ID [3300h], and Typical Application Circuit, added SBS Protocols section All 1 PAGES CHANGED DESCRIPTION Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. w w w . a n a l o g . c o m Analog Devices | 161

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