EVALUATION KIT AVAILABLE
MAX17509
4.5V–16V, Dual 3A, High-Efficiency, Synchronous Step-Down
DC-DC Converter with Resistor Programmability
General Description
The MAX17509 integrates two 3A internal switch step-down
regulators with programmable features. The device can
be configured as two single-phase independent, 3A power
supplies or as a dual-phase, single-output 6A power
supply. The device operates from 4.5V to 16V input and
generates independently adjustable output voltage in the
ranges of 0.904V to 3.782V and 4.756V to 5.048V, with
±2% system accuracy.
This device provides maximum flexibility to the end-user
by allowing to choose multiple programmable options by
connecting resistors to the configuration pins. Two key
highlights of the device are the self-configured compensation for any output voltage and the ability to program
the slew rate of LX switching nodes to mitigate noise
concerns. In noise-sensitive applications, such as highspeed multi-gigabit transceivers in FPGAs, RF, and audio
benefit from this unique slew rate control. SYNC input is
provided for synchronized operation of multiple devices
with system clocks.
MAX17509 offers output overvoltage (OV) and
undervoltage (UV) protection, as well as overcurrent
(OC) and undercurrent (UC) protection with a selectable
hiccup/latch option. It operates over the -40°C to +125°C
temperature range, with thermal sensing and shutdown
provided for overtemperature (OT) protection. The device
is available in a 32-pin 5mm x 5mm TQFN package.
Applications
●●
●●
●●
●●
FPGA and DSP Core Power
Industrial Control Equipment
Multiple Point-of-Load (POL) Power Supplies
Base Station Point-of-Load Regulator
Ordering Information appears at end of data sheet.
Features and Benefits
●● Reduces Number of DC-DC Regulators in Inventory
• Output Voltage (0.904V to 3.782V and 4.756V to
5.048V with 20mV Resolution)
• Configurable Two Independent Outputs (3A/3A) or
a Dual-Phase Single Output (6A)
●● Mitigate Noise Concerns and EMI
• Adjustable Switching Frequency with Selectable
0/180° Phase Shift
• External Frequency Synchronization
• Adjustable Switching Slew Rate
• Passes EN55022 (CISPR22) Class-B Radiated
and Conducted EMI Standard
●● Ease of System Design
• All Ceramic Capacitors Solution
• Auto-Configured Internal Compensation
• Selectable Hiccup or Brickwall Mode
• Adjustable Soft-Start Rise/Fall Time with Soft Stop
Modes and Prebias Startup
• -40°C to +125°C Operation
●● Reliable Operation
• Robust Fault Protections (VIN_UVLO, UV/OV, UC/
OC, OT)
• Power Good
Application Circuit
MAX17509
PGOOD1, 2
CVCC
CAVCC
RCOARSE1
RFINE1
RSS1
RCOARSE2
RFINE2
RSS2
RMODE
VCC
VIN
IN1
AVCC
BST1
COARSE1
CIN1
CBST1
LX1
OUT1
FINE1
SS1
L1
VIN
IN2
COARSE2
BST2
FINE2
LX2
SS2
OUT2
MODE
PGND2
EP
VOUT1
COUT1
PGND1
SGND
19-7051; Rev 0; 2/15
AVCC
EN1, 2
SYNC
CIN2
CBST2
L2
COUT2
VOUT2
MAX17509
4.5–16V, Dual 3A, High-Efficiency, Synchronous Step-Down
DC-DC Converter with Resistor Programmability
Absolute Maximum Ratings
IN_ to PGND_..........................................................-0.3V to 22V
BST_ to PGND_.......................................................-0.3V to 28V
BST_ to LX_...............................................................-0.3V to 6V
BST_ to VCC............................................................-0.3V to 22V
LX_ to PGND_....... -0.3V to the lower of +22V or (VIN_ + 0.3V)
VCC to SGND.......... -0.3V to the lower of +6V or (VIN1 + 0.3V)
AVCC to SGND........ -0.3V to the lower of +6V or (VIN1 + 0.3V)
OUT_, EN_, PGOOD_, SYNC, COARSE_, FINE_, SS_,
MODE to SGND.....................................................-0.3V to 6V
PGND_ to SGND....................................................-0.3V to 0.3V
EP to SGND..........................................................-0.3V to +0.3V
Operating Temperature Range...........................-40ºC to +125ºC
Junction Temperature.......................................................+150°C
Storage Temperature Range..............................-65ºC to +160°C
Lead Temperature (soldering, 10s).................................. +300°C
Soldering Temperature (reflow)........................................+260°C
Package Thermal Characteristics (Note 2)
32 TQFN T3255+4
Junction-to-Ambient Thermal Resistance (θJA)
Continuous Power Dissipation (TA = +70°C)
32 TQFN.......................................................................29°C/W
32 TQFN (derate 34.5 mW/°C above +70°C)
Junction-to-Case Thermal Resistance (θJC)
(multilayer board) ...................................................2758.6mW
32 TQFN......................................................................1.7°C/W
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Electrical Characteristics
(VIN_ = 10V, VOUT_ = 3.3V, CVIN_ = 1µF, CAVCC = 1µF, CVCC = 2.2µF, CBST_ = 0.1µF, TA = TJ = -40°C to +125°C, with typical
value at TA = 25°C, unless otherwise stated) (See Typical Application Circuits) (Note 1).
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
16
V
INPUT SUPPLY VIN_
IN1-2 Voltage Range
VIN_RANGE
IN1 Standby Current
IIN1_STBY
EN1-2 = SGND (shutdown)
1
1.9
mA
IN2 Standby Current
IIN2_STBY
EN1-2 = SGND (shutdown)
10
20
µA
IN1-2 Undervoltage Lockout
IN1-2 Undervoltage Lockout
for VOUT > 4.75V
4.5
VIN_UVLO_R
Rising
4.0
4.2
4.4
V
VIN_UVLO_F
Falling
3.2
3.4
3.6
V
VIN_UVLO_R
5VOUT
Rising
5.8
6.0
6.2
V
VIN_UVLO_F
5VOUT
Falling
4.1
4.3
4.5
V
1242
1262
1287
mV
ENABLES
EN_ Rising Threshold
EN_TH_R
EN_ Threshold Hysteresis
EN_TH_HYS
EN_ Input Leakage Current
EN_ILEAK
LDO
VCC Output Voltage Range
250
VEN = 5V, TA = 25°C
-100
0
mV
100
nA
VCC_RANGE
VCC Output Voltage (Dropout)
VCC Current Capability
VCC_DROP
I_VCC
6V < VIN1 < 16V
4.5
V
VIN1 = 4.5 V, IVCC = 20mA
4.3
V
VCC = 4.3V, VIN1 = 6V
50
mA
INTERNAL CHIP INPUT SUPPLY
AVCC UVLO
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AVCC_TH_R
Rising
AVCC_TH_F
Falling
3.9
3.2
V
V
Maxim Integrated │ 2
MAX17509
4.5–16V, Dual 3A, High-Efficiency, Synchronous Step-Down
DC-DC Converter with Resistor Programmability
Electrical Characteristics (continued)
(VIN_ = 10V, VOUT_ = 3.3V, CVIN_ = 1µF, CAVCC = 1µF, CVCC = 2.2µF, CBST_ = 0.1µF, TA = -40°C to +125°C with typical value at
TA = 25°C, unless otherwise stated) (See Typical Application Circuits) (Note 1).
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CONFIGURATION PINS
COARSE_, FINE_, SS_,
MODE pins Analog Resolution
#BITS_L
4
Bits
Thermal Shutdown Threshold
TW_TH
Temperature rising (Note 3)
160
°C
Thermal Shutdown Hysteresis
TW_HYS
Temperature falling (Note 3)
20
°C
SYNC_H
SYNC_L
THERMAL SHUTDOWN
SYNCHRONIZATION
SYNC Threshold Level High
SYNC Threshold Level Low
SYNC Frequency Range
1.8
V
0.6
V
SYNC_FREQ1
6V < VIN_ < 16V
0.9
1.3
MHz
SYNC_FREQ2
4.5V ≤ VIN_ ≤ 6V
0.45
2.2
MHz
Minimum SYNC Pulse Width
SYNC_PW
30
ns
SYNC Pull-Down Resistance
SYNC_PD
1
High-Side RDSon
HS_RON
For converter 1,2
50
90
mΩ
Low-Side RDSon
LS_RON
For converter 1,2
50
90
mΩ
LX_ Leakage Current
LX_LEAK
VLX = VIN – 1V, VLX = VPGND + 1V,
TA = 25°C
5
µA
BST_ On resistance
BST_RON
Note: Min BST capacitance = 10nF;
IBST = 10mA, VCC = 5V
TOFF_MIN
Set by the internal clock. (Note 2)
MΩ
POWER SWITCHES
4.5
Ω
OSCILLATOR
Minimum Off-Time
6.5
FREQ_RANGE1 1MHz; 6V < VIN_ < 16V
Frequency Range
FREQ_RANGE2
500kHz, 1MHz, 1.5MHz, 2MHz;
4.5V ≤ VIN_ ≤ 6V
1000
%TSW
kHz
500
2000
kHz
Frequency Accuracy
FREQ_1MHZ
FSW = 1MHz
969
1030
kHz
Frequency Accuracy Range 1
FREQ_ACC1
FSW = 500kHz and 2MHz
-3.1
+3
%
Frequency Accuracy Range 2
FREQ_ACC2
FSW = 1.5MHz. (Note 3)
-4
+4
%
OUTPUT VOLTAGE
VOUT_0.9V
No load output voltage accuracy
T = 25°C; VOUT = 0.9V;
4.5V < VIN_ < 16V. COARSE_ = 0010;
FINE_ = 1101.
0.8927
0.9045
0.9166
V
VOUT_1.2V
No load output voltage accuracy
T = -40°C to 125°C; VOUT = 1.2V;
4.5V < VIN_ < 16V COARSE_ = 0011;
Fine_ = 1100
1.1750
1.1990
1.2230
V
VOUT1-2 Output Voltage
Accuracy
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Maxim Integrated │ 3
MAX17509
4.5–16V, Dual 3A, High-Efficiency, Synchronous Step-Down
DC-DC Converter with Resistor Programmability
Electrical Characteristics (continued)
(VIN_ = 10V, VOUT_ = 3.3V, CVIN_ = 1µF, CAVCC = 1µF, CVCC = 2.2µF, CBST_ = 0.1µF, TA = -40°C to +125°C with typical value at
TA = 25°C, unless otherwise stated) (See Typical Application Circuits) (Note 1).
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
VOUT1-2 Output Voltage
Lower Range
8-bit resolution over 5.048V range.
VOUT_RANGEL LSB = ~20mV; Min_VOUT = 0010 1101;
Max_VOUT = 1011 1111.
0.9045
3.786
V
VOUT1-2 Output Voltage
Higher Range
8-bit resolution over 5.048V range.
VOUT_RANGEH LSB = ~20mV; Min_VOUT = 11xx 0000;
Max_VOUT = 11xx 1111.
4.752
5.048
V
OUT_ Pull-Down Resistance
OUT_RES
VOUT1-2 = 3.3V; ADDR = Disabled
TA = 25°C
30
42.5
55
kΩ
OUTPUT VOLTAGE FAULT THRESHOLDS
Overvoltage Threshold
OV_TH
VOUT1-2 = 0.9V
116.4
119.7
122.9
%VOUT
Undervoltage Threshold
UV_TH
VOUT1-2 = 0.9V
78.1
79.9
81.7
%VOUT
Power Good Threshold High
PGOOD_H
VOUT1-2 = 0.9V
111.8
114.6
116.8
%VOUT
Power Good Threshold Low
PGOOD_L
VOUT1-2 = 0.9V
84.0
86.1
88.1
%VOUT
SS_00
0.850
1
1.150
ms
SS_01
3.40
4
4.60
ms
SS_10
6.80
8
9.20
ms
SS_11
13.60
16
18.40
ms
ILIM
(Note 4)
3.59
4.2
4.7
A
Buck1,2 LS Runaway Current
Limit Fault Threshold
IRWY
(Note 4)
4.72
5.6
6.82
A
Number of Peak Current Limit
Events Before LATCHOFF
#ILIM
7
Events
Number of Runaway Current
Limit Events Before HICCUP
or LATCHOFF
#RWY
1
Event
Cycles of programmable soft-start time
before retry
64
Cycles
SOFT-START/STOP TIME
Programmable Soft-Start
Time Duration
CURRENT LIMIT
Buck1,2 LS Peak Current
Limit Fault Threshold
Buck HICCUP Timeout
THICCUP
Note 1: Limits are 100% tested at TA = 25°C. Maximum and Minimum limits are guaranteed by design and characterization over
temperature
Note 2: Design Guaranteed by ATE characterization. Limits are not production tested
Note 3: Guaranteed by design; not production tested
Note 4: Current Limit and Runaway thresholds tracks in value and in temperature (see Typical Operating Characteristics section).
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Maxim Integrated │ 4
MAX17509
4.5–16V, Dual 3A, High-Efficiency, Synchronous Step-Down
DC-DC Converter with Resistor Programmability
Typical Operating Characteristics
(CVIN_ = 10µF, CAVCC = 1µF, CVCC = 2.2µF, CBST_ = 0.1µF, fSW = 1MHz, TA = +25°C unless otherwise stated, default state on
configuration setting.)
EFFICIENCY
vs. OUTPUT CURRENT
toc01
100
85
80
VOUT = 1.8V
75
VOUT = 1.2V
VOUT = 1.0V
70
80
75
65
VIN1 = 5V
EN2 = 0V
65
0
1000
2000
0
3000
0.9070
VIN = 12V
VIN = 5V
VIN = 16V
3000
1.0
1.5
2.0
0.9060
2.5
3.0
IOUT = 0A
0.0
5.0
10.0
15.0
20.0
1.00
0.99
0.98
FREQ MIN
0.97
FREQ AVG
CURRENT (A)
FREQ MAX
0
50
TEMPERATURE (°C)
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100
0
50
100
LOAD CURRENT TRANSIENT RESPONSE
VIN = 12V, VOUT = 1.2V, IOUT = 1.5 - 3A
toc09
50mV/div
(AC
COUPLED)
VOUT
5.0
ILIM
4.5
3.5
-50
-50
IRWY
4.0
0.96
VOUT MIN
TEMPERATURE (°C)
5.5
1.01
890
toc08
6.0
1.03
VOUT AVG
895
1.04
1.02
905
CURRENT LIMIT vs. TEMPERATURE
toc07
VOUT MAX
910
INPUT VOLTAGE (V)
FREQUENCY vs. TEMPERATURE
3000
toc06
900
OUTPUT CURRENT (A)
1.05
VOUT (mV)
IOUT = 3A
0.9050
2000
OUTPUT VOLTAGE vs. TEMPERATURE
0.9065
0.9040
0.5
1000
920
915
0.9045
0.0
VOUT
0
VOUT = 1.8V
VOUT = 1.2V
VIN1 = 16V
EN2 = 0V
= 1.0V
OUTPUT CURRENT (mA)
0.9055
0.9045
FREQUENCY (MHz)
60
toc05
0.9070
0.9055
0.95
65
0.9075
VOUT (V)
VOUT (V)
2000
0.9080
0.9060
0.9040
1000
70
LINE REGULATION
VOUT = 0.9V
toc04
0.9065
0.9050
75
OUTPUT CURRENT (mA)
OUTPUT CURRENT (mA)
LOAD REGULATION
VOUT = 0.9V
80
VIN1 = 12V
EN2 = 0V
VOUT = 1.0V
60
VOUT = 5.0V
85
VOUT = 1.8V
VOUT = 1.2V
VOUT = 2.5V
90
85
70
VOUT = 3.3V
95
EFFICIENCY (%)
90
EFFICIENCY (%)
EFFICIENCY (%)
90
60
VOUT = 3.3V
VOUT = 5.0V
VOUT = 2.5V
95
toc03
100
toc02
100
VOUT = 2.5V VOUT = 3.3V
95
EFFICIENCY
vs. OUTPUT CURRENT
EFFICIENCY
vs. OUTPUT CURRENT
VIN = 10V
VOUT = 3.3V
-50
0
50
100
1A/div
IOUT
40µs/div
TEMPERATURE (°C)
Maxim Integrated │ 5
MAX17509
4.5–16V, Dual 3A, High-Efficiency, Synchronous Step-Down
DC-DC Converter with Resistor Programmability
Typical Operating Characteristics (continued)
(CVIN_ = 10µF, CAVCC = 1µF, CVCC = 2.2µF, CBST_ = 0.1µF, fSW = 1MHz, TA = +25°C unless otherwise stated, default state on
configuration setting.)
STARTUP/SOFTSTOP DISABLED
VIN = 12V, VOUT = 1.2V, IOUT = 0A, TSS = 4ms
LOAD CURRENT TRANSIENT RESPONSE
VIN = 12V, VOUT = 3.3V, IOUT = 1.5 - 3A
VOUT
STARTUP/SOFTSTOP DISABLED
VIN = 12V, VOUT = 1.2V, IOUT = 3A, TSS = 4ms
toc11
toc10
toc12
EN
5V/div
200mV/div
PGOOD
(AC
COUPLED)
2V/div
EN
5V/div
PGOOD
2V/div
500mV/div
500mV/div
VOUT
VOUT
1A/div
IOUT
10V/div
LX
2ms/div
2ms/div
40µs/div
5V/div
2V/div
PGOOD
EN
5V/div
PGOOD
5V/div
500mV/div
500mV/div
10V/div
LX
10V/div
LX
1ms/div
LOAD SHORT-CIRCUIT SHUTDOWN (HICCUP)
VIN = 12V, VOUT = 1.2V
toc17
toc16
10V/div
LX
LOAD SHORT-CIRCUIT SHUTDOWN (LATCH)
VIN = 12V, VOUT = 1.2V
STARTUP INTO PRE-BIAS (120% OF TARGET)
VIN = 12V, VOUT = 1.2V, IOUT = 0A, TSS = 4ms
500mV/div
VOUT
2ms/div
2ms/div
5V/div
PGOOD
0V
VOUT
VOUT
toc15
toc14
toc13
EN
STARTUP INTO PRE-BIAS (50% OF TARGET)
VIN = 12V, VOUT = 1.2V, IOUT = 0A, TSS = 4ms
STARTUP/SOFTSTOP DISABLED
VIN = 12V, VOUT = 1.2V, IOUT = 3A, TSS = 4ms
STARTUP/SOFTSTOP ENABLED
VIN = 12V, VOUT = 1.2V, IOUT = 0A, TSS = 4ms
10V/div
LX
toc18
PGOOD
PGOOD
5V/div
5V/div
VOUT
VOUT
500mV/div
500mV/div
IL
0V
10V/div
LX
1ms/div
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2A/div
10V/div
LX
4µs/div
PGOOD
5V/div
500mV/div
VOUT
IL
5A/div
10V/div
LX
4µs/div
Maxim Integrated │ 6
MAX17509
4.5–16V, Dual 3A, High-Efficiency, Synchronous Step-Down
DC-DC Converter with Resistor Programmability
Typical Operating Characteristics (continued)
(CVIN_ = 10µF, CAVCC = 1µF, CVCC = 2.2µF, CBST_ = 0.1µF, fSW = 1MHz, TA = +25°C unless otherwise stated, default state on
configuration setting.)
SYNCHRONIZATION vs. LX1 and LX2
180 OUT-OF-PHASE
LOAD SHORT-CIRCUIT RECOVERY (HICCUP)
VIN = 12V, VOUT = 1.2V
toc20
toc19
PGOOD
5V/div
VOUT
500mV/div
10V/div
LX
CLKIN
5V/div
LX1
10V/div
10V/div
LX2
400ns/div
100ms/div
RADIATED EMISSIONS (EN55022 Class B)
VIN = 12V, VOUT1 = 3.3V, IOUT = 2A,
VOUT2 = 1.2V, IOUT = 2A
toc21
Amplitude
(dBuV/m)
Frequency (MHz)
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Maxim Integrated │ 7
MAX17509
4.5–16V, Dual 3A, High-Efficiency, Synchronous Step-Down
DC-DC Converter with Resistor Programmability
OUT2
PGND2
LX2
LX2
IN2
IN2
BST2
TOP VIEW
PGND2
Pin Configuration
24
23
22
21
20
19
18
17
EN2
25
16
PGOOD2
COARSE2
26
15
MODE
FINE2
27
14
NC
SS2
28
13
SYNC
MAX17509
SS1 29
12 VCC
11 AVCC
FINE1 30
COARSE1 31
10 SGND
9
3
4
5
6
PGND1
LX1
LX1
IN1
7
8
IN1
2
BST1
1
PGND1
32
OUT1
EN1
*EP
+
PGOOD1
TQFN
5mm x 5mm
*CONNECT EXPOSED PAD TO GND.
Pin Description
PIN
NAME
FUNCTION
1
OUT1
2, 3
PGND1
4, 5
LX1
Inductor Connection for Regulator 1. Connect LX1 to the switched side of the inductor.
6, 7
IN1
Input Supply for Regulator 1 and Internal 5V LDO. Bypass IN1 to PGND1 with a 10µF and 0.1µF
ceramic capacitor as close as possible to the device.
8
BST1
Regulator 1 High-Side Gate-Driver Supply. Connect a 0.1µF ceramic capacitor from BST1 to LX1.
Regulator 1 Feedback Regulation Point. Connect OUT1 to output of Regulator 1 to sense the
output voltage.
Power Ground Connection for Regulator 1. Connect negative terminal of output capacitor and input
capacitor of Regulator 1 to PGND1. Connect PGND1 externally at a single point to SGND.
Open-Drain Power Good Output for Regulator 1. PGOOD1 is low if OUT1 is 15% (typ) above or below
the normal regulation point. PGOOD1 asserts low during soft-start, and when the device is shut down
due to disabling or due to fault responses. PGOOD1 becomes high impedance when OUT1 is in
regulation. To obtain a logic signal, pullup PGOOD1 with an external resistor (10kΩ) connected to a
positive voltage less than 5.5V.
9
PGOOD1
10
SGND
Signal Ground Connection. Connect SGND to PGND_ at a single point typically near the output
capacitor ground.
11
AVCC
Input for Internal Analog Circuits. Connect a minimum of 1µF ceramic capacitor from AVCC to SGND.
Internally connected to VCC with 28Ω resistor.
12
VCC
Internal 5V LDO Output. it acts as low side gate driver supply. Connect a 2.2µF ceramic capacitor from
VCC to PGND_.
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Maxim Integrated │ 8
MAX17509
4.5–16V, Dual 3A, High-Efficiency, Synchronous Step-Down
DC-DC Converter with Resistor Programmability
Pin Description (continued)
PIN
NAME
13
SYNC
14
N.C.
15
MODE
FUNCTION
External Clock Synchronization Input. Connect an external clock for frequency synchronization to
within 0.7 - 2.75 of the internal switching frequency with a limit of 450kHz to 2.2MHz before regulation
start for stable operation.
No Connect. Connect this pin to ground.
Mode Selection Pin. Programming input to select:
- Two Independent Outputs or Dual-phase Single Output Mode
- Phase Shift (0 or 180°)
- Internal Clock Frequency (500KHz/1.0MHz/1.5MHz/2MHz at 5VIN, or 1.0MHz at 12VIN)
Open-Drain Power-Good Output for Regulator 2. PGOOD2 is low if OUT2 is 15% (typ) above or below
the normal regulation point. PGOOD2 asserts low during soft-start, and when the device is shut down
due to disabling or due to fault responses. PGOOD2 becomes high impedance when OUT2 is in
regulation. To obtain a logic signal, pull up PGOOD2 with an external resistor (10kΩ) connected to a
positive voltage less than 5.5V.
16
PGOOD2
17
BST2
18, 19
IN2
Input Supply for Regulator 2. Bypass IN2 to PGND2 with a 10µF and 0.1µF ceramic capacitor as close
as possible to the device.
20, 21
LX2
Inductor Connection for Regulator 2. Connect LX2 to the switched side of the inductor.
22, 23
PGND2
Power Ground Connection for Regulator 2. Connect negative terminal of output capacitor and input
capacitor of Regulator 2 to PGND2. Connect PGND2 externally at a single point to SGND.
24
OUT2
Regulator 2 Feedback Regulation Point. Connect OUT2 to output of Regulator 2 to sense the output
voltage.
Regulator 2 High-Side Gate-Driver Supply. Connect a 0.1µF ceramic capacitor from BST2 to LX2.
Enable Pin for Regulator 2. The voltage at EN2 is compared to internal comparator reference to
determine when to enable the regulation. Pull-up to AVCC to enable Regulator 2, or optionally connect
to a resistor-divider from IN2 to EN2 to SGND to program the UVLO level. Pull EN2 to SGND to
disable the Regulator 2.
25
EN2
26
COARSE2
27
FINE2
28
SS2
Regulator 2 Soft-Start/Stop Time Programming and Lx-Slew Rate Selection Pin.
29
SS1
Regulator 1 Soft-Start/Stop Time Programming and Overcurrent Response Selection Pin.
30
FINE1
31
COARSE1
32
EN1
EP
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Regulator 2 Output Voltage Coarse Programming.
Regulator 2 Output Voltage Fine Programming.
Regulator 1 Output Voltage Fine Programming.
Regulator 1 Output Voltage Coarse Programming.
Enable Pin for Regulator 1. The voltage at EN1 is compared to internal comparator reference to
determine when to enable the regulation. Pull up to AVCC to enable Regulator 1, or optionally connect
to a resistor-divider from IN1 to EN1 to SGND to program the UVLO level. Pull EN1 to SGND to
disable the Regulator 1.
Exposed Paddle. Connect EP to a large copper plane at SGND potential to improve thermal
dissipation. Do not use EP as SGND ground connection alone.
Maxim Integrated │ 9
MAX17509
4.5–16V, Dual 3A, High-Efficiency, Synchronous Step-Down
DC-DC Converter with Resistor Programmability
Functional Diagram
BST2
BUCK 2
LEVEL
SHIFT
THSD
OSCILLATOR
+ PLL
SYNC
FINE1
SS1
ADC
COARSE 2
LX1
LX_SLEW
CURR
VCC.
LIMIT
ERROR
AMPLIFIER
LOOP
COMP
gM
CURR .
LIMIT
SLOPE
INTERNA
COMP REFIN
L
REF
PWM
SS2
ERROR
AMPLIFIER
COMPARATOR
FINE2
COARSE 2
UVLO
MODE
LOOP
COMP
0.85
ROM1
MODE
REGS_RDY
MUX
FINE2
SS1
ROM2
FINE1
REGS_RDY
REGISTERS
COARSE 1
COARSE 1
SS2
CLK
SLOPE
COMP
PWM
PWM
CONTROL
LOGIC
COMPARATOR
REF
IN1
gM
INTERNAL
PGOOD _ REFIN
REF
L
1.15
REFIN
0.85
OUT1
R
THERMAL
SHDN
PWM
CONTROL
LOGIC
IN_UVLO
LEVEL
SHIFT
PGND1
OUT1
R
REF
THSD
VOLTAGE
REFERENCE
CLK
SGND
BST1
VC
C
BUCK 1
R
IN_UVLO
UVLO
UVLO
AVCC
IN2
IOUT1
R
28Ω
REF
4.5V LDO
GENERATOR
VCC
EN1
PGOOD 1
PGOOD _
H
PGOOD _L
1.15
SS COMPLETE
MAX17509
PGOOD _H
REFIN
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OUT1
Maxim Integrated │ 10
MAX17509
4.5–16V, Dual 3A, High-Efficiency, Synchronous Step-Down
DC-DC Converter with Resistor Programmability
Detailed Description
The MAX17509 is a valley-current-mode, synchronous
pulse-width-modulated (PWM) buck regular designed to
provide either two independent 3A outputs (see Figure 1)
or a single 6A output (see Figure 2). The device operates
over an input-voltage range of 4.5V to 16V and generates
independently adjustable output voltage in the ranges of
0.904V to 3.782V and 4.756V to 5.048V in 20mV steps
with ±2% system accuracy over load, line, and temperature. The power solution can be completed using only
external resistors setting. The self-configured internal
compensation scheme allows a simple plug-and-play
solution without the need for compensation parameter
calculation.
The MAX17509 supports a selectable switching frequency of either 500kHz, 1MHz, 1.5MHz or 2MHz for
input supply rails up to 6V. For supply rails greater
than 6V, the switching frequency can be programmed
only to 1MHz. The device can be synchronized to
an external clock (see Switching Frequency/External
Synchronization/Phase Shift section for details. The
phase shift between the two regulators can be set to
either 0 or 180°. Programmable switching slew rate allows
for electromagnetic compliant optimization. For sequencing purposes, the device provides enable inputs, power
good outputs, the ability to adjust soft-start timing, and the
option to power down with soft-stop. Adjustable soft-start
reduces the inrush current by gradually ramping up the
internal reference voltage, and also powers up glitch-free
into a prebiased output. Protection features include internal input undervoltage lockout (UVLO) with hysteresis,
lossless, cycle-by-cycle current limit, hiccup-mode output
short-circuit protection, undervoltage/overvoltage protection, and thermal shutdown.
Input Supply (IN_)/Internal Linear Regulator (VCC)
The input supply voltage (VIN_) is the input power supply
for internal regulators, which support a voltage range from
4.5V to 16V. In addition, it has an internal linear regulator
(VCC) to provide its own bias from a high-voltage input
supply at VIN1. VCC bias supply provides up to 50mA
typical total current directly for gate drivers for the internal
MOSFETs, and through AVCC pin for the analog controller, reference, and logic blocks. The linear regulator has
an overcurrent threshold of approximately 150mA. In case
of an overcurrent event on VCC, the current is limited, and
VCC voltage starts to droop.
At higher input voltages (VIN1) of 5.0V to 16V, VCC is regulated to 4.5V. At 5.0V or below, the internal linear regulator operates in dropout mode, where VCC follows VIN1.
www.maximintegrated.com
For input voltages of less than 5.5V, connect VIN1 and
VCC together to power the MAX17509 directly to increase
efficiency by bypassing the internal LDO. If VCC is supplied externally and VIN1 < VCC, switching activities will
be inhibited. For input voltage ranges higher than 5.5V,
use the internal regulator. Bypass VIN_ to PGND_ with
a low-ESR, 0.1µF and 10μF or greater ceramic capacitor, and VCC with a low-ESR, ceramic 2.2μF capacitor to
PGND_ placed close to the device.
Once the input bias supply rises above its UVLO rising
threshold 4.2V (typ), the regulators are allowed to regulate the output voltages. If the VIN_ voltage is below the
input undervoltage lockout (VIN_UVLO) threshold 3.4V
(typ), the controller stops switching and turns off both
high-side and low-side gate drivers until the VIN_ voltage
recovers. In case the 5V range output voltage is selected,
VIN_UVLO rising threshold will change in order to allow
proper start-up of the respective channel. In this case, the
VIN_UVLO_ value is 6V rising threshold and 4.3 falling
threshold. See criteria of the device to begin the regulation in the Soft-Start/Soft-Stop and Prebias Condition
section.
Internal Chip Supply Input
Voltage Range (AVCC)
AVCC is the input for internal analog circuitry. The
AVCC input undervoltage lockout (AVCC_UVLO) circuitry
inhibits switching if the 4.5V AVCC supply is below its
AVCC_UVLO threshold, 3.2V (typ). Once the 5V bias supply AVCC rises above its UVLO rising threshold and EN1
and EN2 enable the buck controllers, the controllers start
switching and the output voltages begin to ramp up using
soft-start. Bypass AVCC to SGND with a low-ESR, 1μF
or greater ceramic capacitor placed close to the device.
Device Configuration from
Pin Programming
Power solution with MAX17509 can be configured
completely using 7 configuration pins. The configuration
pins are MODE, SS[1,2], COARSE[1,2], and FINE[1,2].
To recognize the value of resistance reliably, connect
standard 1% resistors between the configuration pins
and SGND, and keep the trace length to below 3cm to
minimize the trace capacitance. These pins are read
once when the voltage on AVCC is above AVCC_TH_R.
The pins are re-read when AVCC rises above AVCC_
TH_R after dropping below AVCC_TH_F. There is a fixed
2ms total time (typ.) required for device configuration.
EN_ signals are ignored during this time, and switching
activity is only allowed to occur subsequently.
Maxim Integrated │ 11
MAX17509
4.5–16V, Dual 3A, High-Efficiency, Synchronous Step-Down
DC-DC Converter with Resistor Programmability
MODE pin chooses between single-phase (two outputs)
and dual-phase (one output), sets the relative phase-shift
of the PWM between two regulators, and sets the internal
switching frequency. SS1 chooses between brickwall/
latchoff and hiccup for the OCP behavior of both regulators, and enables/disables soft-stop along with soft-start/
stop time for Regulator 1. SS2 chooses between maximum and minimum Lx-slew rate for both regulators, and
enables/disables soft-stop along with soft-start/stop time
for Regulator 2. MODE, SS[1,2], COARSE[1,2], and
FINE[1,2] have 16 possible selections.
Table 1. The table also shows a correspondence between
the resistor values to the index numbers. Pin strapping
takes three possible stages: VCC, OPEN, GND. VCC
and OPEN provide the same setting result. The resistor
value for each pin is independent from each other, and
Table 2 show examples of a few scenarios of the settings.
The details of the each functional behavior are described
in the corresponding sections subsequently.
The configuration pins can respond to both pin strapping
and resistor programming, and the settings summarized in
Table 1. Summary of Resistor Programming
5
40.2
6
30.9
7
24.3
2.0MHz
8
19.1
500kHz
9
15
1.0MHz
11.8
11
9.09
12
6.81
13
4.75
14
3.01
15
GND
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500kHz
0°
1.0MHz
1.5MHz
1.5MHz
2.0MHz
180°
500kHz
1.0MHz
1.5MHz
2.0MHz
8
16
DISABLE
53.6
2.0MHz
TSS2
(ms)
COARSE_
FINE_
COARSE
VOUT (V)
FINE
VOUT (V)
1
0.000
0.650
4
0.019
8
0.037
16
0.966
0.057
1
1.281
0.078
4
1.597
0.097
8
1.912
0.115
16
16
2.228
0.135
1
1
2.543
0.157
4
2.859
0.176
1
ENABLE
4
1.5MHz
4
4
8
DISABLE
75
1
SSTOP2
4
8
16
1
4
8
16
ENABLE
115
3
10
1.0MHz
TSS1 LX(ms) SLEW
MAXIMUM
2
DUAL-PHASE, SINGLE-OUTPUT
200
SS2
MINIMUM
180°
1
SSTOP1
DISABLE
500kHz
OC
ENABLE
FSW
DISABLE
475
(OPEN or
VCC)
PHASE
SHIFT
ENABLE
0
MODE
SS1
BRICKWALL AND LATCHOFF
(kΩ)
MODE
HICCUP
1% RES.
TWO SINGLE-PHASE
INDEPENDENT OUTPUTS
INDEX
8
3.174
0.194
16
3.490
0.213
1
4.756
(7V VIN)
0.235
4
4.756
(9V VIN)
0.254
8
4.756
(12V VIN)
0.272
16
4.756
(16V VIN)
0.291
Maxim Integrated │ 12
MAX17509
4.5–16V, Dual 3A, High-Efficiency, Synchronous Step-Down
DC-DC Converter with Resistor Programmability
Table 2. Examples of Resistor Programming
SETTINGS
MODE = Single-Phase (Two Outputs),
180° Phase-Shift, 1MHz
SS1 = Hiccup OCP,
Soft-Stop 1 Disabled,
Soft-Start Time 1 = 8ms
SS2 = Maximum Lx-Slew Rate,
Soft-Stop 2 Enabled,
Soft-Start Time 2 = 16ms
MODE
SS1
SS2
COARSE1
FINE1
COARSE2
FINE2
200kΩ
11.8kΩ
24.3kΩ
3.01kΩ
4.75kΩ
75kΩ
6.81kΩ
9.09kΩ
200kΩ
GND
40.2kΩ
11.8kΩ
40.2kΩ
11.8kΩ
Note: 12VIN
VOUT1 = 5.0V (4.756V + 0.254V)
VOUT2 = 1.2V (0.966V + 0.235V)
MODE = Dual-Phase (Single Output),
180° Phase-Shift, 2.0MHz
SS1 = Brickwall and Latchoff OCP,
Soft-Stop 1 Disabled,
Soft-Start Time 1 = 4ms
SS2 = Minimum Lx-slew Rate
VOUT = 1.8V (1.597V + 0.194V)
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Maxim Integrated │ 13
MAX17509
4.5–16V, Dual 3A, High-Efficiency, Synchronous Step-Down
DC-DC Converter with Resistor Programmability
EN_
A regulator allows to start the regulate output voltage
when the voltage on EN_ is above EN_TH_R level of
1.262V (typ.) after device configuration from pin programming is complete. EN_ below EN_TH_F results in regulator disable.
To configure the device to self-enable when input
voltage is sufficient, pull EN_ to AVCC. Optionally, to
set the voltage at which the device turns on from VIN,
connect a resistive voltage-divider from IN_ to GND
(Figure 1) with the center node of the divider to EN_.
Choose RU to be 10k - 100kΩ, and then calculate RB as:
1.262
R=
B RU ×
V
−
1.262
INU
where VINU is the voltage at which the device is required
to turn on. For adjustable output voltage devices, ensure
that IN_ is higher than 0.93 x VOUT.
Soft-Start/Soft-Stop and Prebias Condition
Once a regulator is enabled by driving the corresponding
EN_ above EN_rising threshold, the soft-start circuitry
gradually ramps up the reference voltage during soft-start
time to reduce the input surge currents during startup.
The device controls switching activities to have only
positive inductor current, and then gradually transition to
PWM mode at the end of soft-start. Before the device can
begin the soft-start, the following conditions must be met:
1) AVCC_ exceeds the 3.9V (max) AVCC rising threshold (AVCC_TH_R).
2) Reading of pin configuration is complete.
3) IN_ exceeds the 4.4V (max) IN undervoltage lockout
threshold (VIN_UVLO_R).
4) EN_ exceeds the 1.3V (max) EN rising threshold
(EN_TH_R).
5) The device temperature is below 160°C thermal
shutdown threshold.
SS_ pins are used to select the soft-start timing among 1,
4, 8, and 16ms, as well as to enable the soft-stop option.
The default setting will be 8ms soft-start timing, and softstop disabled. For VOUT ≥ 2.5V, use a minimum of 4ms
soft-start time.
There are two scenarios for startup sequence depending
on the initial output voltage. During both scenarios, UV
and OV are disabled, and overcurrent protection operates in brickwall mode (±4.2A). In the case that the device
starts from an initial output voltage below the target, the
device will not cause the output voltage to dip down by not
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IN_
IN_
RU
MAX17509
EN_
RB
Figure 1. Adjustable EN network
sinking current from the output. In the case of starting from
an initial output voltage above target, the device smoothly
discharges the output voltage by decreasing the internal
reference voltage down to 0V in 512µs, and then initiates
the soft-start sequence. During this discharge period, the
negative current limit is gradually increased to allow up to
4.2A of negative current to prevent a sudden dip in output
voltage. During the follow soft-start sequence, the device
ramps up the internal reference to the target level with
both high-side and low-side switches activated.
With soft-stop option, when the device is disabled the
soft-stop circuitry gradually ramps down the reference
voltage with the same time as soft-start timing to discharge the remaining energy in the output capacitor in
a controlled manner. During a soft-stop event, faults are
masked as during start-up, and no hiccup will occur after
a fault even though hiccup is set. To ensure a proper softstop sequence the device must be in PWM mode. This
requires the duration of the EN_ signal to be longer than
the soft-start time. Soft-stop should be used for two-independent-output configuration only, and not in dual-phase,
single-output mode.
Switching Frequency/External
Synchronization/Phase Shift
The MAX17509 supports a selectable switching frequency of either 500kHz, 1MHz, 1.5MHz, or 2MHz for input
supply rails up to 6V. For supply rails greater than 6V, the
switching frequency can be programmed only to 1MHz.
High-frequency operation optimizes the application for
the smallest component size, lower output ripple, and
improve transient response, but trading off efficiency to
higher switching losses. Low-frequency operation offers
Maxim Integrated │ 14
MAX17509
4.5–16V, Dual 3A, High-Efficiency, Synchronous Step-Down
DC-DC Converter with Resistor Programmability
the best overall efficiency at the expense of component
size and board space. The device also offers the option to
set the relative PWM phase-shift between the regulators
to be in-phase (0°) or interleave (180° out-of-phase). With
in-phase setting, Regulator 2’s low-side MOSFET turn
on at the same time as Regulator 1. With out-of-phase
setting, the Regulator 2’s low-side MOSFET turns on with
a time delay corresponding to half of the switching period.
The instantaneous input current peaks of both regulators
do not overlap, resulting in reduced RMS ripple current
and input voltage ripple. This reduces the required input
capacitor ripple current rating, allows for fewer or less
expensive capacitors, and reduces shielding requirements
for electromagnetic interference (EMI). A resistor on the
MODE pin allows the user to set the desired switching
frequency, phase shift, and independent output/dualphase operation.
pull-down to GND for minimum. The OCP behavior is
recommended to be set to brickwall and latchoff option.
The operation and functional behavior (startup/shutdown,
regulation, fault responses) will be uniform between the
two phases.
The device can be synchronized to an external clock
by connecting the external clock signal to SYNC with
frequency within 900kHz to 1.3MHz before regulation start
for a stable operation for 1.0MHz internal switching frequency
at 12VIN range, and within 0.7 - 2.75 of the internal switching
frequency with a limit of 450kHz to 2.2MHz for 5VIN range.
With lower switching frequency, the pre-set peak current
limit tends to make the effective DC current limit lower
due to higher inductor peak current, but this can be compensated by choosing higher inductance value. Regulator
1’s high-side MOSFET turning off with a time delay
corresponding to 58% of the switching period (210°) with
respect to the rising edge of SYNC signal, and Regulator
2’s high-side MOSFET turning on depends on the
relative phase-shift setting. The minimum external clock
pulse-width high should be greater than 30ns.
The target output voltage is achieved by the sum of
coarse voltage (COARSE_) and an offset (FINE_). The
resistor value can be found from cross-referencing the
index number to the resistor value on Table 1. For a
target output voltage between 0.904V to 3.782V, the index
of the two resistors can be found from (Equations 2 and
3) with a minimum VCOARSE of 0.904V. For 4.756V to
5.048V, COARSE_ resistor is selected based on input
voltage with index from 12 to 15, and FINE_ resistor can
be found from (Eq.3), where VOUTCOARSE is 4.756V.
Table 3 shows resistor setting for typical output voltages.
Single and Dual-Phase mode
MODE pin is used to configure MAX17509 to produce two
single-phase independent outputs or a dual-phase singleoutput regulator. In single-phase mode, the component
selection and operation of each phase is independent
from each other.
Output Voltage Setting (COARSE_ and FINE_)
and Sensing (VOUT_)
COARSE_ and FINE_ pins set the output range of each
regulator in MAX17509 in 20mV steps from 0.904V to
3.782V and 4.756V to 5.048V provided that the input
voltage is higher than the desired output voltage by an
amount sufficient to prevent the device from exceeding
its maximum duty cycle specification. VOUT_ senses the
output voltage feedback used for output voltage monitoring and fault detection. Connect VOUT_ directly to the
point of regulation
5.048
VOUT
=
16 × Index COARSE + 1 + Index FINE
256
(Equation 1) for 0.904V ≤ VOUT ≤ 3.782V, min.
IndexCOARSE = 2
1 256 × VOUT
=
− 1
Index COARSE Integer
16 5.048
(Equation 2) for 0.904V < VOUT < 3.782V
256
In dual-phase mode, the two phases operate to supply a
Index FINE Integer
=
VOUT − VOUTCOARSE
shared output current up to 6A with 180° relative phase
5.048
shift of PWM. The inductor selection must be the same,
(Equation 3)
and EN_ should be connected together. The configuration of both phases is determined by that of Regulator 1
(OC, SSTOP, TSS, COARSE1, FINE1). SS2 is still needed
to set Lx-slew of both phases with the option to use only
pin strapping: pull-up to VCC for maximum Lx-slew and
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Maxim Integrated │ 15
MAX17509
4.5–16V, Dual 3A, High-Efficiency, Synchronous Step-Down
DC-DC Converter with Resistor Programmability
Table 3. VOUT Setting for Common Output
Voltages
VOUT (V)
COARSE FINE
COARSE
FINE
INDEX
INDEX RESISTOR RESISTOR
0.9
2
13
115k
4.75k
1.0
3
2
75k
115k
1.2
3
12
75k
6.81k
1.5
4
11
53.6k
9.09k
2.0
6
5
30.9k
40.2k
2.5
7
14
24.3k
3.01k
3.0
9
7
15.0k
24.3k
3.3
10
7
11.8k
24.3k
5.0 (7V VIN)
5.0 (9V VIN)
5.0 (12V VIN)
5.0 (16V VIN)
12
13
14
15
13
6.81k
4.75k
3.01k
GND
4.75k
High-Side Gate-Driver Supply (BST_)
The high-side MOSFET is turned on by closing an internal switch between BST_ and DH_ and transferring the
bootstrap capacitor’s (at BST_) charge to the gate of the
internal high-side MOSFET. This charge refreshes when
the high-side MOSFET turns off and the LX_ voltage
drops down to ground potential, taking the negative terminal of the capacitor to the same potential. At this time,
the bootstrap diode recharges the positive terminal of the
bootstrap capacitor. The boost capacitor should be a lowESR ceramic capacitor with a minimum value of 100nF.
Adjustable Switching Slew Rate
Reducing the LX switching transition time has the benefit of improved efficiency; however, the fast slewing
of the LX slew nodes results in relatively high radiated
EMI. MAX17509 has the ability to program the slew rate
of LX switching nodes to address noise requirements
in sensitive applications such as multi-GB transceiver
supplies in FPGA applications. SS2 pin can set Lx-slew
rate of both regulators to be either the maximum (5V/ns)
or minimum value (0.25V/ns).
Current Protections (UC/OCP/OCR) and Retry
Setting (Hiccup vs. Brickwall and Latchoff)
The current protection circuit monitors the output current levels through both internal high-side and low-side
MOSFETs during all switching activities to protect them
during overload and short-circuit conditions. Peak positive current limit (OC), valley negative undercurrent limit
(UC), and positive runway overcurrent (OCR) limit are
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three types current fault events. Peak positive current
limit can occur when the load demand is greater than the
regulator capability (overloading). Valley negative current
limit can occur when the regulator sinks current, where
the device draws the energy back from the output, such
as during soft-start from above target output voltage level
or soft-stop. OCR can occur when the output is short to
ground, and the cycle-by-cycle switching results in a rapid
increase in current without sufficient voltage across inductor to properly discharge. OCR current limit is declared
when the current level reached 5.6A (typ), and the
regulator shuts immediately similar to fault response due to
output undervoltage (UV) or output overvoltage (OV)
events.
SS1 pin sets options to attempt regulation following those
fault event(s), in addition to fault response due to UC/
OC protection. The two options for fault response due to
UC/OC protection are (1) Hiccup and (2) Brickwall and
Latchoff.
With Hiccup setting, the UC/OC current fault protection
is set to shut down immediately, which implies that the
regulators shut down immediately after UC/OC/OCR/UV
or OV occurs. An UC or OC event is declared after the
device sensed seven consecutives peak positive current
limit above 4.2A (typ), or consecutives valley negative
undercurrent limit below -4.2A (typ). Subsequently, the
regulator attempts a soft-start sequence after the Hiccup
timeout period expired, which corresponds to the 64
times period set for soft-start time. This allows the overload current to decay due to power loss in the converter
resistances, load, and the inductor before soft-start is
attempted again.
With Brickwall and Latchoff setting, the current fault
protection is set to constant current mode. The device
attempts to provide continuous output current limited by
peak positive current-limit (4.2A typ) in current-sourcing
event, while in a current-sinking event it attempts to continuously sink current limited by valley negative undercurrent limit (-4.2A typ). With this setting UC/OC status is
latched, and the switching activities continue until OCR/
UV/OV/OT or disable event(s) occur. If a shutdown due
to an OCR/UV or OV event occurs, the regulator remains
shutdown until the EN_ input is toggled.
During current-sinking, the input voltage can increase
since the energy is delivered back to the input. It is recommended to monitor the input voltage to ensure that it
is below the device’s limit. In an application where the
load is inductive, the output could swing negatively below
ground when it is suddenly shorted to ground. In order
to withstand such a stress it is recommended to place
Maxim Integrated │ 16
MAX17509
4.5–16V, Dual 3A, High-Efficiency, Synchronous Step-Down
DC-DC Converter with Resistor Programmability
a 50Ω series resistor close to the IC from OUT_ to the
regulation point.
Design Procedure
Output Overvoltage Protection (OVP)
The maximum value (VIN (MAX)) and minimum value
(VIN (MIN)) must accommodate the worst-case conditions
accounting for the input voltage soars and drops. If there
is a choice at all, lower input voltages result in better
efficiency. With a maximum duty cycle of 93%, VOUT is
limited to 0.93 x VIN.
The MAX17509 includes an output overvoltage protection
(OVP) circuit that begins to monitor the output through
VOUT_ pin once the soft-start is complete. If the output
voltage rises above 120% (typ) of its nominal regulation voltage, the regulator shuts down. The subsequent
response depends on retry setting.
Output Undervoltage Protection (UVP)
The MAX17509 includes an output undervoltage protection (UVP) circuit that begins to monitor the output
through VOUT_ pin once the soft-start is complete. If the
output voltage drops below 80% (typ) of its nominal regulation voltage, the regulator shuts down. The subsequent
response depends on retry setting.
Over Thermal Protection
The MAX17509 features a thermal-fault protection circuit.
When the junction temperature rises above +160°C (typ),
a thermal sensor activates, pulls down the PGOOD outputs, and shuts down both regulators. The regulators are
allowed to restart after the junction temperature cools by
20°C (typ).
Input Voltage Range
Input Capacitor Selection
The input capacitor must meet the ripple current requirement (IRMS) imposed by the switching currents. The
IRMS requirements of the regulator can be determined by
the following equation:
IRMS= I OUT × D × (1 − D)
where D = VOUT/VIN is the duty ratio of the controller.
The worst-case RMS current requirement occurs when
operating with D = 0.5. At this point, the above equation
simplifies to IRMS = 0.5 x IOUT.
The minimum input capacitor required can be calculated
by the following equation,
Power Good Output (PGOOD_)
PGOOD_ is an open-drain output of the window comparator that continuously monitors output voltage. Effectively,
it indicates fault conditions, including UV/OV of output
voltage, OCR of regulators’ current, and OT. PGOOD_
can be used to enable circuits that are supplied by the
corresponding voltage rail, or to turn on subsequent supplies.
Each PGOOD_ goes high (high impedance) when the
corresponding channel has completed soft-start, regulator
output voltage is in regulation. Each PGOOD_ goes low
when the corresponding regulator output voltage drops
below 15% (typ) or rises above 15% (typ) of its nominal
regulated voltage. PGOOD_ asserts low during soft-start,
soft-stop, fault conditions, and when the corresponding
regulator is disabled. Connect a 1k – 100kΩ (10kΩ, typ)
pullup resistor from PGOOD_ to the relevant logic rail to
level-shift the signal. PGOOD pins cannot sink more than
10mA of current.
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C IN =
(IIN_AVG ) × (1 − D)
(∆VIN) × FSW
Where,
IIN_AVG is the average input current given by,
IIN_AVG =
POUT
η × VIN
D is the operating duty cycle, which is approximately
equal to VOUT /VIN
∆VIN is the required input voltage ripple
fSW is the operating switching frequency
POUT is the out power, which is equal to VOUT x IOUT
η is the efficiency.
For the MAX17509 system (IN_) supply, ceramic capacitors are preferred due to their resilience to inrush surge
currents typical of systems, and due to their low parasitic
inductance, which helps reduce the high-frequency ringing on the IN supply when the internal MOSFETs are
turned off. Choose an input capacitor that exhibits less
than +10°C temperature rise at the RMS input current
for optimal circuit longevity. A 10µF works well in general
Maxim Integrated │ 17
MAX17509
4.5–16V, Dual 3A, High-Efficiency, Synchronous Step-Down
DC-DC Converter with Resistor Programmability
application. Place an additional 0.1µF between IN_ and
PGND_ as close to the device as possible.
Inductor Selection
Three key inductor parameters must be specified for
operation with the MAX17509: inductance value (L),
inductor saturation current (ISAT), and DC resistance
(RDCR). To select inductance value, the ratio of inductor peak-to-peak AC current to DC average current (LIR)
must be selected first. MAX17509 is optimally designed
to work with 30% peak-to-peak ripple current to averagecurrent ratio (LIR = 0.3). The switching frequency, input
voltage, output voltage, and selected LIR then determine
the inductor value as follows:
(
VOUT (VSUP − VOUT )
∆IINDUCTOR =
VSUP × f SW × L
where ΔIINDUCTOR is in mA, L is in μH, and fSW is in kHz
The inductor specification must be large enough not
to saturate at the peak inductor current (IPEAK), or at
least in a range where the inductance does not degrade
significantly. The maximum inductor current equals the
maximum load current in addition to half of the peakto-peak ripple current. The runaway peak current limit
(5.6A) can be used directly for the inductor saturation
current specification of a conservative system design.
=
IPEAK ILOAD(MAX) +
)
VOUT VSUP(MIN) − VOUT
L=
VSUP(MIN) × f SW × I OUT(MAX) × LIR
where VSUP(MIN) is the minimum supply voltage, VOUT is
the typical output voltage, and IOUT(MAX) is the maximum
load current. fSW is the switching frequency. However, if it
is necessary, higher inductor values can be selected.
For the selected inductance value, the actual peak-topeak inductor ripple current (ΔIINDUCTOR) is defined by:
∆IINDUCTOR
2
Table 4 summarizes the optimal inductor and output
capacitor value selection for typical 5VIN and 12VIN
range. The requirement is to select an inductor greater
than or equal to the value shown, and output capacitor
the same actual value (not nominal value) or higher. The
components listed optimize the transient response time
and set bandwidth to be fSW/8.
Table 4. Optimal Inductor and Output Capacitor Selection
6 ≤ VIN ≤ 16V
(TYPICAL 12VIN
RANGE DOWN TO 6VIN)
4.5V ≤ VIN ≤ 6V
(TYPICAL 5VIN RANGE)
VOUT (V)
FSW = 500KHZ
LMIN
(µH)
COUTMIN
(µF)
0.9
2.2
1
1.2
1.5
1.8
2
2.5
3
3.3
3.6
2.2
2.7
3.3
3.9
3.9
4.7
4.7
3.3
2.7
FSW = 1MHZ
FSW = 1.5MHZ
LMIN
(µH)
COUTMIN
(µF)
LMIN
(µH)
COUTMIN
(µF)
LMIN
(µH)
COUTMIN
(µF)
139
1
100
0.82
78
0.56
107
89
71
59
54
43
36
36
36
1.2
1.2
1.5
1.8
2.2
2.2
2.2
1.5
1.5
82
68
55
46
41
33
18
18
18
0.82
1
1
1.2
1.2
1.5
1.5
1.2
1.2
55
46
36
30
27
22
12
12
12
0.56
0.68
0.82
0.82
1
1.2
1.2
0.82
0.82
5.0 (7VIN)
5.0 (9VIN)
5.0 (12VIN)
5.0 (16VIN)
www.maximintegrated.com
FSW = 2MHZ
(NOT APPLICABLE)
FSW = 1MHZ
LMIN
(µH)
COUTMIN (µF)
50
1
100
41
34
27
23
21
16
9
9
9
1.2
1.2
1.5
1.8
2.2
2.2
2.2
2.2
2.7
82
68
55
46
41
33
18
18
18
1.8
18
2.7
18
3.9
18
4.7
18
Maxim Integrated │ 18
MAX17509
4.5–16V, Dual 3A, High-Efficiency, Synchronous Step-Down
DC-DC Converter with Resistor Programmability
Output Capacitor Selection
The output capacitor selection requires careful evaluation
of several different design requirements – DC voltage
rating, stability, transient response, and output ripple
voltage. Based on these requirements, a combination of
low-ESR polymer capacitor (lower cost but higher outputripple voltage) and ceramic capacitor (higher cost but low
output-ripple voltage) should be used to achieve stability
with low output ripple.
When choosing the ceramic capacitors, it is recommended
to choose the X5R and X7R dielectric formulations,
since the dielectrics have the best temperature and
voltage characteristics of all the ceramics for a given
value and size. It is important to note that the capacitance decreases as the voltage applied increases; thus
a ceramic capacitor rated at 47µF 6.3V may measure
47µF at 0V but measure 34µF with an applied voltage of
3.3V depending on the type of capacitor selected. Consult
capacitor manufacturer datasheet for the derating.
Loop Compensation
The simplified equation for minimum capacitor is shown
in the table below, where fSW is the switch frequency in
MHz, and COUT is the output capacitor in (µF). It is recommended to use all ceramic output capacitor solution,
so that the ESR is placed such that the zero frequency
formed by output capacitor and ESR is at or above fSW/2.
Output Ripple Voltage
With polymer capacitors, the ESR dominates and determines the output ripple voltage. The step-down regulator’s
output ripple voltage (VRIPPLE) equals the total inductor
ripple current (ΔIL) multiplied by the output capacitor’s
ESR. Therefore, the maximum ESR to meet the output
ripple voltage requirement is:
V
R ESR ≤ RIPPLE
∆IL
where,
1
V − VOUT VOUT
=
∆IL IN
×
×
L
VIN f SW
where fSW is the switching frequency and L is the Inductor.
The actual capacitance value required relates to the
physical case size needed to achieve the ESR requirement, as well as to the capacitor chemistry. Thus, polymer
capacitor selection is usually limited by ESR and voltage
rating rather than by capacitance value.
www.maximintegrated.com
With ceramic capacitors, the ripple voltage due to capacitance dominates the output ripple voltage. Therefore
the minimum capacitance needed with ceramic output
capacitors is,
∆IL
1
=
C OUT
×
8 × f SW VRIPPLE
Alternatively, combining ceramics (for the low ESR) and
polymers (for the bulk capacitance) helps balance the
output capacitance vs. output ripple voltage requirements.
Load Transient Response
The load transient response depends on the overall output impedance over frequency, and the overall amplitude
and slew rate of the load step. In applications with large,
fast load transients (load step > 80% of full load and slew
rate > 10A/μs), the output capacitor’s high-frequency
response–ESL and ESR–needs to be considered. To
prevent the output voltage from spiking too low under a
load-transient event, the ESR is limited by the following
equation (ignoring the sag due to finite capacitance):
V
R ESR ≤ RIPPLESTEP
∆IOUTSTEP
Table 5. Simplified Equation for
Minimum Output Capacitor Requirement
FREQUENCY
PROGRAMMED
VOUT (V)
500kHz 1MHz
1.MHz
0.904 to 2.839
2.859 to 5.048
107/ VOUT
2MHz
82/(fSW x VOUT)
18/fSW
where VRIPPLESTEP is the allowed voltage drop during
load current transient, IOUTSTEP is the maximum load
current step.
The capacitance value dominates the mid frequency
output impedance and continues to dominate the load
transient response as long as the load transient’s slew
rate is fewer than two switching cycles. Under these
conditions, the sag and soar voltages depend on the
output capacitance, inductance value, and delays in the
transient response. Low inductor values allow the inductor current to slew faster, replenishing charge removed
from or added to the output filter capacitors by a sudden
load step, especially with low differential voltages across
the inductor. The sag voltage (VSAG) that occurs after
applying the load current can be estimated as:
Maxim Integrated │ 19
MAX17509
4.5–16V, Dual 3A, High-Efficiency, Synchronous Step-Down
DC-DC Converter with Resistor Programmability
L × ∆IOUT 2
1
STEP
1
C OUT_SAG
=
× 2 (VIN × D MAX ) − VOUT
VSAG
+(∆IOUT
(T
T))
×
−
∆
STEP
SW
If the application has a thermal-management system that
ensures that the devices’ exposed pad is maintained at a
given temperature (TEP_MAX) by using proper heatsinks,
then the junction temperature rise can be estimated
at any given maximum ambient temperature from the
following equation:
Where
TJ_MAX = TEP_MAX + (θJC x PLOSS)
DMAX is the maximum duty factor (93%),
where,
TSW is the switching period (1/fSW)
ΔT equals VOUT / VIN x TSW
The amount of overshoot voltage (VSOAR) that occurs
after load removal (due to stored inductor energy) can be
calculated as:
C OUT_SOAR =
(∆IOUTSTEP )
2
L
PLOSS is the maximum allowed power losses with
maximum allowed junction temperature
TJ_MAX is the maximum allowed Junction temperature
TA is operating ambient temperature
θJA is the junction-to-ambient thermal resistance
θJC is the junction-to-case thermal resistance
2VOUT VSOAR
When the MAX17509 is operating under low duty cycle
the output capacitor size is usually determined by the
COUTSOAR.
Power dissipation
Ensure that the junction temperature of the device
does not exceed +125ºC under the operating conditions
specified for the power supply.
At a particular operating condition, the power losses that
lead to temperature rise of the part are estimated as
follows:
PLOSS = (POUT x (1 -1) - (I OUT2 x RDCR)
POUT = VOUT x IOUT
where POUT is the total output power, η is the efficiency
of the converter, and RDCR is the DC resistances of
the inductor (see the Typical Operating Characteristics
for more information on efficiency at typical operating
conditions.)
For a multilayer board, the thermal-performance metrics
for the package are given below:
θJA = 29°C/W
θJC = 1.7°C/W
The junction temperature rise of the devices can be
estimated at any given ambient temperature (TA) from the
following equation:
TJ_MAX = TA + (θJA x PLOSS)
www.maximintegrated.com
Maxim Integrated │ 20
MAX17509
4.5–16V, Dual 3A, High-Efficiency, Synchronous Step-Down
DC-DC Converter with Resistor Programmability
PCB Layout Guidelines
Careful PCB layout is critical to achieving low switching
losses and clean, stable operation. Use the following
guidelines for good PCB layout shown in Figure 4. The
layout of Regulator 2 can be achieved by applying the
recommended layout of Regulator 1 symmetrically.
●●
Keep the bypass capacitors as close as possible to
the pins and the return path (1) VIN_ and PGND_
pins, (2) VCC and PGND_ pins, (3) OUT side of the
inductor and PGND_ pins, (4) BST_ and LX_ pins,
and (5) AVCC and SGND pin.
●●
Route high-speed switching nodes (BST_ and LX_)
away from sensitive analog areas (OUT_, AVCC).
●●
Connect resistors between device configuration pins
and SGND, and keep the trace length to below 3cm
to minimize the trace capacitance
L1
●●
Connect EP to SGND plane, and connect to PGND_
at a single point typically at the output capacitor
ground.
●●
Keep the power traces and load connections short.
This practice is essential for high efficiency. Using
thick copper PCBs (2oz vs. 1oz) can enhance full
load efficiency. Correctly routing PCB traces is a
difficult task that must be approached in terms of
fractions of centimeters, where a single milliohm of
excess trace resistance causes a measurable efficiency penalty.
●●
Use multiple vias to connect internal PGND_ planes
(not shown) to the top layer PGND_ plane. Connect
PGND1 and PGND2 together to become PGND
using large copper plane.
VOUT1
LX1
LX1
PGND
EN1
FINE1
SS1
SS2
FINE2
COARSE2
EN2
32
31
30
29
28
27
26
25
24
2
23
PGND2
PGND1
3
22
LX1
5
21 20
LX2
IN1
6
19
IN2
18
IN2
17
BST2
PGOOD2
VCC
SYNC
MODE
AVCC
N.C.
13
16
12
14
11
15
9
TOP LAYER
10
VIAS TO BOTTOM-SIDE PGND PLANE
VIAS TO BOTTOM-SIDE LX1
VIAS TO BOTTOM-SIDE SGND
SGND
BST1
8
IN1
PGOOD1
IN1
7
PGND2
LX1
4
CIN1
1
OUT2
PGND1
OUT1
PGND
COARSE1
COUT1
LX2
CBST1
PGND
BOTTOM LAYER
Figure 4: Recommended Layout
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Maxim Integrated │ 21
MAX17509
4.5–16V, Dual 3A, High-Efficiency, Synchronous Step-Down
DC-DC Converter with Resistor Programmability
Typical Application Circuits
SGND
PGND1
L1
VOUT1
3
4
FINE2
RCOARSE 2
RFINE 2
27
26
PGND1 PGND2
25
EN2
RSS2
RSS1
SS1
28
COARSE2
OUT1
2
29
AVCC
SS2
1
30
FINE1
EN1
SGND
31
COARSE1
32
EP
RFINE 1
RCOARSE 1
AVCC
OUT2
PGND1
PGND2
PGND1
PGND2
LX1
LX2
MAX17509
PGND1
6 IN1
IN2
7 IN1
IN2
9
PGND1
10
11
12
14
15
PGOOD2
N.C.
13
LX2
MODE
VCC
CBST1
PGND1
8 BST1
AVCC
CIN1
PGOOD1
VIN1
SYNC
5 LX1
SGND
COUT 1
BST2
24
23
22
PGND2
21
L2
20
COUT 2
19
PGND2
18
VIN2
17
16
VOUT2
CIN2
CBST2
PGND2
PGND2
RMODE
CVCC
CAVCC
AVCC
PGND1 SGND
SGND
SGND PGND2
SGND PGND1
SGND
SGND
Figure 5: Two Independent Outputs
www.maximintegrated.com
Maxim Integrated │ 22
MAX17509
4.5–16V, Dual 3A, High-Efficiency, Synchronous Step-Down
DC-DC Converter with Resistor Programmability
Typical Application Circuits (continued)
VOUT
SGND
AVCC
COUT
AVCC
2
4
RCOARSE 2
RFINE 2
EN2
RSS2
RSS1
SS1
SS2
FINE2
OUT2
PGND1
LX1
LX2
MAX17509
LX2
IN2
9
PGND1
10
11
12
13
N.C.
AVCC
8 BST1
14
15
PGOOD2
IN2
7 IN1
MODE
6 IN1
SGND
CBST1
PGND1
25
PGND2
PGOOD1
CIN1
26
PGND2
5 LX1
VIN
27
PGND1
VCC
L1
3
28
SYNC
PGND1
29
COARSE2
OUT1
FINE1
1
30
31
COARSE1
EN1
EP 32
SGND
RFINE 1
RCOARSE 1
PGND
BST2
24
23
22
PGND2
21
L2
20
19
18
VIN
17
CIN2
CBST2
16
PGND2
PGND2
RMODE
CVCC
CAVCC
AVCC
PGND1 SGND
PGND
SGND
SGND
SGND
PGND
SGND
PGND2
PGND1 PGND2
SGND
Figure 6: Dual-Phase Single Output
Ordering Information
Package Information
PART
TEMP RANGE
PIN-PACKAGE
MAX17509ATJ+
-40ºC to +125ºC
32 TQFN-EP*
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed paddle.
Chip Information
PROCESS: BiCMOS
www.maximintegrated.com
For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
32 TQFN-EP
T3255+4
21-0140
90-0012
Maxim Integrated │ 23
MAX17509
4.5–16V, Dual 3A, High-Efficiency, Synchronous Step-Down
DC-DC Converter with Resistor Programmability
Revision History
REVISION
NUMBER
REVISION
DATE
0
2/15
DESCRIPTION
Initial release
PAGES
CHANGED
—
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
© 2015 Maxim Integrated Products, Inc. │ 24
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