EVALUATION KIT AVAILABLE
MAX17600–MAX17605
General Description
The MAX17600–MAX17605 devices are high-speed
MOSFET drivers capable of sinking /sourcing 4A peak
currents. The devices have various inverting and noninverting part options that provide greater flexibility in
controlling the MOSFET. The devices have internal
logic circuitry that prevents shoot-through during outputstate changes. The logic inputs are protected against
voltage spikes up to +14V, regardless of VDD voltage. Propagation delay time is minimized and matched
between the dual channels. The devices have very fast
switching time, combined with short propagation delays
(12ns typ), making them ideal for high-frequency circuits.
The devices operate from a +4V to +14V single power
supply and typically consume 1mA of supply current. The
MAX17600/MAX17601 have standard TTL input logic
levels, while the MAX17603 /MAX17604/MAX17605 have
CMOS-like high-noise margin (HNM) input logic levels.
The MAX17600/MAX17603 are dual inverting input drivers, the MAX17601/MAX17604 are dual noninverting
input drivers, and the MAX17602/MAX17605 devices
have one noninverting and one inverting input. These
devices are provided with enable pins (ENA, ENB) for
better control of driver operation.
These devices are available in 8-pin (3mm x 3mm) TDFN,
8-pin (3mm x 5mm) µMAX®, and 8-pin SO packages and
operate over the -40°C to +125°C temperature range.
4A Sink/Source Current,
12ns, Dual MOSFET Drivers
Features
●● Dual Drivers with Enable Inputs
●● +4V to +14V Single Power-Supply Range
●● 4A Peak Sink /Source Current
●● Inputs Rated to +14V, Regardless of VDD Voltage
●● Low 12ns Propagation Delay
●● 6ns Typical Rise and 5ns Typical Fall Times with
1nF Load
●● Matched Delays Between Channels
●● Parallel Operation of Dual Outputs for Larger
Driver Output Current
●● TTL or HNM Logic-Level Inputs with Hysteresis for
Noise Immunity
●● Low Input Capacitance: 10pF (typ)
●● Thermal Shutdown Protection
●● TDFN, μMAX, and SO Package Options
●● -40°C to +125°C Operating Temperature Range
Typical Operating Circuit
VDD
(UP TO +14V)
ENA
VDD
Applications
●●
●●
●●
●●
●●
Power MOSFET Switching
Switch-Mode Power Supplies
DC-DC Converters
Motor Control
Power-Supply Modules
Ordering Information appears at end of data sheet.
μMAX is a registered trademark of Maxim Integrated
Products, Inc.
19-6177; Rev 2; 6/17
INA
INB
MAX17600
MAX17601
MAX17602
MAX17603
MAX17604
MAX17605
OUTA
ENB
OUTB
GND
MAX17600–MAX17605
4A Sink/Source Current,
12ns, Dual MOSFET Drivers
Absolute Maximum Ratings
VDD, INA, INB, ENA, ENB to GND........................-0.3V to +16V
OUTA, OUTB to GND............................................-0.3V to +16V
Junction Operating Temperature Range........... -40°C to +125°C
Continuous Power Dissipation (TA = +70°C)
8-Pin TDFN (derate 23.8mW/°C above +70°C).........1904mW
8-Pin SO (derate 74mW/°C above +70°C).............. 588.2mW*
8-Pin µMAX (derate 12.9mW/°C above +70°C)......1030.9mW
Operating Temperature Range.......................... -40°C to +125°C
Junction Temperature.......................................................+150°C
Storage Temperature Range............................. -65°C to +150°C
Lead Temperature (soldering, 10s).................................. +300°C
Soldering Temperature (reflow)........................................+240°C
*As per JEDEC 51 standard.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Information
PACKAGE TYPE: 8 TDFN
Package Code
T833+2
Outline Number
21-0137
Land Pattern Number
90-0059
THERMAL RESISTANCE, FOUR-LAYER BOARD
Junction to Ambient (θJA)
42°C/W
Junction to Case (θJC)
8°C/W
PACKAGE TYPE: 8 SO
Package Code
S8+2
Outline Number
21-0041
Land Pattern Number
90-0096
THERMAL RESISTANCE, FOUR-LAYER BOARD
Junction to Ambient (θJA)
136°C/W
Junction to Case (θJC)
38°C/W
PACKAGE TYPE: 8 µMAX
Package Code
U8E+2
Outline Number
21-0107
Land Pattern Number
90-0145
THERMAL RESISTANCE, FOUR-LAYER BOARD
Junction to Ambient (θJA)
77.6°C/W
Junction to Case (θJC)
5°C/W
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board.
For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
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Maxim Integrated │ 2
MAX17600–MAX17605
4A Sink/Source Current,
12ns, Dual MOSFET Drivers
Electrical Characteristics
(VDD = 12V, CL = 0F, at TA = -40°C to +125°C, unless otherwise noted. Typical values are specified at TA = +25°C. Parameters
specified at VDD = 4V apply to the TTL versions only.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER SUPPLY (VDD)
VDD Operating Range
VDD
VDD Undervoltage Lockout
UVLO
TTL versions
4
14
HNM versions
6
14
VDD rising
3
VDD UVLO Hysteresis
VDD UVLO to OUT_ Delay
VDD rising
IDD_Q
VDD Supply Current
IDD_SW
3.5
3.85
V
V
200
mV
120
µs
Not switching, VDD = 14V (Note 2)
1
2
VDD = 4.5V, CL = 1nF, both channels
switching at 1MHz
12
18
VDD = 14V, CL = 10nF (Note 2)
4
mA
DRIVER OUTPUT (SOURCE) (OUTA, OUTB)
Peak Output Current (Sourcing)
IPK-P
Driver Output Resistance Pulling Up
(Note 3)
RON-P
A
VDD = 14V, IOUT_ = 100mA
0.88
1.85
VDD = 4V, IOUT_ = 100mA
0.91
1.95
Ω
DRIVER OUTPUT (SINK) (OUTA, OUTB)
Peak Output Current (Sinking)
IPK-N
Driver Output Resistance Pulling
Down (Note 3)
RON-N
VDD = 14V, CL = 10nF (Note 2)
4
A
VDD = 14V, IOUT_ = -100mA
0.5
0.95
VDD = 4V, IOUT_ = -100mA
0.52
1
Ω
LOGIC INPUT (INA, INB)
VIN_ Logic-High Input Voltage
VIH
VIN_ Logic-Low Input Voltage
VIL
Logic Input Hysteresis
VHYS
MAX17600/1/2
2.1
MAX17603/4/5
4.25
V
MAX17600/1/2
0.8
MAX17603/4/5
2.0
MAX17600/1/2
0.34
MAX17603/4/5
0.9
V
Logic Input Leakage Current
ILKG
VINA = VINB = 0V or VDD (MAX17600/1/2)
Logic Input Bias Current
IBIAS
VINA = VINB = 0V or VDD (MAX17603/4/5)
10
µA
Logic Input Capacitance
CIN
(Note 2)
10
pF
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-1
V
+0.02
+1
µA
Maxim Integrated │ 3
MAX17600–MAX17605
4A Sink/Source Current,
12ns, Dual MOSFET Drivers
Electrical Characteristics (continued)
(VDD = 12V, CL = 0F, at TA = -40°C to +125°C, unless otherwise noted. Typical values are specified at TA = +25°C. Parameters
specified at VDD = 4V apply to the TTL versions only.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ENABLE (ENA, ENB)
VEN_H High Level Voltage
VEN_L Low Level Voltage
Enable Hysteresis
EN_HYS
Enable Pullup Resistor to VDD
Rpu
Propagation Delay from EN_ to OUT_
(Note 2)
tpd
MAX17600/1/2
2.1
MAX17603/4/5
4.25
V
MAX17600/1/2
0.8
MAX17603/4/5
2.0
MAX17600/1/2
0.34
MAX17603/4/5
0.9
V
MAX17600/1/2
50
100
200
MAX17603/4/5
100
200
400
EN_ rising
7
EN_ falling
7
V
kΩ
ns
SWITCHING CHARACTERISTICS (VDD = 14V) (Note 2)
OUT_ Rise Time
tR
OUT_ Fall Time
tF
CL = 1nF
6
CL = 4.7nF
20
CL = 10nF
40
CL = 1nF
6
CL = 4.7nF
16
ns
ns
CL = 10nF
25
Turn-On Delay Time
tD-ON
CL = 1nF
12
ns
Turn-Off Delay Time
tD-OFF
CL = 1nF
12
ns
SWITCHING CHARACTERISTICS (VDD = 4.5V) (Note 2)
OUT_ Rise Time
tR
OUT_ Fall Time
tF
CL = 1nF
5
CL = 4.7nF
15
CL = 10nF
28
CL = 1nF
5
CL = 4.7nF
10
CL = 10nF
18
ns
ns
Turn-On Delay Time
tD-ON
CL = 1nF
12
ns
Turn-Off Delay Time
tD-OFF
CL = 1nF
12
ns
VDD = 14V, CL = 10nF
8
ns
MATCHING CHARACTERISTICS (Note 2)
Matching Propagation Delays
Between Channel A and Channel B
Note 1: All devices are production tested at TA = +25°C. Limits over temperature are guaranteed by design.
Note 2: Design guaranteed by bench characterization. Limits are not production tested.
Note 3: For SOIC, μMAX package options, these are only Typ parameters.
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Maxim Integrated │ 4
MAX17600–MAX17605
4A Sink/Source Current,
12ns, Dual MOSFET Drivers
Typical Operating Characteristics
(CL = 1nF, TA = +25°C, unless otherwise noted.)
RISE TIME vs. SUPPLY VOLTAGE
(COUT_ = 1nF)
5.0
4.5
4.0
TA = +85°C
FALL TIME (ns)
TA = +125°C
4.5
TA = +25°C
4.0
3.5
2.5
4
6
8
10
12
1.5
14
TA = -40°C
TA = 0°C
4
6
8
10
14
12
PROPAGATION DELAY TIME (HIGH TO LOW)
vs. SUPPLY VOLTAGE (COUT_ = 1nF)
TA = +85°C
TA = +25°C
10
TA = 0°C
6
4
8
PROPAGATION DELAY TIME (ns)
TA = +125°C
18
TA = -40°C
10
12
TA = +125°C
16
TA = +85°C
14
TA = +25°C
12
TA = 0°C
TA = -40°C
10
8
14
MAX17600 toc04
PROPAGATION DELAY TIME (LOW TO HIGH)
vs. SUPPLY VOLTAGE (COUT_ = 1nF)
MAX17600 toc03
SUPPLY VOLTAGE, VDD (V)
12
6
4
8
10
12
14
SUPPLY CURRENT vs. SUPPLY VOLTAGE
(COUT_ = 0nF)
SUPPLY CURRRENT vs. LOAD CAPACITANCE
(VDD = 12V, COUTB = 0nF)
1MHz
500kHz
2.0
100kHz
1.5
1.0
NO SWITCHING
4
6
8
10
12
SUPPLY VOLTAGE, VDD (V)
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14
140
130
120
110
100
90
80
70
60
50
40
30
20
10
0
MAX17600 toc06
SUPPLY VOLTAGE, VDD (V)
SUPPLY CURRENT (mA)
SUPPLY VOLTAGE, VDD (V)
2.5
0.5
3.0
SUPPLY VOLTAGE, VDD (V)
14
3.0
SUPPLY CURRENT (mA)
TA = 0°C
16
8
TA = +25°C
3.5
2.0
TA = -40°C
MAX17600 toc05
PROPAGATION DELAY TIME (ns)
18
TA = +85°C
TA = +125°C
2.5
3.0
2.0
MAX17600 toc02
5.5
RISE TIME (ns)
5.0
MAX17600 toc01
6.0
FALL TIME vs. SUPPLY VOLTAGE
(COUT_ = 1nF)
500kHz
1MHz
NO
SWITCHING
100kHz
0
1
2
3
4
5
6
7
8
9
10
LOAD CAPACITANCE (nF)
Maxim Integrated │ 5
MAX17600–MAX17605
4A Sink/Source Current,
12ns, Dual MOSFET Drivers
Typical Operating Characteristics (continued)
(CL = 1nF, TA = +25°C, unless otherwise noted.)
2.0
100kHz
1.5
1.0
2.0
RISING
FALLING
1.5
1.0
0.5
-40
-20
0
20
40
60
80
0
100 120
1.2
1.1
RISING
1.0
0.9
FALLING
0.8
0.7
NO SWITCHING
0.5
SUPPLY CURRENT vs. LOGIC INPUT
VOLTAGE (VDD = 12V, COUT_ = 0nF)
MAX17600 toc09
MAX17600 toc08
2.5
1.3
SUPPLY CURRENT (mA)
500kHz
2.5
INPUT THRESHOLD VOLTAGE
vs. SUPPLY VOLTAGE (COUT_ = 0nF)
3.0
INPUT THRESHOLD VOLTAGE (V)
1MHz
3.0
SUPPLY CURRENT (mA)
MAX17600 toc07
3.5
SUPPLY CURRENT vs. TEMPERATURE
(VDD = 12V, COUT_ = 0nF)
4
6
8
10
12
0.6
14
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
AMBIENT TEMPERATURE (°C)
SUPPLY VOLTAGE, VDD (V)
LOGIC INPUT VOLTAGE (V)
LOGIC INPUT VOLTAGE
vs. OUTPUT VOLTAGE (MAX17601)
(VDD = +4V, COUTA = 4.7nF)
LOGIC INPUT VOLTAGE
vs. OUTPUT VOLTAGE (MAX17601)
(VDD = +4V, COUTA = 10nF)
LOGIC INPUT VOLTAGE
vs. OUTPUT VOLTAGE (MAX17601)
(VDD = +4V, COUTA = 4.7nF)
MAX17600 toc10
MAX17600 toc11
INA
2V/div
MAX17600 toc12
INA
2V/div
INA
2V/div
OUTA
2V/div
OUTA
2V/div
OUTA
2V/div
20ns/div
20ns/div
20ns/div
LOGIC INPUT VOLTAGE
vs. OUTPUT VOLTAGE (MAX17601)
(VDD = +4V, COUTA = 10nF)
LOGIC INPUT VOLTAGE
vs. OUTPUT VOLTAGE (MAX17601)
(VDD = +14V, COUTA = 4.7nF)
LOGIC INPUT VOLTAGE
vs. OUTPUT VOLTAGE (MAX17601)
(VDD = +14V, COUTA = 10nF)
MAX17600 toc13
MAX17600 toc14
MAX17600 toc15
INA
5V/div
INA
5V/div
INA
2V/div
OUTA
5V/div
OUTA
5V/div
OUTA
2V/div
20ns/div
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20ns/div
20ns/div
Maxim Integrated │ 6
MAX17600–MAX17605
4A Sink/Source Current,
12ns, Dual MOSFET Drivers
Typical Operating Characteristics (continued)
(CL = 1nF, TA = +25°C, unless otherwise noted.)
LOGIC INPUT VOLTAGE
vs. OUTPUT VOLTAGE (MAX17601)
(VDD = +14V, COUTA = 4.7nF)
LOGIC INPUT VOLTAGE
vs. OUTPUT VOLTAGE (MAX17601)
(VDD = +14V, COUTA = 10nF)
MAX17600 toc16
LOGIC INPUT VOLTAGE
vs. OUTPUT VOLTAGE (MAX17604)
(VDD = +14V, COUTA = 4.7nF)
MAX17600 toc17
MAX17600 toc18
INA
5V/div
INA
5V/div
OUTA
5V/div
OUTA
5V/div
20ns/div
INA
5V/div
OUTA
5V/div
20ns/div
LOGIC INPUT VOLTAGE
vs. OUTPUT VOLTAGE (MAX17604)
(VDD = +14V, COUTA = 10nF)
20ns/div
LOGIC INPUT VOLTAGE
vs. OUTPUT VOLTAGE (MAX17604)
(VDD = +14V, COUTA = 4.7nF)
MAX17600 toc19
MAX17600 toc20
INA
5V/div
INA
5V/div
OUTA
5V/div
OUTA
5V/div
20ns/div
20ns/div
LOGIC INPUT VOLTAGE
vs. OUTPUT VOLTAGE (MAX17604)
(VDD = +14V, COUTA = 10nF)
LOGIC OUTPUT vs. ENABLE
(VDD = +14V, COUTA = 0nF)
MAX17600 toc21
MAX17600 toc22
ENA
5V/div
INA
5V/div
INA
5V/div
OUTA
5V/div
20ns/div
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VDD
5V/div
OUTA
10V/div
4µs/div
Maxim Integrated │ 7
MAX17600–MAX17605
4A Sink/Source Current,
12ns, Dual MOSFET Drivers
Pin Configurations
TOP VIEW
TOP VIEW
ENA
INA
1
2
GND
3
INB
4
ENB OUTA VDD OUTB
8
+
MAX17600
MAX17601
MAX17602
MAX17603
MAX17604
MAX17605
8
7
ENB
VDD
5
OUTB
SO
6
5
MAX17600
MAX17601
MAX17602
MAX17603
MAX17604
MAX17605
OUTA
6
7
TOP VIEW
ENA 1
INA 2
GND 3
INB 4
+
+
MAX17600
MAX17601
MAX17602
MAX17603
MAX17604
MAX17605
8 ENB
7 OUTA
6 VDD
5 OUTB
µMAX
1
2
3
4
ENA
INA
GND
INB
TDFN
Pin Description
PIN
NAME
FUNCTION
1
ENA
Enable Input for Driver A. Internally pulled to VDD through a 100kΩ resistor. Leave unconnected for
always-on operation. Connect to GND for disabling the corresponding channel.
2
INA
Logic Input for Channel A
3
GND
Ground
4
INB
Logic Input for Channel B
5
OUTB
6
VDD
7
OUTA
Channel A Driver Output. Sources and sinks current for channel A to turn the external MOSFET at OUTA
on or off.
8
ENB
Enable Input for Driver B. Internally pulled to VDD through a 100kΩ resistor. Leave unconnected for
always-on operation. Connect to GND for disabling the corresponding channel.
—
EP
Channel B Driver Output. Sources and sinks current for channel B to turn the external MOSFET at OUTB
on or off.
Power-Supply Input. Bypass to GND with one or more low-ESR 0.1µF ceramic capacitors.
Exposed Pad (TDFN Only). Internally connected to GND. Do not use the EP as the only ground connection.
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Maxim Integrated │ 8
MAX17600–MAX17605
4A Sink/Source Current,
12ns, Dual MOSFET Drivers
Functional Diagram
INA
VIH
VIL
CHANNEL B
GND
OUTA
90%
10%
IN LOGIC
LEVEL SHIFT DOWN
INB
tD-ON
tD-OFF
PREDRIVER
tR
tF
VL = 5V
OUTB
BBM
INB
VIH
VIL
ENB
IN LOGIC
LEVEL SHIFT UP
BG + UVLO +
TSHDN
BG + UVLO +
TSHDN
IN LOGIC
LEVEL SHIFT UP
OUTB
90%
PREDRIVER
10%
Figure 1. Timing Diagram for the MAX17601/MAX17604
VDD - 5V
INA
PREDRIVER
90%
OUTA
BBM
10%
tD-ON
VL = 5V
tD-OFF
tR
tF
PREDRIVER
INA
VIH
VIL
GND
CHANNEL A
VIH
VIL
OUTA
IN LOGIC
LEVEL SHIFT DOWN
tR
tF
VDD
ENA
INA
tD-ON
tD-OFF
VDD - 5V
OUTB
90%
10%
tD-ON
tD-OFF
tF
tR
Figure 2. Timing Diagram for the MAX17602/MAX17605
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Maxim Integrated │ 9
MAX17600–MAX17605
4A Sink/Source Current,
12ns, Dual MOSFET Drivers
Detailed Description
INA
The MAX17600–MAX17605 are high-speed MOSFET
drivers capable of sinking/sourcing 4A peak currents.
The devices have various inverting and noninverting part
options that provide greater flexibility in controlling the
MOSFET. The devices have internal logic circuitry that
prevents shoot-through during output-state changes.
The logic inputs are protected against voltage spikes
up to +16V, regardless of VDD voltage. Propagation
delay time is minimized and matched between the dual
channels. The devices have very fast switching time,
combined with short propagation delays (12ns typ),
making them ideal for high-frequency circuits. The
devices operate from a +4V to +14V single power
supply and typically consume 1mA of supply current.
The MAX17600/MAX17601/MAX17602 have standard
TTL input logic levels, while the MAX17603/MAX17604/
MAX17605 have CMOS-like high-noise margin (HNM)
input logic levels. The MAX17600/MAX17603 are dual
inverting input drivers, the MAX17601/MAX17604 are
dual noninverting input drivers, and the MAX17602/
MAX17605 have one noninverting and one inverting
input. These devices are provided with enable pins
(ENA and ENB) for better control of driver operation.
VIH
VIL
OUTA
90%
10%
tD-ON
tD-OFF
tR
tF
INB
VIH
VIL
OUTB
90%
10%
tD-ON
tD-OFF
tR
tF
Figure 3. Timing Diagram for the MAX17600/MAX17603
ENB
ENA
MAX17600
MAX17601
INA MAX17602 OUTA
MAX17603
VDD
GND MAX17604
MAX17605
Logic Inputs
VDD
COUTA
OUTB
INB
COUTB
The MAX17600/MAX17601/MAX17602 have standard
TTL input logic levels, while the MAX17603/MAX17604/
MAX17605 have CMOS-like HNM input logic levels (see
the Electrical Characteristics table). Table 1 gives the truth
table for various part options.
Figure 4. Test Circuit for the Timing Diagrams
Table 1. Truth Table
ENABLE
INPUTS
LOGIC
INPUTS
DUAL NONINVERTING
DRIVER
DUAL INVERTING
DRIVER
ONE INVERTING AND ONE
NONINVERTING DRIVER
ENA
ENB
INA
INB
OUTA
OUTB
OUTA
OUTB
OUTA
OUTB
H
H
H
H
H
H
L
L
L
H
H
H
H
L
H
L
L
H
L
L
H
H
L
H
L
H
H
L
H
H
H
H
L
L
L
L
H
H
H
L
L
L
X
X
L
L
L
L
L
L
L = Logic-low, H = Logic-high.
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Maxim Integrated │ 10
MAX17600–MAX17605
Undervoltage Lockout (UVLO)
When VDD is below the UVLO threshold, the output
stage n-channel device is on and the p-channel is off,
independent of the state of the inputs. This holds the
outputs low. The UVLO is typically 3.6V with 200mV
typical hysteresis to avoid chattering. A typical falling
delay of 2µs makes the UVLO immune to narrow negative
transients in noisy environments.
Driver Outputs
The devices feature 4A peak sourcing/sinking capabilities
to provide fast rise and fall times of the MOSFET gate.
Add a resistor in series with OUT_ to slow the corresponding rise/fall time of the MOSFET gate.
Applications Information
Supply Bypassing, Device
Grounding, and Placement
Ample supply bypassing and device grounding are
extremely important because when large external
capacitive loads are driven, the peak current at the VDD
pin can approach 4A, while at the GND pin, the peak
current can approach 4A. VDD drops and ground shifts
are forms of negative feedback for inverters and, if
excessive, can cause multiple switching when the
inverting input is used and the input slew rate is low. The
device driving the input should be referenced to the devices’ GND pin, especially when the inverting input is used.
Ground shifts due to insufficient device grounding can
disturb other circuits sharing the same AC ground return
path. Any series inductance in the VDD, OUT_, and/or
GND paths can cause oscillations due to the very high
di/dt that results when the devices are switched with any
capacitive load. A 2.2µF or larger value ceramic
capacitor is recommended, bypassing VDD to GND and
placed as close as possible to the pins. When driving very
large loads (e.g., 10nF) at minimum rise time, 10µF or
more of parallel storage capacitance is recommended. A
ground plane is highly recommended to minimize ground
return resistance and series inductance. Care should be
taken to place the devices as close as possible to the
external MOSFET being driven to further minimize board
inductance and AC path resistance.
Power Dissipation
Power dissipation of the devices consists of three
components, caused by the quiescent current, capacitive
charge and discharge of internal nodes, and the output
current (either capacitive or resistive load). The sum of
these components must be kept below the maximum
power-dissipation limit.
www.maximintegrated.com
4A Sink/Source Current,
12ns, Dual MOSFET Drivers
The quiescent current is 1mA typical. The current required
to charge and discharge the internal nodes is frequency
dependent (see the Typical Operating Characteristics).
The devices’ power dissipation when driving a ground
referenced resistive load is:
P = D x RON (MAX) x ILOAD2 per channel
where D is the fraction of the period the devices’ output
pulls high, RON (MAX) is the maximum pullup on-resistance of the device with the output high, and ILOAD is the
output load current of the devices.
For capacitive loads, the power dissipation is:
P = CLOAD x (VDD)2 x FREQ per channel
where CLOAD is the capacitive load, VDD is the supply
voltage, and FREQ is the switching frequency.
Layout Information
The devices’ MOSFET drivers source and sink large
currents to create very fast rise and fall edges at the
gate of the switching MOSFET. The high di/dt can cause
unacceptable ringing if the trace lengths and
impedances are not well controlled. The following PCB
layout guidelines are recommended when designing with
the devices:
●● Place at least one 2.2µF decoupling ceramic capacitor from VDD to GND as close as possible to the IC.
At least one storage capacitor of 10µF (min) should
be located on the PCB with a low-resistance path
to the VDD pin of the devices. There are two AC
current loops formed between the IC and the gate of
the MOSFET being driven. The MOSFET looks like
a large capacitance from gate to source when the
gate is being pulled low. The active current loop is
from OUT_ of the devices to the MOSFET gate to the
MOSFET source and to GND of the devices. When
the gate of the MOSFET is being pulled high, the
active current loop is from OUT_ of the devices to the
MOSFET gate to the MOSFET source to the GND terminal of the decoupling capacitor to the VDD terminal
of the decoupling capacitor and to the VDD terminal of
the devices. While the charging current loop is important, the discharging current loop is also critical. It is
important to minimize the physical distance and the
impedance in these AC current paths.
●● In a multilayer PCB, the component surface layer
surrounding the devices should consist of a ground
plane containing the discharging and charging current
loops.
Maxim Integrated │ 11
MAX17600–MAX17605
4A Sink/Source Current,
12ns, Dual MOSFET Drivers
Ordering Information/Selector Guide
PART
PIN-PACKAGE
CONFIGURATION
LOGIC LEVELS
TOP MARK
MAX17600ATA+
8 TDFN-EP* (3mm x 3mm)
Dual/Inverting
TTL
+BOJ
MAX17600ASA+
8 SO
Dual/Inverting
TTL
+
MAX17600AUA+
8 µMAX-EP*
Dual/Inverting
TTL
+AACI
MAX17601ATA+
8 TDFN-EP* (3mm x 3mm)
Dual/Noninverting
TTL
+BOK
MAX17601ASA+
8 SO
Dual/Noninverting
TTL
+
MAX17601AUA+
8 µMAX-EP*
Dual/Noninverting
TTL
+AACJ
MAX17602ATA+
8 TDFN-EP* (3mm x 3mm)
Inverting/Noninverting
TTL
+BOL
MAX17602ASA+
8 SO
Inverting/Noninverting
TTL
+
MAX17602AUA+
8 µMAX-EP*
Inverting/Noninverting
TTL
+AACK
MAX17603ATA+
8 TDFN-EP* (3mm x 3mm)
Dual/Inverting
HNM
+BOM
MAX17603ASA+
8 SO
Dual/Inverting
HNM
+
MAX17603AUA+
8 µMAX-EP*
Dual/Inverting
HNM
+AACL
MAX17604ATA+
8 TDFN-EP* (3mm x 3mm)
Dual/Noninverting
HNM
+BON
MAX17604ASA+
8 SO
Dual/Noninverting
HNM
+
MAX17604AUA+
8 µMAX-EP*
Dual/Noninverting
HNM
+AACM
MAX17605ATA+
8 TDFN-EP* (3mm x 3mm)
Inverting/Noninverting
HNM
+BOO
MAX17605ASA+
8 SO
Inverting/Noninverting
HNM
+
MAX17605AUA+
8 µMAX-EP*
Inverting/Noninverting
HNM
+AACN
Note: All devices are specified over the -40°C to +125°C temperature range. Optional 8-pin 2mm x 3mm TDFN package is available.
Contact your Maxim sales representative for more information.
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
Chip Information
PROCESS: BiCMOS
www.maximintegrated.com
Maxim Integrated │ 12
MAX17600–MAX17605
4A Sink/Source Current,
12ns, Dual MOSFET Drivers
Revision History
REVISION
NUMBER
REVISION
DATE
PAGES
CHANGED
0
1/12
Initial release
1
5/12
Added the MAX17600
1–12
2
6/17
Updated Electrical Characteristics table OUT_ Rise Time for Switching Characteristics
(VDD = 14V and VDD = 4.5V) units from pF to nF.
3–4
DESCRIPTION
—
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
© 2017 Maxim Integrated Products, Inc. │ 13
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