19-5098; Rev 0; 1/10
Ultra-Low-Power, 10Msps, Dual 8-Bit ADC
Features
The MAX19192 is an ultra-low-power, dual, 8-bit, 10Msps
analog-to-digital converter (ADC). The device features
two fully differential wideband track-and-hold (T/H)
inputs. These inputs have a 440MHz bandwidth and
accept fully differential or single-ended signals. The
MAX19192 delivers a typical signal-to-noise and distortion (SINAD) of 48.6dB at an input frequency of
1.875MHz and a sampling rate of 10Msps while consuming only 15.3mW. This ADC operates from a 2.7V to 3.6V
analog power supply. A separate 1.8V to 3.6V supply
powers the digital output driver. In addition to ultra-low
operating power, the MAX19192 features three powerdown modes to conserve power during idle periods.
Excellent dynamic performance, ultra-low power, and
small size make the MAX19192 ideal for applications in
imaging, instrumentation, and digital communications.
An internal 1.024V precision bandgap reference sets
the full-scale range of the ADC to ±0.512V. A flexible
reference structure allows the MAX19192 to use its
internal reference or accept an externally applied reference for applications requiring increased accuracy.
The MAX19192 features parallel, multiplexed, CMOScompatible three-state outputs. The digital output format is offset binary. A separate digital power input
accepts a voltage from 1.8V to 3.6V for flexible interfacing to different logic levels. The MAX19192 is available
in a 5mm × 5mm, 28-pin thin QFN package, and is
specified for the extended industrial (-40°C to +85°C)
temperature range.
o Ultra-Low Power
15.3mW (Normal Operation: 10Msps)
2µW (Shutdown Mode)
o Excellent Dynamic Performance
48.6dB SNR at fIN = 1.875MHz
70dBc SFDR at fIN = 1.875MHz
o 2.7V to 3.6V Single Analog Supply
o 1.8V to 3.6V TTL/CMOS-Compatible Digital
Outputs
o Fully Differential or Single-Ended Analog Inputs
o Internal/External Reference Option
o Multiplexed CMOS-Compatible Three-State Outputs
o 28-Pin Thin QFN Package
o Evaluation Kit Available (Order MAX19192EVKIT+)
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
/V denotes an automotive qualified part.
**Future product—contact factory for availability.
Pin Configuration
VDD
REFP
REFN
COM
REFIN
PD0
PD1
27
26
25
24
23
22
TOP VIEW
21
D0
2
20
D1
GND
3
19
D2
CLK
4
18
D3
GND
5
17
A/B
INB+
6
16
D4
15
D5
VDD
14
7
D6
EXPOSED PAD
13
INB-
MAX19192
D7
INA+
+
12
1
OVDD
INA-
8
Digital Audio Receiver Front-End
28 Thin QFN-EP*
11
WLAN, Mobile DSL, WLL Receiver
28 Thin QFN-EP*
-40°C to +85°C
OGND
Low-Power Video
-40°C to +85°C
MAX19192ETI/V+**
10
Battery-Powered Portable Instruments
MAX19192ETI+
GND
IQ Baseband Sampling
PIN-PACKAGE
9
Ultrasound and Medical Imaging
TEMP RANGE
VDD
Applications
PART
28
For higher sampling frequency applications, refer to the
MAX1195–MAX1198 dual 8-bit ADCs. Pin-compatible
versions of the MAX19192 are also available. Refer to
the MAX1191 data sheet for 7.5Msps, the MAX1192
data sheet for 22Msps, and the MAX1193 data sheet
for 45Msps.
Ordering Information
5mm x 5mm THIN QFN
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1
MAX19192
General Description
MAX19192
Ultra-Low-Power, 10Msps, Dual 8-Bit ADC
ABSOLUTE MAXIMUM RATINGS
VDD, OVDD to GND ...............................................-0.3V to +3.9V
OGND to GND.......................................................-0.3V to +0.3V
INA+, INA-, INB+,
INB- to GND.............-0.3V to the lesser of (VDD + 0.3V or + 3.9V)
CLK, REFIN, REFP, REFN, COM to GND ....-0.3V to the lesser of
(VDD + 0.3V or + 3.9V)
PD0, PD1 to OGND ...........-0.3V to the lesser of (OVDD + 0.3V or + 3.9V)
Digital Outputs to OGND.............................-0.3V to the lesser of
(OVDD + 0.3V or + 3.9V)
Continuous Power Dissipation (TA = +70°C)
28-Pin Thin QFN (derated 20.8mW/°C above +70°C) ...1667mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = 3.0V, OVDD = 1.8V, VREFIN = VDD (internal reference), CL ≈ 10pF at digital outputs, fCLK = 10MHz, CREFP = CREFN = CCOM =
0.33µF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
±0.14
±1.00
LSB
±0.12
±1.00
LSB
DC ACCURACY
Resolution
8
Integral Nonlinearity
INL
Differential Nonlinearity
DNL
Offset Error
Gain Error
No missing codes over temperature
Bits
≥ +25°C
±4
< +25°C
±6
Excludes REFP - REFN error
±2
DC Gain Matching
±0.01
Gain Temperature Coefficient
±30
Power-Supply Rejection
±0.2
%FS
%FS
dB
ppm/°C
Offset (VDD ±5%)
±0.2
Gain (VDD ±5%)
±0.05
Differential or single-ended inputs
±0.512
V
VDD/2
V
540
kΩ
5
pF
LSB
ANALOG INPUT
Differential Input Voltage Range
VDIFF
Common-Mode Input Voltage
Range
VCOM
Input Resistance
RIN
Input Capacitance
CIN
Switched capacitor load
CONVERSION RATE
Maximum Clock Frequency
fCLK
Data Latency
10
MHz
Channel A
5.0
Channel B
5.5
Clock
cycles
DYNAMIC CHARACTERISTICS (Differential Inputs, 4096-Point FFT)
Signal-to-Noise Ratio
(Note 2)
Signal-to-Noise and Distortion
(Note 2)
2
SNR
SINAD
fIN = 1.875MHz
47
fIN = 3.0MHz
fIN = 1.875MHz
fIN = 3.0MHz
48.6
48.6
47
48.6
48.5
_______________________________________________________________________________________
dB
dB
Ultra-Low-Power, 10Msps, Dual 8-Bit ADC
(VDD = 3.0V, OVDD = 1.8V, VREFIN = VDD (internal reference), CL ≈ 10pF at digital outputs, fCLK = 10MHz, CREFP = CREFN = CCOM =
0.33µF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
Spurious-Free Dynamic Range
(Note 2)
SFDR
Third-Harmonic Distortion
(Note 2)
HD3
Intermodulation Distortion
CONDITIONS
fIN = 1.875MHz
MIN
TYP
59
70
fIN = 3.0MHz
MAX
UNITS
dBc
70
fIN = 1.875MHz
-71
fIN = 3.0MHz
-71
IMD
fIN1 = 1.8MHz at -7dBFS,
fIN2 = 3.0MHz at -7dBFS
-64
dBc
Third-Order Intermodulation
IM3
fIN1 = 1.8MHz at -7dBFS,
fIN2 = 3.0MHz at -7dBFS
-64
dBc
Total Harmonic Distortion
(Note 2)
THD
fIN = 1.875MHz
-69
fIN = 3.0MHz
dBc
-57.0
-67.0
dBc
Small-Signal Bandwidth
SSBW
Input at -20dBFS
440
MHz
Full-Power Bandwidth
FPBW
Input at -0.5dBFS
440
MHz
1.5
ns
2
psRMS
2
ns
Aperture Delay
tAD
Aperture Jitter
tAJ
1.5 × full-scale input
Overdrive Recovery Time
INTERNAL REFERENCE (REFIN = VDD; VREFP, VREFN, and VCOM are Generated Internally)
REFP Output Voltage
VREFP - VCOM
0.256
V
REFN Output Voltage
VREFN - VCOM
-0.256
V
COM Output Voltage
VCOM
Differential Reference Output
VREF
Differential Reference Output
Temperature Coefficient
Maximum REFP/REFN/COM
Source Current
Maximum REFP/REFN/COM Sink
Current
VDD/2
- 0.15
VREFP - VREFN
VDD/2
VDD/2
+ 0.15
V
0.512
V
VREFTC
±30
ppm/°C
ISOURCE
2
mA
ISINK
2
mA
BUFFERED EXTERNAL REFERENCE (VREFIN = 1.024V, VREFP, VREFN, and VCOM are Generated Internally)
REFIN Input Voltage
VREFIN
COM Output Voltage
VCOM
Differential Reference Output
VREF
Maximum REFP/REFN/COM
Source Current
Maximum REFP/REFN/COM Sink
Current
1.024
VDD/2
- 0.15
VREFP - VREFN
VDD/2
V
VDD/2
+ 0.15
V
0.512
V
ISOURCE
2
mA
ISINK
2
mA
_______________________________________________________________________________________
3
MAX19192
ELECTRICAL CHARACTERISTICS (continued)
MAX19192
Ultra-Low-Power, 10Msps, Dual 8-Bit ADC
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3.0V, OVDD = 1.8V, VREFIN = VDD (internal reference), CL ≈ 10pF at digital outputs, fCLK = 10MHz, CREFP = CREFN = CCOM =
0.33µF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
REFIN Input Resistance
REFIN Input Current
TYP
MAX
UNITS
> 500
kΩ
-0.7
µA
UNBUFFERED EXTERNAL REFERENCE (REFIN = GND, VREFP, VREFN, and VCOM are Applied Externally)
REFP Input Voltage
VREFP - VCOM
0.256
V
REFN Input Voltage
VREFN - VCOM
-0.256
V
VDD/2
V
0.512
V
COM Input Voltage
VCOM
Differential Reference Input
Voltage
VREF
VREFP - VREFN
REFP Input Resistance
RREFP
Measured between REFP and COM
4
kΩ
REFN Input Resistance
RREFN
Measured between REFN and COM
4
kΩ
DIGITAL INPUTS (CLK, PD0, PD1)
Input High Threshold
VIH
Input Low Threshold
VIL
Input Hysteresis
CLK
0.7 x VDD
PD0, PD1
0.7 x OVDD
CLK
0.3 x VDD
PD0, PD1
0.3 x OVDD
VHYST
Digital Input Leakage Current
DIIN
Digital Input Capacitance
DCIN
V
0.1
V
V
CLK at GND or VDD
±5
PD0 and PD1 at OGND or OVDD
±5
5
µA
pF
DIGITAL OUTPUTS (D7–D0, A/B)
Output-Voltage Low
VOL
ISINK = 200µA
Output-Voltage High
VOH
ISOURCE = 200µA
Three-State Leakage Current
ILEAK
Three-State Output Capacitance
COUT
0.2 x OVDD
0.8 x OVDD
V
V
±5
5
µA
pF
POWER REQUIREMENTS
Analog Supply Voltage
Digital Output Supply Voltage
Analog Supply Current
4
VDD
2.7
OVDD
1.8
IDD
3.0
Normal operating mode, fIN = 1.875MHz
at -0.5dBFS, CLK input from GND to VDD
5.1
Idle mode (three-state), fIN = 1.875MHz
at -0.5dBFS, CLK input from GND to VDD
5.1
Standby mode, CLK input from GND to
VDD, PD0 = OGND, PD1 = OVDD
2.9
Shutdown mode, CLK = GND or VDD,
PD0 = PD1 = OGND
0.6
_______________________________________________________________________________________
3.6
V
VDD
V
5.8
mA
5.0
µA
Ultra-Low-Power, 10Msps, Dual 8-Bit ADC
(VDD = 3.0V, OVDD = 1.8V, VREFIN = VDD (internal reference), CL ≈ 10pF at digital outputs, fCLK = 10MHz, CREFP = CREFN = CCOM =
0.33µF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
Digital Output Supply Current
(Note 3)
SYMBOL
IODD
CONDITIONS
MIN
TYP
MAX
Normal operating mode,
fIN = 1.875MHz at -0.5dBFS, CL ≈ 10pF
1.6
Idle mode (three-state), DC input, CLK =
GND or VDD, PD0 = OVDD, PD1 = OGND
0.1
Standby mode, DC input, CLK = GND or
VDD, PD0 = OGND, PD1 = OVDD
0.1
Shutdown mode, CLK = GND or VDD,
PD0 = PD1 = OGND
0.1
5.0
UNITS
mA
5.0
µA
TIMING CHARACTERISTICS
CLK Rise to CHA Output Data
Valid
tDOA
50% of CLK to 50% of data, Figure 5
(Note 4)
1
6
8.5
ns
CLK Fall to CHB Output Data
Valid
tDOB
50% of CLK to 50% of data, Figure 5
(Note 4)
1
6
8.5
ns
CLK Rise/Fall to A/B Rise/Fall
Time
tDA/B
50% of CLK to 50% of A/B, Figure 5
(Note 4)
1
6
8.5
ns
PD1 Rise to Output Enable
tEN
PD0 = OVDD
5
ns
PD1 Fall to Output Disable
tDIS
PD0 = OVDD
5
ns
CLK Duty Cycle
CLK Duty-Cycle Variation
50
%
±10
%
Wake-Up Time from Shutdown
Mode
tWAKE, SD (Note 5)
20
µs
Wake-Up Time from Standby
Mode
tWAKE, ST (Note 5)
5.5
µs
2
ns
-75
dB
Digital Output Rise/Fall Time
20% to 80%
INTERCHANNEL CHARACTERISTICS
Crosstalk Rejection
fIN,X = 1.875MHz at -0.5dBFS,
fIN,Y = 3.0MHz at -0.5dBFS
Amplitude Matching
fIN = 1.875MHz at -0.5dBFS (Note 6)
±0.03
dB
Phase Matching
fIN = 1.875MHz at -0.5dBFS (Note 6)
±0.03
Degrees
Note 1: Specifications ≥ +25°C guaranteed by production test, < +25°C guaranteed by design and characterization.
Note 2: SNR, SINAD, SFDR, HD3, and THD are based on a differential analog input voltage of -0.5dBFS referenced to the amplitude
of the digital output. SNR and THD are calculated using HD2 through HD6.
Note 3: The power consumption of the output driver is proportional to the load capacitance (CL).
Note 4: Guaranteed by design and characterization. Not production tested.
Note 5: SINAD settles to within 0.5dB of its typical value.
Note 6: Amplitude/phase matching is measured by applying the same signal to each channel, and comparing the magnitude and
phase of the fundamental bin on the calculated FFT.
_______________________________________________________________________________________
5
MAX19192
ELECTRICAL CHARACTERISTICS (continued)
Typical Operating Characteristics
HD3
fINB HD2
MAX19192 toc02
-50
-60
fINA
HD2
-30
-40
-50
-70
-80
-80
-80
-90
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
TWO-TONE IMD PLOT (DIFFERENTIAL
INPUTS, 8192-POINT DATA RECORD)
FFT PLOT CHANNEL A (SINGLE-ENDED
INPUTS, 8192-POINT DATA RECORD)
FFT PLOT (8192 SAMPLES)
-40
-50
HD3
-60
fINA
-70
HD2
-20
-80
-40
-20
-50
-60
-30
-40
-50
-60
-70
-70
-80
-80
0
-90
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
fINB
0
HD2
HD3
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
FREQUENCY (MHz)
FFT PLOT CHANNEL B (SINGLE-ENDED
INPUTS, 8192-POINT DATA RECORD)
FFT PLOT (8192 SAMPLES)
FFT PLOT CHANNEL A (SINGLE-ENDED
INPUTS, 8192-POINT DATA RECORD)
FFT PLOT (8192 SAMPLES)
FFT PLOT CHANNEL B (SINGLE-ENDED
INPUTS, 8192-POINT DATA RECORD)
FFT PLOT (8192 SAMPLES)
HD2
-30
-40
-50
-60
-70
-70
-80
-80
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
FREQUENCY (MHz)
MAX19192 toc08
-20
-90
HD3
fINB
0
HD2
fCLK = 10.000000MHz
fINA = 2.9870605MHz
fINB = 1.7956543MHz
AINA = AINB = -0.5dBFS
-10
-20
AMPLITUDE (dBFS)
fINA
fCLK = 10.000000MHz
fINA = 2.9870605MHz
fINB = 1.7956543MHz
AINA = AINB = -0.5dBFS
-10
AMPLITUDE (dBFS)
HD3
0
MAX19192 toc07
-50
0
fIN2
fCLK = 10.000000MHz
fINA = 1.7956543MHz
fINB = 2.9870605MHz
AINA = AINB = -0.5dBFS
ANALOG INPUT FREQUENCY (MHz)
-40
-90
fIN1
0
-10
FREQUENCY (MHz)
-30
-60
-30
-90
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
fCLK = 10.000000MHz
fINA = 1.7956543MHz
fINB = 2.9870605MHz
AINA = AINB = -0.5dBFS
-20
fCLK = 10.000000MHz
fIN1 = 1.7956543MHz
fIN2 = 3.001709MHz
AIN1 = AIN2 = -7dBFS
MAX19192 toc05
0
-10
AMPLITUDE (dBFS)
-30
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
FFT PLOT CHANNEL B (DIFFERENTIAL
INPUTS, 8192-POINT DATA RECORD)
FFT PLOT (8192 SAMPLES)
-20
-10
0
FREQUENCY (MHz)
fCLK = 10.000000MHz
fINA = 2.9870605MHz
fINB = 1.7956543MHz
AINA = AINB = -0.5dBFS
0
-90
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
HD2
FREQUENCY (MHz)
0
-90
0
fINB
FREQUENCY (MHz)
AMPLITUDE (dBFS)
0
HD3
-60
-70
-10
AMPLITUDE (dBFS)
-40
HD3
-20
-70
-90
6
-30
fCLK = 10.000000MHz
fINA = 2.9870605MHz
fINB = 1.7956543MHz
AINA = AINB = -0.5dBFS
MAX19192 toc06
-50
-60
-20
0
-10
MAX19192 toc09
-40
fCLK = 10.000000MHz
fINA = 1.7956543MHz
fINB = 2.9870605MHz
AINA = AINB = -0.5dBFS
AMPLITUDE (dBFS)
-30
MAX19192 toc04
AMPLITUDE (dBFS)
-20
0
-10
AMPLITUDE (dBFS)
fCLK = 10.000000MHz
fINA = 1.7956543MHz
fINB = 2.9870605MHz
AINA = AINB = -0.5dBFS
MAX19192 toc01
0
-10
MAX19192 toc03
(VDD = 3.0V, OVDD = 2.5V, VREFIN = VDD (internal reference), CL ≈ 10pF at digital outputs, differential input at -0.5dBFS, fCLK = 10MHz
at 50% duty cycle, TA = +25°C, unless otherwise noted.)
FFT PLOT CHANNEL A (DIFFERENTIAL
FFT PLOT CHANNEL A (DIFFERENTIAL
FFT PLOT CHANNEL B (DIFFERENTIAL
INPUTS, 8192-POINT DATA RECORD)
INPUTS, 8192-POINT DATA RECORD)
INPUTS, 8192-POINT DATA RECORD)
FFT PLOT (8192 SAMPLES)
FFT PLOT (8192 SAMPLES)
FFT PLOT (8192 SAMPLES)
AMPLITUDE (dBFS)
MAX19192
Ultra-Low-Power, 10Msps, Dual 8-Bit ADC
-30
-40
-50
-60
fINA
-70
HD2
HD3
-80
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
FREQUENCY (MHz)
-90
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
FREQUENCY (MHz)
_______________________________________________________________________________________
Ultra-Low-Power, 10Msps, Dual 8-Bit ADC
49
-55
MAX19192 toc11
50
MAX19192 toc10
50
TOTAL HARMONIC DISTORTION
vs. ANALOG INPUT FREQUENCY
SIGNAL-TO-NOISE AND DISTORTION
vs. ANALOG INPUT FREQUENCY
49
MAX19192 toc12
SIGNAL-TO-NOISE RATIO
vs. ANALOG INPUT FREQUENCY
-60
47
46
48
THD (dBc)
SINAD (dB)
SNR (dB)
48
47
-65
46
-70
45
20
40
60
80
100
80
100
0
20
40
60
80
100
SIGNAL-TO-NOISE AND DISTORTION
vs. ANALOG INPUT POWER
fIN = 2.9902649MHz
40
60
80
100
fIN = 2.9902649MHz
50
SINAD (dB)
50
40
30
10
120
40
30
20
20
CHANNEL A
CHANNEL B
20
60
-30
-25
-20
-15
-10
-5
10
0
-30
-25
-20
-15
-10
fIN (MHz)
ANALOG INPUT POWER (dBFS)
ANALOG INPUT POWER (dBFS)
TOTAL HARMONIC DISTORTION
vs. ANALOG INPUT POWER
SPURIOUS-FREE DYNAMIC RANGE
vs. ANALOG INPUT POWER
SIGNAL-TO-NOISE RATIO
vs. SAMPLING RATE
fIN = 2.9902649MHz
70
SFDR (dBc)
-40
-50
-60
60
-20
-15
-10
ANALOG INPUT POWER (dBFS)
-5
0
0
fIN = 2.9902649MHz
50
48
50
46
40
-25
52
SNR (dB)
fIN = 2.9902649MHz
-5
MAX19192 toc18
80
MAX19192 toc16
-30
120
MAX19192 toc15
60
MAX19192 toc13
65
-30
-75
120
SIGNAL-TO-NOISE RATIO
vs. ANALOG INPUT POWER
SNR (dB)
SFDR (dBc)
60
SPURIOUS-FREE DYNAMIC RANGE
vs. ANALOG INPUT FREQUENCY
60
THD (dBc)
40
fIN (MHz)
70
-70
20
fIN (MHz)
75
0
0
fIN (MHz)
80
55
44
120
CHANNEL A
CHANNEL B
MAX19192 toc14
0
CHANNEL A
CHANNEL B
MAX19192 toc17
44
45
CHANNEL A
CHANNEL B
30
44
-30
-25
-20
-15
-10
ANALOG INPUT POWER (dBFS)
-5
0
6
8
10
12
14
16
18
20
fCLK (MHz)
_______________________________________________________________________________________
7
MAX19192
Typical Operating Characteristics (continued)
(VDD = 3.0V, OVDD = 2.5V, VREFIN = VDD (internal reference), CL ≈ 10pF at digital outputs, differential input at -0.5dBFS, fCLK = 10MHz
at 50% duty cycle, TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics (continued)
(VDD = 3.0V, OVDD = 2.5V, VREFIN = VDD (internal reference), CL ≈ 10pF at digital outputs, differential input at -0.5dBFS, fCLK = 10MHz
at 50% duty cycle, TA = +25°C, unless otherwise noted.)
fIN = 2.9902649MHz
fIN = 2.9902649MHz
46
10
12
14
16
18
-75
20
6
8
10
12
14
16
18
60
20
10
12
14
16
18
fCLK (MHz)
SIGNAL-TO-NOISE RATIO
vs. DUTY CYCLE
SIGNAL-TO-NOISE AND DISTORTION
vs. DUTY CYCLE
TOTAL HARMONIC DISTORTION
vs. DUTY CYCLE
fIN = 2.9902649MHz
50
SINAD (dB)
-55
49
48
fIN = 2.9902649MHz
-60
50
55
46
60
-65
-70
-75
47
45
40
45
50
55
-80
60
40
45
50
60
55
DUTY CYCLE (%)
DUTY CYCLE (%)
DUTY CYCLE (%)
SPURIOUS-FREE DYNAMIC RANGE
vs. DUTY CYCLE
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
80
0.3
0.2
0.2
0.1
INL (LSB)
70
65
0
50
DUTY CYCLE (%)
55
60
0
-0.1
-0.1
-0.2
-0.2
-0.3
45
DNL (LSB)
0.1
75
MAX19192 toc27
fIN = 2.9902649MHz
MAX19192 toc26
0.3
MAX19192 toc25
85
20
MAX19192 toc24
MAX19192 toc22
51
47
40
8
fCLK (MHz)
48
60
6
fCLK (MHz)
49
40
70
65
THD (dBc)
8
50
SNR (dB)
-65
MAX19192 toc23
6
fIN = 2.9902649MHz
8
75
-70
51
46
fIN = 2.9902649MHz
SFDR (dBc)
48
44
80
-60
THD (dBc)
SINAD (dB)
50
SPURIOUS-FREE DYNAMIC RANGE
vs. SAMPLING RATE
MAX19192 toc20
-55
MAX19192 toc19
52
TOTAL HARMONIC DISTORTION
vs. SAMPLING RATE
MAX19192 toc21
SIGNAL-TO-NOISE AND DISTORTION
vs. SAMPLING RATE
SFDR (dBc)
MAX19192
Ultra-Low-Power, 10Msps, Dual 8-Bit ADC
0
32
64
96
128 160 192
DIGITAL OUTPUT CODE
224 256
-0.3
0
32
64
96
128 160 192
DIGITAL OUTPUT CODE
_______________________________________________________________________________________
224 256
Ultra-Low-Power, 10Msps, Dual 8-Bit ADC
GAIN ERROR
vs. TEMPERATURE
0.2
0.30
0.20
0.10
2
0.1
0
0
FULL-POWER
BANDWIDTH
-0.5dBFS
-2
-4
-0.1
-6
-0.2
CHANNEL A
CHANNEL B
0
-15
10
35
60
-0.3
85
CHANNEL A
CHANNEL B
-8
-10
-40
-15
10
TEMPERATURE (°C)
35
85
60
100
10
1000
ANALOG INPUT FREQUENCY (MHz)
REFERENCE VOLTAGE
vs. TEMPERATURE
REFERENCE VOLTAGE
vs. ANALOG SUPPLY VOLTAGE
0.5140
VREFP - VREFN (V)
0.5120
MAX19192 toc32
0.5160
MAX19192 toc31
0.5130
0.5110
0.5100
0.5090
0.5120
0.5100
0.5080
0.5060
0.5040
2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
-40
-15
ANALOG SUPPLY VOLTAGE (V)
10
35
60
85
TEMPERATURE (°C)
SUPPLY CURRENT vs. SAMPLING RATE
10
MAX19192 toc33
0.5080
1
TEMPERATURE (°C)
fIN = 2.9902649MHz
8
SUPPLY CURRENT (mA)
-40
VREFP - VREFN (V)
-0.10
SMALL-SIGNAL
BANDWIDTH
-20dBFS
4
GAIN (dB)
GAIN ERROR (%FS)
0.40
6
MAX19192 toc29
0.50
OFFSET ERROR (%FS)
0.3
MAX19192 toc28
0.60
INPUT BANDWIDTH
vs. ANALOG INPUT FREQUENCY
MAX19192 toc30
OFFSET ERROR
vs. TEMPERATURE
6
A
B
4
C
2
0
0
5
10
15
20
fCLK (MHz)
A: ANALOG SUPPLY CURRENT (IVDD) - INTERNAL AND BUFFERED EXTERNAL REFERENCE MODES
B: ANALOG SUPPLY CURRENT (IVDD) - UNBUFFERED EXTERNAL REFERENCE MODE
C: DIGITAL SUPPLY CURRENT (IOVDD) - OVDD = 2.5V, ALL REFERENCE MODES
_______________________________________________________________________________________
9
MAX19192
Typical Operating Characteristics (continued)
(VDD = 3.0V, OVDD = 2.5V, VREFIN = VDD (internal reference), CL ≈ 10pF at digital outputs, differential input at -0.5dBFS, fCLK = 10MHz
at 50% duty cycle, TA = +25°C, unless otherwise noted.)
Ultra-Low-Power, 10Msps, Dual 8-Bit ADC
MAX19192
Pin Description
10
PIN
NAME
1
INA-
Channel A Negative Analog Input. For single-ended operation, connect INA- to COM.
FUNCTION
2
INA+
Channel A Positive Analog Input. For single-ended operation, connect signal source to INA+.
3, 5, 10
GND
Analog Ground. Connect all GND pins together.
4
CLK
Converter Clock Input
6
INB+
Channel B Positive Analog Input. For single-ended operation, connect signal source to INB+.
7
INB-
Channel B Negative Analog Input. For single-ended operation, connect INB- to COM.
8, 9, 28
VDD
Converter Power Input. Connect to a 2.7V to 3.6V power supply. Bypass VDD to GND with a
combination of a 2.2μF capacitor in parallel with a 0.1μF capacitor.
11
OGND
Output Driver Ground
12
OVDD
Output Driver Power Input. Connect to a 1.8V to VDD power supply. Bypass OVDD to GND with a
combination of a 2.2μF capacitor in parallel with a 0.1μF capacitor.
13
D7
Three-State Digital Output. D7 is the most significant bit (MSB).
14
D6
Three-State Digital Output
15
D5
Three-State Digital Output
16
D4
Three-State Digital Output
17
A/B
Channel Data Indicator. This digital output indicates channel A data (A/B = 1) or channel B data
(A/B = 0) is present on the output.
18
D3
Three-State Digital Output
19
D2
Three-State Digital Output
20
D1
Three-State Digital Output
21
D0
22
PD1
Three-State Digital Output. D0 is the least significant bit (LSB).
Power-Down Digital Input 1. See Table 3.
23
PD0
24
REFIN
Reference Input. Internally pulled up to VDD.
Power-Down Digital Input 0. See Table 3.
25
COM
Common-Mode Voltage I/O. Bypass COM to GND with a 0.33μF capacitor.
26
REFN
Negative Reference I/O. Conversion range is ±(VREFP - VREFN). Bypass REFN to GND with a
0.33μF capacitor.
27
REFP
Positive Reference I/O. Conversion range is ±(VREFP - VREFN). Bypass REFP to GND with a 0.33μF
capacitor.
—
EP
Exposed Pad. Internally connected to pin 3. Externally connect EP to GND.
______________________________________________________________________________________
Ultra-Low-Power, 10Msps, Dual 8-Bit ADC
The MAX19192 uses a seven-stage, fully differential,
pipelined architecture (Figure 1) that allows for highspeed conversion while minimizing power consumption. Samples taken at the inputs move progressively
through the pipeline stages every half-clock cycle.
Including the delay through the output latch, the total
clock-cycle latency is 5 clock cycles for channel A and
5.5 clock cycles for channel B.
At each stage, flash ADCs convert the held input voltages into a digital code. The following digital-to-analog
converter (DAC) converts the digitized result back into
an analog voltage, which is then subtracted from the
original held input signal. The resulting error signal is
then multiplied by two, and the product is passed along
to the next pipeline stage where the process is repeated until the signal has been processed by all stages.
Digital error correction compensates for ADC comparator offsets in each pipeline stage and ensures no missing codes. Figure 2 shows the MAX19192 functional
diagram.
x2
DAC
1.5 BITS
INA+
STAGE 1
T/H
STAGE 2
STAGE 7
INA-
DIGITAL ERROR CORRECTION
D0–D7
Figure 1. Pipeline Architecture—Stage Blocks
INA+
T/H
INA-
REFIN
REFP
PIPELINE
ADC
A
/
DEC
REFERENCE
SYSTEM AND
BIAS
CIRCUITS
COM
REFN
VDD
GND
MAX19192
POWER
CONTROL
PD0
PD1
OVDD
D0–D7
MULTIPLEXER
OUTPUT
DRIVERS
A/B
OGND
INB+
T/H
INB-
PIPELINE
ADC
B
/
DEC
/
FLASH
ADC
/
T/H
/
+
TIMING
CLK
Figure 2. MAX19192 Functional Diagram
______________________________________________________________________________________
11
MAX19192
Detailed Description
MAX19192
Ultra-Low-Power, 10Msps, Dual 8-Bit ADC
INTERNAL
BIAS
COM
S5a
S2a
C1a
S3a
S4a
INA+
OUT
C2a
S4c
S1
OUT
INAS4b
C2b
C1b
S3b
S5b
S2b
INTERNAL
BIAS
COM
HOLD
INTERNAL
BIAS
TRACK
COM
CLK
HOLD
TRACK
INTERNAL
NONOVERLAPPING
CLOCK SIGNALS
S5a
S2a
C1a
S3a
S4a
INB+
OUT
C2a
S4c
S1
MAX19192
OUT
INBS4b
C2b
C1b
S3b
S5b
S2b
INTERNAL
BIAS
COM
Figure 3. Internal T/H Circuits
Input Track-and-Hold (T/H) Circuits
Figure 3 displays a simplified functional diagram of the
input T/H circuits. In track mode, switches S1, S2a,
S2b, S4a, S4b, S5a, and S5b are closed. The fully differential circuits sample the input signals onto the two
capacitors (C2a and C2b) through switches S4a and
S4b. S2a and S2b set the common mode for the ampli12
fier input, and open simultaneously with S1, sampling
the input waveform. Switches S4a, S4b, S5a, and S5b
are then opened before switches S3a and S3b connect
capacitors C1a and C1b to the output of the amplifier
and switch S4c is closed. The resulting differential voltages are held on capacitors C2a and C2b. The amplifiers charge capacitors C1a and C1b to the same
______________________________________________________________________________________
Ultra-Low-Power, 10Msps, Dual 8-Bit ADC
VREFIN
REFERENCE MODE
> 0.8 x VDD
Internal reference mode. VREF is internally generated to be 0.512V. Bypass REFP, REFN, and
COM each with a 0.33μF capacitor.
1.024V ±10%
Buffered external reference mode. An external 1.024V ±10% reference voltage is applied to
REFIN. VREF is internally generated to be VREFIN/2. Bypass REFP, REFN, and COM each with a
0.33μF capacitor. Bypass REFIN to GND with a 0.1μF capacitor.
< 0.3V
Unbuffered external reference mode. REFP, REFN, and COM are driven by external reference
sources. VREF is the difference between the externally applied VREFP and VREFN. Bypass REFP,
REFN, and COM each with a 0.33μF capacitor.
values originally held on C2a and C2b. These values
are then presented to the first stage quantizers and isolate the pipelines from the fast-changing inputs. The
wide input bandwidth T/H amplifiers allow the
MAX19192 to track and sample/hold analog inputs of
high frequencies (> Nyquist). Both ADC inputs (INA+,
INB+, INA-, and INB-) can be driven either differentially
or single ended. Match the impedance of INA+ and
INA-, as well as INB+ and INB-, and set the commonmode voltage to midsupply (VDD/2) for optimum performance.
Analog Inputs and Reference
Configurations
The MAX19192 full-scale analog input range is ±VREF
with a common-mode input range of VDD/2 ±0.2V. VREF
is the difference between V REFP and V REFN . The
MAX19192 provides three modes of reference operation. The voltage at REFIN (VREFIN) sets the reference
operation mode (Table 1).
In internal reference mode, connect REFIN to VDD or
leave REFIN unconnected. VREF is internally generated
to be 0.512V ±3%. COM, REFP, and REFN are lowimpedance outputs with VCOM = VDD/2, VREFP = VDD/2
+ VREF/2, and VREFN = VDD/2 - VREF/2. Bypass REFP,
REFN, and COM each with a 0.33µF capacitor.
In buffered external reference mode, apply a 1.024V
±10% at REFIN. In this mode, COM, REFP, and REFN
are low-impedance outputs with VCOM = VDD/2, VREFP =
V DD /2 + V REFIN /4, and V REFN = V DD /2 - V REFIN /4.
Bypass REFP, REFN, and COM each with a 0.33µF
capacitor. Bypass REFIN to GND with a 0.1µF capacitor.
In unbuffered external reference mode, connect REFIN
to GND. This deactivates the on-chip reference buffers
for COM, REFP, and REFN. With their buffers shut
down, these nodes become high-impedance inputs
(Figure 4) and can be driven through separate, external
62.5μA
MAX19192
REFP
1.75V
4kΩ
0μA
COM
1.5V
4kΩ
62.5μA
REFN
1.25V
Figure 4. Unbuffered External Reference Mode Impedance
reference sources. Drive VCOM to VDD/2 ±10%, drive
VREFP to (VDD/2 +0.256V) ±10%, and drive VREFN to
(VDD/2 - 0.256V) ±10%. Bypass REFP, REFN, and COM
each with a 0.33µF capacitor.
For detailed circuit suggestions and how to drive this
dual ADC in buffered/unbuffered external reference
mode, see the Applications Information section.
Clock Input (CLK)
CLK accepts a CMOS-compatible signal level. Since
the interstage conversion of the device depends on the
repeatability of the rising and falling edges of the external clock, use a clock with low jitter and fast rise and
fall times (< 2ns). In particular, sampling occurs on the
______________________________________________________________________________________
13
MAX19192
Table 1. Reference Modes
MAX19192
Ultra-Low-Power, 10Msps, Dual 8-Bit ADC
5 CLOCK-CYCLE LATENCY (CHA), 5.5 CLOCK-CYCLE LATENCY (CHB)
CHA
CHB
tCLK
tCL
tCH
CLK
tDOB
A/B
tDOA
CHB
CHA
CHB
CHA
CHB
CHA
CHB
CHA
CHB
CHA
CHB
CHA
CHB
D0B
D1A
D1B
D2A
D2B
D3A
D3B
D4A
D4B
D5A
D5B
D6A
D6B
tDA/B
D0–D7
Figure 5. System Timing Diagram
rising edge of the clock signal, requiring this edge to
provide lowest possible jitter. Any significant aperture
jitter would limit the SNR performance of the on-chip
ADCs as follows:
2 x VREF
256
VREF
14
VREF
VREF
1111 1111
1111 1110
1111 1101
1000 0001
1000 0000
0111 1111
(COM)
0000 0011
0000 0010
0000 0001
0000 0000
-128 -127 -126 -125
-1
0
+1
+125 +126 +127 +128
(COM)
System Timing Requirements
Figure 5 shows the relationship between the clock, analog inputs, A/B indicator, and the resulting output data.
Channel A (CHA) and channel B (CHB) are simultaneously sampled on the rising edge of the clock signal
(CLK) and the resulting data is multiplexed at the output. CHA data is updated on the rising edge and CHB
data is updated on the falling edge of the CLK. The A/B
indicator follows CLK with a typical delay time of 6ns
and remains high when CHA data is updated and low
when CHB data is updated. Including the delay
through the output latch, the total clock-cycle latency is
5 clock cycles for CHA and 5.5 clock cycles for CHB.
VREF = VREFP - VREFN
VREF
where fIN represents the analog input frequency and
tAJ is the time of the aperture jitter.
Clock jitter is especially critical for undersampling
applications. The clock input should always be considered as an analog input and routed away from any analog input or other digital signal lines. The MAX19192
clock input operates with a VDD/2 voltage threshold
and accepts a 50% ±10% duty cycle (see the Typical
Operating Characteristics).
OFFSET BINARY OUTPUT CODE (LSB)
⎛
⎞
1
SNR = 20 × log ⎜
⎟
2
×
π
×
f
×
t
⎝
IN
AJ ⎠
1LSB =
INPUT VOLTAGE (LSB)
Figure 6. Transfer Function
Digital Output Data (D0–D7),
Channel Data Indicator (A/B)
D0–D7 and A/B are TTL/CMOS-logic compatible. The
digital output coding is offset binary (Table 2, Figure 6).
The capacitive load on the digital outputs D0–D7
should be kept as low as possible (< 15pF) to avoid
large digital currents feeding back into the analog portion of the MAX19192 and degrading its dynamic performance. Buffers on the digital outputs isolate them
______________________________________________________________________________________
Ultra-Low-Power, 10Msps, Dual 8-Bit ADC
MAX19192
Table 2. Output Codes vs. Input Voltage
DIFFERENTIAL INPUT VOLTAGE
(IN+ - IN-)
DIFFERENTIAL INPUT
(LSB)
OFFSET BINARY
(D7–D0)
OUTPUT DECIMAL CODE
VREF ×
127
128
+127
(+ full scale - 1 LSB)
1111 1111
255
VREF ×
126
128
+126
(+ full scale - 2 LSB)
1111 1110
254
VREF ×
1
128
+1
1000 0001
129
VREF ×
0
128
0 (bipolar zero)
1000 0000
128
- VREF ×
1
128
-1
0111 1111
127
- VREF ×
127
128
-127
(- full scale + 1 LSB)
0000 0001
1
- VREF ×
128
128
-128 (- full scale)
0000 0000
0
Table 3. Power Logic
PD0
PD1
POWER MODE
0
0
Shutdown
0
1
Standby
1
0
Idle
1
1
Normal operating
INTERNAL
REFERENCE
CLOCK DISTRIBUTION
OUTPUTS
Off
Off
Off
Three-state
Off
On
On
Three-state
On
On
On
Three-state
On
On
On
On
ADC
from heavy capacitive loads. To improve the dynamic
performance of the MAX19192, add 100Ω resistors in
series with the digital outputs close to the MAX19192.
Refer to the MAX19192 evaluation kit schematic for an
example of the digital outputs driving a digital buffer
through 100Ω series resistors.
Power Modes (PD0, PD1)
The MAX19192 has four power modes that are controlled with PD0 and PD1. Four power modes allow the
MAX19192 to efficiently use power by transitioning to a
low-power state when conversions are not required
(Table 3).
Shutdown mode offers the most dramatic power savings by shutting down all the analog sections of the
MAX19192 and placing the outputs in three-state. The
wake-up time from shutdown mode is dominated by the
time required to charge the capacitors at REFP, REFN,
and COM. In internal reference mode and buffered
external reference mode, the wake-up time is typically
20µs. When operating in the unbuffered external reference mode, the wake-up time is dependent on the
external reference drivers. When the outputs transition
from three-state to on, the last converted word is
placed on the digital outputs.
In standby mode, the reference and clock distribution
circuits are powered up, but the pipeline ADCs are
unpowered and the outputs are in three-state. The
wake-up time from standby mode is dominated by the
5.5µs required to activate the pipeline ADCs. When the
outputs transition from three-state to on, the last converted word is placed on the digital outputs.
______________________________________________________________________________________
15
MAX19192
Ultra-Low-Power, 10Msps, Dual 8-Bit ADC
R4
600Ω
R5
600Ω
MAX19192
RISO
22Ω
R1
600Ω
VCOM = 0.5V TO 1.5V
VSIG = ±85mVP-P
R2
300Ω
R3
600Ω
INACIN
5pF
R6
600Ω
R7
600Ω
COM
AV = 6V/V
VCOM = VDD/2
R8
600Ω
R9
600Ω
RISO
22Ω
CIN
5pF
R10
600Ω
OPERATIONAL AMPLIFIERS
CHOOSE EITHER OF THE MAX4452/MAX4453/MAX4454 SINGLE/
DUAL/QUAD 3V, 200MHz OP AMPS FOR USE WITH THIS CIRCUIT.
CONNECT THE POSITIVE SUPPLY RAIL (VCC) TO 3V. CONNECT THE
NEGATIVE SUPPLY RAIL (VEE) TO GROUND. DECOUPLE VCC WITH A
0.1μF CAPACITOR TO GROUND.
INA+
R11
600Ω
RESISTOR NETWORKS
RESISTOR NETWORKS ENSURE PROPER THERMAL AND TOLERANCE
MATCHING. FOR R1, R2, AND R3 USE A NETWORK SUCH AS VISHAY'S
3R MODEL NUMBER 300192. FOR R4–R11, USE A NETWORK SUCH AS
VISHAY'S 4R MODEL NUMBER 300197.
Figure 7. DC-Coupled Differential Input Driver
In idle mode, the pipeline ADCs, reference, and clock
distribution circuits are powered, but the outputs are
forced to three-state. The wake-up time from idle mode
is dominated by the 5ns required for the output drivers
to start from three-state. When the outputs transition
from three-state to on, the last converted word is
placed on the digital outputs.
In the normal operating mode, all sections of the
MAX19192 are powered.
16
Applications Information
The circuit of Figure 7 operates from a single 3V supply
and accommodates a wide 0.5V to 1.5V input commonmode voltage range for the analog interface between
an RF quadrature demodulator (differential, DC-coupled signal source) and a high-speed ADC.
Furthermore, the circuit provides required SINAD and
SFDR to demodulate a wideband (BW = 3.84MHz),
QAM-16 communication link. RISO isolates the op amp
output from the ADC capacitive input to prevent ringing
and oscillation. CIN filters high-frequency noise.
______________________________________________________________________________________
Ultra-Low-Power, 10Msps, Dual 8-Bit ADC
MAX19192
REFP
25Ω
INA+
22pF
1kΩ
VIN
0.1μF
1
VIN
T1
RISO
50Ω
6
INA+
MAX4108
2
5
3
4
N.C.
0.1μF
100Ω
1kΩ
COM
2.2μF
CIN
22pF
0.1μF
COM
REFN
MINICIRCUITS
TT1-6-KK81
0.1μF
RISO
50Ω
25Ω
INA-
INA-
100Ω
CIN
22pF
22pF
MAX19192
REFP
25Ω
MAX19192
INB+
22pF
VIN
0.1μF
1
VIN
N.C.
T1
0.1μF
1kΩ
RISO
50Ω
6
INB+
MAX4108
2
5
3
4
100Ω
2.2μF
1kΩ
CIN
22pF
0.1μF
REFN
MINICIRCUITS
TT1-6-KK81
0.1μF
RISO
50Ω
25Ω
INB22pF
Figure 8. Transformer-Coupled Input Drive
Using Transformer Coupling
An RF transformer (Figure 8) provides an excellent
solution to convert a single-ended source signal to a
fully differential signal, required by the MAX19192 for
optimum performance. Connecting the center tap of the
transformer to COM provides a VDD/2 DC level shift to
the input. Although a 1:1 transformer is shown, a stepup transformer can be selected to reduce the drive
requirements. A reduced signal swing from the input
driver, such as an op amp, can also improve the overall
distortion.
In general, the MAX19192 provides better SFDR and
THD with fully differential input signals than singleended drive, especially for high input frequencies. In
differential input mode, even-order harmonics are lower
as both inputs (INA+, INA- and/or INB+, INB-) are bal-
100Ω
INBCIN
22pF
Figure 9. Using an Op Amp for Single-Ended, AC-Coupled
Input Drive
anced, and each of the ADC inputs only requires half
the signal swing compared to single-ended mode.
Single-Ended AC-Coupled Input Signal
Figure 9 shows an AC-coupled, single-ended application. Amplifiers such as the MAX4108 provide high
speed, high bandwidth, low noise, and low distortion to
maintain the input signal integrity.
Buffered External Reference Drives
Multiple ADCs
The buffered external reference mode allows for more
control over the MAX19192 reference voltage and
allows multiple converters to use a common reference.
To drive one MAX19192 in buffered external reference
mode, the external circuit must sink 0.7µA, allowing one
reference circuit to easily drive the REFIN of multiple
converters to 1.024V ±10%.
______________________________________________________________________________________
17
MAX19192
Ultra-Low-Power, 10Msps, Dual 8-Bit ADC
3V
24
0.1μF
1.248V
VDD
REFIN
0.1μF
1
2
27
MAX6061
3
10Hz
LOWPASS
FILTER
N=1
REFP
0.33μF
1%
20kΩ
MAX19192
26
REFN
0.33μF
1μF
1%
90.9kΩ
25
3V
5
3
NOTE: ONE FRONT-END REFERENCE
CIRCUIT PROVIDES ±15mA OF OUTPUT
DRIVE AND SUPPORTS OVER 1000 MAX19192s.
MAX4250
4
COM
GND
0.33μF
0.1μF
1
15Ω
2
1.023V
24
VDD
REFIN
0.1μF
2.2μF
0.1μF
27
REFP N = 1000
0.33μF
MAX19192
26
REFN
0.33μF
25
COM
0.33μF
GND
Figure 10. External Buffered (MAX4250) Reference Drive Using a MAX6061 Bandgap Reference
Figure 10 shows the MAX6061 precision bandgap reference used as a common reference for multiple converters. The 1.248V output of the MAX6061 is divided
down to 1.023V as it passes through a one-pole, 10Hz,
lowpass filter to the MAX4250. The MAX4250 buffers
the 1.023V reference before its output is applied to the
MAX19192. The MAX4250 provides a low offset voltage
(for high gain accuracy) and a low noise level.
18
Unbuffered External Reference Drives
Multiple ADCs
The unbuffered external reference mode allows for precise control over the MAX19192 reference and allows
multiple converters to use a common reference.
Connecting REFIN to GND disables the internal reference, allowing REFP, REFN, and COM to be driven
directly by a set of external reference sources.
______________________________________________________________________________________
Ultra-Low-Power, 10Msps, Dual 8-Bit ADC
MAX19192
3V
2.500V
1
0.1μF
2
27
MAX6066
1%
30.1kΩ
3
3
10μF
6V
0.1μF
12
1MΩ
13
14
MAX4254
10μF
6V
24
COM
GND
0.33μF
0.1μF
27
330μF
6V
1.47kΩ
VDD
REFP
N = 160
0.33μF
47Ω
8
MAX4254
10μF
6V
2.2μF
1.47kΩ
1.248V
1/4
11
25
330μF
6V
10
9
REFIN
47Ω
7
1%
10.0kΩ
4
1/4
1.47kΩ
MAX4254
3V
UNCOMMITTED
MAX19192
1.498V
1/4
1MΩ
REFN
0.33μF
330μF
6V
1%
10.0kΩ
5
6
26
47Ω
1
MAX4254
1μF
NOTE: ONE FRONT-END
REFERENCE CIRCUIT
SUPPORTS UP TO 160 MAX19192s.
N=1
0.33μF
1.748V
1/4
2
VDD
REFP
26
REFN
MAX19192
REFIN
24
0.33μF
1%
49.9kΩ
25
0.33μF
COM
GND
Figure 11. External Unbuffered Reference Driving 160 ADCs with the MAX4254 and MAX6066
Figure 11 shows the MAX6066 precision bandgap reference used as a common reference for multiple converters. The 2.500V output of the MAX6066 is followed
by a 10Hz lowpass filter and precision voltage-divider.
The MAX4254 buffers the taps of this divider to provide
the 1.75V, 1.5V, and 1.25V sources to drive REFP,
REFN, and COM. The MAX4254 provides a low offset
voltage and low noise level. The individual voltage followers are connected to 10Hz lowpass filters, which filter both the reference-voltage and amplifier noise to a
level of 3nV/√Hz. The 1.75V and 1.25V reference volt-
ages set the differential full-scale range of the associated ADCs at ±0.5V.
The common power supply for all active components
removes any concern regarding power-supply
sequencing when powering up or down.
With the outputs of the MAX4252 matching better than
0.1%, the buffers and subsequent lowpass filters support as many as 160 MAX19192s.
______________________________________________________________________________________
19
MAX19192
Ultra-Low-Power, 10Msps, Dual 8-Bit ADC
A/B
MAX2451
INA+
INA0°
90°
MAX19192
DSP
POSTPROCESSING
INB+
INBDOWNCONVERTER
÷8
Figure 12. Typical QAM Receiver Application
Typical QAM Demodulation Application
Quadrature amplitude modulation (QAM) is frequently
used in digital communications. Typically found in
spread-spectrum-based systems, a QAM signal represents a carrier frequency modulated in both amplitude
and phase. At the transmitter, modulating the baseband
signal with quadrature outputs, a local oscillator followed by subsequent upconversion can generate the
QAM signal. The result is an in-phase (I) and a quadrature (Q) carrier component, where the Q component is
90° phase shifted with respect to the in-phase component. At the receiver, the QAM signal is demodulated
into analog I and Q components. Figure 12 displays the
demodulation process performed in the analog domain
using the MAX19192 dual-matched, 3V, 8-bit ADC and
the MAX2451 quadrature demodulator to recover and
digitize the I and Q baseband signals. Before being digitized by the MAX19192, the mixed-down signal components can be filtered by matched analog filters, such as
Nyquist or pulse-shaping filters. The filters remove
unwanted images from the mixing process, thereby
enhancing the overall signal-to-noise (SNR) performance and minimizing intersymbol interference.
Grounding, Bypassing,
and Board Layout
The MAX19192 requires high-speed board layout
design techniques. Refer to the MAX19192 evaluation
kit data sheet for a board layout reference. Locate all
bypass capacitors as close as possible to the device,
20
preferably on the same side as the ADC, using surfacemount devices for minimum inductance. Bypass VDD to
GND with a 0.1µF ceramic capacitor in parallel with a
2.2µF bipolar capacitor. Bypass OVDD to OGND with a
0.1µF ceramic capacitor in parallel with a 2.2µF bipolar
capacitor. Bypass REFP, REFN, and COM each to
GND with a 0.33µF ceramic capacitor.
Multilayer boards with separated ground and power
planes produce the highest level of signal integrity. Use
a split ground plane arranged to match the physical
location of the analog ground (GND) and the digital
output driver ground (OGND) on the ADC’s package.
Connect the MAX19192 exposed backside pad to
GND. Join the two ground planes at a single point so
that the noisy digital ground currents do not interfere
with the analog ground plane. The ideal location of this
connection can be determined experimentally at a
point along the gap between the two ground planes,
which produces optimum results. Make this connection
with a low-value, surface-mount resistor (1Ω to 5Ω), a
ferrite bead, or a direct short. Alternatively, all ground
pins could share the same ground plane, if the ground
plane is sufficiently isolated from any noisy, digital systems ground plane (e.g., downstream output buffer or
DSP ground plane).
Route high-speed digital signal traces away from the
sensitive analog traces of either channel. Make sure to
isolate the analog input lines to each respective converter to minimize channel-to-channel crosstalk. Keep
all signal lines short and free of 90° turns.
______________________________________________________________________________________
Ultra-Low-Power, 10Msps, Dual 8-Bit ADC
CLK
ANALOG
INPUT
tAD
tAJ
SAMPLED
DATA (T/H)
T/H
TRACK
HOLD
TRACK
Figure 13. T/H Aperture Timing
Signal-to-Noise Plus Distortion (SINAD)
Static Parameter Definitions
Integral Nonlinearity (INL)
Integral nonlinearity is the deviation of the values on an
actual transfer function from a straight line. This straight
line can be either a best-straight-line fit or a line drawn
between the end points of the transfer function, once
offset and gain errors have been nullified. The static linearity parameters for the MAX19192 are measured
using the end-point method.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between an
actual step width and the ideal value of 1LSB. A DNL
error specification of less than 1LSB guarantees no
missing codes and a monotonic transfer function.
Offset Error
Ideally, the midscale MAX19192 transition occurs at 0.5
LSB above midscale. The offset error is the amount of
deviation between the measured transition point and
the ideal transition point.
Gain Error
Ideally, the full-scale MAX19192 transition occurs at 1.5
LSB below full-scale. The gain error is the amount of
deviation between the measured transition point and
the ideal transition point with the offset error removed.
Dynamic Parameter Definitions
Aperture Jitter
Figure 13 depicts the aperture jitter (tAJ), which is the
sample-to-sample variation in the aperture delay.
Aperture Delay
Aperture delay (tAD) is the time defined between the
rising edge of the sampling clock and the instant when
an actual sample is taken (Figure 13).
SINAD is computed by taking the ratio of the RMS signal to the RMS noise. RMS noise includes all spectral
components to the Nyquist frequency excluding the
the fundamental and the DC offset.
Effective Number of Bits (ENOB)
ENOB specifies the dynamic performance of an ADC at
a specific input frequency and sampling rate. An ideal
ADC’s error consists of quantization noise only. ENOB
for a full-scale sinusoidal input waveform is computed
from:
ENOB =
SINAD - 1.76
6.02
Total Harmonic Distortion (THD)
THD is typically the ratio of the RMS sum of the first five
harmonics of the input signal to the fundamental itself.
This is expressed as:
⎡
2
2
2
2
2
⎢ V2 + V3 + V4 + V5 + V6
THD = 20 × log ⎢
V1
⎢⎣
⎤
⎥
⎥
⎥⎦
where V1 is the fundamental amplitude, and V2–V6 are
the amplitudes of the 2nd- through 6th-order harmonics.
Third Harmonic Distortion (HD3)
HD3 is defined as the ratio of the RMS value of the third
harmonic component to the fundamental input signal.
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio expressed in decibels of the RMS
amplitude of the fundamental (maximum signal component) to the RMS value of the next-largest spurious
component, excluding DC offset.
______________________________________________________________________________________
21
MAX19192
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital
samples, the theoretical maximum SNR is the ratio of
the full-scale analog input (RMS value) to the RMS
quantization error (residual error). The ideal, theoretical
minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC’s resolution (N bits):
SNRdB[max] = 6.02 × N + 1.76
In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter,
etc. SNR is computed by taking the ratio of the RMS
signal to the RMS noise. RMS noise includes all spectral components to the Nyquist frequency excluding the
fundamental, the first five harmonics, and the DC offset.
MAX19192
Ultra-Low-Power, 10Msps, Dual 8-Bit ADC
Intermodulation Distortion (IMD)
Small-Signal Bandwidth
IMD is the total power of the intermodulation products
relative to the total input power when two tones, f1 and
f2, are present at the inputs. The intermodulation products are (f1 ± f2), (2 x f1), (2 x f2), (2 x f1 ± f2), (2 x f2 ±
f1). The individual input tone levels are at -7dBFS.
A small -20dBFS analog input signal is applied to an
ADC in such a way that the signal’s slew rate does not
limit the ADC’s performance. The input frequency is
then swept up to the point where the amplitude of the
digitized conversion result has decreased by -3dB.
Note that the track/hold (T/H) performance is usually
the limiting factor for the small-signal input bandwidth.
Third-Order Intermodulation (IM3)
IM3 is the power of the worst third-order intermodulation product relative to the input power of either input
tone when two tones, f1 and f2, are present at the
inputs. The third-order intermodulation products are (2
x f1 ± f2), (2 x f2 ± f1). The individual input tone levels
are at -7dBFS.
Power-Supply Rejection
Power-supply rejection is defined as the shift in offset
and gain error when the power supplies are moved
±5%.
Full-Power Bandwidth
A large -0.5dBFS analog input signal is applied to an
ADC, and the input frequency is swept up to the point
where the amplitude of the digitized conversion result
has decreased by -3dB. This point is defined as fullpower input bandwidth frequency.
Chip Information
PROCESS: CMOS
Package Information
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in
the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
PACKAGE TYPE
PACKAGE CODE
DOCUMENT NO.
28 TQFN-EP
T2855+8
21-0140
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
22 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2010 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
工商网监
湘ICP备2023018690号
