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Digitally Controlled, 0.5% Accurate,
Safest APD Bias Supply
MAX1932
General Description
Benefits and Features
The MAX1932 generates a low-noise, high-voltage output
to bias avalanche photodiodes (APDs) in optical
receivers. Very low output ripple and noise is achieved by
a constant-frequency, pulse-width modulated (PWM)
boost topology combined with a unique architecture that
maintains regulation with an optional RC or LC post filter
inside its feedback loop. A precision reference and error
amplifier maintain 0.5% output voltage accuracy.
The MAX1932 protects expensive APDs against adverse
operating conditions while providing optimal bias.
Traditional boost converters measure switch current for
protection, whereas the MAX1932 integrates accurate
high-side current limiting to protect APDs under
avalanche conditions. A current-limit flag allows easy calibration of the APD operating point by indicating the precise point of avalanche breakdown. The MAX1932 control
scheme prevents output overshoot and undershoot to
provide safe APD operation without data loss.
• Unique Architecture Delivers Excellent Accuracy for
The output voltage can be accurately set with either
external resistors, an internal 8-bit DAC, an external
DAC, or other voltage source. Output span and offset
are independently settable with external resistors. This
optimizes the utilization of DAC resolution for applications that may require limited output voltage range, such
as 4.5V to 15V, 4.5V to 45V, 20V to 60V, or 40V to 90V.
•
•
•
•
Improved System Performance
• 0.5% Accurate Output
• Low Ripple Output (< 1mV)
Protection Features Guarantee Safe Operation
• Accurate High-Side Current Limit
• Avalanche Indicator Flag
Output-Voltage Flexibility Facilitates Multiple
Applications and Design Approaches
• 4.5V to 90V Output
• Set Output Voltage via 8-Bit SPI-Compatible
Internal DAC, External DAC, or External Resistors
Small Circuit Footprint Reduces Equipment Size
• 12-Pin, 4mm x 4mm Thin QFN Package
• Circuit Height < 2mm
Commonly Available 2.7V to 5.5V Input Voltage
Range
Ordering Information
PART
TEMP RANGE
MAX1932ETC
PIN-PACKAGE
-40°C to +85°C 12 Thin QFN
Applications
Optical Receivers and Modules
Fiber Optic Network Equipment
Telecom Equipment
Laser Range Finders
PIN Diode Bias Supply
Typical Application Circuit
INPUT
2.7V TO 5.5V
Pin Configuration
SCLK
1
DIN
2
CS
VIN
GATE
VIN
12
11
10
MAX1932
COMP
9
GND
8
COMP
GATE
CS
DAC INPUTS
19-2555; Rev 2; 5/15
4
5
6
DACOUT
7
CS-
3
CS+
CL
APD BIAS OUTPUT
4.5V TO 90V
MAX1932
FB
SCLK
CS+
CS-
DIN
AVALANCHE
INDICATOR
FLAG
CL
FB
GND
DACOUT
Digitally Controlled, 0.5% Accurate,
Safest APD Bias Supply
MAX1932
Absolute Maximum Ratings
VIN to GND...............................................................-0.3V to +6V
DIN, SCLK, CS, FB to GND ......................................-0.3V to +6V
COMP, DACOUT, GATE, CL to GND ...........-0.3V to (VIN +0.3V)
CS+, CS- to GND .................................................-0.3V to +110V
Continuous Power Dissipation (TA = +70°C)
12-Pin Thin QFN (derate 16.9mW/°C above +70°C) .1349mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering 10s) ..................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Electrical Characteristics
(VIN = 3.3V, CS = SCLK = DIN = 3.3V, CS+ = CS- = 45V, Circuit of Figure 2, TA = 0°C to +85°C, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
2.7
5.5
V
2.1
2.6
V
0.5
1
mA
25
65
µA
0.5
1
2.0
MΩ
1.80
2.00
2.20
V
GENERAL
Input Supply Range
VIN Undervoltage Lockout
Operating Supply Current
VIN Shutdown Supply Current
VIN
UVLO
Both rise/fall, hysteresis = 100mV
IIN
ISHDN
Input Resistance for CS+/CS-
00 hex loaded to DAC
Resistance from either pin to ground
Current-Limit Threshold
for CS+/CSCommon-Mode Rejection
of Current Threshold
CS+ = 3V to 100V
Gate-Driver Resistance
Gate high or low, IGATE = ±50mA
FB Input Bias Current
FB Voltage
FB Voltage
Temperature Coefficient
VFB
1.24375 1.2500 1.25625
0.0007
DAC code = 00 hex
DACOUT to FB Voltage Difference
DAC code = FF hex
DACOUT Differential Nonlinearity
(Note 1)
DAC Code = 01 to FF hex,
DAC guaranteed monotonic
50
tON
%/°C
µS
100
Ω
-3
+3
mV
-1
+1
LSB
0.0007
DAC code = 0F to FF hex, source or sink
50µA
fOSC
110
V
200
TCVDACOUT
GATE Maximum On-Time
Ω
nA
1.24250 1.2500 1.25750
COMP Pulldown Resistance
in Shutdown
Switching Frequency
10
+25
TA = 0°C to +85°C
TCVFB
DACOUT Load Regulation
%/V
TA = +25°C
COMP = 1.5V
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5
-25
FB to COMP Transconductance
DACOUT Voltage Temperature
Coefficient
±0.005
-1
250
300
3
%/°C
+1
mV
340
kHz
µs
Maxim Integrated | 2
Digitally Controlled, 0.5% Accurate,
Safest APD Bias Supply
MAX1932
Electrical Characteristics (continued)
(VIN = 3.3V, CS = SCLK = DIN = 3.3V, CS+ = CS- = 45V, Circuit of Figure 2, TA = 0°C to +85°C, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
0.6
V
DIGITAL INPUTS (DIN, SCLK, CS)
Input Low Voltage
Input High Voltage
1.4
Input Hysteresis
V
200
TA = +25°C
Input Leakage Current
-1
TA = 0°C to +85°C
Input Capacitance
mV
+1
µA
10
nA
5
pF
DIGITAL OUTPUT (CL)
Output Low Voltage
ISINK = 1mA
Output High Voltage
ISOURCE = 0.5mA
0.1
VIN - 0.5
V
V
SPI TIMING (FIGURE 5)
SCLK Clock Frequency
SCLK Low Period
fSCLK
2
MHz
tCL
125
ns
SCLK High Period
tCH
125
ns
Data Hold Time
tDH
0
ns
Data Setup Time
tDS
125
ns
CS Assertion to SCLK
Rising Edge Setup Time
tCSS0
200
ns
CS Deassertion to SCLK
Rising Edge Setup Time
tCSS1
200
ns
SCLK Rising Edge
to CS Deassertion
tCSH1
200
ns
SCLK Rising Edge
to CS Assertion
tCSH0
200
ns
CS High Period
tCSW
300
ns
Electrical Characteristics
(VIN = 3.3V, CS = SCLK = DIN = 3.3V, CS+ = CS- = 45V, Circuit of Figure 2, TA = -40°C to +85°C, unless otherwise noted.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
2.7
5.5
V
2.1
2.6
V
1
mA
GENERAL
Input Supply Range
VIN
VIN Undervoltage Lockout
UVLO
Operating Supply Current
IIN
VIN Shutdown Supply Current
Input Resistance for CS+/CS-
ISHDN
Both rise/fall, hysteresis = 100mV
00 hex loaded to DAC
Resistance from either pin to ground
Current-Limit Threshold
for CS+/CSGate-Driver Resistance
FB Input Bias Current
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65
µA
0.5
2
MΩ
1.80
2.20
V
10
Ω
+30
nA
Gate high or low, IGATE = ±50mA
-30
Maxim Integrated | 3
Digitally Controlled, 0.5% Accurate,
Safest APD Bias Supply
MAX1932
Electrical Characteristics (continued)
(VIN = 3.3V, CS = SCLK = DIN = 3.3V, CS+ = CS- = 45V, Circuit of Figure 2, TA = -40°C to +85°C, unless otherwise noted.) (Note 2)
PARAMETER
FB Voltage
SYMBOL
CONDITIONS
VFB
TYP
MAX
UNITS
1.23875
1.26125
V
50
200
µS
100
Ω
-4
+4
mV
DAC Code = 01 to FF hex, DAC
guaranteed monotonic
-1
+1
LSB
DAC code = 0F to FF hex, source or sink
50µA
-1
+1
mV
240
360
kHz
0.6
V
FB to COMP Transconductance
COMP = 1.5V
COMP Pulldown Resistance
in Shutdown
DAC code = 00 hex
DACOUT to FB Voltage Difference
DAC code = FF hex
DACOUT Differential Nonlinearity
(Note 1)
DACOUT Load Regulation
Switching Frequency
MIN
fOSC
DIGITAL INPUTS (DIN, SCLK, CS)
Input Low Voltage
Input High Voltage
1.4
V
DIGITAL OUTPUT (CL)
Output Low Voltage
ISINK = 1mA
Output High Voltage
ISOURCE = 0.5mA
0.1
VIN - 0.5
V
V
SPI TIMING (FIGURE 5)
SCLK Clock Frequency
fSCLK
2
MHz
SCLK Low Period
tCL
125
ns
SCLK High Period
tCH
125
ns
Data Hold Time
tDH
0
ns
Data Setup Time
tDS
125
ns
CS Assertion to SCLK
Rising Edge Setup Time
tCSS0
200
ns
CS Deassertion to SCLK
Rising Edge Setup Time
tCSS1
200
ns
SCLK Rising Edge
to CS Deassertion
tCSH1
200
ns
SCLK Rising Edge
to CS Assertion
tCSH0
200
ns
CS High Period
tCSW
300
ns
Note 1: DACOUT = DAC code x (1.25V/256) + 1.25V/256.
Note 2: Specifications to -40°C are guaranteed by design and not production tested.
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Maxim Integrated | 4
Digitally Controlled, 0.5% Accurate,
Safest APD Bias Supply
MAX1932
Typical Operating Characteristics
(VIN = 5V, Circuit of Figure 2, TA =+25°C, unless otherwise noted)
SWITCHING WAVEFORM WITH LC FILTER
SWITCHING WAVEFORMS
MAX1932 toc01
STARTUP AND SHUTDOWN WAVEFORMS
MAX1932 toc03
MAX1932 toc02
VLX
VLX
50V/div
50V/div
IL
IL
VOUT RIPPLE (AC-COUPLED)
0.002V/div
50V/div
INPUT
CURRENT
50mA/div
0.05A/div
0.05A/div
VOUT RIPPLE (AC-COUPLED)
OUTPUT
VOLTAGE
0.002V/div
VOUT = 90V, L = 300μH, C = 1μF, FIGURE 7
20ms/div
OUTPUT VOLTAGE vs. INPUT VOLTAGE
VFB vs. TEMPERATURE
OUTPUT VOLTAGE vs. LOAD CURRENT
95
MAX1932 toc05
1μs/div
90
CURRENT LIMIT
ACTIVATED
85
OUTPUT VOLTAGE (V)
MAX1932 toc04
1μs/div
MAX1932 toc06
VOUT = 90V
80
75
70
65
VCC = 5V, INDUCTOR = 100μH,
R1 = 806Ω
FEEDBACK DIVIDER CURRENT AND CSCURRENT INCLUDED
60
55
50
2.5
3.5
5.5
4.5
60
-40
-20
0
20
40
60
80
100
0
0.5
1.0
1.5
2.0
2.5
INPUT VOLTAGE (V)
TEMPERATURE (°C)
LOAD CURRENT (mA)
OUTPUT VOLTAGE STEP-DOWN
DUE TO DAC CHANGE
OUTPUT VOLTAGE STEP-UP
DUE TO DAC CHANGE
OUTPUT VOLTAGE STEP
DUE TO DACOUT CHANGE
MAX1932 toc07
MAX1932 toc09
MAX1932 toc08
OFFSET = 62.962V = 88 hex
STEP DOWN FROM 80 hex TO 88 hex
OFFSET = 62.962V = 88 hex
STEP VALUE = 64.233 = 80 hex
1V/div
3.0
20V/div
1V/div
DACOUT EXTERNAL SOURCE
0.5V/div
10ms/div
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10ms/div
20ms/div
Maxim Integrated | 5
Digitally Controlled, 0.5% Accurate,
Safest APD Bias Supply
MAX1932
Pin Description
PIN
NAME
FUNCTION
1
SCLK
DAC Serial Clock Input
2
DIN
DAC Serial Data Input
3
CL
Current-Limit Indicator Flag. CL = 0 indicates that the part is in current limit. Logic high level = VIN.
4
CS+
Current-Limit Plus Sense Input. Connect a resistor from CS+ to CS- in series with the output. The differential
threshold is 2V. CS+ has typically 1MΩ resistance to ground.
5
CS-
Current-Limit Minus Sense Input. CS- has typically 1MΩ resistance to ground.
6
DACOUT
7
FB
8
COMP
Internal DAC Output. Generates a control voltage for adjustable output operation. DACOUT can source or
sink 50µA.
Feedback input. Connect to a resistive voltage-divider between the output voltage (VOUT) and FB to set the
output voltage. The feedback set point is 1.25V.
Compensation Pin. Compensates the DC-DC converter control loop with a series RC to GND. COMP is
actively discharged to ground during shutdown or undervoltage conditions.
9
GND
Ground
10
GATE
Gate-Driver Output for External N-FET
11
VIN
IC Supply Voltage (2.7V to 5.5V). Bypass VIN with a 1µF or greater ceramic capacitor.
12
CS
DAC Chip-Select Input
Detailed Description
Fixed Frequency PWM
The MAX1932 uses a constant frequency, PWM, controller architecture. This controller sets the switch ontime and drives an external N-channel MOSFET (see
Figure 1). As the load varies, the error amplifier sets the
inductor peak current necessary to supply the load and
regulate the output voltage.
Output Current Limit
The MAX1932 uses an external resistor at CS+ and CSto sense the output current (see Figure 2). The typical
current-limit threshold is 2V. CL is designed to help find
the optimum APD bias point by going low to indicate
when the APD reaches avalanche and that current limit
has been activated. To minimize noise, CL only
changes state on an internal oscillator edge.
Output Control DAC
An internal digital-to-analog converter can be used to
control the output voltage of the DC-DC converter
(Figure 2). The DAC output is changed through an SPI™
serial interface using an 8-bit control byte. On power-up,
the DAC defaults to FF hex (1.25V), which corresponds
to a minimum boost converter output voltage.
Alternately, the output voltage can be set with external
resistors, an external DAC, or a voltage source. Output
span and offset are independently settable with external resistors. See the Applications Information section
for output control equations.
SPI Interface/Shutdown
Use an SPI-compatible 3-wire serial interface with the
MAX1932 to control the DAC output voltage and to shut
down the MAX1932. Figures 4 and 5 show timing diagrams
for the SPI protocol. The MAX1932 is a write-only device
and uses CS along with SCLK and DIN to communicate.
The serial port is always operational when the device is
powered. To shut down the DC-DC converter portion only,
update the DAC registers to 00 hex.
Applications Information
Voltage Feedback Sense Point
Feedback can be taken from in front of, or after, the current-limit sense resistor. The current-limit sense resistor
forms a lowpass filter with the output capacitor. Taking
feedback after the current-limit sense resistor (see Figure
2), optimizes the output voltage accuracy, but requires
overcompensation, which slows down the control loop
response. For faster response, the feedback can be
taken from in front of the current-sense resistor (see
Figure 3). This configuration however, makes the output
voltage more sensitive to load variation and degrades
output accuracy by an amount equal to the load current
times the current-sense resistor value.
SPI is a trademark of Motorola, Inc.
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Maxim Integrated | 6
Digitally Controlled, 0.5% Accurate,
Safest APD Bias Supply
MAX1932
Output and DAC Adjustments Range
Many biasing applications require an adjustable output
voltage, which is easily obtained using the MAX1932’s
DAC output (Figure 2).
The DAC output voltage is given by the following equation:
⎛ 1.25V ⎞ ⎛ 1.25V ⎞
VDACOUT = CODE × ⎜
⎟ +⎜
⎟
⎝ 256 ⎠ ⎝ 256 ⎠
On power-up, DACOUT defaults to FF hex or 1.25V,
which corresponds to the minimum VOUT output voltage.
The voltage generated at DACOUT is coupled to FB
through R6. DACOUT can sink only 50µA so:
R6 ≥
1.25V
50μA
Select the minimum output voltage (VOUTFF), and the
maximum output voltage (V OUT01 ) for the desired
adjustment range. R5 sets the adjustment span using
the following equation:
The inductance value is given by:
L=
R8 = (1.25V ✕ R5)/(VOUTFF)
Setting the Output Voltage without
the DAC
Adjust the output voltage by connecting a voltagedivider from the output (VOUT) to FB (Figure 2 with R6
omitted). Select R8 between 10kΩ to 50kΩ. Calculate
R5 with the following equation:
⎛ VOUT ⎞
R5 = R8 ⎜
− 1⎟
⎝ 1.25V ⎠
Inductor Selection
Optimum inductor selection depends on input voltage,
output voltage, maximum output current, switching frequency, and inductor size. Inductors are typically specified by their inductance (L), peak current (IPK), and
resistance (LR).
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2IOUT(MAX) × VOUT
where VIN is the input voltage, IOUT(MAX) is the maximum output current delivered, VOUT is the output voltage, and T is the switching period (3.3µs), η is the
estimated power conversion efficiency, and D is the
maximum duty cycle:
D < (VOUT - VIN)/VOUT up to a maximum of 0.9
Since the L equation factors in efficiency, for inductor calculation purposes, an η of 0.5 to 0.75 is usually suitable.
For example, with a maximum DC load current of 2.5mA,
a 90V output, VIN = 5V, D = 0.9, T = 3.3µs, and η estimated at 0.75, the above equation yields an L of 111µH,
so 100µH would be a suitable value.
The peak inductor current is given by:
V ×D× T
IPK = IN
L
R5 = (VOUTFF - VOUT01) (R6/1.25V)
R8 sets the minimum output of the adjustment range
with the following equation:
(VIN )2 × D2 × T × η
These are typical calculations. For worst case, refer to
the article titled “Choosing the MAX1932 External
Indicator, Diode, Current Sense Resistor, and Output
Filter Capacitor for Worst Case Conditions” located on
the Maxim website in the Application Notes section (visit
www.maxim-ic.com/an1805).
External Power-Transistor Selection
An N-FET power switch is required for the MAX1932. The
N-FET switch should be selected to have adequate onresistance with the MOSFET VGS = VIN(MIN). The breakdown voltage of the N-FET must be greater than VOUT.
For higher-current output applications (such as 5mA at
90V), SOT23 high-voltage low-gate-threshold N-FETs
may not have adequate current capability. For example,
with a 5V input, a 90V, 5mA output requires an inductor
peak of 240mA. For such cases it may be necessary to
simply parallel two N-FETs to achieve the required current rating. With SOT23 devices this often results in
smaller and lower cost than using a larger N-FET device.
Diode Selection
The output diode should be rated to handle the output
voltage and the peak switch current. Make sure that the
diode’s peak current rating is at least IPK and that its
breakdown voltage exceeds VOUT. Fast reverse recovery time (t rr < 10ns) and low junction capacitance
Maxim Integrated | 7
Digitally Controlled, 0.5% Accurate,
Safest APD Bias Supply
MAX1932
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