19-3154; Rev 1; 5/05
KIT
ATION
EVALU
E
L
B
A
IL
AVA
Low-Cost, Current-Mode PWM Buck
Controller with Foldback Current Limit
The MAX1954A synchronous current-mode, pulsewidth modulation (PWM) buck controller is pin compatible with the popular MAX1954 and is suitable for
applications where cost and size are critical.
The MAX1954A operates from an input voltage range of
3.0V to 13.2V, independent of the IC supply. The output
voltage is adjustable down to 0.8V. The IC operates at
a fixed 300kHz switching frequency and provides up to
25A of output current with efficiency up to 95%. This
controller has excellent transient response resulting in
smaller output capacitance.
The MAX1954A features foldback current limiting that
greatly reduces input current and component power
dissipation during output overload or short-circuit
conditions.
The compensation and shutdown control (COMP) input,
in addition to providing compensation to the error
amplifier, can be pulled low to shut down the converter.
An input undervoltage lockout is provided to ensure
proper operation during power sags to prevent the
external power MOSFETs from overheating. Internal
digital soft-start is included to reduce inrush current
and save an external capacitor.
Features
♦ Current-Mode Controller
♦ Fixed-Frequency PWM
♦ Foldback Current Limit
♦ Output Down to 0.8V with ±1% FB Accuracy
♦ 3.0V to 13.2V Input Voltage
♦ 300kHz Switching Frequency
♦ 25A Output-Current Capability
♦ 93% Efficiency
♦ All-N-Channel-MOSFET Design for Low Cost
♦ No Current-Sense Resistor Needed
♦ Internal Digital Soft-Start
♦ Small 10-Pin µMAX Package
The MAX1954A is available in a tiny 10-pin µMAX®
package to minimize PC board space.
Applications
Printers and Scanners
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
Graphic Cards and Video Cards
MAX1954AEUB
-40°C to +85°C
10 µMAX
PCs and Servers
MAX1954AEUB+
-40°C to +85°C
10 µMAX
Microprocessor Cores
+Denotes lead-free package.
Low-Voltage Distributed Power
Telecom/Networks
Pin Configuration
TOP VIEW
HSD 1
COMP
µMAX is a registered trademark of Maxim Integrated Products, Inc.
10 BST
2
MAX1954A
9
LX
FB
3
8
DH
GND
4
7
PGND
IN
5
6
DL
µMAX
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX1954A
General Description
MAX1954A
Low-Cost, Current-Mode PWM Buck
Controller with Foldback Current Limit
ABSOLUTE MAXIMUM RATINGS
IN, FB to GND...........................................................-0.3V to +6V
LX to BST..................................................................-6V to +0.3V
BST to GND ............................................................-0.3V to +20V
DH to LX ................................................... -0.3V to (VBST + 0.3V)
DL, COMP to GND.......................................-0.3V to (VIN + 0.3V)
HSD to GND..............................................................-0.3V to 14V
PGND to GND .......................................................-0.3V to +0.3V
Continuous Power Dissipation (TA = +70°C)
10-Pin µMAX (derate 5.6mW/°C above +70°C) ...........444mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range ............................+65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VIN = 5V, VBST - VLX = 5V, TA = 0°C to +85°C, unless otherwise noted.)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
3.0
5.5
V
3.0
13.2
V
2
mA
2
mA
2.9
V
GENERAL
Operating Input Voltage Range
HSD Voltage Range
(Note 1)
Quiescent Supply Current
VFB = 1.5V
Standby Supply Current
VIN = VBST = 5.5V, VHSD = 13.2V, LX = unconnected,
COMP = GND
Undervoltage-Lockout Trip Level
Falling VIN, 50mV (typ) hysteresis
2.5
Maximum output voltage depends on external components
and maximum duty cycle
0.8
1
2.7
DC-DC CONTROLLER
Output-Voltage Adjust Range
(VOUT)
V
ERROR AMPLIFIER
FB Regulation Voltage
Transconductance
-1.0
+0.8
+1.0
70
110
160
Voltage Gain
FB Input Leakage Current
200
500
NA
-0.1
+1.5
V
COMP Output-Voltage Swing
0.80
2.36
V
Current-Sense Amplifier
Voltage Gain
3.15
3.5
3.85
V/V
VFB = 0.8V
110
135
145
VFB = 0V
21
36
51
300
360
kHz
91
93
%
2.5
3
%
VPGND - VLX
50
µS
V/ V
FB Input Common-Mode Range
Current-Limit Threshold
VFB = 0.9V
%
mV
OSCILLATOR
Switching Frequency
MAX1954A
240
Maximum Duty Cycle
Measured at DH
89
Minimum Duty Cycle
VCOMP = 1.25V, LX = GND, VBST = VIN = 3.3V
2
_______________________________________________________________________________________
Low-Cost, Current-Mode PWM Buck
Controller with Foldback Current Limit
(VIN = 5V, VBST - VLX = 5V, TA = 0°C to +85°C, unless otherwise noted.)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
SOFT-START
Soft-Start Period
3.4
ms
Soft-Start Levels
12.5
mV
FET DRIVERS
DH, DL Output Low Voltage
ISINK = 10mA
DH, DL Output High Voltage
ISOURCE = 10mA
0.1
VIN - 0.1V or
VBST - 0.1V
DH Pullup/Pulldown,
DL Pullup On-Resistance
LX, BST, HSD Leakage Current
V
1.5
DL Pulldown On-Resistance
V
1
VBST = 18.7V, VLX = 13.2V, VIN = 5.5V, VHSD = 13.2V
3
Ω
2
Ω
30
µA
THERMAL PROTECTION
Thermal Shutdown
Rising temperature, 15°C hysteresis
°C
+160
SHUTDOWN CONTROL
COMP Logic-Level Low
3V < VIN < 5.5V
COMP Logic-Level High
3V < VIN < 5.5V
0.25
V
100
µA
MAX
UNITS
3.0
5.5
V
3.0
13.2
V
0.8
COMP Pullup Current
V
ELECTRICAL CHARACTERISTICS
(VIN = 5V, VBST - VLX = 5V, TA = -40°C to +85°C, unless otherwise noted.) (Note 2)
PARAMETER
CONDITIONS
MIN
GENERAL
Operating Input Voltage Range
HSD Voltage Range
(Note 1)
Quiescent Supply Current
VFB = 1.5V
2
mA
Standby Supply Current
VIN = VBST = 5.5V, VHSD = 13.2V, LX = unconnected,
COMP = GND
2
mA
Undervoltage Lockout Trip Level
Rising VIN 3% (typ) hysteresis
2.93
V
2.50
DC-DC CONTROLLER
Output-Voltage Adjust Range
(VOUT)
0.8
0.9 x VIN
V
-2.5
+1.0
%
70
160
µS
500
NA
ERROR AMPLIFIER
FB Regulation Voltage
Transconductance
FB Input Leakage Current
VFB = 0.9V
FB Input Common-Mode Range
-0.1
+1.5
V
COMP Output-Voltage Swing
0.8
2.2
V
_______________________________________________________________________________________
3
MAX1954A
ELECTRICAL CHARACTERISTICS (continued)
MAX1954A
Low-Cost, Current-Mode PWM Buck
Controller with Foldback Current Limit
ELECTRICAL CHARACTERISTICS (continued)
(VIN = 5V, VBST - VLX = 5V, TA = -40°C to +85°C, unless otherwise noted.) (Note 2)
PARAMETER
CONDITIONS
MIN
MAX
UNITS
3.15
3.85
V/V
VFB = 0.8V
110
145
VFB = 0V
21
51
240
360
kHz
89
93
%
3
%
0.1
V
Current-Sense Amplifier
Voltage Gain
Current-Limit Threshold
VPGND - VLX, MAX1954A
mV
OSCILLATOR
Switching Frequency
Maximum Duty Cycle
Measured at DH
Minimum Duty Cycle
VCOMP = 1.25V, LX = GND, VBST = VIN = 3.3V
FET DRIVERS
DH, DL Output Low Voltage
ISINK = 10mA
DH, DL Output High Voltage
ISOURCE = 10mA
VIN - 0.1V or
VBST - 0.1V
V
DH Pullup/Pulldown,
DL Pullup On-Resistance
3
Ω
DL Pulldown On-Resistance
2
Ω
30
µA
0.25
V
100
µA
LX, BST, HSD Leakage Current
VBST = 18.7V, VLX = 13.2V, VIN = 5.5V, VHSD = 13.2V
SHUTDOWN CONTROL
COMP Logic-Level Low
3V < VIN < 5.5V
COMP Logic-Level High
3V < VIN < 5.5V
0.8
COMP Pullup Current
Note 1: HSD and IN are externally connected for applications where HSD < 5.5V.
Note 2: Specifications to -40°C are guaranteed by design and not production tested.
4
_______________________________________________________________________________________
V
Low-Cost, Current-Mode PWM Buck
Controller with Foldback Current Limit
MAX1954A
Typical Operating Characteristics
(TA = +25°C, unless otherwise noted.)
OUTPUT VOLTAGE
vs. LOAD CURRENT
OUTPUT VOLTAGE (V)
EFFICIENCY (%)
VOUT = 1.5V
70
60
2.55
2.50
2.45
50
VIN = VHSD = 5V
VIN = VHSD = 5V
2.40
40
0.1
1
2
3
4
LOAD CURRENT (A)
OUTPUT VOLTAGE
vs. INPUT VOLTAGE
OSCILLATOR FREQUENCY
vs. INPUT VOLTAGE
0.80
0.80
VIN = VHSD
IOUT = 5A
5
VOUT = 2.5V
10
-10
VOUT = 0.8V
-30
-50
VIN = VHSD
IOUT = 5A
3.0
3.5
4.0
4.5
5.0
5.5
LOAD TRANSIENT
MAX1954A toc06
330
MAX1954A toc05
MAX1954A toc04
0.81
30
INPUT VOLTAGE (V)
350
OSCILLATOR FREQUENCY (kHz)
OUTPUT VOLTAGE (V)
1
LOAD CURRENT (A)
0.81
50
-70
0
10
70
MAX1954A toc03
90
MAX1954A toc02
VOUT = 2.5V
80
2.60
MAX1954A toc01
100
OUTPUT VOLTAGE CHANGE
vs. INPUT VOLTAGE
CHANGE IN OUTPUT VOLTAGE (mV)
EFFICIENCY
vs. LOAD CURRENT
TA = -40°C
VOUT
AC-COUPLED
100mV/div
310
5A
290
TA = +85°C
TA = +25°C
IOUT
5A/µs
270
500mA
VIN = VHSD
250
0.79
10.8
11.4
12.0
INPUT VOLTAGE (V)
12.6
13.2
3.0
3.5
4.0
4.5
5.0
5.5
40µs/div
INPUT VOLTAGE (V)
_______________________________________________________________________________________
5
MAX1954A
Low-Cost, Current-Mode PWM Buck
Controller with Foldback Current Limit
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
NO-LOAD SWITCHING WAVEFORMS
LOAD TRANSIENT
MAX1954A toc08
MAX1954A toc07
VOUT
AC-COUPLED
IL
2A/div
DH
10V/div
LX
5V/div
DL
5V/div
100mV/div
5A
IOUT
5A/µs
2.5A
2µs/div
40µs/div
HEAVY-LOAD SWITCHING WAVEFORMS
ILOAD = 5A
POWER-UP/POWER-DOWN WAVEFORMS
MAX1954A toc10
MAX1954A toc09
IL
2A/div
DH
10V/div
LX
DL
VIN
5V/div
5V/div
VOUT
2V/div
5V/div
ILX
5A/div
2µs/div
4ms/div
SHORT CIRCUIT AND RECOVERY
STARTUP INTO PREBIASED OUTPUT
(OUTPUT PREBIASED AT ~1.7V)
MAX1954A toc11
VOUT
1V/div
VIN
2V/div
IIN
2A/div
VOUT
1V/div
VIN
5V/div
DH
5V/div
DL
5V/div
5A/div
ILX
200µs/div
6
MAX1954A toc12
2ms/div
_______________________________________________________________________________________
Low-Cost, Current-Mode PWM Buck
Controller with Foldback Current Limit
PIN
NAME
FUNCTION
1
HSD
2
COMP
Compensation and Shutdown Control Pin. Connect appropriate RC networks to compensate the control loop.
Pull to GND to shut down the IC. See the Compensation Design section for instructions on calculating the RC
values.
3
FB
Feedback Input. Regulates at VFB = 0.8V. Connect FB to the center tap of a resistor-divider from the output to
GND to set the output voltage.
4
GND
5
IN
IC Supply Voltage. Provides power for the IC. Connect to a 3V to 5.5V power supply. Bypass to GND with a
0.22µF ceramic capacitor and to PGND with a 1µF ceramic capacitor.
6
DL
Low-Side Gate-Drive Output. Drives the synchronous-rectifier MOSFET. Swings from 0 to VIN. DL is low in
shutdown and UVLO.
7
PGND
8
DH
High-Side Gate-Drive Output. Drives the high-side N-channel MOSFET. DH is a floating driver output that swings
from VLX to VBST. DH is low in shutdown and UVLO.
9
LX
Controller Current-Sense Input. Connect LX to the junction of the MOSFETs and inductor. LX is the reference
point for the current limit.
10
BST
High-Side MOSFET Supply Input. Connect a 0.1µF ceramic capacitor from BST to LX to supply the necessary
gate drive for the high-side N-channel MOSFET.
High-Side Drain Current-Sense Input. HSD senses the voltage at the drain of the high-side, N-channel MOSFET.
Connect to the high-side MOSFET drain using a Kelvin connection.
Ground
Power Ground
Detailed Description
The MAX1954A single-output, current-mode, PWM, stepdown DC-DC controller features foldback current limit
and switches at 300kHz for high efficiency. The
MAX1954A is designed to drive a pair of external Nchannel power MOSFETs in a synchronous buck topology to improve efficiency and cost compared with a
P-channel power-MOSFET topology. The on-resistance
of the low-side MOSFET is used for short-circuit currentlimit sensing, while the high-side MOSFET’s on-resistance is used for current-mode feedback, thus
eliminating the need for current-sense resistors. The
short-circuit current limit is fixed at 135mV. The foldback
current scheme reduces the input current during shortcircuit and severe-overload conditions. The MAX1954A
is configured with a high-side drain input (HSD) allowing
an extended input voltage range of 3V to 13.2V that is
independent of the IC input supply (Figure 1).
DC-DC Converter Control Architecture
The MAX1954A step-down converter uses a PWM, current-mode control scheme. An internal transconductance
amplifier establishes an integrated error voltage. An
open-loop comparator compares the integrated voltagefeedback signal against the amplified current-sense signal plus the slope compensation ramp, which is summed
into the main PWM comparator to preserve inner-loop stability and eliminate inductor staircasing. At each rising
edge of the internal clock, the high-side MOSFET turns on
until the PWM comparator trips or the maximum duty
cycle is reached. During this on-time, current ramps up
through the inductor, storing energy in a magnetic field
and sourcing current to the output. The current-mode
feedback system regulates the peak inductor current as a
function of the output-voltage error signal. The circuit acts
as a switch-mode transconductance amplifier because
the average inductor current is close to the peak inductor
current (assuming the inductor is large enough to provide
a reasonably small ripple current). This pushes the output
inductance-capacitance filter pole normally found in a
voltage-mode PWM to a higher frequency.
_______________________________________________________________________________________
7
MAX1954A
Pin Description
Low-Cost, Current-Mode PWM Buck
Controller with Foldback Current Limit
MAX1954A
Functional Diagram
IN
THERMAL
LIMIT
SHUTDOWN
COMPARATOR
UVLO
MAX1954A
SLOPE
COMPENSATION
0.5V
HSD
COMP
2.36V
CLAMP
ERROR
AMPLIFIER
BST
FB
PWM
CONTROL
CIRCUITRY
DH
CURRENTSENSE
CIRCUITRY
LX
IN
DL
CURRENT-LIMIT
COMPARATOR
REFERENCE
AND
SOFT-START
DIGITAL-TO-ANALOG
CONVERTER
PGND
SHORT-CIRCUIT
CURRENT-LIMIT
CIRCUITRY
CLOCK
FOLDBACK CURRENTLIMIT CIRCUITRY
GND
During the second half of the cycle, the high-side
MOSFET turns off and the low-side MOSFET turns on. The
inductor releases the stored energy as the current ramps
down, providing current to the output. The output capacitor stores charge when the inductor current exceeds the
required load current and discharges when the inductor
current is lower, smoothing the voltage across the load.
Under overload conditions, when the inductor current
exceeds the current limit (see the Current-Limit Circuit
section), the high-side MOSFET is not turned on at the rising clock edge and the low-side MOSFET remains on to
let the inductor current ramp down.
8
The MAX1954A operates in a forced-PWM mode; therefore, the controller maintains a constant switching frequency, regardless of load, to allow for easier postfiltering of the switching noise.
Current-Sense Amplifier
The current-sense circuit amplifies the current-sense
voltage (the high-side MOSFET’s on-resistance
(RDS(ON)) multiplied by the inductor current). This amplified current-sense signal and the internal slope-compensation signal are summed (VSUM) together and fed into
the PWM comparator’s inverting input. The PWM comparator shuts off the high-side MOSFET when VSUM
exceeds the integrated feedback voltage (V COMP ).
_______________________________________________________________________________________
Low-Cost, Current-Mode PWM Buck
Controller with Foldback Current Limit
C1
VIN
3V TO 5.5V
C2
C3
D1
IN
VHSD
5.5V TO 13.2V
HSD
N1
BST
DH
C4
L1
MAX1954A LX
RC
COMP
CC
R1
R3
DL
CF
VOUT
1.8V
C5
C6
PGND
R2
FB
GND
Figure 1. MAX1954A Typical Application Circuit
VHSD
10.8V TO 13.2V
VIN
3V TO 5.5V
D1
HSD
C1
0.22µF
IN
BST
C15
N1
DH
C7
0.1µF
MAX1954A
RC
270kΩ
L1
0.8µH
VOUT
+1.8V AT 20A
LX
N3
COMP
CC
560pF
C2–C6
10µF
N2
CF
15pF
N4
R3
DL
R1
10kΩ
C14
C8–C13
270µF
PGND
R2
8.06kΩ
GND
FB
Figure 2. MAX1954A Circuit Capable of 20A Output
Place the high-side MOSFET as close as possible to
the controller and connect HSD and LX to the MOSFET
using Kelvin-sense connections to guarantee currentsense accuracy and improve stability.
Current-Limit Circuit
The current-limit circuit employs a lossless, foldback,
valley current-limiting algorithm that uses the low-side
MOSFET’s on-resistance as the sensing element. Once
the high-side MOSFET turns off, the voltage across the
low-side MOSFET is monitored. If the voltage across the
low-side MOSFET (R DS(ON) x I INDUCTOR ) does not
exceed the current limit, the high-side MOSFET turns on
normally. In this condition, the output drops smoothly out
of regulation. If the voltage across the low-side MOSFET
exceeds the current-limit threshold at the beginning of a
new oscillator cycle, the low-side MOSFET remains on
and the high-side MOSFET remains off.
_______________________________________________________________________________________
9
MAX1954A
Typical Application Circuits
MAX1954A
Low-Cost, Current-Mode PWM Buck
Controller with Foldback Current Limit
When the output is shorted, the foldback current limit
reduces the current-limit threshold linearly to 20% of
the nominal value to reduce the power dissipation of
components and the input current. Once the voltage
across the low-side MOSFET drops below the currentlimit threshold, the high-side MOSFET is turned on at
the next clock cycle. During severe-overload and shortcircuit conditions, the frequency of the MAX1954A
appears to decrease because the on-time of the
low-side MOSFET extends beyond a clock cycle. The
current-limit threshold is preset to 135mV.
In addition to the valley current limit, the MAX1954A
also features a cycle-by-cycle peak-current clamp that
limits the voltage across the high-side MOSFET by terminating its on-time. This, together with the valley foldback current limit, provides a very robust overload and
short-circuit protection.
Synchronous-Rectifier Driver (DL)
Synchronous rectification reduces conduction losses in
the rectifier by replacing the normal Schottky catch
diode with a low-resistance MOSFET switch. The
MAX1954A also uses the synchronous rectifier to ensure
proper startup of the boost gate-driver circuit and to
provide the current-limit signal. The DL low-side waveform is always the complement of the DH high-side
drive waveform (with controlled dead time to prevent
crossconduction or shoot-through). A dead-time circuit
monitors the DL output and prevents the high-side
MOSFET from turning on until DL is fully off. For the
dead-time circuit to work properly, there must be a lowresistance, low-inductance path from the DL driver to
the MOSFET gate. Otherwise, the sense circuitry in the
MAX1954A interprets the MOSFET gate as off although
gate charge actually remains. Use very short, wide
traces (50 mils to 100 mils wide if the MOSFET is 1in
from the device). The dead time at the other edge (DH
turning off) is also determined through gate sensing.
Undervoltage Lockout (UVLO)
If VIN drops below 2.7V, the MAX1954A assumes that
the supply voltage is too low for proper circuit operation, so the UVLO circuitry inhibits switching and forces
the DL and DH gate drivers low. After VIN rises above
2.7V, the controller goes into the startup sequence and
resumes normal operation.
Startup
The MAX1954A begins switching when VIN rises above
the UVLO threshold. However, the controller is not
enabled unless five conditions are met:
1) VIN exceeds the 2.7V UVLO threshold.
2) The internal reference exceeds 92% of its nominal
value (VREF > 1V).
3) The internal bias circuitry powers up.
4) The thermal-overload limit is not exceeded.
5) The feedback voltage is below the regulation
threshold.
If these conditions are met, the step-down controller
enables soft-start and begins switching. The soft-start circuitry gradually ramps up the output voltage until the voltage at FB is equal to the reference voltage. This controls
the rate of rise of the output voltage and reduces input
surge currents during startup. The soft-start period is
1024 clock cycles (1024 / fS). The output voltage is incremented through 64 equal steps. The output reaches regulation when soft-start is completed, regardless of output
capacitance and load.
The MAX1954A also has internal circuitry to prevent
discharging of a precharged output capacitor during
soft-start or in UVLO. This feature (monotonic startup)
is needed in applications where the MAX1954A output
is connected in parallel with another power-supply
output, such as redundant-power or standby-power
applications.
High-Side Gate-Drive Supply (BST)
Gate-drive voltage for the high-side, N-channel switch
is generated by a flying-capacitor boost circuit (Figure
3). The capacitor between BST and LX is charged from
the VIN supply up to VIN minus the diode drop while the
low-side MOSFET is on. When the low-side MOSFET is
switched off, the stored voltage of the capacitor is
stacked above LX to provide the necessary turn-on
voltage (VGS) for the high-side MOSFET. The controller
then closes an internal switch between BST and DH to
turn the high-side MOSFET on.
IN
BST
DH
MAX1954A
LX
DL
Figure 3. DH Boost Circuit
10
N
______________________________________________________________________________________
N
Low-Cost, Current-Mode PWM Buck
Controller with Foldback Current Limit
MAX1954A
Table 1. Suggested Components
MAX1954A
(FIGURE 1)
PART DESIGNATOR
20A CIRCUIT
(FIGURE 2)
C1
0.22µF, 10V X7R ceramic capacitor
Kemet C0603C224M8RAC
0.22µF, 10V X7R ceramic capacitor
Kemet C0603C224M8RAC
C2
1µF, 6.3V X5R ceramic capacitor
Taiyo Yuden JMK212BJ106MG
10µF, 16V X5R ceramic capacitor
Taiyo Yuden EMK325BJ106MN
C3
10µF, 16V X5R ceramic capacitor
Taiyo Yuden EMK325BJ106MN
10µF, 16V X5R ceramic capacitor
Taiyo Yuden EMK325BJ106MN
C4
0.1µF, 6.3V X7R ceramic capacitor
10µF, 16V X5R ceramic capacitor
Taiyo Yuden EMK325BJ106MN
C5
180µF, 4V SP polymer capacitor
Panasonic EEFUEOG181R
10µF, 16V X5R ceramic capacitor
Taiyo Yuden EMK325BJ106MN
C6
1500pF, 50V X7R ceramic capacitor
TDK C1608X7R1H152K
10µF, 16V X5R ceramic capacitor
Taiyo Yuden EMK325BJ106MN
C7
—
0.1µF, 50V X7R ceramic capacitor
Taiyo Yuden UMK107BJ104KA
C8
—
270µF, 2V SP polymer capacitor
Panasonic EEFUEOD271R
C9–C13
—
270µF, 2V SP polymer capacitors
Panasonic EEFUEOD271R
Cc
680pF, 10V X7R ceramic capacitor
Kemet C0402C681M8RAC
560pF, 10V X7R ceramic capacitor
Kemet C0402C561M8RAC
CF
—
15pF, 10V C0G ceramic capacitor
Kemet C0402C150K8GAC
R1
16.9kΩ ±1% resistor
10kΩ ±1% resistor
R2
8.06kΩ ±1% resistor
8.06kΩ ±1% resistor
R3
2Ω ±5% resistor
—
RC
62kΩ ±5% resistor
270kΩ ±5% resistor
D1
Schottky diode
Central Semiconductor CMPSH1-4
Schottky diode
Central Semiconductor CMPSH1-4
N1, N2
20V, 5A dual MOSFETs
Fairchild FDS6898A
30V N-channel MOSFETs
International Rectifier IRF7811
N3, N4
—
30V N-channel MOSFETs
Siliconix Si4842DY
1µH, 3.6A inductor
TOKO 817FY-1R0M
0.8µH, 27.5A inductor
Sumida CEP125U-0R8
L1
______________________________________________________________________________________
11
MAX1954A
Low-Cost, Current-Mode PWM Buck
Controller with Foldback Current Limit
Shutdown
The MAX1954A features a low-power shutdown mode.
Use an open-collector, NPN transistor to pull COMP low
and shut down the IC. COMP must be pulled below
0.25V to shut down the MAX1954A. Choose a transistor
with a VCE(SAT) below 0.25V. During shutdown, the output is high impedance. Shutdown reduces the quiescent current (IQ) to 220µA (typ). Note that implementing
shutdown in this fashion discharges the output only
until the inductor runs out of energy. Upon recovery,
soft-start is not available. Only the foldback current limit
results in pseudo-soft-start mode.
Thermal-Overload Protection
Thermal-overload protection limits total power dissipation in the MAX1954A. When the junction temperature
exceeds TJ = +160°C, an internal thermal sensor shuts
down the IC, allowing the IC to cool. The thermal sensor
turns the IC on again after the junction temperature
cools by 15°C, resulting in a pulsed output during continuous thermal-overload conditions.
Design Procedures
Setting the Output Voltage
To set the output voltage for the MAX1954A, connect
FB to the center of an external resistor-divider from the
output to GND (Figures 1 and 2). Select R2 between
8kΩ and 24kΩ, and calculate R1 by:
⎛V
⎞
R1 = R2 × ⎜ OUT − 1⎟
⎝ VFB
⎠
where VFB = 0.8V. R1 and R2 should be placed as
close as possible to the IC.
Inductor Value
There are several parameters that must be examined
when determining which inductor to use. Input voltage,
output voltage, load current, switching frequency, and
LIR. LIR is the ratio of inductor current ripple to DC load
current. A higher LIR value allows for a smaller inductor, but results in higher losses and higher output ripple. A good compromise between size and efficiency is
an LIR of 30%. Once all of the parameters are chosen,
the inductor value is determined as follows:
VOUT × (VIN − VOUT )
L=
VIN × fS × ILOAD(MAX ) × LIR
where fS is the switching frequency. Choose a standard
value close to the calculated value. The exact inductor
value is not critical and can be adjusted to make tradeoffs among size, cost, and efficiency. Lower inductor val12
ues minimize size and cost, but they also increase the
output ripple and reduce the efficiency due to higher
peak currents. On the other hand, higher inductor values
increase efficiency, but eventually resistive losses, due to
extra turns of wire, exceed the benefit gained from lower
AC levels. Find a low-loss inductor with the lowest possible DC resistance that fits the allotted dimensions. Ferrite
cores are often the best choice. However, powdered iron
is inexpensive and can work well at 300kHz. The chosen
inductor’s saturation current rating must exceed the peak
inductor current determined as:
⎛ LIR ⎞
IPEAK = ILOAD(MAX ) + ⎜
⎟ × ILOAD(MAX )
⎝ 2 ⎠
Setting the Current Limit
The MAX1954A uses a valley current-sense method for
current limiting. The voltage drop across the low-side
MOSFET due to its on-resistance is used to sense the
inductor current. The voltage drop across the low-side
MOSFET at the valley point and at ILOAD(MAX) is:
⎛ LIR ⎞
VVALLEY = RDS(ON) × (ILOAD(MAX) − ⎜
⎟ × ILOAD MAX )
⎝ 2 ⎠
( )
The calculated VVALLEY must be less than the minimum
current-limit threshold specified.
Additionally, the high-side MOSFET RDS(ON) must meet
the following equation to avoid tripping the internal
peak-current clamp circuit prematurely:
RDS(ON) < 0.8V / (3.65 x (ILOAD(MAX) x ( 1 + LIR / 2)))
Use the maximum RDS(ON) value at the desired maximum operating junction temperature of the MOSFET. A
good general rule is to allow 0.5% additional resistance
for each °C of MOSFET junction-temperature rise.
MOSFET Selection
The MAX1954A drives two external, logic-level, N-channel MOSFETs as the circuit-switch elements. The key
selection parameters are:
1) On-resistance (R DS(ON) ): the lower, the better.
However, the current-sense signal (RDS x IPEAK)
must be greater than 16mV at maximum load.
2) Maximum drain-to-source voltage (VDSS): it should
be at least 20% higher than the input supply rail at
the high-side MOSFET’s drain.
3) Gate charges (Qg, Qgd, Qgs): the lower, the better.
For a 3.3V input application, choose a MOSFET with a
rated RDS(ON) at VGS = 2.5V. For a 5V input application,
choose the MOSFETs with rated RDS(ON) at VGS ≤ 4.5V.
For a good compromise between efficiency and cost,
______________________________________________________________________________________
Low-Cost, Current-Mode PWM Buck
Controller with Foldback Current Limit
For proper thermal-management design, the power dissipation must be calculated at the desired maximum
operating junction temperature, TJ(MAX). N1 and N2
have different loss components due to the circuit operation. N2 operates as a zero-voltage switch; therefore,
major losses are the channel-conduction loss (PN2CC)
and the body-diode conduction loss (PN2DC).
⎛ LIR ⎞
VVALLEY = RDS(ON) × (ILOAD(MAX) − ⎜
⎟ × ILOAD MAX
⎝ 2 ⎠
( )
In addition to the losses above, allow approximately
20% for additional losses due to MOSFET output capacitances and N2 body-diode reverse-recovery charge
dissipated in N1 that exists, but is not well defined, in
the MOSFET data sheet. Refer to the MOSFET data
sheet for thermal-resistance specification to calculate
the PC board area needed to maintain the desired maximum operating junction temperature with the above calculated power dissipations.
To reduce electromagnetic interference (EMI) caused
by switching noise, add a 0.1µF ceramic capacitor from
the high-side switch drain to the low-side switch source
or add resistors in series with DH and DL to slow down
the switching transitions. However, adding series resistors increases the power dissipation of the MOSFET, so
be sure this does not overheat the MOSFET.
The minimum load current must exceed the high-side
MOSFET’s maximum leakage-current overtemperature
if fault conditions are expected.
Use RDS(ON) at TJ(MAX) .
PN2DC = 2 × ILOAD × VF × t dt × fS
where VF is the body-diode forward-voltage drop, tdt is
the dead time between N1 and N2 switching transitions,
fS is the switching frequency, and tdt is 20ns (typ).
N1 operates as a duty-cycle control switch and has the
following major losses: the channel-conduction loss
(PN1CC), the VL overlapping switching loss (PN1SW),
and the drive loss (PN1DR). N1 does not have bodydiode conduction loss, because the diode never conducts current.
⎛V
⎞
PN1CC = ⎜ OUT ⎟ × I2 LOAD × RDS(ON)
⎝ VIN ⎠
Use RDS(ON) at TJ(MAX) .
⎛Q + Q
gs
gd
PN1SW = VIN × ILOAD × ⎜
⎜ I
GATE
⎝
⎞
⎟ × fS
⎟
⎠
where IGATE is the average DH-driver output current
capability determined by:
IGATE ≅ 0.5 ×
VIN
RDS(ON)(N2) + RGATE
where RDS(ON)(N2) is the high-side MOSFET driver’s
on-resistance (1.5Ω typ) and RGATE is the internal gate
resistance of the MOSFET (~2Ω).
PN1DR = Qg × VGS × fS ×
RGATE
RGATE + RDS(ON)(N2)
MOSFET Snubber Circuit
Fast-switching transitions cause ringing because of
resonating circuit parasitic inductance and capacitance at the switching nodes. This high-frequency ringing occurs at LX’s rising and falling transitions and can
interfere with circuit performance and generate EMI. To
dampen this ringing, a series RC snubber circuit is
added across each switch. Below is the procedure for
selecting the value of the series RC circuit:
1) Connect a scope probe to measure the voltage
from LX to GND, and observe the ringing frequency, fR.
2) Find the capacitor value (connected from LX to
GND) that reduces the ringing frequency by half.
The circuit parasitic capacitance (CPAR) at LX is then
equal to 1/3rd of the value of the added capacitance
above. The circuit parasitic inductance (LPAR) is calculated by:
LPAR =
1
(2π fR )
2
× CPAR
The resistor for critical dampening (RSNUB) is equal to
2π x fR x LPAR. Adjust the resistor value up or down to
tailor the desired damping and the peak voltage excursion. The capacitor (CSNUB) should be at least two to
four times the value of the CPAR to be effective. The
power loss of the snubber circuit (PRSNUB) is dissipated in the resistor RSNUB and can be calculated as:
PRSNUB = CSNUB × (VIN ) × fS
2
where VGS~VIN.
______________________________________________________________________________________
13
MAX1954A
choose the high-side MOSFET (N1) that has conduction
losses equal to switching loss at nominal input voltage
and output current. The selected MOSFETs must have an
RDS(ON) that satisfies the current-limit setting condition
above. For N2, ensure that it does not spuriously turn on
due to dV/dt caused by N1 turning on, as this would
result in shoot-through current degrading the efficiency.
MOSFETs with a lower Qgd/Qgs ratio have higher immunity to dV/dt.
MAX1954A
Low-Cost, Current-Mode PWM Buck
Controller with Foldback Current Limit
where VIN is the input voltage and fS is the switching
frequency. Choose a RSNUB power rating that meets
the specific application’s derating rule for the power
dissipation calculated.
Input Capacitor
The input filter capacitor reduces peak currents drawn
from the power source and reduces noise and voltage
ripple on the input caused by the circuit’s switching.
The input capacitor must meet the ripple current
requirement (IRMS) imposed by the switching currents
defined by the following equation:
IRMS =
ILOAD ×
(
VOUT × VIN − VOUT
)
VIN
I RMS has a maximum value when the input voltage
equals twice the output voltage (VIN = 2 x VOUT); therefore, IRMS(MAX) = ILOAD / 2. Ceramic capacitors are
recommended due to their low equivalent series resistance (ESR) and equivalent series inductance (ESL) at
high frequencies, and their relatively low cost. Choose
a capacitor that exhibits less than 10°C temperature
rise at the maximum operating root-mean-square (RMS)
current for optimum long-term reliability.
Output Capacitor
The key selection parameters for the output capacitor
are the actual capacitance value, ESR, ESL, and the
voltage-rating requirements. These parameters affect
the overall stability, output voltage ripple, and transient
response. The output ripple has three components: variations in the charge stored in the output capacitor, and
the voltage drop across the capacitor’s ESR and ESL
caused by the current into and out of the capacitor. The
equation below estimates the maximum ripple voltage:
VRIPPLE = VRIPPLE(ESR) + VRIPPLE(C) + VRIPPLE(ESL)
The output voltage ripple as a consequence of the ESR,
output capacitance, and ESL are as follows:
VRIPPLE(ESR) = IP−P × ESR
VRIPPLE(C) =
IP−P
8 × COUT × fS
⎛V ⎞
VRIPPLE(ESL) = ⎜ IN ⎟ × ESL
⎝ L ⎠
⎛V − V
⎞
⎛V
⎞
OUT
OUT
IP−P = ⎜ IN
⎟ × ⎜
⎟
fS × L ⎠
⎝ VIN ⎠
⎝
14
where IP-P is the peak-to-peak inductor current (see the
Inductor Value section). These equations are suitable
for initial capacitor selection, but final values should be
chosen based on a prototype or evaluation circuit. As a
general rule, a smaller current ripple results in less output voltage ripple. Since the inductor ripple current is a
factor of the inductor value and input voltage, the output voltage ripple decreases with larger inductance,
and increases with higher input voltages. For the
MAX1954A polymer, tantalum, or aluminum electrolytic
capacitors are recommended. Lower-cost aluminum
electrolytic capacitors with relatively low ESR are available and can be used for the MAX1954A, if the larger
physical size is acceptable. For reliable and safe operation, ensure that the capacitor’s voltage and ripplecurrent ratings exceed the calculated values.
The devices’ response to a load transient depends on
the selected output capacitors. After a load transient,
the output voltage instantly changes by ESR x ∆ILOAD.
Before the controller can respond, the output voltage
deviates further depending on the inductor and output
capacitor values. After a short period of time (see the
Typical Operating Characteristics), the controller
responds by regulating the output voltage back to its
nominal state. The controller response time depends on
its closed-loop bandwidth. With a higher bandwidth, the
response time is faster, thus preventing the output voltage from deviating further from its regulation value.
Compensation Design
The MAX1954A uses an internal transconductance
error amplifier whose output compensates the control
loop. The external inductor, high-side MOSFET, output
capacitor, compensation resistor, and compensation
capacitors determine the loop stability. The inductor
and output capacitors are chosen based on performance, size, and cost. Additionally, the compensation
resistor and capacitors are selected to optimize controlloop stability. The component values in Figures 1 and 2
yield stable operation over the given range of input-tooutput voltages and load currents. The controller uses a
current-mode control scheme that regulates the output
voltage by forcing the required current through the
external inductor. The MAX1954A uses the voltage
across the high-side MOSFET’s on-resistance
(RDS(ON)) to sense the inductor current. Current-mode
control eliminates the double pole in the feedback loop
caused by the inductor and output capacitor, resulting
in a smaller phase shift and requiring less elaborate
error-amplifier compensation. A single-series compensation resistor (RC) and compensation capacitor (CC) is
all that is needed to have a stable high-bandwidth loop
in applications where ceramic capacitors are used for
______________________________________________________________________________________
Low-Cost, Current-Mode PWM Buck
Controller with Foldback Current Limit
GMOD = gmc ×
RLOAD × fS × L
RLOAD + fS × L
where RLOAD = VOUT / IOUT(MAX), and gmc = 1 / (ACS x
RDS(ON)), where ACS is the gain of the current-sense
amplifier and RDS(ON) is the on-resistance of the highside power MOSFET. ACS is 3.5. The frequencies at
which the pole and zero due to the power modulator
occur are determined as follows:
1
fpMOD =
⎛R
⎞
× fS × L
2π × COUT × ⎜ LOAD
+ RESR ⎟
⎝ RLOAD + fS × L
⎠
fzMOD =
1
2π × COUT × RESR
The feedback voltage-divider used has a gain of GFB =
VFB / VOUT, where VFB is equal to 0.8V. The transconductance error amplifier has DC gain, GEA(DC) = gm x
RO. The amplifier output resistance (RO) is typically
10MΩ. The CC, RO, and the RC set a dominant pole.
The RC and the CC set a zero. There is an optional pole
set by CF and RC to cancel the output-capacitor ESR
zero if it occurs before crossover frequency (fC):
fpdEA =
1
2 π × CC × (RO + RC )
1
fzEA =
2π × C C × R C
1
fpEA =
2π × C F × R C
The fC should be much higher than the power modulator pole fPMOD. Also, the crossover frequency should
be less than 1/8th of the switching frequency:
fpMOD
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