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Small, Single-/Multi-Cell Solar Harvester with
MPPT and Harvest Counter
MAX20361
General Description
Benefits and Features
The MAX20361 is a fully integrated solution for
harvesting energy from single-/multi-cell solar sources.
The device includes an ultra-low quiescent current
(360nA) boost converter that is capable of starting from
input voltages as low as 225mV (typ). In order to
maximize the power extracted from the source, the
MAX20361 implements a proprietary maximum power
point tracking (MPPT) technique that allows efficient
harvesting from 15μW to over 300mW of available input
power.
•
Single-/Multi-Cell Solar Energy Harvester
• 225mV to 2.5V (typ) Input-Voltage Range
• Efficient Harvesting from 15μW to Over 300mW
of Available Input Power
- 86% Efficiency at VSYS = 3.8V, ISRC = 30mA
• Small Solution Size
- Utilizes Small 2016 4.7μH Inductor
•
Maximum Power Point Tracking (MPPT) Technique
Using Fractional VOC Method
• Programmable Fractional VOC Regulation Point
through I2C Interface
•
Battery/Supercapacitor Charger
• Programmable Battery Termination Voltage
through I2C Interface
• Programmable Power Good Wake-Up Signal
Output Threshold through I2C Interface
The MAX20361 also features an integrated charging
and protection circuit that is optimized for Li-ion
batteries, but can also be used to charge
supercapacitors, thin-film batteries, or traditional
capacitors. The charger features a programmable
charging cut-off voltage with thresholds programmable
through I2C interface as well as temperature shutoff.
The MAX20361 is available in a 12-bump, 0.4mm pitch,
1.63mm x 1.23mm wafer-level package (WLP).
Ordering Information appears at end of data sheet
Applications
•
•
•
•
•
Wearable Fitness
Medical Devices
Industrial IoT Sensors
Asset Tracking Devices
Wireless Sensor Networks
19-100866; Rev 5; 8/23
© 2023 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.
MAX20361
Small, Single-/Multi-Cell Solar Harvester with
MPPT and Harvest Counter
Simplified Block Diagram
SRC
LX
MAX20361
CHARGE
PUMP
SYS
VBatReg
or
VSysReg
BOOST
CONTROLLER
VBatReChg
VCC
REF
INTERNAL
SUPPLY
MPPT
CONTROLLER
VWAKE
SDA
VTEMP
THM
LOW IQ
OSCILLATOR
WAKE
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SCL
DIGITAL LOGIC
AND I/O
EN
INT
GND
Analog Devices | 2
MAX20361
Small, Single-/Multi-Cell Solar Harvester with
MPPT and Harvest Counter
Absolute Maximum Ratings
SYS, VCC to GND ................................................ -0.3V to +6V
Continuous Current into any other Pin .......... -0.05A to +0.05A
SRC to GND ...................................................... -0.3V to +3.5V
INT, EN, SDA, SCL to GND.................................. -0.3V to +6V
Continuous Power Dissipation (Multilayer Board) (T A = +70oC,
derate 13.73mW/oC above +70oC) ......................... 1098.4mW
WAKE to GND ....................................... -0.3V to (SYS + 0.3V)
Operating Temperature Range ........................ -40oC to +85oC
REF, THM to GND.................................. -0.3V to (VCC + 0.3V)
Junction Temperature Range ......................... -40oC to +150oC
LX to GND .............................................. -0.3V to (VCC + 0.3V)
Storage Temperature Range ......................... -40oC to +150oC
Continuous Current into LX, GND or SYS ......... -0.5A to +0.5A
Soldering Temperature (reflow).................................... +260oC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress rati ngs only, and functional operation of the device at these or
any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolut e maximum rating conditions for extended periods may affect
device reliability.
Package Information
12-WLP
Package Code
W121C1+2
Outline Number
21-100426
Land Pattern Number
Refer to Application Note 1891
THERMAL RESISTANCE, FOUR LAYER BOARD
Junction-to-Ambient (θJA)
72.82oC/W
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51 -7, using a four-layer board.
For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
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Analog Devices | 3
MAX20361
Small, Single-/Multi-Cell Solar Harvester with
MPPT and Harvest Counter
Electrical Characteristics
(VSYS = +3.0V to +4.2V, VSRC = +0.3V to +2.5V, typical value is at VSYS = +3.8V, VSRC = +0.6V, TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SUPPLY
SYS Shutdown Supply
Current
SYS Sleep Supply
Current
SYS Idle Supply Current
ISYS_SHDN
DeviceEnb = 1, any VSRC
190
650
nA
ISYS_SLEEP
DeviceEnb = 0, VSRC = 0V
360
1200
nA
ISYS_IDLE
EN = 0V, boost not switching, not in sleep
mode
1.43
μA
VSYS_REG
50mV steps, programmable through I 2C
4 to 4.7
V
SYSTEM CONTROL (SYS)
System Termination
Voltage-Programmable
Range
System RegulationVoltage Accuracy
WAKE VoltageProgrammable Range
WAKE Voltage
Accuracy
WAKE Debounce Time
VSYS_REG_AC
C
VWAKE_RANG
E
TA = 0°C to +60°C
SysReg[3:0] = 7,
SYS rising
-1
100mV steps, programmable through I 2C
WakeThr[2:0] = 0,
SYS rising
VWAKE_ACC
+1
3 to 3.7
%
V
-2
+2
%
tWAKE_TDEB
7x
Tmeas
8x
Tmeas
ms
VSRC_RANGE
0
2.5
V
350
mV
BOOST REGULATOR
Input Operating Voltage
at SRC
Minimum Cold-Start
Voltage
Efficiency
VSC
BOOST_EFF
TA = 25°C (Note 3)
225
VSRC = 0.75V, VSYS = 3.8V,
ISRC = 100μA, L = 4.7μH, DFE201612E-
77
4R7M = P2 Series Inductor
VSRC = 0.75V, VSYS = 3.8V,
ISRC = 30mA, L = 4.7μH, DFE201612E-
%
86
4R7M = P2 Series Inductor
LX Low-Side On
Resistance
LX SYS High-Side On
Resistance
SRC LX Slow Snubber
Resistance
SRC LX Snubber
Resistance
Peak Current
RON_LXL
0.1
0.14
Ω
RON_LX_SYS
0.29
0.39
Ω
RLX_SSNUB
20
kΩ
RLX_SNUB
342
Ω
IBSTpk0
90
IBSTpk1
120
IBSTpk2
145
IBSTpk3
180
IBSTpk4
285
IBSTpk5
355
IBSTpk6
470
IBSTpk7
715
mA
SRC METER
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Analog Devices | 4
MAX20361
Small, Single-/Multi-Cell Solar Harvester with
MPPT and Harvest Counter
(VSYS = +3.0V to +4.2V, VSRC = +0.3V to +2.5V, typical value is at VSYS = +3.8V, VSRC = +0.6V, TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SRC DAC Full-Scale
VDACFS
SRC equivalent voltage
2.595
V
SRC Leakage
ILNKSRC
VSRC = 1V
0.75
μA
42.5 to
89.0
%
MAXIMUM POWER POINT TRACKING
Fractional Open Circuit
Voltage-Programmable
Range
VFRAC_VOC_P
1.5% steps, programmable through I 2C
VSRC = 0.6V,
Error of Fractional VOC
Regulation Point
VFRAC_VOC_E
RROR
includes
measurement error
of VOC and input
voltage regulation
error, excludes
SRC ripple (Note 3)
VOC[7:0] = 75,
Frac[4:0] = 25,
BSTpk = 3, ISRC =
-4.7
tFRAC_VOC
64 *
Tmeas
128 *
Tmeas
256 *
Tmeas
ATper = 0, Tper = 01, see text
ATper = 0, Tper = 10, see text
Open Circuit
Measurement Settling
Time
%
1mA
ATper = 0, Tper = 00, see text
Open Circuit
Measurement Period
+4.7
ATmeas = 0, Tmeas = 00, see text
50
tFRAC_VOC_S
ATmeas = 0, Tmeas = 01, see text
100
ETTLE
ATmeas = 0, Tmeas = 10, see text
250
ATmeas = 0, Tmeas = 11, see text
500
s
ms
EN
EN Input Threshold
EN Input Resistance
VILENB
VIHENB
1.0
RENB
0.7
1
0.4
V
1.3
MΩ
0.3
V
+1
μA
0.3
V
SCL, SDA, INT
SDA and INT OutputLow Voltage
SDA, SCL, INT Input
Current
VOLSDA,
VOLINT
ISDA, ISCL, IINT
I = 5mA
V_ from 0V to 5.5V
-1
0
WAKE
WAKE Output-Low
Voltage
WAKE Output-High
Voltage
VOLWAKE
I = 5mA
VOHWAKE
I = -5mA
SYS 0.3
V
THERMAL MONITORING (REF, THM)
REF Voltage
Cold Temperature TripPoint Programmable
Range
Hot Temperature TripPoint Programmable
Range
THM Input Leakage
VREF
IREF from 0μA to 100μA
1.15
1.2
1.25
V
VCOLD
53.5
57.5
60
%VREF
VHOT
16.2
18.7
22
%VREF
ITHM
-1
+1
μA
I2C INTERFACE
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Analog Devices | 5
MAX20361
Small, Single-/Multi-Cell Solar Harvester with
MPPT and Harvest Counter
(VSYS = +3.0V to +4.2V, VSRC = +0.3V to +2.5V, typical value is at VSYS = +3.8V, VSRC = +0.6V, TA = +25°C.) (Note 1)
PARAMETER
SCL and SDA Input
Threshold
SYMBOL
CONDITIONS
MIN
VIL
VIH
TYP
MAX
UNITS
0.4
V
1
I2C TIMINGS
Serial Operating
Frequency
fSCL
400
kHz
Maximum Clock Period
tSCLMAX
2.5
μs
START Condition Hold
Time
tHD:STA
0.6
μs
Clock Low Period
tLOW
1.3
μs
Clock High Period
tHIGH
0.6
μs
START Condition Setup
Time
Repeat START
Condition Setup Time
tSU:STA
0.6
μs
tSU:STA
0.6
μs
Data Hold Time
tHD:DAT
Data Valid to SCL Rise
Time
STOP Condition Setup
Time
Bus Free Time Between
STOP and START
Conditions
tSU:DAT
100
ns
tSU:STO
0.6
μs
tBUF
1.3
μs
0
ns
Note 1: All devices 100% productions tested at 25°C. Limits over the operating temperature range are guaranteed by design.
Note 2: All capacitance values listed in this document refer to effective capacitance. Be sure to specify capacitors that meets these
requirements under typical system operating conditions, taking into consideration the effects of voltage and temperature.
Note 3: Not production tested. Guaranteed by design.
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Analog Devices | 6
MAX20361
Small, Single-/Multi-Cell Solar Harvester with
MPPT and Harvest Counter
Typical Operating Characteristics
(TA = 25°C, unless otherwise noted.)
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Analog Devices | 7
MAX20361
Small, Single-/Multi-Cell Solar Harvester with
MPPT and Harvest Counter
(TA = 25°C, unless otherwise noted.)
www.analog.com
Analog Devices | 8
MAX20361
Small, Single-/Multi-Cell Solar Harvester with
MPPT and Harvest Counter
(TA = 25°C, unless otherwise noted.)
www.analog.com
Analog Devices | 9
MAX20361
Small, Single-/Multi-Cell Solar Harvester with
MPPT and Harvest Counter
(TA = 25°C, unless otherwise noted.)
www.analog.com
Analog Devices | 10
MAX20361
Small, Single-/Multi-Cell Solar Harvester with
MPPT and Harvest Counter
(TA = 25°C, unless otherwise noted.)
www.analog.com
Analog Devices | 11
MAX20361
Small, Single-/Multi-Cell Solar Harvester with
MPPT and Harvest Counter
Bump Configuration
TOP VIEW
(BUMP SIDE DOWN)
MAX20361
1
2
3
4
A
EN
WAKE
SDA
SCL
B
SRC
GND
INT
REF
C
LX
SYS
VCC
THM
WLP
(1.63mm x 1.23mm, 0.4mm PITCH)
Pin Descriptions
PIN
NAME
FUNCTION
Active Low Enable Input. When EN is high the device stops switching and enters a low power state. EN
is internally pulled down to GND by a 1MΩ resistor. In the shutdown state, I 2C is still operational.
Wake Signal for System MCU. This push-pull output is asserted when SYS is above WakeThr[2:0] and
the device is not in sleep mode.
A1
EN
A2
WAKE
A3
SDA
I2C Serial Data
A4
SCL
I2C Serial Clock
B1
SRC
Source Input. Connect the harvesting source power output to SRC. Connect a 10μF capacitor between
SRC and GND.
B2
GND
Ground
B3
INT
Open-Drain Interrupt Output
B4
REF
Internal-Voltage Reference
C1
LX
C2
SYS
C3
VCC
C4
THM
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Boost-Converter Switching Node. Connect a 4.7μH inductor between LX and the harvesting source
power output (e.g., anode of solar cell).
System Output. Connect to system input of power management IC. Connect a 1μF bypass capacitor
between SYS and GND.
Internal Supply. Connect a 1μF bypass capacitor between VCC and GND.
Thermistor Input. Connect THM to a voltage divider formed by a pullup resistor and a pulldown
thermistor.
Analog Devices | 12
MAX20361
Small, Single-/Multi-Cell Solar Harvester with
MPPT and Harvest Counter
Detailed Description
The MAX20361 is a fully integrated solution for harvesting energy from single-/multi-cell solar sources. The device
includes an ultra-low quiescent-current boost converter that is capable of starting from input voltage as low as 225mV
(typ). In order to maximize the power extracted from the source, the MAX20361 implements a proprietary maximum
power point tracking (MPPT) technique that allows efficient harvesting from 15μW to over 300mW of available input
power.
The MAX20361 also features an integrated charging and protection circuit that is optimized for Li-ion batteries, but can
also be used to charge supercapacitors, thin-film batteries, or traditional capacitors. The charger features a programmable
charging cut-off voltage with thresholds programmable through the I2C interface as well as temperature shutoff.
Boost Converter
The MAX20361 boost converter is optimized to efficiently harvest energy from a single-/multi-cell solar source. The
MAX20361 implements a boost converter, which collects the current from the low-voltage SRC input and transfers it to
the higher-voltage SYS output.
The switching frequency is not fixed but changes with the SRC voltage, SYS voltage and inductance values. Each time
the SRC voltage drops below its regulation point, the boost is halted. SRC capacitance is needed to reduce the SRC
ripple, but its value is not critical for stability (see the Applications Information section for more details).
The SYS voltage is monitored and when it reaches the regulation point, the boost is halted to avoid overcharging of the
the battery, or an overvoltage on the SYS node.
Harvesting Meter
The MAX20361 reports the count of the switching cycles of the boost converter during the last Tmeas[5:4](0x07) time in
the HarvCntH(0x0A) and HarvCntL(0x0B) registers. This “harvesting count” is proportional to the current harvested during
that period. To avoid a false read, the update of HarvCntH and HarvCntL is inhibited if the boost was halted in the last
Tmeas period due to thermal monitoring, open-circuit voltage measurement, SYS overvoltage detected, sleep mode or
I2C commands.
Every time a new valid value of HarvCntH/L is loaded, the HARrdy[4](0x01) bit is set.
Maximum Power Point Tracking (MPPT)
During normal operation, the MAX20361 automatically measures the open-circuit voltage and computes the optimal SRC
voltage to transfer the maximum power from the solar cell. Every Tper[1:0](0x07) (by default 64 x Tmeas, with Tmeas =
50ms, every 3.2s), or when requested by I2C, the internal boost is halted for Tmeas[5:4](0x07) and the SRC voltage is
measured with the internal 8-bit ADC.
The SRC regulation point is computed by multiplying the measured voltage at SRC by the Frac[4:0](0x06) field. At powerup, the MAX20361 regulates the SRC voltage at a level determined by the value of Frac[4:0] and the default value of
VOC[7:0]. (For example, if Frac[4:0] is set to 80% and the default value of VOC[7:0] is 29 decimal, the SRC regulation
voltage is 230mV typical, which is 80% of 290mV) until the first VOC measure or an I2C write on VOC[7:0] register is
performed. Refer to Figure 1 for the operation of VSRC during MPPT.
To adapt the SRC measurement time, if the ATmeas[3](0x07) bit is set, the MAX20361 modulates the measurement time
based on the last measured “harvesting count” (HarvCntH/L registers), as specified in Table 1 below.
Table 1. Measurement Time Based on Harvesting Count
HARVESTING COUNT VALUE
Less than 13
Between 13 and 26
Between 26 and 52
Above 52
USED MEASUREMENT TIME
2 x Tmeas
Tmeas
Tmeas / 2
Tmeas / 4
The MAX20361 automatically adapts the measurement period when the ATper[2](0x07) bit is set. After power-on reset,
the device ignores the first result of harvesting count and stores the second result in the HarvCntH and HarvCntL registers.
If any future harvesting count is greater or lower than the existing stored harvesting count by a factor of 2, the Tper timer
is reset and a new VOC measurement is forced immediately.
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Analog Devices | 13
MAX20361
Small, Single-/Multi-Cell Solar Harvester with
MPPT and Harvest Counter
A VOC measurement can be requested through the FrcMeas[7](0x07) bit. The measurement starts within Tmeas and
results are stored in the VOCMeas(0x09) register, and VOCrdy[3](0x01) bit is set with the corresponding interrupt.
VSRC
Tmeas OR ATmeas
Tmeas OR ATmeas
Tmeas OR ATmeas
VOC
VREGULATION
(VOC[7:0] x Frac[4:0])
Tper OR ATper
VINIT
(230mV)
Tper OR ATper
TIME
SWITCHING
SWITCHING
SWITCHING
SWITCHING
BOOST
ON/OFF
Figure 1. VSRC During Maximum Power Point Tracking
Low-Light Sleep Mode
To save power, the MAX20361 enters sleep mode when the harvesting meter value is below SlpThd[7:0](0x0C) threshold
(default 0x00) or when VOC[7:0] is set below the default VOC value by either the VOC measurement or a direct I2C write
to it. In sleep mode, the internal reference, the boost and the THM monitor are turned off, and SYS and THM are not
monitored, and WAKE output is forced low. The MAX20361 remains in sleep mode until the next VOC or THM
measurement, or a write to VOC[7:0] with a value equal or above the default VOC value. Low-power mode is inhibited
during cold startup.
WAKE Output
Except in Shutdown or Sleep modes, the MAX20361 monitors the SYS output. When SYS is above the WAKE threshold
for at least 7 to 8 x Tmeas (typ), the WAKE output is asserted (and the WAKEbSt[0](0x01) bit is set to 0). When the device
goes into Sleep or Shutdown mode, WAKE output is forced low. Refer to Figure 2 for the waveform of VSYS and WAKE
output.
VSYS
SysReg[3:0]
SysReChg[2:0]
WAKE THRESHOLD
(WakeThr[2:0])
TIME
SWITCHING
SWITCHING
SWITCHING
SWITCHING
BOOST
ON/OFF
WAKE OUTPUT
SysBatSel
Figure 2. Waveform of VSYS and WAKE Output
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Analog Devices | 14
MAX20361
Small, Single-/Multi-Cell Solar Harvester with
MPPT and Harvest Counter
Thermal Monitor
When ThmEn[3](0x08) is 1, the MAX20361 monitors the voltage on THM. The device checks V THM once if
FrcTHM[6](0x07) is 1 or periodically every Tper[1:0](0x07) time if THMper[6](0x05) is 1. During that process, the
MAX20361 drives REF to 1.2V (typ) for 1ms (typ). The voltage divider, formed by the pullup resistor from THM to REF
and the NTC thermistor from THM to ground, provides a voltage at THM proportional to the temperature as a fraction of
VREF. When VTHM is above 57.5% of VREF or below 18.7% of VREF, THMflag[6](0x01) is set and the boost is halted. These
thresholds are equivalent to 0°C and 45°C if a 10kΩ NTC thermistor with β = 3380 and a 22kΩ pullup resistor are used.
The device also performs a THM check at power-on and on the EN falling edge. A fault condition is assumed until this
first THM check is completed.
Shutdown
The device enters Shutdown mode when the EN pin is high or DeviceEnb[1](0x08) is 1. In this condition, current
consumption is minimized, SYS, THM and SRC are not monitored, WAKE output is forced low and the internal oscillator
is turned off. All internal logic, except those values under I2C, is held in reset. In the shutdown state, only the POR on
VCC is active, and the VCC-SYS switch is left open until VCC is above the POR threshold. The device exits Shutdown
mode when EN is low and DeviceEnb is 0.
Cold-Startup
The cold start feature of the MAX20361 allows the device to start up even if VSYS is below the wake threshold or absent.
For a cold startup, the device initially uses a low power charge pump to charge up V CC from the power source (such as
a solar cell) on SRC while SYS is not charged. Once VCC is charged above the POR level, the internal references are
enabled and the main boost takes over from the charge pump. As the main boost continues to charge, VCC and SYS gets
charged above the wake threshold, the VCC-SYS switch is closed and the device is powered from SYS. This completes
the cold startup, and the normal operation of the device assumes.
Source Clamp
By the DISintb[4](0x05) bit, the INT output can be reconfigured as a push-pull DISsrc output to drive an external clamp
circuit used to prevent overvoltage on SRC. The clamp circuit (see Figure 3) can be formed by an external nMOS and a
load resistor. When the clamp circuit is turned on, the SRC is discharged through the external load resistor. When the
boost converter is enabled, the DISsrc is driven to divert excess input current in order to let SRC regulate. In shutdown
mode, the DISsrc output is driven statically high. The DISsrc output is disabled during VOC measurement and sleep
mode. Refer to the nMOS Transistor Selection section.
SRC
CSRC
POWER
RESISTOR
INT (DISsrc)
10MΩ
Figure 3. Source Clamp Circuitry
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Analog Devices | 15
MAX20361
Small, Single-/Multi-Cell Solar Harvester with
MPPT and Harvest Counter
I2C Interface
The MAX20361 contains an I2C-compatible interface for data communication with a host controller (SCL and SDA). The
interface supports a clock frequency of up to 400kHz. SCL and SDA require pullup resistors that are connected to a
positive supply.
When writing to the MAX20361 using I2C, the master sends a START condition (S) followed by the MAX20361 I2C
address. After the address, the master sends the register address of the register that is to be programmed. The master
then ends communication by issuing a STOP condition (P) to relinquish control of the bus, or a REPEATED START
condition (Sr) to communicate to another I2C slave.
tSU:STA
tSU:STO
SDA
tSU:DAT
tLOW
SCL
tHD:STA
tR
tHD:STA
tBUF
tR
tHU:DAT
tHIGH
START
REPEATED START
STOP
START
Figure 4. I2C Interface Timing
S
Sr
P
SCL
SDA
Figure 5. I2C START, STOP, and REPEATED START Conditions
Slave Address
Set the Read/Write bit high to configure the MAX20361 to read mode (see Table 2). Set the Read/Write bit low to configure
the MAX20361 to write mode. The address is the first byte of information sent to the MAX20361 after the START condition.
Table 2. I2C Slave Addresses
ADDRESS FORMAT
7-Bit Slave ID
Write Address
Read Address
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HEX
0x15
0x2A
0x2B
BINARY
0010101
00101010
00101011
Analog Devices | 16
MAX20361
Small, Single-/Multi-Cell Solar Harvester with
MPPT and Harvest Counter
Bit Transfer
One data bit is transferred on the rising edge of each SCL clock cycle. The data on SDA must remain stable during the
high period of the SCL clock pulse. Changes in SDA while SCL is high and stable are considered control signals (see the
Start, Stop, And Repeated Start Conditions section). Both SDA and SCL remain high when the bus is not active.
Single-Byte Write
In this operation, the master sends an address and two data bytes to the slave device. The following procedure describes
the single byte write operation:
1.
2.
3.
4.
5.
6.
7.
8.
The master sends a START condition.
The master sends the 7-bit slave address plus a write bit (low).
The addressed slave asserts an ACK on the data line.
The master sends the 8-bit register address.
The slave asserts an ACK on the data line only if the address is valid (NAK if not).
The master sends 8 data bits.
The slave asserts an ACK on the data line.
The master generates a STOP condition.
WRITE SINGLE BYTE
S
DEVICE SLAVE ADDRESS - W A
8 DATA BITS
FROM MASTER TO SLAVE
A
REGISTER ADDRESS
A
P
FROM SLAVE TO MASTER
Figure 6. Write Byte Sequence
Burst Write
In this operation, the master sends an address and multiple data bytes to the slave device. The slave device automatically
increments the register address after each data byte is sent. The following procedure describes the burst write operation:
1.
2.
3.
4.
5.
6.
7.
8.
9.
The master sends a START condition.
The master sends the 7-bit slave address plus a write bit (low).
The addressed slave asserts an ACK on the data line.
The master sends the 8-bit register address.
The slave asserts an ACK on the data line only if the address is valid (NAK if not).
The master sends eight data bits.
The slave asserts an ACK on the data line.
Repeat 6 and 7 N-1 times.
The master generates a STOP condition.
BURST WRITE
S
DEVICE SLAVE ADDRESS - W A
8 DATA BITS - 1
FROM MASTER TO SLAVE
A
REGISTER ADDRESS
A
8 DATA BITS - 2
A
8 DATA BITS - N
A
P
FROM SLAVE TO MASTER
Figure 7. Burst Write Sequence
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Analog Devices | 17
MAX20361
Small, Single-/Multi-Cell Solar Harvester with
MPPT and Harvest Counter
Single Byte Read
In this operation, the master sends an address plus two data bytes and receives one data byte from the slave device. The
following procedure describes the single byte read operation:
1. The master sends a START condition.
2. The master sends the 7-bit slave address plus a write bit (low).
3. The addressed slave asserts an ACK on the data line.
4. The master sends the 8-bit register address.
5. The slave asserts an ACK on the data line only if the address is valid (NAK if not).
6. The master sends a REPEATED START condition.
7. The master sends the 7-bit slave address plus a read bit (high).bz
8. The addressed slave asserts an ACK on the data line.
9. The slave sends eight data bits.
10. The master asserts a NACK on the data line.
11. The master generates a STOP condition.
READ SINGLE BYTE
S
DEVICE SLAVE ADDRESS - W A
Sr
DEVICE SLAVE ADDRESS - R
FROM MASTER TO SLAVE
REGISTER ADDRESS
A
8 DATA BITS
NA
A
P
FROM SLAVE TO MASTER
Figure 8. Read Byte Sequence
Burst Read
In this operation, the master sends an address plus two data bytes and receives multiple data bytes from the slave device.
The following procedure describes the burst byte read operation:
1. The master sends a START condition.
2. The master sends the 7-bit slave address plus a write bit (low).
3. The addressed slave asserts an ACK on the data line.
4. The master sends the 8-bit register address.
5. The slave asserts an ACK on the data line only if the address is valid (NAK if not).
6. The master sends a REPEATED START condition.
7. The master sends the 7-bit slave address plus a read bit (high).
8. The slave asserts an ACK on the data line.
9. The slave sends eight data bits.
10. The master asserts an ACK on the data line.
11. Repeat 9 and 10 N-2 times.
12. The slave sends the last eight data bits.
13. The master asserts a NACK on the data line.
14. The master generates a STOP condition.
BURST READ
S
DEVICE SLAVE ADDRESS - W A
Sr
DEVICE SLAVE ADDRESS - R
8 DATA BITS - 2
FROM MASTER TO SLAVE
REGISTER ADDRESS
A
A
8 DATA BITS - 1
A
A
8 DATA BITS - 3
A
8 DATA BITS - N
NA
P
FROM SLAVE TO MASTER
Figure 9. Burst Read Sequence
www.analog.com
Analog Devices | 18
MAX20361
Small, Single-/Multi-Cell Solar Harvester with
MPPT and Harvest Counter
Acknowledge Bits
Data transfers are acknowledged with an acknowledge bit (ACK) or a not-acknowledge bit (NACK). Both the master and
the MAX20361 generate ACK bits. To generate an ACK, pull SDA low before the rising edge of the ninth clock pulse and
hold it low during the high period of the ninth clock pulse. To generate a NACK, leave SDA high before the rising edge of
the ninth clock pulse and leave it high for the duration of the ninth clock pulse. Monitoring for NACK bits allows for detection
of unsuccessful data transfers.
S
SCL
NOT ACKNOWLEDGE
SDA
ACKNOWLEDGE
Figure 10. Acknowledge Bits
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Analog Devices | 19
MAX20361
Small, Single-/Multi-Cell Solar Harvester with
MPPT and Harvest Counter
Register Map
MAX20361
ADDRESS
NAME
MSB
LSB
User Registers
0x00
DeviceID[7:0]
0x01
Status[7:0]
0x02
ChipID[3:0]
ChipRev[3:0]
VOCValid
THMflag
HSYSFlag
HARrdy
VOCrdy
Sleep
ENbStat
WAKEbSt
Int[7:0]
–
–
–
HARrdyInt
VOCrdyInt
VOCValidInt
EnbStatInt
WakebStInt
0x03
IntMsk[7:0]
–
–
–
HARrdyMsk
VOCrdyMsk
VOCValidMsk
EnbStatMsk
WakebStMsk
0x04
SysRegCfg[7:0]
0x05
WakeCfg[7:0]
VOCper
THMper
–
0x06
MpptCfg[7:0]
–
–
–
0x07
MeasCfg[7:0]
FrcMeas
FrcTHM
0x08
DevCntl[7:0]
–
0x09
VOCMeas[7:0]
VOC[7:0]
0x0A
HarvCntH[7:0]
HARhigh[7:0]
0x0B
HarvCntL[7:0]
HARlow[7:0]
0x0C
SleepThd[7:0]
SlpThd[7:0]
SysBatSel
SysReChg[2:0]
SysReg[3:0]
DISintb
–
WakeThr[2:0]
Frac[4:0]
Tmeas[1:0]
ATmeas
ATper
ThmEn
FrcWAKE
BSTpk[2:0]
Tper[1:0]
DeviceEnb
BoostEnb
Register Details
DeviceID (0x00)
BIT
7
6
5
4
3
2
1
Field
ChipID[3:0]
ChipRev[3:0]
Reset
0x1
0x1
Read Only
Read Only
Access Type
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0
Analog Devices | 20
MAX20361
Small, Single-/Multi-Cell Solar Harvester with
MPPT and Harvest Counter
BITFIELD
BITS
DESCRIPTION
ChipID
7:4
Chip Identification
ChipRev
3:0
Chip Revision
Status (0x01)
BIT
7
6
5
4
3
2
1
0
Field
VOCValid
THMflag
HSYSFlag
HARrdy
VOCrdy
Sleep
ENbStat
WAKEbSt
Reset
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Access Type
BITFIELD
BITS
DESCRIPTION
Indicates if at least one SRC open-circuit measurement was performed since the last
VCC POR event. This bit is also reset when a write to the VOCMeas register is
performed.This bit is not set after a VOC measurement.
VOCValid
7
0b0: No SRC open-circuit measurement was performed since the last V CC POR event.
0b1: At least one SRC open-circuit measurement was performed since the last V CC POR
event.
THM Fault Status
THMflag
6
0b0: No THM fault detected
0b1: THM fault detected during the last Tmeas period
SysReg Overvoltage Fault Flag
HSYSFlag
5
0b0: VSYS is not over VSYS_REG
0b1: VSYS is over VSYS_REG
Harvest Meter Status
HARrdy
4
0b0: Harvest meter has not been updated since the last read of HarvCnth/L register.
0b1: Harvest meter has been updated since the last read of HarvCnth/L register.
Note: this bit is reset when the HarvCntH register is read.
Open-Circuit Voltage Status
VOCrdy
3
0b0: No new open-circuit voltage measurement since the last read of VOCMeas
register.
0b1: New open-circuit voltage available since the last read of VOCMeas register.
Sleep
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2
Indicates if the Device is in Sleep Mode
Analog Devices | 21
MAX20361
Small, Single-/Multi-Cell Solar Harvester with
MPPT and Harvest Counter
BITFIELD
BITS
DESCRIPTION
0b0: Device is not in sleep mode and it is harvesting.
0b1: Device is in sleep mode to save SYS power (no harvesting).
Indicates if the Device is in Shutdown (or Between ENb Pin Input and DeviceEnb Bit)
ENbStat
1
0b0: ENb pin low and DeviceEnb bit set to 0.
0b1: ENb pin high or DeviceEnb bit set to 1.
Indicates the Status of the WAKE Pin Output
Only the SYS comparator; does not include the FrcWAKE).
WAKEbSt
This bit is not valid if the Sleep flag is set.
0
0b0: WAKE pin high (SYS above WakeThr[2:0](0x05) threshold)
0b1: WAKE pin low (SYS below WakeThr[2:0](0x05) threshold)
Int (0x02)
BIT
7
6
5
4
3
2
1
0
Field
–
–
–
HARrdyInt
VOCrdyInt
VOCValidInt
EnbStatInt
WakebStInt
Reset
–
–
–
0x0
0x0
0x0
0x0
0x0
Access Type
–
–
–
Read Clears
Read Clears
Read Clears
Read Clears
Read Clears
All
All
All
All
All
BITFIELD
BITS
DESCRIPTION
HARrdy Interrupt
HARrdyInt
4
0b0: No change in status of HARrdy
0b1: Change in status of HARrdy
VOCrdy Interrupt
VOCrdyInt
3
0b0: No change in status of VOCrdy
0b1: Change in status of VOCrdy
VOCValid Interrupt
VOCValidInt
2
0b0: No change in status of VOCValid
0b1: Change in status of VOCValid
EnbStat Interrupt
EnbStatInt
1
0b0: No change in status of EnbStat
0b1: Change in status of EnbStat
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Analog Devices | 22
MAX20361
Small, Single-/Multi-Cell Solar Harvester with
MPPT and Harvest Counter
BITFIELD
BITS
DESCRIPTION
WakebSt Interrupt
WakebStInt
0
0b0: No change in status of WakebSt
0b1: Change in status of WakebSt
IntMsk (0x03)
BIT
7
6
5
4
3
2
1
0
Field
–
–
–
HARrdyMsk
VOCrdyMsk
VOCValidMsk
EnbStatMsk
WakebStMsk
Reset
–
–
–
0x0
0x0
0x0
0x0
0x0
Access Type
–
–
–
Write, Read
Write, Read
Write, Read
Write, Read
Write, Read
1
0
BITFIELD
BITS
DESCRIPTION
HARrdyInt Interrupt Mask
HARrdyMsk
4
0b0: HARrdy interrupt not masked
0b1: HARrdy interrupt masked
VOCrdy Interrupt Mask
VOCrdyMsk
3
0b0: VOCrdy interrupt not masked
0b1: VOCrdy interrupt masked
VOCValid Interrupt Mask
VOCValidMsk
2
0b0: VOCValid interrupt not masked
0b1: VOCValid interrupt masked
EnbStat Interrupt Mask
EnbStatMsk
1
0b0: EnbStat interrupt not masked
0b1: EnbStat interrupt masked
WakebSt Interrupt Mask
WakebStMsk
0
0b0: WakebSt interrupt not masked
0b1: WakebSt interrupt masked
SysRegCfg (0x04)
BIT
Field
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7
SysBatSel
6
5
SysReChg[2:0]
4
3
2
SysReg[3:0]
Analog Devices | 23
MAX20361
Small, Single-/Multi-Cell Solar Harvester with
MPPT and Harvest Counter
Reset
Access Type
0x0
0x0
0x7
Write, Read
Write, Read
Write, Read
BITFIELD
BITS
DESCRIPTION
Selects Regulation Mode of SYS
SysBatSel
0b0: The boost attempts to regulate the SYS node at V SysReg.
7
0b1: The boost charges the SYS node until it reaches V SysReg and then switches off until
SYS drops to VSysReg - VSysReChg.
Battery Recharge Threshold Voltage
0b000: 25mV
0b001: 50mV
SysReChg
0b010: 75mV
6:4
0b011: 100mV
0b100: 150mV
0b101: 200mV
0b110: 250mV
0b111: 300mV
System Regulation or Battery Termination Voltage On the SYS Node
SysReg
0b0000: 4.0V
3:0
… linear step, 50mV
0b1111: 4.75V
WakeCfg (0x05)
BIT
7
6
5
4
3
Field
VOCper
THMper
–
DISintb
–
WakeThr[2:0]
Reset
0x1
0x0
–
0x0
–
0x7
Write, Read
Write, Read
–
Write, Read
–
Write, Read
Access Type
BITFIELD
BITS
2
1
0
DESCRIPTION
VOC Every Tper (Perform Open Circuit Measurement Every Tper Period)
VOCper
7
0b0: VOC measurement performed only on request
0b1: VOC measurement performed every "Tper" time
Note: this bit also disables the first VOC measurement after POR.
THMper
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6
Thermal Monitor Every Tper
Analog Devices | 24
MAX20361
Small, Single-/Multi-Cell Solar Harvester with
MPPT and Harvest Counter
BITFIELD
BITS
DESCRIPTION
0b0: Thermal monitoring is not performed every Tper time.
0b1: Thermal monitoring is performed every Tper time (only if also ThmEn is set).
Disable the INTb Pin and Convert It Into a Push-Pull Output to Discharge SRC (Clamp
SRC Voltage)
DISintb
4
0b0: INTb is an open-drain output for interrupt.
0b1: INTb becomes a DISsrc push-pull output (to VCC). When high, discharge SRC
through a resistor.
Wake Threshold. When BAT reaches this voltage, the device asserts the WAKE output.
0b000: 3.0V
0b001: 3.1V
WakeThr
0b010: 3.2V
2:0
0b011: 3.3V
0b100: 3.4V
0b101: 3.5V
0b110: 3.6V
0b111: 3.7V
MpptCfg (0x06)
BIT
7
6
5
Field
–
–
–
Frac[4:0]
Reset
–
–
–
0x19
Access Type
–
–
–
Write, Read
BITFIELD
4
3
BITS
2
1
0
DESCRIPTION
Set the Fraction of the Open-Circuit Voltage to which the Boost Converter Attempts to
Regulate at VSRC.
Frac
4:0
0b00000: 42.5%
…Linear scale, 1.5% / LSB
0b11111: 89.0%
MeasCfg (0x07)
BIT
7
6
Field
FrcMeas
FrcTHM
Reset
0x0
0x0
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5
4
3
2
1
0
Tmeas[1:0]
ATmeas
ATper
Tper[1:0]
0x0
0x1
0x1
0x2
Analog Devices | 25
MAX20361
Access Type
Small, Single-/Multi-Cell Solar Harvester with
MPPT and Harvest Counter
Write Only
Write Only
Clears All
Clears All
BITFIELD
Write, Read
Write, Read
BITS
Write, Read
Write, Read
DESCRIPTION
Writing 1 to this bit forces a measure of an open-circuit voltage measurement (if
NoVOCMeas is 0) at SRC. This bit is automatically forced to 0.
FrcMeas
7
The measurement algorithm and time for VOC at SRC is set by ATmeas and Tmeas
bits.
Until FrcMeas is set, the VOC register should not be written.
FrcTHM
Writing 1 to this bit forces a measure of thermal monitoring (only if ThmEn bit is 1). This
6
bit is automatically forced to 0.
Set the Measurement Time
Tmeas
0b00: 50ms
5:4
0b01: 100ms
0b10: 250ms
0b11: 500ms
Set the Algorithm Used to Adjust the Settling Time for VOC Measure
ATmeas
0b0: The settling time is fixed and set by Tmeas bits.
3
0b1: Adaptative measuring time based on the current HarvCnt value, from Tmeas / 4 to
2 x Tmeas.
Adaptative Period (Valid Only If Tper < 0b11)
0b0: Disabled
ATper
2
0b1: Store HarvCntH/L after 2 x Tmeas (or more, see text). A measure is forced (if not in
sleep) when the future harvesting value is greater or lower than the existing stored
measurement by a factor of 2 (future HarvCnt/current HarvCnt < 0.5 or future
HarvCnt/current HarvCnt > 2).
Set the Period of Automatic Measurement
0b00: 64 x Tmeas
0b01: 128 x Tmeas
Tper
1:0
0b10: 256 x Tmeas
0b11: Disabled
When “Disabled”, VOC and THM are never automatically read. The system should
periodically use the FrcMeas and FrcTHM bit to force measurements.
DevCntl (0x08)
BIT
Field
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7
–
6
5
BSTpk[2:0]
4
3
2
1
0
ThmEn
FrcWAKE
DeviceEnb
BoostEnb
Analog Devices | 26
MAX20361
Small, Single-/Multi-Cell Solar Harvester with
MPPT and Harvest Counter
Reset
–
0x3
0x0
0x0
0x0
0x0
Access Type
–
Write, Read
Write, Read
Write, Read
Write, Read
Write, Read
BITFIELD
BITS
DESCRIPTION
Select the Peak Current for The Boost Converter
0b000: 90mA
0b001: 120mA
BSTpk
0b010: 145mA
6:4
0b011: 180mA
0b100: 285mA
0b101: 355mA
0b110: 470mA
0b111: 715mA
Thermal Monitoring Enable Bit
0b0: Thermal monitoring is not enabled, and temperature does not affect boost
ThmEn
operation.
3
0b1: Thermal monitoring is enabled. The thermal monitoring circuit on every Tper
period (if THMper is set) or when FrcTHM is set, and if necessary, turns off the boost
converter to halt charging of the battery.
I2C Control of The WAKE Output
FrcWAKE
2
0b0: WAKE output is controlled by the WAKE comparator.
0b1: WAKE output is high regardless of the status of the WAKE comparator.
I2C Control of Device Enable
DeviceEnb
1
0b0: Device enable is controlled by the ENb pin.
0b1: Device disabled regardless of the status of the ENb pin.
I2C Enable of the Boost Converter
BoostEnb
0
0b0: Boost converter is controlled by the internal digital logic.
0b1: Boost converter is disabled regardless of the internal digital logic.
VOCMeas (0x09)
BIT
7
6
5
4
3
Field
VOC[7:0]
Reset
0x1D
Access Type
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2
1
0
Write, Read
Analog Devices | 27
MAX20361
Small, Single-/Multi-Cell Solar Harvester with
MPPT and Harvest Counter
BITFIELD
BITS
DESCRIPTION
Most Recent Result of Open-Circuit Voltage Measurement at SRC. This value can be
read anytime without triggering the FrcMeas bit.
0: 0V
…
255: 2.55V
VOC
7:0
This register can be written to override the VOC measure.
Every time the VOC register is updated to value below the default VOC value (either by
VOC measurement or by I 2C writing), the boost is halted and sleep mode is entered to
save power, until the next VOC measurement (upon Tper or FrcVOC) or until VOC is
written to a higher value.
The VOC register should not be written to when FrcMeas is set.
HarvCntH (0x0A)
BIT
7
6
5
4
3
Field
HARhigh[7:0]
Reset
0x0
Access Type
2
1
0
Read Only
BITFIELD
BITS
DESCRIPTION
Return the Number of “LX Pulses” of the Boost, the only 8 MSBits of Counter.
This number is valid only when SYS is above the WAKE threshold. This number is
HARhigh
7:0
proportional to the SYS “charging” current.
When the counter overflows, it returns to 0xFFFF.
Note: the HarvCnt is not updated when the device is in sleep mode.
HarvCntL (0x0B)
BIT
7
6
5
4
3
Field
HARlow[7:0]
Reset
0x0
Access Type
BITFIELD
HARlow
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2
1
0
Read Only
BITS
7:0
DESCRIPTION
Return the Number of “LX Pulses” of the Boost, the only 8 LSBs of the Counter.
This number is valid only when SYS is above WAKE threshold. This number is
Analog Devices | 28
MAX20361
Small, Single-/Multi-Cell Solar Harvester with
MPPT and Harvest Counter
BITFIELD
BITS
DESCRIPTION
proportional to the SYS “charging” current.
When the counter overflows, it returns to 0xFFFF.
SleepThd (0x0C)
BIT
7
6
5
4
3
Field
SlpThd[7:0]
Reset
0x0
Access Type
BITFIELD
2
1
0
Write, Read
BITS
DESCRIPTION
The “Harvesting Count” Threshold to Enter Sleep Mode Until the Next VOC Measure.
SlpThd
7:0
This value is compared with the HarvCnt (the bits returned in registers HarvCntH/L).
This feature is ignored if SlpThd = 0.
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Analog Devices | 29
MAX20361
Small, Single-/Multi-Cell Solar Harvester with
MPPT and Harvest Counter
Applications Information
Inductor Selection
The operation of the boost regulator requires a properly sized inductor with the appropriate value. The inductor must be
connected between SRC (pin B1) and LX (pin C1). The boost regulator performance, such as efficiency, is optimized to
control the switching behavior with a nominal inductance of 4.7µH ± 20%. The inductor must have low series resistance
(DCR) to minimize loss and maintain high efficiency. The recommended inductance range is between 4.7µH and 22µH.
Refer to Table 3 for a list of recommended inductors.
Table 3. Boost Regulator Inductor Recommendation
INDUCTANCE (µH)
DIMENSIONS (mm)
PART NUMBER
MANUFACTURER
4.7
2 x 1.6 x 1.2
DFE201612E-4R7M=P2
Murata
4.7
2.5 x 2 x 1
DFE252010F-4R7M=P2
Murata
4.7
4.8 x 4.8 x 3
744043004
Wurth
15
3.8 x 3.8 x 1.8
744031150
Wurth
22
7.3 x 7.3 x 4.5
7447779122
Wurth
Capacitor Selection
All selected capacitors need to have low leakage. Any leakage from capacitors contributes to the loss of efficiency,
increases the quiescent current, and reduces the effectiveness of the energy harvesting process. The capacitance
specified in the data sheet refers to the effective capacitance after accounting for the voltage derating. Small ceramic
capacitors tend to lose effective capacitance very quickly as DC bias is increased. Ensure that DC degradation would not
affect the effective capacitance of bypass capacitors located at VCC, SRC, and SYS.
SRC Capacitance
The capacitor connected to pin SRC (CSRC) is used to initially store energy from the harvesting input source. The output
capacitance of the input energy source determines the value of the SRC capacitor. A minimum effective capacitance of
10µF is recommended. Larger capacitance (22µF) is recommended for 10µH and 22µH inductances.
SYS and VCC Capacitance
Connect a bypass capacitor to the system output (CSYS) of the MAX20361. This capacitor needs to have low equivalent
series resistance (ESR). An effective capacitance of 1µF is recommended.
nMOS Transistor Selection
See Table 4 for a list of recommended nMOS transistors used for the source clamp circuitry. The gate to source threshold
voltage and drive voltage must be lower than 2V for this application.
Table 4. nMOS Transistor Recommendation
MANUFACTURER
PART NUMBER
DRAIN-TOSOURCE
VOLTAGE (V)
CONTINUOUSDRAIN CURRENT
(A)
GATE-TO-SOURCE
VOLTAGE
THRESHOLD (V)
DRIVE
VOLTAGE (V)
Diodes Incorporated
DMN2230U-7
20
2
1
1.8
ON Semiconductor
FDMA410NZ
20
9.5
1
1.5
Diodes Incorporated
DMC1028UVT-7
12
6.1
1
1.8
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Analog Devices | 30
MAX20361
Small, Single-/Multi-Cell Solar Harvester with
MPPT and Harvest Counter
Typical Application Circuits
Solar Application Circuit
4.7µH
*
SRC
LX
10µF
MAX20361
SYS
1µF
SOURCE CLAMP
SRC
VBatReg
or
VSysReg
POWER
RESISTOR
CHARGE
PUMP
(DISsrc)
INT
BOOST
CONTROLLER
10MΩ
VBatReChg
VCC
INTERNAL
SUPPLY
1µF
REF
MPPT
CONTROLLER
VWAKE
SDA
VTEMP
THM
LOW IQ
OSCILLATOR
SCL
DIGITAL LOGIC
AND I/O
INT
NTC
WAKE
EN
GND
* ONE OR MORE SOLAR CELLS
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Analog Devices | 31
MAX20361
Small, Single-/Multi-Cell Solar Harvester with
MPPT and Harvest Counter
Register Bit Default Values
Table 5 shows the default settings for different versions. These default values are OTP programmable. Some bits can be
changed through the I2C interface after power-up, while some bits are set through OTP.
Table 5. Device Default Settings
REGISTER BITS
SysBatSel
SysReChg [2:0]
SysReg [3:0]
BSTpk0[2:0]
ThmEn
WakeThr [2:0]
Frac [4:0]
VOCper
THMper
Tmeas[1:0]
ATmeas
ATper
Tper [1:0]
VOC [7:0]
SlpThd [7:0]
MAX20361A
0
25mV
4.35V
3
Disabled
3.7V
80.0%
Enabled
Disabled
50ms
1
Enabled
0b10
0.29V
0V
MAX20361B
0
25mV
4.1V
3
Enabled
3.1V
80.0%
Enabled
Enabled
50ms
1
Enabled
0b10
0V
0V
MAX20361C
0
25mV
4.1V
3
Disabled
3.7V
80.0%
Enabled
Disabled
50ms
1
Enabled
0b10
0.29V
0V
MAX20361D
0
25mV
4.1V
3
Enabled
3.1V
80.0%
Enabled
Enabled
50ms
1
Enabled
0b10
0.05V
0V
Register Default Values
Table 6 shows the default values of all the registers.
Table 6. I2C Direct Register Defaults
REGISTER
ADDRESS
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
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REGISTER
NAME
DeviceID
Status
Int
IntMsk
SysRegCfg
WakeCfg
MpptCfg
MeasCfg
DevCntl
VOCMeas
HarvCntH
HarvCntL
SleepThd
MAX20361A
MAX20361B
MAX20361C
MAX20361D
0x11
0x00
0x00
0x00
0x07
0x87
0x19
0x0E
0x30
0x1D
0x00
0x00
0x00
0x11
0x00
0x00
0x00
0x02
0xC1
0x19
0x0E
0x38
0x00
0x00
0x00
0x00
0x11
0x00
0x00
0x00
0x02
0x87
0x19
0x0E
0x30
0x1D
0x00
0x00
0x00
0x11
0x00
0x00
0x00
0x02
0xC1
0x19
0x0E
0x38
0x05
0x00
0x00
0x00
Analog Devices | 32
MAX20361
Small, Single-/Multi-Cell Solar Harvester with
MPPT and Harvest Counter
Ordering Information
PART NUMBER
TEMP RANGE
PIN-PACKAGE
MAX20361AEWC+
-40°C to +85°C
12 WLP
MAX20361AEWC+T
-40°C to +85°C
12 WLP
MAX20361BEWC+
-40°C to +85°C
12 WLP
MAX20361BEWC+T
-40°C to +85°C
12 WLP
MAX20361CEWC+
-40°C to +85°C
12 WLP
MAX20361CEWC+T
-40°C to +85°C
12 WLP
MAX20361DEWC+
-40°C to +85°C
12 WLP
MAX20361DEWC+T
-40°C to +85°C
12 WLP
+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
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Analog Devices | 33
MAX20361
Small, Single-/Multi-Cell Solar Harvester with
MPPT and Harvest Counter
Revision History
REVISION
NUMBER
0
1
2
3
4
5
REVISION
DESCRIPTION
DATE
9/20
Release for Market Intro
Updated the General Description, Benefits and Features, Electrical Characteristics, and
9/20
Detailed Description
Added Table 5 and Table 6. Added MAX20361BEWC+ and MAX20361BEWC+T in
12/22
Ordering Information
Updated Maximum Power Point Tracking section, Low-Light Sleep Mode section, and
3/23
VOC register. Added MAX20361CEWC+ and MAX20361CEWC+T in Table 5 and Table
6 and Ordering Information.
5/23
Updated HSYSFlag description in Register Map.
Added MAX20361DEWC+ and MAX20361DEWC+T in Table 5, Table 6, and Ordering
8/23
Information.
PAGES
CHANGED
—
1, 4, 13
31, 32
13, 14, 28, 32,
33
21
32,33
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is
assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may
result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their
respective owners.
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Analog Devices | 34
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