MAX21000+TWCHS

MAX21000 USER GUIDE Revision 2.6, May 2015 MAX21000 User Guide ©2015 Maxim Integrated Products, Inc. All rights reserved. No part of this documentation may be reproduced nor distributed in any form or by any means, graphic, electronic, or mechanical, including but not limited to photocopying, scanning, recording, taping, e-mailing, or storing in information storage and retrieval systems without the written permission of Maxim Integrated Products, Inc. (hereafter, “Maxim”). Products that are referenced in this document such as Microsoft Windows® may be trademarks and/or registered trademarks of their respective owners. Maxim makes no claim to these trademarks. While every precaution has been taken in the preparation of this document, individually, as a series, in whole, or in part, Maxim, the publisher, and the author assume no responsibility for errors or omissions, including any damages resulting from the express or implied application of information contained in this document or from the use of products, services, or programs that may accompany it. In no event shall Maxim, publishers, authors, or editors of this guide be liable for any loss of profit or any other commercial damage caused or alleged to have been caused directly or indirectly by this document. Rev. 2.6, May 2015 MAX21000 User Guide CONTENTS 1 Revision History ...............................................................................................................................7 2 Introduction.....................................................................................................................................8 3 Nomenclature ..................................................................................................................................9 4 MAX21000 Description ..................................................................................................................10 5 Pin Description ..............................................................................................................................11 6 I C Interface ...................................................................................................................................12 2 2 6.1 6.2 6.3 6.4 6.5 6.5.1 6.5.2 6.5.3 6.5.4 7 I C Protocol ......................................................................................................................................13 Slave Address ...................................................................................................................................13 Acknowledge ...................................................................................................................................13 Register Address ..............................................................................................................................14 2 I C Operations..................................................................................................................................14 Write One Byte .............................................................................................................................14 Write a Burst of Data ....................................................................................................................14 Read One Byte ..............................................................................................................................15 Read a Burst of Data ....................................................................................................................15 SPI Interface...................................................................................................................................17 7.1 7.2 8 SPI Protocol .....................................................................................................................................17 Register Address ..............................................................................................................................18 Interrupts ......................................................................................................................................20 8.1 8.2 8.3 9 Interrupt Flags .................................................................................................................................20 Interrupt Lines .................................................................................................................................20 Rate Interrupts ................................................................................................................................20 Reading Data from MAX21000 and FIFO Operation .......................................................................22 9.1 9.2 9.3 9.3.1 9.3.2 9.3.3 9.3.4 9.4 10 Synchronous Reading ......................................................................................................................22 Asynchronous Reading ....................................................................................................................22 FIFO Modes Description ..................................................................................................................22 FIFO OFF Mode .............................................................................................................................22 Normal Mode ...............................................................................................................................22 Interrupt Mode .............................................................................................................................24 Snapshot Mode.............................................................................................................................27 Example of FIFO Read/Write Pointers Evolution .............................................................................27 Programming Example ...................................................................................................................29 10.1 10.2 10.3 11 Simple Read-Out Sequence, No FIFO, No Interrupts .......................................................................30 Simple Read-Out Sequence, FIFO Normal Mode, No Interrupts .....................................................31 Simple Read-Out Sequence, Normal Mode, Data-Ready Interrupts ...............................................32 DSYNC ............................................................................................................................................ 33 11.1 11.1.1 11.2 11.2.1 11.3 Power Mode Switching Using DSYNC ..............................................................................................33 Example Register Settings for Power Mode Switching .................................................................33 Filling FIFO with DSYNC Edge ...........................................................................................................33 Example Register Settings for FIFO Filling with DSYNC .................................................................34 Map DSYNC on LSb ..........................................................................................................................34 Rev. 2.6, May 2015 Maxim Integrated 3 MAX21000 User Guide 11.3.1 11.4 12 Example Register Settings for Mapping DSYNC level on LSB ........................................................34 Example of DSYNC Application: Generation of Non-Standard ODR ................................................35 Register Map .................................................................................................................................36 12.1 COMMON BANK ..............................................................................................................................36 12.1.1 WHO_AM_I ..................................................................................................................................37 12.1.2 BANK_SELECT ...............................................................................................................................37 12.1.3 SYSTEM_STATUS ...........................................................................................................................38 12.1.4 GYRO_X_H ....................................................................................................................................38 12.1.5 GYRO_X_L .....................................................................................................................................39 12.1.6 GYRO_Y_H ....................................................................................................................................39 12.1.7 GYRO_Y_L .....................................................................................................................................39 12.1.8 GYRO_Z_H ....................................................................................................................................40 12.1.9 GYRO_Z_L .....................................................................................................................................40 12.1.10 TEMP_H ........................................................................................................................................40 12.1.11 TEMP_L .........................................................................................................................................41 12.1.12 HP_RST .........................................................................................................................................41 12.1.13 FIFO_COUNT .................................................................................................................................41 12.1.14 FIFO_STATUS .................................................................................................................................42 12.1.15 FIFO_DATA ....................................................................................................................................43 12.1.16 PAR_RST........................................................................................................................................43 12.2 USER BANK #0 (bank_sel = 0000) ....................................................................................................44 12.2.1 POWER_CFG .................................................................................................................................45 12.2.2 SENSE_CFG1 .................................................................................................................................46 12.2.3 SENSE_CFG2 .................................................................................................................................47 12.2.4 SENSE_CFG3 .................................................................................................................................47 12.2.5 DR_CFG .........................................................................................................................................48 12.2.6 IO_CFG ..........................................................................................................................................49 12.2.7 I2C_CFG ........................................................................................................................................49 12.2.8 ITF_OTP ........................................................................................................................................50 12.2.9 FIFO_TH ........................................................................................................................................50 12.2.10 FIFO_CFG ......................................................................................................................................51 12.2.11 DSYNC_CFG...................................................................................................................................52 12.2.12 DSYNC_CNT ..................................................................................................................................52 12.3 USER BANK #1 (bank_sel = 0001) ....................................................................................................53 12.3.1 INT_REF_X ....................................................................................................................................54 12.3.2 INT_REF_Y ....................................................................................................................................54 12.3.3 INT_REF_Z ....................................................................................................................................54 12.3.4 INT_DEB_X....................................................................................................................................55 12.3.5 INT_DEB_Y ....................................................................................................................................55 12.3.6 INT_DEB_Z ....................................................................................................................................56 12.3.7 INT_MSK_X ...................................................................................................................................56 12.3.8 INT_MSK_Y ...................................................................................................................................57 12.3.9 INT_MSK_Z ...................................................................................................................................58 12.3.10 INT_MSK_AO ................................................................................................................................58 12.3.11 INT_CFG1 ......................................................................................................................................59 12.3.12 INT_CFG2 ......................................................................................................................................59 12.3.13 INT_TMO ......................................................................................................................................60 12.3.14 INT_STS_UL ..................................................................................................................................61 Rev. 2.6, May 2015 Maxim Integrated 4 MAX21000 User Guide 12.3.15 12.3.16 12.3.17 12.3.18 12.3.19 12.3.20 12.3.21 13 INT1_STS .......................................................................................................................................61 INT2_STS .......................................................................................................................................62 INT1_MSK .....................................................................................................................................62 INT2_MSK .....................................................................................................................................63 OTP_STATUS..................................................................................................................................63 SILICON_REV_OTP ........................................................................................................................64 SERIAL_[0:5] .................................................................................................................................64 Definitions .....................................................................................................................................65 TABLES Table 1: Pin Description .................................................................................................................................11 2 Table 2: I C External Component Properties..................................................................................................12 2 Table 3: I C Device Addresses ........................................................................................................................13 Table 4: SPI External Component Properties .................................................................................................17 Table 5: Register Settings for Switching Power Mode....................................................................................33 Table 6: Register Settings for FIFO Filling with DSYNC ...................................................................................34 Table 7: Register Settings for Mapping LSB ....................................................................................................34 Table 8: Common Bank ..................................................................................................................................36 Table 9: User Bank 0 ......................................................................................................................................44 Table 10: Power Mode Configuration ............................................................................................................45 Table 11: Bandwidth Configuration ...............................................................................................................46 Table 12: HPF Cut-Off Frequencies ................................................................................................................48 Table 13: User Bank 1 ....................................................................................................................................53 FIGURES Figure 1: Block Diagram .................................................................................................................................10 2 Figure 2: I C Interface Connection to an Application Processor ....................................................................12 Figure 3: START (S), STOP (P), and Repeated START (Sr) Conditions ..............................................................13 2 Figure 4: I C Write One Byte ..........................................................................................................................14 2 Figure 5: I C Write a Burst of Data .................................................................................................................15 2 Figure 6: I C Read One Byte ...........................................................................................................................15 2 Figure 7: I C Read a Burst of Data ..................................................................................................................16 Figure 8: SPI Interface Connection to an Application Processor ....................................................................17 Figure 9: SPI Protocol .....................................................................................................................................18 Figure 10: Conditional Ranges .......................................................................................................................21 Figure 11: FIFO Normal Mode, Stop on Full...................................................................................................23 Figure 12: FIFO Normal Mode, Overwrite .....................................................................................................24 Figure 13: FIFO Interrupt Mode, Stop on Full ................................................................................................25 Figure 14: FIFO Interrupt Mode, Overwrite ...................................................................................................26 Figure 15: FIFO Snapshot Mode.....................................................................................................................27 Rev. 2.6, May 2015 Maxim Integrated 5 MAX21000 User Guide Figure 16: FIFO Read/Write Pointer Evolution ...............................................................................................28 Figure 17: Simple Read-Out Sequence, No FIFO, No Interrupts ....................................................................30 Figure 18: Simple Read-Out Sequence, FIFO Normal, No Interrupts .............................................................31 Figure 19: Simple Read-Out Sequence, Normal Mode, w/Data Ready Interrupts and No FIFO ....................32 Figure 20: Timing Diagram to Generate a Nonstandard ODR ........................................................................35 Figure 21: FIFO Flags ......................................................................................................................................42 Rev. 2.6, May 2015 Maxim Integrated 6 MAX21000 User Guide Chapter 1: Revision History 1 Revision History Date Revision 1.0 2.0 2.1 2.2 2.3 12/12/2012 3/4/2015 3/5/2015 3/6/2015 3/6/2015 2.4 4/13/2015 2.5 05/01/2015 2.6 05/18/2015 Rev. 2.6, May 2015 Description Inital Release Initial release with new format First review with new format Misspellings and mis-references are fixed Registers are renamed DSYNC section is added Bit fields are updated Detailed endian information is included Detailed if_parity information is included Added new programming examples Re-formatting Typos and mis-references fixed Updated register definitions Re-formatting Fixed broken links Fixed register fields name Review for errors Maxim Integrated 7 MAX21000 User Guide Chapter 2: Introduction 2 Introduction MEMS sensors are revolutionizing the way people interact with everyday technology, making it easier and more user-friendly. Maxim can leverage its analog integration expertise to develop and manufacture new breakthrough MEMS sensors being smaller, lower power and more accurate than ever. Owning the entire supply chain, Maxim brings its customers complete, reliable and cost-effective solutions, ensuring prompt time-to-volume and time-to-market to effectively address high-volume applications in consumer and industrial market segments. Thanks to its leadership in analog integration and its manufacturing experience in MEMS, Maxim is capable of high-volume production to meet the market's demands. Maxim’s manufacturing expertise and highest quality standards also guarantee high performance and product reliability. Every MEMS sensor is tested and trimmed in factory so that for most consumer applications, no additional sensor calibrations are required. The end user can quickly verify the sensor’s operation without physically tilting or rotating the sensor thanks to the built-in self-test feature, which allows accelerating the time-to-market for mass production. This User Guide will provide a clear picture of the guidelines for its use in consumer applications and a comprehensive description of his unique features. The final section of this guide will present the structure of the register file, the purpose of each field or every register, including two examples about typical programming sequences. Rev. 2.6, May 2015 Maxim Integrated 8 MAX21000 User Guide Chapter 3: Nomenclature 3 Nomenclature ODR Output Data Rate BW Bandwidth FS Fulllscale UI User Interface OIS Optical Image Stabilization MSB Most Significant Bit or Byte LSB Least Significant Bit or Byte HPF Highpass Filter LPF Lowpass Filter dps Degrees per seconds RFU Reserved for future uses Rev. 2.6, May 2015 Maxim Integrated 9 MAX21000 User Guide Chapter 4: MAX21000 Description 4 MAX21000 Description The MAX21000 is a low-power, low-noise, three-axis angular rate sensor able to offer unprecedented accuracy and sensitivity over temperature and time. It is capable of working with a supply voltage as low as 1.71V for minimum power consumption. It includes a sensing element and an IC interface capable of providing the measured angular rate to the external world 2 (I C/SPI). The MAX21000 has a configurable full scale of ±31.25/±62.5/±125/±250/±500/±1000/±2000dps and is capable of measuring rates with a finely tunable user-selectable bandwidth. The high output data rate (ODR) and the large bandwidth (BW), together with the low phase delay, make the MAX21000 suitable for both user interface (UI) and optical image stabilization (OIS) applications. The MAX21000 is a highly integrated solution requiring only two external capacitors, available in a compact 3mm x 3mm x 0.9mm plastic land grid array (LGA) package and can operate within a temperature range of -40°C to +85°C. Figure 1: Block Diagram Rev. 2.6, May 2015 Maxim Integrated 10 MAX21000 User Guide Chapter 5: Pin Description 5 Pin Description Table 1: Pin Description PIN NAME FUNCTION 1 VDDIO Interface and Interrupt Pad Supply Voltage. Same range of VDD. VDDIO ≤ VDD (diode). 2 N.C. Not Internally Connected 3 N.C. Not Internally Connected 4 SCL_CLK 5 GND 6 SDA_SDI_O 7 SA0_SDO 8 CS 9 INT2 10 RESERVED 11 INT1 12 DSYNC 13 RESERVED 14 VDD Analog Power Supply Pin: Bypass to GND with a 0.1µF capacitor and one 10µF capacitor. 15 VDD Must be tied to VDD in the application. 16 N.C. Not Internally Connected 2 2 SPI and I C Clock. When in I C mode, the IO has selectable anti-spike filter and delay to ensure correct hold time. Power-Supply Ground 2 Rev. 2.6, May 2015 2 SPI In/Out Pin and I C Serial Data. When in I C mode, the IO has selectable anti-spike filter and delay to ensure correct hold time. 2 SPI Serial Data Out or I C Slave Address LSB SPI Chip Select/Serial Interface Selection Interrupt Line #2 Must be connected to GND Interrupt Line #1 Data Synchronization Pin to wake up MAX21000 from power down/standby or to synchronize data with an external device. Leave unconnected Maxim Integrated 11 2 MAX21000 User Guide Chapter 6: I C Interface 6 I2C Interface 2 To connect a MAX21000 device to an I C master, the SDA_SDI_O pin of the MAX21000 device must be connected 2 to the SDA pin of the I C master and the SCL_CLK pin of the MAX21000 device must be connected to the SCL pin 2 of the I C master. Both SDA and SCL lines must be connected to a pullup resistor. The SA0_SDO pin must be 2 2 connected to VDD or GND to configure the MAX21000 I C slave address (see Table 3: I C Device Addresses). I2C Mode VDD VDDIO C3 C2 VDDIO 1 16 15 RPU VDD VDD NC VDDIO RPU 14 13 DSYNC RESERVED C1 NC NC SCLK DND 12 2 3 MAX21000 11 10 4 5 7 6 9 8 DSYNC INT1 INT1 INT2 SA0 RESERVED SDA INT2 SCL CS SA0_SDO VDDIO SDA_SDI_0 Main Application Processor 2 Figure 2: I C Interface Connection to an Application Processor 2 Table 2: I C External Component Properties COMPONENT LABEL VDDIO /VDD Bypass Capacitor C1,C2 VDD Bypass Capacitor 2 Pullup Resistor (I C Mode only) Rev. 2.6, May 2015 SPECIFICATION QUANTITY Ceramic, X7R, 100nF ±10%, 4V 2 C3 Ceramic, X7R, 1uF ±10%, 4V 1 RPU 1.1kΩ - 10kΩ (min - max) 2 Maxim Integrated 12 2 MAX21000 User Guide Chapter 6: I C Interface 6.1 I2C Protocol 2 2 To start an I C request, the master sends a START condition (S), followed by the MAX21000’s I C address. Then, the master sends the address of the register to be programmed. The master then terminates the communication by issuing a STOP condition (P) to relinquish the control of the bus, or a repeated START condition (Sr) to keep controlling it. This image cannot currently be displayed. Figure 3: START (S), STOP (P), and Repeated START (Sr) Conditions 6.2 Slave Address 2 The slave address is used to identify the MAX21000 device in I C communications. The address is defined as the seven most significant bits followed by the read/write bit. Set the read/write bit to 1 to request a read operation, or 0 to request a write operation (see Table 3). 2 Table 3: I C Device Addresses 2 I C Base Address SA0_SDO pin R/W bit Resulting Address 0x2C (6bit) 0 0 0xB0 0x2C 0 1 0xB1 0x2C 1 0 0xB2 0x2C 1 1 0xB3 6.3 Acknowledge The acknowledge bit is sent after every byte. This bit allows the receiver to notify the transmitter that the byte has been received correctly and another byte may be sent. The master generates all clock pulses, including the acknowledge’s ninth clock pulse (8 bits of data + ACK). To allow the receiver to send the acknowledge, the transmitter releases the SDA line during the acknowledge pulse, so that the receiver can pull the SDA line LOW during the ninth clock pulse to signal an Acknowledge (ACK), or release the SDA line (HIGH) to signal a Not Acknowledge (NACK). Rev. 2.6, May 2015 Maxim Integrated 13 2 MAX21000 User Guide Chapter 6: I C Interface The NACK is sent if the device is busy or a system fault occurs. It is also used by the master to signal the end of the transfer during a read operation. 6.4 Register Address 2 The I C register address for the MAX21000 is composed by 6 bits of address and 1 bit (if_parity) whose meaning can be configured as: if 0, in case of burst operation the initial register address is auto-incremented after every data byte; if 1, the operation is executed always on the same register; this bit represents the even parity computed on the 6 bits of the register address; this bit represents the odd parity computed on the 6 bits of the register address; Auto-increment: Even parity Odd Parity 6.5 I2C Operations 6.5.1 Write One Byte To write one byte, the following steps must be executed: 1: 2: 3: 4: 5: 6: 7: 8: The master sends a START condition. The master sends the 7 bits slave ID plus a write bit (low) The addressed slave asserts an ACK on the data line. The master sends 8 bits of the Register Address. The slave asserts an ACK on the data line only if the address is valid (NACK if not). The master sends 8 bits of data. The slave asserts an ACK on the data line. The master generates a STOP condition. 2 S I C Slave Address + W ACK Data ACK Register Address ACK P From Master to Slave From Slave to Master 2 Figure 4: I C Write One Byte 6.5.2 Write a Burst of Data To execute a write of a burst of data, the following steps must be executed: 1: 2: 3: 4: 5: 6: 7: 8: Rev. 2.6, May 2015 The master sends a START condition. The master sends the 7 bits slave ID plus a write bit (low). The addressed slave asserts an ACK on the data line. The master sends 8 bits of the Register Address. The slave asserts an ACK on the data line only if the address is valid (NACK if not). The master sends 8 bits of data. The slave asserts an ACK on the data line. Repeat 6 and 7 as long as needed. Maxim Integrated 14 2 MAX21000 User Guide Chapter 6: I C Interface 2 S I C Slave Address + W ACK Register Address ACK Data 1 ACK Data 2 ACK … Data N ACK P From Master to Slave From Slave to Master 2 Figure 5: I C Write a Burst of Data 6.5.3 Read One Byte To read one byte, the following steps must be executed: 1: 2: 3: 4: 5: 6: 7: 8: 9: 10: 11: The master sends a START condition. The master sends the 7 bits slave ID plus a write bit (low). The addressed slave asserts an ACK on the data line. The master sends 8 data bits. The active slave asserts an ACK on the data line only if the address is valid (NACK if not). The master sends a restart condition. The master sends the 7 bits slave ID plus a read bit (high). The addressed slave asserts an ACK on the data line. The slave sends 8 data bits. The master asserts a NACK on the data line. The master generates a STOP condition. 2 S I C Slave Address + W Sr I C Slave Address + R ACK Data NACK 2 ACK Register Address ACK P From Master to Slave From Slave to Master 2 Figure 6: I C Read One Byte 6.5.4 Read a Burst of Data To execute a read of a burst of data, the following steps must be executed: Rev. 2.6, May 2015 Maxim Integrated 15 2 MAX21000 User Guide 1: 2: 3: 4: 5: 6: 7: 8: 9: 10: 11: 12: Chapter 6: I C Interface The master sends a START condition. The master sends the 7 bits slave ID plus a write bit (low). The addressed slave asserts an ACK on the data line. The master sends 8 bits of the Register Address. The slave asserts an ACK on the data line only if the address is valid (NACK if not). The master sends a repeated START condition. The master sends the 7 bits slave ID plus a read bit (high). The slave asserts an ACK on the data line. The slave sends 8 bits of data. The master asserts an ACK on the data line. Repeat 9 and 10 as long as needed. The master generates a STOP condition. 2 S I C Slave Address + W ACK Register Address ACK Sr I C Slave Address + R ACK Data 1 ACK Data 2 ACK Data 3 ACK 2 … Data N NACK P From Master to Slave From Slave to Master 2 Figure 7: I C Read a Burst of Data Rev. 2.6, May 2015 Maxim Integrated 16 MAX21000 User Guide Chapter 7: SPI Interface 7 SPI Interface To connect a MAX21000 device to an SPI master, the CS pin of the MAX21000 device must be connected to the CSn pin of the SPI master, the SDA_SDI_O pin of the MAX21000 device must be connected to the MOSI pin of the SPI master, the SA0_SDO pin of the MAX21000 device must be connected to the MISO pin of the SPI master and the SCL_CLK pin of the MAX21000 device must be connected to the SCLK pin of the SPI master. For external component parameters, refer to Table 4: SPI External Component Properties. SPI Mode VDD C2 VDDIO 1 VDD VDD NC VDDIO 16 15 C3 14 13 RESERVED C1 NC NC SCLK DND 2 3 12 MAX21000 11 4 10 5 9 6 7 8 DSYNC DSYNC INT1 INT1 INT2 MISO CSn RESERVED Main Application Processor MOSI INT2 CS SA0_SDO SDA_SDI_0 SCLK Figure 8: SPI Interface Connection to an Application Processor Table 4: SPI External Component Properties COMPONENT LABEL VDDIO /VDD Bypass Capacitor C1,C2 VDD Bypass Capacitor C3 SPECIFICATION QUANTITY Ceramic, X7R, 100nF ±10%, 4V 2 Ceramic, X7R, 1µF ±10%, 4V 1 7.1 SPI Protocol CSn is the serial port enable and is controlled by the SPI master. It goes low at the start of the transmission and returns to high at the end. Rev. 2.6, May 2015 Maxim Integrated 17 MAX21000 User Guide Chapter 7: SPI Interface SCLK is the serial port clock and is controlled by the SPI master. It is kept high when CSn is high (no transmission). MISO and MOSI are, respectively, the serial port data input and output. These lines are driven at the falling edge of SCLK and are sampled at the rising edge of SCLK. Both the read register and write register commands are completed in 16 clock pulses, or in multiples of 8 in case of multiple read/write bytes. Bit duration is the time between two falling edges of SCLK. Figure 9: SPI Protocol 7.2 Register Address The SPI register address for the MAX21000 is composed by 6 bits of address, 1 bit to select the direction of the operation (Read/Write) and 1 bit whose meaning can be configured as: if 0, in case of burst operation the initial register address is auto-incremented after every data byte; if 1, the operation is executed always on the same register; this bit represents the even parity computed on the 6 bits of the register address; this bit represents the odd parity computed on the 6 bits of the register address; Auto-increment: Even parity Odd Parity parity_error and if_parity are used to manage the parity bit during the SPI communication. The parity bit is an additional bit added to the end of a digital word and it indicates whether the number of bits in the word with the value one is even or odd. Parity bit is used to verify if there was a communication error. According to the datasheet, during a SPI communication, the first byte is the register address you want to read/write: Bit 7 R/W Bit 7: Bit 6: Bit [5:0] If_parity = ‘00’: if_parity = ‘01’: if_parity = ‘10’: Rev. 2.6, May 2015 Bit 6 MS/Parity Bit 5 A5 Bit 4 A4 Bit 3 A3 Bit 2 A2 Bit 1 A1 Bit 0 A0 Is used to define if you want to read or write a register. 0 = write, 1 = read; Can have 2 different functionalities, in according with the if_parity (see below) Address of the register you want to read or write; Bit 6 is used to set the multi-addressing standard mode (MS). MS = 0 -> the address is auto incremented in multiple read/write command MS = 1 -> the address remains unchanged in multiple read/write commands; Bit 6 is used to check the even parity with the register address (A[5:0]); Bit 6 is used to check the odd parity with the register address (A[5:0]); Maxim Integrated 18 MAX21000 User Guide Chapter 7: SPI Interface Here are shown some examples: Address count of 1 bits 000000 (0x00) 100000 (0x20) 100011 (0x23) 111111 (0x3F) 0 1 3 6 8 bits including parity Even x0000000 x1100000 x1100011 x0111111 Odd x1000000 x0100000 x0100011 x1111111 Bit 7 – indicated with x, can be 0 or 1, depending on if you want to write or read the correspondent register For further explanation: - to write register 0x00, using odd parity, you have to send from your MCU the byte ‘01000000’ (0x40); to read register 0x20, using even parity, you have to send from your MCU the byte ‘11100000’ (0xE0); to read register 0x23, using odd parity, you have to send from your MCU the byte ‘10100011’ (0xA3); to read register 0x3F, using even parity, you have to send from your MCU the byte ‘10111111’ (0xBF); When the device receives the above bytes from the MCU, it will try to calculate the parity bit, in according with the rule set in the if_parity field. If the parity calculated by the device is the same of the parity bit, the communication was good and the content of parity_error bit will be 0. If instead the parity calculated by the device is different from the parity bit, the content of parity_error bit is set to ‘1’, reporting that there was an error in the serial communication. Rev. 2.6, May 2015 Maxim Integrated 19 MAX21000 User Guide Chapter 8: Interrupts 8 Interrupts The MAX21000 is equipped with an interrupt module to control a set of interrupt flags and two interrupt lines (INT1 and INT2). This module allows to: 1: 2: 3: Configure the behavior of the interrupt lines (INT1 and INT2) Map each interrupt flag to one of both the interrupt lines Create a conditional interrupt (Rate interrupt) based on four different thresholds 8.1 Interrupt Flags The interrupt module provides several interrupt flags in the INT_STS_UL register. Each flag reports the occurrence of a significant event inside the device. 8.2 Interrupt Lines An interrupt line is a dedicated pin where a notification to an external application processor can be provided. The MAX21000 is equipped with two interrupt lines that can be configured independently. For each interrupt line, it is possible to (refer to INT_CFG2): - Enable/disable them Set the active level to low Set the output type to push-pull or open drain configuration To map an interrupt flag to an interrupt line it is necessary to enable it through the INT1_MSK for INT1 and INT2_MSK for INT2: by setting its corresponding bit to 1 on the bit-mask, the interrupt flag is mapped to the related interrupt line. The output of the two INT1 and INT2 interrupt lines is then computed by applying the OR operator to all the enabled interrupt flags contained in the INT1_STS and INT2_STS registers, respectively. Please note that the enable is not applied to the INT1_STS and INT2_STS registers, so those registers contain also the value of the interrupt flags that are not enabled. An interrupt line can be configured in order to keep the status until the master requests to clear it (latched) or after a timeout. Those modes can be selected through the int1_latch_mode and int2_latch_mode register fields (INT_TMO). The only exception is the gyro_dr flag that is always unlatched regardless of the int1_latch_mode and int2_latch_mode register fields setting. The lines can be configured also to auto-clear its status after a period of time where the duration to clear the interrupt is programmable (see Timed Mode at INT_TMO). 8.3 Rate Interrupts The rate interrupt allows generating an interrupt event when the gyroscope data falls inside a range of values defined by a set of thresholds. By setting the absolute value of the threshold (|TH|) for each gyroscope axis, four ranges are defined: Rev. 2.6, May 2015 Maxim Integrated 20 MAX21000 User Guide Axis data Chapter 8: Interrupts high_pos +|TH| low_pos Positive threshold time high_neg Negative threshold -|TH| low_neg Figure 10: Conditional Ranges For each range, it is possible to select if it contributes to the generation of the rate interrupt for each axis. Then, the rate interrupts are computed as follow: - int_and: Active if the defined conditions are satisfied for all the gyroscope axes at the same time; int_or: Active if the defined conditions are satisfied for at least one of the gyroscope axes. The threshold absolute value can be set by writing the INT_REF_X, INT_REF_Y and INT_REF_Z registers. Those registers represent the most significant byte of the real threshold; so, to compute the actual absolute value of the threshold, the register value must be multiplied by 256. If the application requires a better resolution, it is possible to specify a 16-bit threshold by setting the int_single_ref register field; in this case, all the axes share the same threshold that is defined as the combination of INT_REF_X and INT_REF_Y where the first one is the most significant byte and the last one is the least significant byte of the threshold. Once the thresholds are defined, the INT_MSK_X, INT_MSK_Y and INT_MSK_Z permits to select which range contributes to the generation of the rate interrupts for each axis as follow: - int_axis_high_pos_en: if enabled, the condition is satisfied if the data of the axis falls in the high_pos range; int_axis_high_neg_en: if enabled, the condition is satisfied if the data of the axis falls in the high_neg range; int_axis_low_pos_en: if enabled, the condition is satisfied if the data of the axis falls in the low_pos range; int_axis_low_neg_en: if enabled, the condition is satisfied if the data of the axis falls in the low_neg range. Then, the desired axes must be enabled by setting to 1 the corresponding bit of the int_mask_xyx_and for the int_and and int_mask_xyz_or for the int_or. Through the INT_MSK_X, INT_MSK_Y and INT_MSK_Z registers, it is also possible to read the current value of the conditions, regardless of the content of the int_mask_xyz_or and int_mask_xyz_and register fields. Each of these values can be configured as latched by setting the int_freeze register field. For the rate interrupts, it is possible also to define a de-bounce value by defining the number of samples the axis data has to satisfy the condition before asserting the corresponding interrupt. Those values can be set in the INT_DEB_X, INT_DEB_Y and INT_DEB_Z registers. If the required value is greater than 255, it is possible to define a 16-bit debounce value by setting int_single_deb register field; in this case, all the conditions share the same de-bounce value that is defined as the combination of INT_DEB_X and INT_DEB_Y where the first one is the most significant byte and the last one is the least significant byte of the debounce value. Rev. 2.6, May 2015 Maxim Integrated 21 MAX21000 User Guide Chapter 9: Reading Data from MAX21000 and FIFO Operation 9 Reading Data from MAX21000 and FIFO Operation MAX21000 sensor output data can be read by the processor in two different mechanisms: synchronous (DATA_READY interrupt) and asynchronous (polling) reading methods. 9.1 Synchronous Reading In this mode, the processor reads the data set (e.g. 6 bytes for a 3 axes configuration) generated by the MAX21000 every time that gyro_dr flag is set. The processor must read the output data only once the gyro_dr flag is set in order to avoid data inconsistencies. Benefits of using this approach include the perfect reconstruction of the signal coming from the sensors and minimization of the data traffic at the interface. 9.2 Asynchronous Reading In this mode, the processor reads the data generated by the MAX21000 regardless the status of the gyro_dr flag. To minimize the error caused by different samples being read a different number of times, the access frequency to be used must be higher than the selected ODR. 9.3 FIFO Modes Description The MAX21000 also embeds a 256-slot of a 16-bit data FIFO for each of the three output channel; X, Y and Z. This allows a consistent power saving for the system since the host processor does not need to continuously poll data from the sensor, but it can wake up only when needed and burst the data out from the FIFO. When configured in Snapshot mode, it offers the ideal mechanism to capture the data following a Rate Interrupt event. The data order in FIFO depends on the endian setting (endian): Big Endian: Little Endian: GYRO_X_H, GYRO_X_L, GYRO_Y_H, GYRO_Y_L, GYRO_Z_H, GYRO_Z_L GYRO_X_L, GYRO_X_H, GYRO_Y_L, GYRO_Y_H, GYRO_Z_L, GYRO_Z_H The FIFO buffer can work according to four main different modes (see FIFO_CFG): off, normal, interrupt and snapshot. Both normal and Interrupt modes can be optionally configured to operate in overrun Mode, depending on whether, in case of buffer under-run, newer or older data are lost. 9.3.1 FIFO OFF Mode In this mode, the FIFO is turned off; data are stored only in the data registers. No data are available from FIFO if read. When the FIFO is turned OFF, there are two options to use the device: synchronous/asynchronous reading. 9.3.2 Normal Mode The behavior of the FIFO in Normal mode varies depending on the Overrun settings (fifo_overrun register field). The following paragraphs show a description of the behavior for both settings of the overrun. For the next sections, the following descriptions are useful for the user’s understanding of FIFO: Write Pointer (WP): Read Pointer (RP): Level Rev. 2.6, May 2015 Write pointer is the address number where the next data will be written in FIFO, and whenever there is a new data is written, the write pointer is incremented by 1, Read pointer is the address number from where the first data in FIFO is read, and whenever there is a new data is read, the read pointer is incremented by 1, Level tells the difference between Write pointer and Read pointer, which also gives you the total number of data available in FIFO Maxim Integrated 22 MAX21000 User Guide 9.3.2.1 - Chapter 9: Reading Data from MAX21000 and FIFO Operation Stop on Full FIFO is turned on. FIFO is filled with the data at the selected Output Data Rate (ODR). When FIFO is full, an interrupt can be generated. When FIFO is full, all the new incoming data will be discharged. Reading only a subset of the data already stored into the FIFO keeps locked the possibility for new data to be written. Only if all the data are read the FIFO will restart saving data. If the communication speed is high, data loss can be prevented. In order to prevent a FIFO full condition, the required condition is to complete the reading of the data set before the next DATA_READY occurs. If this condition is not guaranteed, data can be lost. 255 255 255 (WP-RP) = Level (WP-RP) = Level (WP-RP) = Level Threshold 0 Threshold 0 Level increments with new samples stored and decrements with new readings Threshold 0 FIFO_OVTHOLD Interrupt generated FIFO_FULL Interrupt generated No new data stored until the entire FIFO is read Figure 11: FIFO Normal Mode, Stop on Full 9.3.2.2 - Overwrite FIFO is turned on. FIFO is filled with the data at the selected ODR. When FIFO is full, an interrupt can be generated. When FIFO is full, the oldest data will be overwritten with the new ones. If communication speed is high, data integrity can be preserved. In order to prevent a data lost condition, the requirement is to complete the reading of the data set before the next DATA_READY occurs. If this condition is not guaranteed, data can be overwritten. When an overrun condition occurs the Reading pointer is forced to Writing Pointer -1, to make sure only older data are discarded and newer data have a chance to be read. Rev. 2.6, May 2015 Maxim Integrated 23 MAX21000 User Guide Chapter 9: Reading Data from MAX21000 and FIFO Operation FIFO used as circular buffer FIFO used as circular buffer FIFO used as circular buffer RP WP Threshold Threshold WP Threshold RP WP RP WP-RP increments with new samples stored and decrements with new readings FIFO_OVTHOLD Interrupt generated FIFO_FULL Interrupt generated. New incoming data would overwrite the older ones Figure 12: FIFO Normal Mode, Overwrite 9.3.3 Interrupt Mode The behavior of the FIFO in Interrupt mode varies depending on the Overrun settings (fifo_overrun register field). The following paragraphs show a description of the behavior for both settings of the overrun. 9.3.3.1 - Stop on Full FIFO is initially disabled. Data is stored only in the data registers. When a Rate Interrupt (either OR or AND) is generated, the FIFO is turned on automatically. It stores the data at the selected ODR. Rate interrupt are documented starting from INT_REF_X. When FIFO is full, all the new incoming data will be discharged. Reading only a subset of the data already stored into the FIFO keeps locked the possibility for new data to be written. Only if all the data are read the FIFO will restart saving data. If communication speed is high, data loss can be prevented. In order to prevent a FIFO full condition, the required condition is to complete the reading of the data set before the next DATA_READY occurs. If this condition is not guaranteed, data can be lost. Rev. 2.6, May 2015 Maxim Integrated 24 MAX21000 User Guide Chapter 9: Reading Data from MAX21000 and FIFO Operation MAX FIFO initially OFF. When the programmed Rate Interrupt occurs, turn FIFO ON Level 0 MAX MAX MAX (WP-RP) = Level (WP-RP) = Level (WP-RP) = Level 0 Level increments with new samples stored and decrements with new readings Threshold Threshold Threshold 0 FIFO_OVTHOLD Interrupt generated 0 FIFO_FULL Interrupt generated No new data stored until the entire FIFO is read Figure 13: FIFO Interrupt Mode, Stop on Full 9.3.3.2 - Overwrite FIFO is initially disabled. Data is stored only in the data registers. When a Rate Interrupt (either OR or AND) is generated, the FIFO is turned on automatically. It stores the data at the selected ODR. When FIFO is full, an interrupt can be generated. When FIFO is full, the oldest data will be overwritten with the new ones. If communication speed is high, data integrity can be preserved. In order to prevent a data lost condition, the required condition is to complete the reading of the data set before the next DATA_READY occurs. If this condition is not guaranteed, data can be overwritten. When an overrun condition occurs the Reading pointer is forced to Writing Pointer -1, to make sure only older data are discarded and newer data have a chance to be read. Rev. 2.6, May 2015 Maxim Integrated 25 MAX21000 User Guide Chapter 9: Reading Data from MAX21000 and FIFO Operation MAX FIFO initially OFF. When the programmed Rate Interrupt occurs, turn FIFO ON Level 0 RP WP WP Threshold Threshold Threshold RP WP = RP WP-RP increments with new samples stored and decrements with new readings FIFO_OVTHOLD Interrupt generated FIFO_FULL Interrupt generated. New incoming data would overwrite the older ones Figure 14: FIFO Interrupt Mode, Overwrite Rev. 2.6, May 2015 Maxim Integrated 26 MAX21000 User Guide Chapter 9: Reading Data from MAX21000 and FIFO Operation FIFO used as circular buffer FIFO used as circular buffer FIFO used as circular buffer RP WP WP Threshold Threshold Threshold RP WP RP RATE INTERRUPT SNAPSHOT CAPTURED MAX MAX MAX (WP-RP) = Level (WP-RP) = Level (WP-RP) = Level Threshold 0 Threshold 0 Threshold 0 Figure 15: FIFO Snapshot Mode 9.3.4 Snapshot Mode - FIFO is initially in normal mode with overrun enabled. When a Rate Interrupt (either OR or AND) is generated, the FIFO switches automatically to not-overrun mode. It stores the data at the selected ODR until the FIFO becomes full. When FIFO is full, an interrupt can be generated. When FIFO is full, all the new incoming data will be discharged. Reading only a subset of the data already stored into the FIFO keeps locked the possibility for new data to be written. Only if all the data are read the FIFO will restart saving data. If communication speed is high, data loss can be prevented. In order to prevent a FIFO full condition, the required condition is to complete the reading of the data set before the next DATA_READY occurs. If this condition is not guaranteed, data can be lost. 9.4 Example of FIFO Read/Write Pointers Evolution The following drawing assumes: - A reading frequency roughly twice the writing frequency (ODR); A FIFO threshold = 126 FIFO is in normal mode Rev. 2.6, May 2015 Maxim Integrated 27 MAX21000 User Guide Chapter 9: Reading Data from MAX21000 and FIFO Operation Slope is ODR 255 Write Pointer (Data from Sensor) 126 Time 255 Read pointer (I2C/SPI) 126 Time 255 Wp-Rp 126 Time OverThreshold Time Figure 16: FIFO Read/Write Pointer Evolution Rev. 2.6, May 2015 Maxim Integrated 28 MAX21000 User Guide Chapter 10: Programming Example 10 Programming Example This chapter shows some examples on how to execute some operations on the device. Two functions are defined 2 to abstract the SPI/I C communication: - Write(, ): Writes the to the register at the ; - Read(): Returns the value of the register at the ; - ReadBurstNoInc(, ): Returns an array of count elements with the result of a burst read with no auto-increment on register; Rev. 2.6, May 2015 Maxim Integrated 29 MAX21000 User Guide Chapter 10: Programming Example 10.1 Simple Read-Out Sequence, No FIFO, No Interrupts Start Write(0x21, 0x00) // BNK 00 Write(0x00, 0x07) // 2kdps FS, 3D MAX21000 Configuration Write(0x01, 0x10) // 10Hz BW Write(0x02, 0x01) // 5 KHz ODR Write(0x00, 0x0F) // Normal Mode while (keep_reading_flag) { while (Read(0x22)==0); // wait DATA_READY X_H = Read(0x23); // MSB X X_L = Read(0x24); // LSB X MAX21000 Get Data Y_H = Read(0x25); // MSB Y Y_L = Read(0x26); // LSB Y Z_H = Read(0x27); // MSB Z Z_L = Read(0x28); // LSB Z } MAX21000 Standby Write(0x00, 0x17); // Standby Mode MAX21000 Resume to Normal Write(0x00, 0x0F); // Normal Mode MAX21000 Powerdown Write(0x00, 0x00); // Powerdown Mode Stop Figure 17: Simple Read-Out Sequence, No FIFO, No Interrupts Rev. 2.6, May 2015 Maxim Integrated 30 MAX21000 User Guide Chapter 10: Programming Example 10.2 Simple Read-Out Sequence, FIFO Normal Mode, No Interrupts Start threshold = 0x3E; // FIFO Thr. = 126 Write(0x21, 0x00) // BNK 00 Write(0x00, 0x07) // 2kdps FS, 3D MAX21000 Configuration Write(0x01, 0x10) // 10Hz BW Write(0x02, 0x01) // 5 KHz ODR Write(0x00, 0x0F) // Normal Mode Write(0x17, threshold) // Set FIFO Threshold Write(0x18, 0x47) // FIFO Mode = NORMAL while(keep_reading_flag) { fifo_ovt = Read(0x3D)&(1