MAX2986
Integrated Powerline Digital Transceiver
General Description
The MAX2986 powerline transceiver utilizes state-of-theart CMOS design techniques to deliver the highest level of
performance and flexibility. This highly integrated design
combines the media access control layer (MAC) and the
physical layer (PHY) in a single chip. The MAX2986 digital baseband and its companion device, the MAX2980*
analog front-end (AFE), offer a complete high-speed
powerline communication solution that is fully compatible
with third-party HomePlug® 1.0 devices.
The MAX2986 digital transceiver utilizes Maxim’s
advanced OFDM powerline engine with adaptive data
rates up to 14Mbps. The MAX2986’s open architecture
allows extensive programmability, feature enhancement
capability, and improved testability in the MAC for optimum performance. Hence, this device is aimed at applications such as local area networks (LANs), audio, voice,
home automation, industrial automation, and broadbandover-powerline (BPL), as well as spectral shaping and
tone notching capability, providing an unparalleled level of
flexibility to conform to the disparate local regulatory bodies. Maxim’s modified OFDM technique allows shaping of
power spectral density of the transmitted signal arbitrarily
to accommodate any desired subcarrier set and to place
spectral nulls at any unwanted frequency location. The
automatic channel adaptation and interference rejection
features of the MAX2986 guarantee outstanding performance. Privacy is provided by a 56-bit DES encryption
with key management.
The MAX2986 operates with IEEE 802.03 standard
media independent interface (MII), reduced media independent interface (rMII), buffered FIFO data communication, IEEE 802.03 compatible 10/100 Ethernet MAC, or
USB 1.1 interfaces. These interfaces allow the MAX2986
to be paired with almost any data communication devices
to use in a variety of information appliances.
Features
●● Single-Chip Powerline Networking Transceiver
●● Up to 14Mbps Data Rate
●● 4.49MHz to 20.7MHz Frequency Band
●● Upgradeable/Programmable MAC
• Spectral Shaping Including Bandwidth and
Notching Capability
• Programmable Preamble
• Access to Application Protocol Interface (API)
• 128kB Internal SRAM
●● JTAG Interface
●● Large Bridge Table: Up to 512 Addresses
●● 56-Bit DES Encryption with Key Management for
Secure Communication
●● Advanced Narrowband Interference Rejection
Circuitry
●● OFDM-Based PHY
• 84 Carriers
• Automatic Channel Adaptation
• FEC (Forward Error Correction)
• DQPSK, DBPSK, ROBO
●● On-Chip Interfaces
• 10/100 Ethernet
• USB 1.1
• MII/rMII/FIFO
●● Compatible with HomePlug 1.0 Standard
Ordering Information
PART
TEMP RANGE
MAX2986CXV
0°C to +70°C
PIN-PACKAGE
144 CSBGA
Applications
●● Broadband-Over-Powerline ●● Industrial Automation
●● Local Area Networks
(Remote Monitoring and
(LANs)
Control)
●● Multimedia-Over-Powerline ●● Home Automation
●● Voice-Over-Powerline
●● Security and Safety
*Future product—contact factory for availability.
HomePlug is a registered trademark of HomePlug Powerline
Alliance, Inc.
19-3484; Rev 0; 11/04
Pin Configuration and Typical Application Circuit appear at
end of data sheet.
MAX2986
Integrated Powerline Digital Transceiver
Absolute Maximum Ratings
VDD33 to DGND....................................................-0.5V to +4.6V
VDD18 to DGND, DVDD to DVSS..........................-0.5V to +2.5V
AVDD to AVSS........................................................-0.5V to +2.5V
All Other Input Pins..................................................-0.5V to +6V
All Other Output Pins............................................-0.5V to +4.6V
Continuous Power Dissipation (TA = +70°C)
144-Bump CSBGA (derate 25.6mW/°C at +70°C).....2045mW
Operating Temperature Range................................0°C to +70°C
Junction Temperature.......................................................+150°C
Storage Temperature Range............................. -65°C to +150°C
CAUTION! ESD SENSITIVE DEVICE
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Electrical Characteristics
(VDD33 = +3.3V, VDD18 = DVDD = AVDD = +1.8V, AVSS = DVSS = DGND = 0, TA = 0°C to +70°C, unless otherwise noted. Typical
values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
3.0
3.3
3.6
V
1.62
1.8
1.98
POWER-SUPPLY CHARACTERISTICS
Digital-Supply Voltage Range
VDD33
Guaranteed by PSRR
Core-Supply Voltage Range
VDD18
Digital I/O Supply Current
IDD33
41
mA
Core Supply Current
IDD18
426
mA
PLL Supply Current
IPLL
8
mA
Output-Voltage High
VOH
Output-Voltage Low
VOL
2.3
V
V
0.5
V
LOGIC INPUT CHARACTERISTICS
Input High Voltage
VIH
2.0
5.5
V
Input Low Voltage
VIL
-0.3
+0.8
V
ILEAK
-80
+80
µA
Input Leakage Current
Output High Current
Output Low Current
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IOH
IOL
UARTTXD, AFEFRZ, AFEPDRX, AFEREN,
AFERESET, AFETXEN, ETHMDC, ETHTXD[0],
ETHTXD[1], ETHTXD[2], ETHTXD[3], ETHTXEN,
ETHTXER, JRTCK, MIICRS, MIIRXDV, MIIRXER
4
AFECLK
16
JTDO (tri-state port)
4
UARTTXD, AFEFRZ, AFEPDRX, AFEREN,
AFERESET, AFETXEN, ETHMDC, ETHTXD[0],
ETHTXD[1], ETHTXD[2], ETHTXD[3], ETHTXEN,
ETHTXER, JRTCK, MIICRS, MIIRXDV, MIIRXER
4
AFECLK
16
JTDO (tri-state port)
4
mA
mA
Maxim Integrated │ 2
MAX2986
Integrated Powerline Digital Transceiver
Pin Description
BUMP
NAME
A1, L2
DVDD
1.8V PLL Digital Power Supply. Bypass to DVSS with a 100nF capacitor as close to the pin as
possible.
A2, L3
DVSS
PLL Ground
A3, M1
AVDD
1.8V PLL Analog Power Supply. Bypass to AVSS with a 100nF capacitor as close to the pin as
possible.
A4
GPIO[2]
General-Purpose Input/Output 2. GPIO[2] is in tri-state during boot up. Connect a 100kΩ pullup
or pulldown resistor to GPIO[2] if not used. The MAX2986 software uses GPIO[2] to control
external USB circuit.
A5
GPIO[22]
General-Purpose Input/Output 22. GPIO[22] is in tri-state during boot up. Connect a 100kΩ
pullup or pulldown resistor to GPIO[22] if not used. The MAX2986 MAC uses GPIO[22] for AFE
interface link status LED (output) and boot pin bit 1 (input).
A6, C1, C13, F12,
J1, L1, L4, L10,
M13
VDD33
3.3V Digital Power Supply. Bypass to DGND with a 100nF capacitor as close to the pin as
possible.
A7
GPIO[17]
General-Purpose Input/Output 17. GPIO[17] is in tri-state during boot up. Connect a 100kΩ
pullup or pulldown resistor to GPIO[17] if not used.
A8
GPIO[14]
General-Purpose Input/Output 14. GPIO[14] is in tri-state during boot up. Connect a 100kΩ
pullup or pulldown resistor to GPIO[14] if not used.
A9
GPIO[11]
General-Purpose Input/Output 11. GPIO[11] is in tri-state during boot up. Connect a 100kΩ
pullup or pulldown resistor to GPIO[11] if not used. The MAX2986 MAC uses GPIO[11] as
processor ID, bit 0 (input).
A10
GPIO[9]
General-Purpose Input/Output 9. GPIO[9] is in tri-state during boot up. Connect a 100kΩ pullup
or pulldown resistor to GPIO[9] if not used. The MAX2986 MAC uses GPIO[9] as serial data in
nonvolatile memory interface.
A11
GPIO[7]
General-Purpose Input/Output 7. GPIO[7] is in tri-state during boot up. Connect a 100kΩ pullup
or pulldown resistor to GPIO[7] if not used. The MAX2986 MAC uses GPIO[7] as AFE interface
power-down signal.
A12
GPIO[5]
General-Purpose Input/Output 5. GPIO[5] is in tri-state during boot up. Connect a 100kΩ pullup
or pulldown resistor to GPIO[5] if not used. The MAX2986 MAC uses GPIO[5] as AFE interface
serial data signal.
A13
GPIO[4]
General-Purpose Input/Output 4. GPIO[4] is in tri-state during boot up. Connect a 100kΩ pullup
or pulldown resistor to GPIO[4] if not used. The MAX2986 MAC uses GPIO[4] for AFE interface
serial clock signal (output) and upper layer interface bit 0 (input).
B1, C2, D4– D9,
E3, E11, E12, E13,
F4, F13, K5, K6,
K8, K9, M10, M11,
N1, N6
DGND
Digital Ground
B2, M2
AVSS
Analog PLL Ground
B3
GPIO[0]
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FUNCTION
General-Purpose Input/Output 0. GPIO[0] is in tri-state during boot up. Connect a 100kΩ pullup
or pulldown resistor to GPIO[0] if not used.
Maxim Integrated │ 3
MAX2986
Integrated Powerline Digital Transceiver
Pin Description (continued)
BUMP
NAME
FUNCTION
B4
GPIO[3]
General-Purpose Input/Output 3. GPIO[3] is in tri-state during boot up. Connect a 100kΩ pullup
or pulldown resistor to GPIO[3] if not used.
B5
USBD+
USB Interface Data Signal (+)
B6
GPIO[21]
General-Purpose Input/Output 21. GPIO[21] is in tri-state during boot up. Connect a 100kΩ
pullup or pulldown resistor to GPIO[21] if not used. The MAX2986 MAC uses GPIO[21] for AFE
interface collision LED (output) and boot pin bit 0 (input).
B7
GPIO[18]
General-Purpose Input/Output 18. GPIO[18] is in tri-state during boot up. Connect a 100kΩ
pullup or pulldown resistor to GPIO[18] if not used.
B8
GPIO[15]
General-Purpose Input/Output 15. GPIO[15] is in tri-state during boot up. Connect a 100kΩ
pullup or pulldown resistor to GPIO[15] if not used.
B9
GPIO[12]
General-Purpose Input/Output 12. GPIO[12] is in tri-state during boot up. Connect a 100kΩ
pullup or pulldown resistor to GPIO[12] if not used. The MAX2986 MAC uses GPIO[12] as
processor ID, bit 1 (input).
B10
GPIO[10]
General-Purpose Input/Output 10. GPIO[10] is in tri-state during boot up. Connect a 100kΩ
pullup or pulldown resistor to GPIO[10] if not used. The MAX2986 MAC uses GPIO[10] as
nonvolatile memory chip-select signal (output) and nonvolatile memory type, bit 1 (input).
B11
GPIO[8]
General-Purpose Input/Output 8. GPIO[8] is in tri-state during boot up. Connect a 100kΩ pullup
or pulldown resistor to GPIO[8] if not used. The MAX2986 MAC uses GPIO[8] as nonvolatile
memory serial clock signal (output) and nonvolatile memory type, bit 0 (input).
B12
GPIO[6]
General-Purpose Input/Output 6. GPIO[6] is in tri-state during boot up. Connect a 100kΩ pullup
or pulldown resistor to GPIO[6] if not used. The MAX2986 MAC uses GPIO[6] as AFE interface
serial write signal (output) and upper layer interface bit 1 (input).
B13, D1, D11, D12,
D13, E1, K4, M12
N.C.
C3
GPIO[1]
General-Purpose Input/Output 1. GPIO[1] is in tri-state during boot up. Connect a 100kΩ pullup
or pulldown resistor to GPIO[1] if not used.
C4
GPIO[23]
General-Purpose Input/Output 23. GPIO[23] is in tri-state during boot up. Connect a 100kΩ
pullup or pulldown resistor to GPIO[23] if not used. The MAX2986 MAC uses GPIO[23] for AFE
interface link activity LED (output) and boot pin bit 2 (input).
C5
USBD-
C6
GPIO[20]
General-Purpose Input/Output 20. GPIO[20] is in tri-state during boot up. Connect a 100kΩ
pullup or pulldown resistor to GPIO[20] if not used.
C7
GPIO[19]
General-Purpose Input/Output 19. GPIO[19] is in tri-state during boot up. Connect a 100kΩ
pullup or pulldown resistor to GPIO[19] if not used.
C8
GPIO[16]
General-Purpose Input/Output 16. GPIO[16] is in tri-state during boot up. Connect a 100kΩ
pullup or pulldown resistor to GPIO[16] if not used.
C9
GPIO[13]
General-Purpose Input/Output 13. GPIO[13] is in tri-state during boot up. Connect a 100kΩ
pullup or pulldown resistor to GPIO[13] if not used. The MAX2986 MAC uses GPIO[13] as
processor ID, bit 2 (input).
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No Connection. Must be left unconnected (floating output).
USB Interface Data Signal (-)
Maxim Integrated │ 4
MAX2986
Integrated Powerline Digital Transceiver
Pin Description (continued)
BUMP
NAME
FUNCTION
C10, D10, E10,
F10, G10, J10, K10
VDD18
+1.8V Digital Power Supply. Bypass to DGND with a 100nF capacitor as close to the pin as
possible.
C11
JTMS
JTAG Test Mode Select
C12
JTDI
JTAG Test Data Input
D2
USBRESET
D3
RESET
Asynchronous, Active-Low Reset Input
E2
JRTCK
JTAG Return Test Clock
E4
AFEFRZ
F1
AFETXEN
F2
XIN
Active-Low USB Reset Signal. Connect to RESET.
Analog Front-End Carrier Sense Indicator
Analog Front-End Transmitter Enable Output
Crystal Input (30MHz)
F3
XOUT
F11
MIITXEN
Crystal Output
G1
AFERESET
AFE Reset
G2
AFEDAD[0]
Analog Front-End DAC/ADC Input/Output 0 Interface
G3
AFEDAD[1]
Analog Front-End DAC/ADC Input/Output 1 Interface
Analog Front-End DAC/ADC Input/Output 2 Interface
MII Transmit Enable
G4
AFEDAD[2]
G11
JTDO
JTAG Test Data Output
G12
JTRST
Active-Low JTAG Test Reset
G13
JTCK
JTAG Test Clock
H1
AFEDAD[3]
Analog Front-End DAC/ADC Input/Output 3 Interface
H2
AFEDAD[4]
Analog Front-End DAC/ADC Input/Output 4 Interface
H3
AFEDAD[5]
Analog Front-End DAC/ADC Input/Output 5 Interface
H4
AFEDAD[6]
Analog Front-End DAC/ADC Input/Output 6 Interface
H10
MIIRXDV
H11
BUFRD
Active-Low FIFO Read Enable
H12
BUFCS
Active-Low FIFO Chip Enable
H13
BUFWR
Active-Low FIFO Write Enable
J2
AFEDAD[7]
Analog Front-End DAC/ADC Input/Output 7 Interface
J3
AFEDAD[8]
Analog Front-End DAC/ADC Input/Output 8 Interface
J4
AFEDAD[9]
Analog Front-End DAC/ADC Input/Output 9 Interface
MII Receive Data Valid
J11
MIIMDC
J12
MIIDAT[7]
MII/FIFO Transmit/Receive Data [7]
J13
MIIDAT[5]
MII/FIFO Transmit/Receive Data [5]
K1
AFECLK
50MHz AFE Clock
K2
AFEREN
Analog Front-End Read Enable Output
K3
AFEPDRX
AFE Receiver Power-Down
K7
UARTTXD
UART Transmit
K11
MIICRS
K12
MIIDAT[6]
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MII Management Data Clock
MII Carrier Sense
MII/FIFO Transmit/Receive Data [6]
Maxim Integrated │ 5
MAX2986
Integrated Powerline Digital Transceiver
Pin Description (continued)
BUMP
NAME
K13
MIIMDIO
L5
ETHRXD[1]
Ethernet MII Receive Data Bit 1
L6
UARTRXD
UART Receive
L7
ETHTXD[3]
Ethernet MII Transmit Data Bit 3
L8
ETHTXD[2]
Ethernet MII Transmit Data Bit 2
L9
ETHTXCLK
Ethernet MII Transmit Clock
L11
MIIRXER
MII Receive-Error Indicator
L12
MIIDAT[4]
MII/FIFO Transmit/Receive Data [4]
L13
MIIDAT[0]
MII/FIFO Transmit/Receive Data [0]
M3
ETHMDC
Ethernet Management Data Interface Clock
M4
ETHRXCLK
Ethernet MII Receive Clock
M5
ETHRXD[2]
Ethernet MII Receive Data Bit 2
M6
ETHRXD[0]
Ethernet MII Receive Data Bit 0
M7
ETHRXDV
Ethernet MII Receive Data Valid
M8
ETHTXD[0]
Ethernet MII Transmit Data Bit 0
M9
ETHTXEN
Ethernet MII Transmit Enable
N2
ETHCOL
Ethernet MII Collision
N3
ETHCRS
Ethernet MII Carrier Sense
N4
ETHMDIO
Ethernet Management Data Input/Output
N5
ETHRXD[3]
Ethernet MII Receive Data Bit 3
N7
ETHRXER
Ethernet MII Receive Error
N8
ETHTXD[1]
Ethernet MII Transmit Data Bit 1
Ethernet MII Transmit Error
N9
ETHTXER
N10
MIICLK
FUNCTION
MII Management Data
MII Clock
N11
MIIDAT[3]
MII/FIFO Transmit/Receive Data [3]
N12
MIIDAT[2]
MII/FIFO Transmit/Receive Data [2]
N13
MIIDAT[1]
MII/FIFO Transmit/Receive Data [1]
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Maxim Integrated │ 6
MAX2986
Integrated Powerline Digital Transceiver
JTMS, JTDO, JTDI
JTRSTN, JTCK
XIN
XOUT
JTAG
PLL 1
I-ITCM
D-ITCM
MAX2986
ENCRYPTION
ENGINE
PLL 2
RESET
I-CACHE D-CACHE
ON-CHIP
CONTROLLER
RAM
AFETXEN
AFERESET
AFEDAD0–9
AFECLK
AFEREN
AFEPDRX
AFEFRZ
DSP ENGINE
ARM®946 PROCESSOR
(MAC SOFTWARE)
AFE REGISTER INTERFACE
ON-CHIP
CONTROLLER
ROM
DMA
ENGINE
UARTRXD
UARTTXD
USB
CONTROLLER
UART
TIMERS
ADDRESS
SEARCH
ENGINE
INTERRUPT
CONTROLLER
ETHERNET
MAC
ETHCOL, ETHMDC,
ETHCRS, ETHRXCLK,
ETHMDIO, ETHRXD0-3,
ETHTXD0-3, ETHRXDV,
ETHRXER, ETHTXCLK,
ETHTXEN, ETHTXER
MII/rMII
FIFO
MIIRXDV, MIICLK
MIITXEN, MIIMDC
MIICRS, MIIRXER
MIIDAT0-7, MIIMDIO
BUFRD, BUFCS
BUFWR
USBDUSBD+
USBRESET
GPIO
GPIO0-23
Figure 1. MAX2986 Functional Diagram
DATA
EXTERNAL
HOST
MAX2986
MAC/PHY
MAX2980
AFE
COUPLER
POWERLINE
Figure 2. Powerline Chipset System Block Diagram
Detailed Description
The MAX2986 powerline transceiver IC is a state-of-theart CMOS device, which delivers high performance at
reduced cost. This highly integrated design combines the
MAC layer with the PHY layer in a single chipset. The
MAX2986 and the companion device, the MAX2980 AFE,
form a complete HomePlug-compatible solution with a
substantially reduced system cost.
ARM is a registered trademark of ARM Ltd.
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MII/rMII/FIFO Interface
The MII/rMII/FIFO block is the interface layer of the
MAX2986 transceiver. This layer is designed to operate
with IEEE 802.3 standard MII, rMII, or any other devices
using the FIFO interface.
The interface is a data channel that transfers data in packets, with flow controlled by the carrier sense (MIICRS)
signal. This signal controls the half-duplex transmission
between the external host and the MAC. While a frame
reception is in progress, (MIICRS and MIIRXDV are
Maxim Integrated │ 7
MAX2986
Integrated Powerline Digital Transceiver
high), the external host must wait until the completion of
reception and the deassertion of MIICRS before starting a
transmission. When sending two consecutive frames, the
minimum time the external host needs to wait is the oneframe transfer time plus an interframe gap.
Note: For information such as signal timing characteristics
and electrical characteristics, refer to the IEEE 802.3u.
Note: The MII signals MIICOL and MIITXER are not used,
as the powerline networking device is able to detect and
manage all transmission failures. The signals MIITXCLK
and MIIRXCLK have the same source and are referred to
as MIICLK in this document.
In MII mode, the data is transferred synchronously with a
2.5MHz/25MHz clock. Data transmission in MII is in nibble
format so the data transmission rate is 10Mbps/100Mbps.
In rMII mode, the data is transferred synchronously with
a 5MHz/50MHz clock. Data transmission in rMII is in 2-bit
format so the data transmission rate is 10Mbps/100Mbps.
In FIFO mode, data is read and written in byte format on
each positive edge of BUFRD and BUFWR. The only limitation in this mode is that BUFRD and BUFWR must be
low for at least three pulses of MIICLK to be considered
a valid signal.
The upper layer interface can be selected according to
the settings shown in Table 1.
MII Interface Signals
Table 2 describes the signals that provide data, status,
and control to and from the MAX2986 in MII mode.
Table 1. Upper Layer Interface-Selection Pin Settings
INTERFACE
GPIO[3]
GPIO[6]
GPIO[4]
MII
0
0
1
rMII
0
1
0
FIFO
0
1
1
Table 2. MII Signal Description
NAME
I/O
DESCRIPTION
4
I
Transmit Data. Data are transferred to the MAX2986 from the external MAC across these four lines, one
nibble at a time, synchronous to MIICLK.
MIITXEN
1
I
Transmit Enable. Provides the framing for the Ethernet packet from the Ethernet MAC. This signal
indicates to the MAX2986 that valid data is present on MIIDAT[3:0] and must be sampled using MIICLK.
MIICRS
1
O
Carrier Sense. Logic-high indicates to the external host that traffic is present on the powerline and
the host must wait until the signal goes invalid before sending additional data. When a packet is being
transmitted, MIICRS is held high.
MIIDAT
[7:4]
4
O
Receive Data. Data are transferred from the MAX2986 to the external MAC across these four lines, one
nibble at a time, synchronous to MIICLK. The MAX2986 properly formats the frame so the Ethernet MAC
is presented with the expected preamble plus the start frame delimiter (SFD).
MIIRXDV
1
O
Receive Data Valid. Logic-high indicates that the incoming data on the MIIDAT pins are valid.
MIIRXER
1
O
Receive Error. Logic-high indicates to the external MAC that the MAX2986 detected a decoding error in
the receive stream.
MIICLK
1
I
Reference Clock. A 2.5MHz (25MHz) clock in 10Mbps (100Mbps) as reference clock.
MIIDAT
[3:0]
LINES
MANAGEMENT DATA UNIT
MIIMDC
1
I
MIIMDIO
1
I/O
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Management Data Clock. A 2.5MHz noncontinuous clock reference for the MIIMDIO signal.
Management Data Input/Output. A bidirectional signal that carries the data for the management data
interface.
Maxim Integrated │ 8
MAX2986
Integrated Powerline Digital Transceiver
MII MAC and PHY Connections
Figure 3 illustrates the connections between MAC and
PHY in MII mode. Although the Tx and Rx data paths
are full duplex, the MII interface is operated in halfduplex
mode. MIIRXDV is never asserted at the same time as
MIITXEN.
On transmit, the MAX2986 asserts MIICRS some time
after MIITXEN is asserted, and drops MIICRS after
MIITXEN is deasserted and when the MAX2986 is
ready to receive another packet. When MIICRS falls, the
Ethernet MAC times out an interframe gap (IFG) (0.96μs
typ) and asserts MIITXEN again if there is another packet
to send. This differs from the nominal behavior of MIICRS
in that MIICRS can extend past the end of the packet by
an arbitrary amount of time, while the MAX2986 is gaining
access to the channel and transmitting the packet.
MACs in 10Mbps mode do not use a jabber timeout, so
there is no timing restriction on how long MIICRS can
assert (other than timeouts the MAX2986 may implement).
Transmissions are modulated onto the wire as soon as
the transfer begins, as the MII fills the MAX2986 buffer faster than data needs to be made available to the
modulator. When a packet arrives at the MAX2986, it
attempts to gain access to the channel. This may not happen before the entire packet is transferred across the MII
interface, so the MAX2986 buffers at least one Ethernet
packet to perform this rate adaptation.
On receive, when the MAX2986 anticipates that it will
have a packet demodulated, it raises MIICRS to seize the
half-duplex MII channel, waits a short time (an IFG), then
possibly defers to MIITXEN (which may just have been
asserted) plus an IFG, and then raises MIIRXDV to transfer the packet. At the end of the transfer, it drops MIICRS
unless the transmit buffer is full or there is another receive
packet ready to transfer. This is illustrated in Figure 4,
where one receive transfer is followed by a second, which
defers to MIITXEN. Data reception needs to have priority
over transmission to ensure that the buffer empties faster
than packets arrive off the wire. The longest the receiver
needs to wait is the time to transfer one Tx frame plus
an IFG or approximately 134μs. However, minimum size
frames can arrive at a peak rate of one every 65μs, so the
receive-side buffer must accommodate multiple frames
(but only a little more than one Ethernet packet of data).
RECEIVE
INCOMING
MIICRS
DEFER
IFG
MIIRXDV
MIITXEN
Figure 4. Receive Defer in MII Mode
CLOCK SOURCE (2.5MHz OR 25MHz)
RXCLK
MIICLK
MAX2986
TXCLK
ETHERNET
802.3 MAC
(MII)
TXEN
MIITXEN
RXDV
MIIRXDV
CRS
MIICRS
TXD[3:0]
MIIDAT[3:0]
RXD[3:0]
MIIDAT[7:4]
RXER
MII
INTERFACE
MAC
PHY
MIIRXER
MDC
MIIMDC
MDIO
MIIMDIO
COL
BUFWR
BUFRD
BUFCS
GND
VCC
Figure 3. MAC and PHY Connection in MII Mode
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Maxim Integrated │ 9
MAX2986
Integrated Powerline Digital Transceiver
MII Signal Timing—Transmitting
When a frame in the external host is ready to transmit
and MIICRS is not high (the previous transmission has
finished), the external host asserts MIITXEN, while data is
ready on MIIDAT[3:0]. In response, the MAX2986 asserts
MIICRS.
While the external host keeps MIITXEN high, data is
sampled synchronously with respect to MIICLK into the
MAX2986 through MIIDAT.
After transmission of the last byte of data and before the
next positive edge of the MIICLK, MIITXEN is reset by the
external host.
The transmission timing of the MII interface is illustrated in
Figure 5, with details in Figure 6 and Table 3.
MIICLK
MIITXEN
MIICRS
DATA
MIIDAT
DATA
DATA
DATA
Figure 5. Transmission Behavior of the MII Interface
tIH
MIIDAT
MIITXEN
PARAMETER
tIS
MIICLK
Figure 6. MII Interface—Detailed Transmit Timing
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Table 3. MII Interface—Detailed Transmit
Timing*
DESCRIPTION
MIN
UNITS
tIS
Setup prior to positive
edge of MIICLK
2.5
ns
tIH
Hold after positive edge
of MIICLK
2.5
ns
*Per IEEE 802.3u standard.
Maxim Integrated │ 10
MAX2986
Integrated Powerline Digital Transceiver
MII Signal Timing—Receiving
When a frame is ready to send from the MAX2986 to the
external host, the MAX2986 asserts MIIRXDV after IFG
(which is about 0.96μs), while there is no transmission
session in progress (with respect to MIICRS).
Note: The receive process cannot start while a transmission is in progress.
While the MAX2986 keeps MIIRXDV high, data is sampled synchronously with respect to MIICLK from the
MAX2986 through MIIDAT. After the last byte of data is
received, the MAX2986 resets MIIRXDV.
Receive timing of the MII interface is illustrated in Figure
7, with details in Figure 8 and Table 4.
MIICLK
MIICRS
IFG
MIIRXDV
DATA
MIIDAT
DATA
DATA
DATA
DATA
Figure 7. Receive Behavior of the MII Interface
tOH
MIIDAT
MIIRXDV
MIICRS
tOV
MIICLK
Figure 8. MII Interface—Detailed Receive Timing
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Table 4. MII Interface—Detailed Receive
Timing*
PARAMETER
DESCRIPTION
MAX
UNITS
tOV
Data valid after positive
edge of MIICLK
2.5
ns
tOH
Nominal data hold time
One
MIICLK
period
ns
*Per IEEE 802.3u standard.
Maxim Integrated │ 11
MAX2986
Integrated Powerline Digital Transceiver
Reduced Media
Independent Interface (rMII)
Table 5 describes the signals that provide data, status,
and control to the MAX2986 in rMII mode. In this mode,
data is transmitted and received in bit pairs. The rMII
mode connections are shown in Figure 9.
In case of an error in the received data, to eliminate
the requirement for MIIRXER and still meet the requirement for undetected error rate, MIIDAT[5:4] replaces the
decoded data in the receive stream with 10 until the end
of carrier activity. By this replacement, the CRC check is
guaranteed to detect an error and reject the packet.
Table 5. rMII Signal Description
DATA
LINES
I/O
MIIDAT[1:0]
2
I
Transmit Data. Data are transferred to the interface from the external MAC across these two
lines, one di-bit at a time. MIIDAT[1:0] is 00 to indicate idle when MIITXEN is deasserted.
MIITXEN
1
I
Transmit Enable. This signal indicates to the MAX2986 that valid data is present on the MIIDAT
pins. MIITXEN is asserted synchronously with the first nibble of the preamble and remains
asserted while all di-bits to be transmitted are presented to the rMII.
MIIDAT[5:4]
2
O
MII Receive Data. Data is transferred from the MAX2986 to the external MAC across these two
lines, one di-bit at a time. Upon assertion of MIIRXDV, the MAX2986 ensures that MIIDAT[5:4] =
00 until proper receive decoding takes place.
MIIRXDV
1
O
Receive Data Valid (CRS_DV). When asserted high, MIIRXDV indicates that the incoming data
on the MIIDAT pins are valid.
MIICLK
1
I
rMII Reference Clock. A continuous clock that provides the timing reference for MIIRXDV,
MIIDAT, MIITXEN, and MIIRXER. MIICLK is sourced by the Ethernet MAC or an external source
and its frequency is 5MHz (50MHz) in 10Mbps (100Mbps) data rate.
MII Management Data Clock. A 2.5MHz noncontinuous clock reference for the MIIMDIO signal.
NAME
DESCRIPTION
MANAGEMENT DATA UNIT
MIIMDC
1
I
MIIMDIO
1
I/O
MII Management Data Input/Output. It is a bidirectional signal that carries the data for the
management data interface.
CLOCK SOURCE (5MHz OR 50MHz)
REFCLK
ETHERNET
802.3 MAC
(RMII)
MAX2986
MIICLK
TXEN
MIITXEN
CRS_DV
MIIRXDV
TXD[1:0]
MIIDAT[1:0]
RXD[1:0]
MIIDAT[5:4]
MDC
MIIMDC
MDIO
MIIMDIO
rMII
INTERFACE
MAC
PHY
BUFWR
BUFRD
BUFCS
VCC
Figure 9. MAC-PHY Connection in rMII Mode
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Maxim Integrated │ 12
MAX2986
Integrated Powerline Digital Transceiver
rMII Signal Timing
rMII transmit and receive timing are the same as for MII,
except that the data are sent and received in 2-bit format
and MIICRS is removed.
FIFO Interface Signals
Table 6 describes signals that provide data, status, and
control to and from the MAX2986 in buffering (FIFO)
mode. The FIFO buffering interface is operated in halfduplex mode. MIIRXDV is never asserted at the same
time as MIITXEN, but it is able to start transmission while
receive is in progress. It is highly recommended to give
reception a higher priority to avoid data loss.
On transmit, the MAX2986 asserts MIICRS after MIITXEN
is asserted, and drops it after MIITXEN is deasserted and
when the MAX2986 is ready to get another packet. When
MIICRS falls, it can be asserted again if there is another
packet to send.
Transmissions are modulated onto the wire as soon as
the transfer begins, as the interface fills the MAX2986
buffer faster than data needs to be made available to
the modulator. When a packet arrives at the MAX2986,
it attempts to gain access to the channel. Since this may
not happen before the entire packet is transferred across
the interface, the MAX2986 buffers at least one Ethernet
packet to perform this rate adaptation.
On receive; when the MAX2986 anticipates that it will
have a packet demodulated, it raises MIIRXDV to identify the upper layer that a packet is ready to transmit.
MIIRXDV drops when the last byte is transmitted.
Receive direction transfers have priority over the transmit
direction to ensure that the buffer empties faster than
packets arrive. The minimum receive time is one Tx frame
plus an IFG.
Table 6. FIFO Signal Description
DATA
LINES
I/O
DESCRIPTION
MIIDAT[7:0]
8
I/O
Transmit/Receive Data. Data are transferred to/from the MAX2986 from/to the external MAC
across this bidirectional port, one byte at a time.
MIITXEN
1
I
Transmit Enable [Active High]. This signal indicates to the MAX2986 that the transmission has
started, and that data on MIIDAT should be sampled using BUFWR. MIITXEN remains high to the
end of the session.
MIICRS
1
O
Transmit In Progress [Active High]. When asserted high, MIICRS indicates to the external host
that outgoing traffic is present on the powerline and the host should wait until the signal goes low
before sending additional data.
BUFWR
1
I
Write [Active Low]. Inputs a write signal to the MAX2986 from the external MAC, writing the
present data on MIIDAT pins into the interface buffer on each positive edge.
MIIRXDV
1
O
Receive Data Valid [Active High]. When asserted high, MIIRXDV indicates that the incoming
data on the MIIDAT pins are valid.
MIIRXER
1
O
Receive Error [Active High]. When asserted high, MIIRXER indicates to the external MAC that
an error has occurred during the frame reception.
BUFRD
1
I
Read [Active Low]. Inputs a read signal to the MAX2986 from the external MAC, reading the data
from the MIIDAT pins of the MAX2986 on each positive edge.
BUFCS
1
I
Chip Select [Active Low]. When asserted low, it enables the chip.
MIICLK
1
I
Reference Clock. Used for sampling BUFWR and BUFRD.
NAME
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Maxim Integrated │ 13
MAX2986
Integrated Powerline Digital Transceiver
FIFO Signal Timing—Transmitting
When the external host is ready to transmit a frame and
MIICRS is low (the previous transmission is finished), it
asserts MIITXEN. The external host must assert MIITXEN
if MIIRXDV is not high to avoid data loss. In response,
MIICRS is asserted by the MAX2986. While the external
host keeps MIITXEN high, 1 byte of data is transmitted
into the MAX2986 through MIIDAT for each positive edge
of BUFWR. After transmission of the last byte of data, the
external host resets MIITXEN. Interactions between the
external host and the MAX2986 baseband chip are shown
in Figure 10.
The overall transmission timing of the FIFO interface
is illustrated in Figure 11 with detailed timing shown in
Figure 12 and Table 7.
START
tIH
MIIDAT
MIITXEN
tIS
NO
YES
1
BUFWR
WRITE TO THE
FIFO
INTERFACE
FRAME
AVAILABLE?
Figure 12. FIFO Interface—Detailed Transmit Timing
NO
CRS OR
RXDV
COUNTER =
FRAME LENGTH
YES
0
Table 7. FIFO Interface—Transmit Timing*
PARAMETER
DESCRIPTION
TYP
UNITS
tIS
Setup prior to positive
edge of BUFWR
3
ns
tIH
Hold after positive
edge of BUFWR
Debounce**
MIICLK
+3
ns
RESET
MIITXEN
ASSERT
MIITXEN
*Per IEEE 802.3u standard.
Figure 10. Buffering Transmission Process from the External
Host View
**The default value of the debounce parameter is 3.
MIITXEN
MIICRS
MIIDAT
DATA
DATA
DATA
DATA
DATA
BUFWR
Figure 11. Transmission Timing of the Buffering (FIFO) Interface
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Maxim Integrated │ 14
MAX2986
Integrated Powerline Digital Transceiver
FIFO Signal Timing—Receiving
When a frame is ready to send from the MAX2986 to
the external host, the MAX2986 asserts MIIRXDV after
an IFG (which is about 0.96μs), while there is no transmission session in progress (with respect to MIICRS). A
receive process cannot start while a transmission is in
progress.
While the MAX2986 keeps MIIRXDV high, it sends 1 byte
of data on MIIDAT for each positive edge on BUFRD. The
first 2 bytes represent frame length in MSB-first format.
After the last byte of data is received, the MAX2986 resets
MIIRXDV. The direction of bidirectional data pins is controlled through BUFCS and BUFRD pins. The MAX2986
enables data output drivers when BUFCS = 0 and BUFRD
= 0. The interactions between the external host and the
MAX2986 baseband is shown in Figure 13 and the overall
receive timing of the buffering interface is illustrated in
Figure 14, with details in Figure 15 and Table 8.
START
tOH
MIIDAT
MIIRXDV
MIICRS
tOV
'0'
BUFRD
READ LENGTH
(LSB)
MIIRXDV
'1'
Figure 15. FIFO Interface—Detailed Receive Timing
READ LENGTH
(MSB)
READ FROM
FIFO INTERFACE
NO
COUNTER =
FRAME LENGTH
YES
Figure 13. Buffering (FIFO) Interface Receive Process from the
External Host View
Table 8. FIFO Interface—Receive Timing*
PARAMETER
DESCRIPTION
MIN
UNITS
tOV
Valid after negative
edge of BUFRD
Debounce**
MIICLK
+3
ns
tOH
Hold after positive
edge of BUFRD
0
ns
*Per IEEE 802.3u standard.
**The default value of the debounce parameter is 3.
MIIRXDV
MIIDAT
FRAME LENGTH
(LSB)
FRAME LENGTH
DATA
(MSB)
DATA
DATA
DATA
BUFRD
Figure 14. Receive Timing of the Buffering (FIFO) Interface
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Maxim Integrated │ 15
MAX2986
Integrated Powerline Digital Transceiver
Management Data Unit MDU
The MIIMDIO pin is a bidirectional data pin for the management data interface. The MIIMDC signal is a clock
reference for the MIIMDIO signal. The write behavior of
the management data unit is illustrated in Figure 16. The
read behavior of the management data unit is illustrated
in Figure 17.
Ethernet Interface
The upper layer interface can be selected according to
the pin settings shown in Table 9.
MIIMDC
MIIMDIO
32-BIT
OPTIONAL
PREAMBLE
START
WRITE
5-BIT
PHYSICAL
ADDRESS
5-BIT
REGISTER
ADDRESS
TA
FROM
HOST
16-BIT OF
DATA
FROM HOST
5-BIT
PHYSICAL
ADDRESS
5-BIT
REGISTER
ADDRESS
TA
TO
HOST
16-BIT OF
DATA
FROM HOST
Figure 16. Write Behavior of the Management Data Unit
MIIMDC
MIIMDIO
32-BIT
OPTIONAL
PREAMBLE
START
READ
Figure 17. Read Behavior of the Management Data Unit
Table 9. Upper Layer Interface-Selection
Pin Settings
INTERFACE
GPIO[3]
GPIO[6]
GPIO[4]
MII
1
0
0
rMII
1
0
1
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Maxim Integrated │ 16
MAX2986
Integrated Powerline Digital Transceiver
Figure 18 shows the transmit timing. tTXDV is the time
that data must be valid for after a low-to-high transition on
ETHTXCLK. tTXDH is the time that data must be held after
a low-to-high transition on ETHTXCLK. Figure 19 shows the
receive timing. tRXS is the setup time prior to the positive
edge of ETHRXCLK. tRXH is the hold time after the positive
edge of ETHRXCLK. For further information on the Ethernet
MAC interface, refer to the IEEE 802.3 specification.
USB Interface
Figure 20 shows the structure of a USB cable. The two
pins USBD+ and USBD- are the data pins used in the
USB interface, and correspond to D+ and D- in Figure 20.
VBUS is nominally +5V at the source. Figure 10 shows
the upper layer interface pin setting to select USB. Refer
to the Universal Serial Bus Specification, Revision 1.1 for
more details on the USB interface.
UART Interface
A serial asynchronous communication protocol using the
UART standard interface is implemented in the MAX2986
baseband chip for the purpose of download/debugging
MAC software. To communicate with the current MAC
software, the UART interface must be configured as
shown in Table 11.
To download and debug HomePlug MAC software, a null
modem cable is required to make a serial connection as
shown in Figure 21. The MAX3221 is used as UART driver.
ETHTXCLK
tTXDH
ETHTXEN
ETHTXD[3:0]
ETHTXER
tTXDV
tTXDV < 25ns
MAX2986
MAX3221
BASEBAND
UART
DRIVER
tTXDH > 5ns
UARTTXD
IN
UARTRXD
OUT
DB9 CONNECTOR
1
6
2
7
3
8
4
9
5
Figure 18. Transmit Timing for Ethernet MAC Interface to the
MAX2986
ETHRXCLK
tRXS
Figure 21. MAX2986 UART Interface with Driver and DB9
Connector
tRXH
Table 10. Upper Layer Interface-Selection
Pin Settings
ETHRXD[3:0],
ETHRXDV
tRXS > 10ns
tRXH < 10ns
Figure 19. Receive Timing for Ethernet MAC Interface to the
MAX2986
VBUS
D+
DGND
VBUS
D+
DGND
INTERFACE
GPIO[3]
GPIO[6]
GPIO[4]
USB
0
0
0
Table 11. UART Interface Configuration
Data Rate
115,200bps
Data Length
8 Bits
Stop Bit
1 Bit
Flow Control
None
Figure 20. USB Cable
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Maxim Integrated │ 17
MAX2986
Integrated Powerline Digital Transceiver
Applications Information
Terminating Interfaces
To terminate either of the interfaces, the corresponding I/O pins should be configured as shown in Tables 12–15.
Table 12. Disabling USB Interface
LOCATION
NAME
DIRECTION
C5
USBD-
I/O
Connect to DGND with a 5.1MΩ resistor.
TERMINATE STATUS
B5
USBD+
I/O
N.C. (no connection).
Table 13. Disabling Ethernet Interface
LOCATION
NAME
DIRECTION
TERMINATE STATUS
L9
ETHTXCLK
I
DGND
M4
ETHRXCLK
I
DGND
N2
ETHCOL
I
DGND
N3
ETHCRS
I
DGND
M9
ETHTXEN
O
N.C.
M7
ETHRXDV
I
DGND
N9
ETHTXER
O
N.C.
N7
ETHRXER
I
DGND
M6
ETHRXD[0]
I
DGND
L5
ETHRXD[1]
I
DGND
M5
ETHRXD[2]
I
DGND
N5
ETHRXD[3]
I
DGND
M8
ETHTXD[0]
O
N.C.
N8
ETHTXD[1]
O
N.C.
L8
ETHTXD[2]
O
N.C.
L7
ETHTXD[3]
O
N.C.
M3
ETHMDC
O
N.C.
N4
ETHMDIO
I/O
N.C.
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Maxim Integrated │ 18
MAX2986
Integrated Powerline Digital Transceiver
Table 14. Disabling MII/rMII/FIFO Interface
LOCATION
NAME
DIRECTION
TERMINATE STATUS
K11
MIICRS
O
N.C.
F11
MIITXEN
I
DGND
DGND
N10
MIICLK
I
J12
MIIDAT[7]
I/O
N.C.
K12
MIIDAT[6]
I/O
N.C.
J13
MIIDAT[5]
I/O
N.C.
L12
MIIDAT[4]
I/O
N.C.
N11
MIIDAT[3]
I/O
N.C.
N12
MIIDAT[2]
I/O
N.C.
N13
MIIDAT[1]
I/O
N.C.
L13
MIIDAT[0]
I/O
N.C.
L11
MIIRXER
O
N.C.
H10
MIIRXDV
O
N.C.
H12
BUFCS
I
VDD
H11
BUFRD
I
VDD
H13
BUFWR
I
VDD
J11
MIIMDC
I
DGND
K13
MIIMDIO
I/O
N.C.
Table 15. Disabling UART
LOCATION
NAME
DIRECTION
TERMINATE STATUS
UARTTXD
K7
O
N.C.
UARTRXD
L6
I
VDD
Note: Disabling the UART interface disables the MAC code update and FLASH programming features of the chip.
Interfacing the MAX2986 to the
MAX2980 Analog Front End (AFE)
The interface to the MAX2980 AFE chip uses a bidirectional bus to pass the digital data to and from the DAC
and ADC. Handshake lines help accomplish the data
transfer as well as operation of the AFE. Figure 22 shows
the interface signals. For AFE pin configuration/description, refer to the MAX2980 data sheet.
MAX2980
MAX2986
AFE
BASEBAND
ADC/DAC
AFEDAT[9:0]
ENREAD
ENTX
SHRCRV
CS
AFEREN
AFETXEN
AFEPDRX
CLK
RESETIN
SHDN
SCLK
SDI/O
SWR
AFEFRZ
AFECLK
AFERESET
GPIO[7]
SI CLOCK
GPIO[4]
R/W SERIAL DATA
GPIO[5]
SERIAL R/W SELECT
GPIO[6]
Figure 22. MAX2980 AFE Interface to the MAX2986
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Maxim Integrated │ 19
MAX2986
Integrated Powerline Digital Transceiver
Table 16. MAX2986 to AFE Signal Interface Description
DATA
LINES
I/O
AFETXEN
1
O
AFE Transmit Enable. The AFETXEN signal is used to enable the transmitter of the
AFE. When AFETXEN and AFEREN are high, data is sent through the AFEDAD[9:0] to
the DAC and then into the powerline.
AFEREN
1
O
Setting Bus Direction. The AFEREN signal sets the direction of the data bus
AFEDAD[9:0]. When high, data can be sent from the MAX2986 to the DAC in the AFE,
and when low, data is sent from the ADC to the MAX2986.
NAME
DESCRIPTION
AFEPDRX
1
O
AFE Receiver Power-Down. When the AFE is in transmit mode, the AFEPDRX signal
goes high, the receiver section of the AFE is powered down. The MAX2980 features a
transmit power-saving mode that reduces current dissipation. To use this power-saving
mode, lower AFEPDRX prior to the end of a transmission. If this mode is not required,
connect AFEPDRX to AFETXEN and AFEREN.
AFEDAD[9:0]
10
I/O
AFE 10-Bit ADC and DAC Bus. AFEDAD[9:0] is the 10-bit bidirectional bus that connects
the MAX2986 to the AFE DAC and ADC. The direction of the bus is controlled by AFEREN
described above.
AFEFRZ
1
O
AFE Receive AGC Control. The AFEFRZ signal controls the AGC circuit in the receive
path in the AFE. When this signal is low, the gain circuit on the input signal continuously
adapts for maximum sensitivity. This signal is raised high when the MAX2986 detects
a valid preamble. After the AFEFRZ signal is raised high, it continues to adapt for an
additional short period of time, then it locks the currently adapted level on the incoming
signal. The MAX2986 holds AFEFRZ high while receiving a transmission, and then lowers
for continuous adaptation for maximum sensitivity of other incoming signals.
AFECLK
1
O
AFE Clock. A 50MHz clock generated for the MAX2980 AFE.
AFERESET
1
O
AFE Reset. To perform a reset on the MAX2980 AFE, AFECLK must be free running and
AFERESET must be LOW for typically 1s. A reset must be performed at power-up.
GPIO[6]
1
O
AFE Serial Interface Read/Write Select.
GPIO[5]
1
I/O
AFE Serial Interface Data (Write/Read).
GPIO[4]
1
O
AFE Serial Interface Clock.
GPIO[7]
1
O
AFE Power-Down.
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Maxim Integrated │ 20
MAX2986
Integrated Powerline Digital Transceiver
AFE Timing
2) Simple code downloaded through UART:
Figure 23 illustrates the relationship of the AFE input clock
and the data into the DAC and out of the ADC.
The MAX2986 is configurable to accept code image
from the UART. The first 4 bytes of the image specify
the memory location in SSRAM to which the binary
image should be copied (0x2020000–0x203FFFF).
The next 4 bytes specify the length of the image
(excluding 8 header and 4 tail bytes), in terms of
words. The specified length cannot be greater than
128kB (size of SSRAM) and must be nonzero, otherwise the boot will restart simple code downloaded
through the UART after issuing an appropriate error
message to the host. The last 4 bytes of image are the
checksum. After the image is loaded and checksum is
valid, the image is launched by jumping to the target
(destination) address, otherwise, the boot restarts
simple code downloaded through the UART.
AFE Serial Interface
The AFE configuration signals GPIO[4], GPIO[5], and
GPIO[6] are used to program the AFE internal registers.
GPIO[4] is the serial clock; GPIO[5] is the bidirectional
data line for register reprogramming and reading, and
when GPIO[6] is asserted HIGH, the registers are in
write mode. Drive these lines low if not used. Refer to the
MAX2980 data sheet for more information on the AFE
serial interface timing.
Upgrading and Programming MAC
There are wide ranges of boot options that provide good
flexibility in running code applications on the MAX2986
through different chip interfaces. The selection of different boot modes is possible through boot pins and flash
type pins, which are sensed during the MAX2986 startup
process. There are two boot modes:
1) Downloading encrypted flash-resident code:
The image can be downloaded into flash memory
using either an I2C™ or SPI™ interface. The code
image address is stored at the start of flash memory.
The encrypted code image in flash can be updated
using TFTP protocol.
Five pins are used to determine the boot mode. Table 17
shows the corresponding settings (PU: pulled up, PD:
pulled down, X: don’t care). Pullup and pulldown resistors are 10kΩ. GPIO[8] and GPIO[10] are two pins that
are used for flash operations. These two pins are output
in flash operations but they would be input in the system
boot process.
If an error occurs during the boot process, the error
code is indicated on the LED pins: GPIO[21] (LED0_
BP0), GPIO[22] (LED1_BP1), and GPIO[23] (LED2_BP2)
tCLK
50MHz AFE CLK
tADCO
ADC DATA OUTPUT
tDACI
DAC DATA INPUT
tCLK = 20ns
tADCO = 2ns
tDACI = 3ns
Figure 23. AFE ADC and DAC Timing Diagram
Purchase of I2C components from Maxim Integrated Products, Inc., or one of its sublicensed Associated Companies, conveys a
license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C
Standard Specification as defined by Philips.
SPI is a trademark of Motorola, Inc.
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Maxim Integrated │ 21
MAX2986
Integrated Powerline Digital Transceiver
according to Table 18. Pullup/pulldown resistors for LEDs
are 1kΩ or less.
integrated PLLs. Figure 24 illustrates how to connect a
crystal to the MAX2986. If the external clock oscillator is
used, leave XOUT unconnected as shown in Figure 25.
The states of GPIO pins and initialization pins during
the boot process are shown in Table 17. See the Pin
Description for more information.
Since the reset signal RESET is used in PLL modules, it
must be activated after the PLL clock generation delay,
which is about 0.5ms.
Clocks and Reset
GPIO Pin Usage
The MAX2986 has a built-in oscillator that requires an
external crystal. Use a 30MHz crystal with stability of
±25ppm max over operating temperature. All other necessary clocks are generated internally by means of two
The MAX2986 firmware makes special use of GPIO pins
as described in Table 19. GPIO pins are utilized in input,
output, or both directions.
Table 17. Boot Modes
BOOT MODE
Encrypted image
downloaded
from flash
BOOT/FT PINS
FLASH TYPE
GPIO[23]
GPIO[22]
GPIO[21]
GPIO[8]
GPIO[10]
Flash type is SPI
(AT45DB)
0
1
0
PU
PU
Flash type is SPI
(SST25VF)
1
1
0
PU
PU
Flash type is I2C
X
1
0
PD
PU
X
0
0
0
X
PU*
Code
downloaded
through UART
X = Don’t care.
*PU: If pin GPIO[10] is pulled down instead of pulled up, it indicates that there is no flash device connected to the chip. If this is the
case and if LED0_BP0 = LED1_BP1 = 0, then the GPIO[8] line must be pulled up.
Table 18. Boot Error Codes
LED2_BP2
LED1_BP1
LED0_BP0
0
0
1
The flash does not contain a valid image.
0
1
0
The size of the image is more than 128kB.
0
1
1
The base address of the image is out of the allowed range.
1
0
0
Checksum error.
1
0
1
No flash is available.
1
1
0
Invalid boot mode.
1
1
1
0
0
0
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BOOT STATUS
No error.
Maxim Integrated │ 22
MAX2986
Integrated Powerline Digital Transceiver
CLOCK OSCILLATOR
OUT
XIN
CRYSTAL
30MHz
RF
1MΩ
MAX2986
XOUT
C1
15pF
XIN
30MHz
C2
15pF
Figure 24. Connecting a Crystal to the MAX2986
www.maximintegrated.com
MAX2986
N.C.
XOUT
Figure 25. Connecting a Clock Oscillator to the MAX2986
Maxim Integrated │ 23
MAX2986
Integrated Powerline Digital Transceiver
Table 19. GPIO Pin Usage by the MAX2986 Firmware
LOCATION
GPIO
MAX2986 EV KIT USE
C4
GPIO[23]
HPACT_BP2
Output: Drive AFE interface activity LED
Input: Boot pin 2
A5
GPIO[22]
HPLINK_BP1
Output: Drive AFE interface link status LED
Input: Boot pin 1
B6
GPIO[21]
HPCOL_BP0
Output: Drive AFE interface collision LED
Input: Boot pin 0
C9
GPIO[13]
PID2
Output: None
Input: Processor ID, bit 2
B9
GPIO[12]
PID1
Output: None
Input: Processor ID, bit 1
A9
GPIO[11]
PID0
Output: None
Input: Processor ID, bit 0
B10
GPIO[10]
IWCS_FT1
Output: Flash interface chip select
Input: Nonvolatile memory bit 1
A10
GPIO[9]
ISDAT
Output: Flash interface data (write)
Input: Flash interface data (read)
B11
GPIO[8]
ISCL_FT0
Output: Flash interface serial clock
Input: Nonvolatile memory, bit 0
A11
GPIO[7]
PDAFE
B12
GPIO[6]
AWR_UL1
A12
GPIO[5]
ASDAT
A13
GPIO[4]
ASCL_UL0
Output: AFE serial interface clock
Input: Upper layer interface select, bit 0
B4
GPIO[3]
UL2
Output: None
Input: Upper layer interface select, bit 2
A4
GPIO[2]
—
www.maximintegrated.com
DESCRIPTION
Output: AFE power-down
Input: None
Output: AFE serial interface write
Input: Upper interface select, bit 1
Output: AFE serial interface data (write)
Input: AFE serial interface data (read)
Output: It is used to control external USB circuit
Input: None
Maxim Integrated │ 24
MAX2986
Integrated Powerline Digital Transceiver
MAX2980 AFE
MAX2986 PHY/MAC
10-BIT
DATA BUS
4-BIT Rx
ETHERNET
CONNECTOR
802.3
ETHERNET
MAC
MII
CONTROLLER
4-BIT Tx
MAC
DSP
SIGNALING
CONTROL
LINE
DRIVE
DAC
HPF
ADC
LPF/AGC
SERIAL BUS
SIGNALING
CONTROL
POWERLINE
Figure 26. Powerline Baseband to MII Application Block Diagram
MAX2980 AFE
MAX2986 PHY/MAC
10-BIT
DATA BUS
USB
CONNECTOR
USB
1.1
MAC
DSP
SIGNALING
CONTROL
LINE
DRIVE
DAC
HPF
ADC
LPF/AGC
SERIAL BUS
CONTROL
Figure 27. Powerline Baseband to USB Application Block Diagram
MAX2980 AFE
MAX2986 PHY/MAC
10-BIT
DATA BUS
FIFO
8-BIT
DATA BUS
FIFO
SIGNALING CONTROLLER
CONTROL
MAC
DSP
SIGNALING
CONTROL
SERIAL BUS
DAC
LINE
DRIVE
HPF
ADC
LPF/AGC
CONTROL
Figure 28. Powerline Baseband to FIFO Application Block Diagram
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Maxim Integrated │ 25
MAX2986
Integrated Powerline Digital Transceiver
Typical Application Circuit
MAX2986 PHY/MAC
MAX2980 AFE
10-BIT
DATA BUS
4-BIT Rx
ETHERNET
CONNECTOR
ETHERNET
PHY
4-BIT Tx
SIGNALING
EMBEDDED
HOMEPLUG
802.3
MAC
ETHERNET
MAC
DSP
SIGNALING
CONTROL
SERIAL BUS
DAC
LINE
DRIVE
HPF
ADC
LPF/AGC
CONTROL
POWERLINE
Chip Information
PROCESS: CMOS
www.maximintegrated.com
Maxim Integrated │ 26
MAX2986
Integrated Powerline Digital Transceiver
Pin Configuration
1
2
3
4
5
6
7
8
9
10
11
12
13
A
DVDD
DVSS
AVDD
GPIO[2]
GPIO[22]
VDD33
GPIO[17]
GPIO[14]
GPIO[11]
GPIO[9]
GPIO[7]
GPIO[5]
GPIO[4]
A
B
DGND
AVSS
GPIO[0]
GPIO[3]
USBD+
GPIO[21]
GPIO[18]
GPIO[15]
GPIO[12]
GPIO[10]
GPIO[8]
GPIO[6]
N.C.
B
C
VDD33
DGND
GPIO[1]
GPIO[23]
USBD-
GPIO[20]
GPIO[19]
GPIO[16]
GPIO[13]
VDD18
JTMS
JTDI
VDD33
C
D
N.C.
USBRESET
RESET
DGND
DGND
DGND
DGND
DGND
DGND
VDD18
N.C.
N.C.
N.C.
D
E
N.C.
JRTCLK
DGND
AFEFRZ
VDD18
DGND
DGND
DGND
E
F
AFETXEN
XIN
XOUT
DGND
VDD18
MIITXEN
VDD33
DGND
F
G
AFERESET AFEDAD[0] AFEDADI1] AFEDAD[2]
VDD18
JTDO
JTRST
JTCK
G
H
AFEDAD[3] AFEDAD[4] AFEDAD[5] AFEDAD[6]
MIIRXDV
BUFRD
BUFCS
BUFWR
H
VDD18
MIIMDC
MIIDAT[7]
MIIDAT[5]
J
VDD18
MIICRS
MIIDAT[6]
MIIMDIO
K
ETHTXD[3] ETHTXD[2] ETHTXCLK
VDD33
MIIRXER
MIIDAT[4]
MIIDAT[0]
L
MAX2986
AFEDAD[7] AFEDAD[8] AFEDAD[9]
J
VDD33
K
AFECLK
AFEREN
AFEPDRX
N.C.
L
VDD33
DVDD
DVSS
VDD33
M
AVDD
AVSS
ETHMDC
ETHRXCLK ETHRXD[2] ETHRXD[0]
ETHRXDV
ETHTXD[0]
ETHTXEN
DGND
DGND
N.C.
VDD33
M
N
DGND
ETHCOL
ETHCRS
ETHMDIO
ETHRXD[3]
DGND
ETHRXER
ETHTXD[1]
ETHTXER
MIICLK
MIIDAT[3]
MIIDAT[2]
MIIDAT[1]
N
1
2
3
4
5
6
7
8
9
10
11
12
13
DGND
DGND
ETHRXD[1] UARTRXD
UARTTXD
DGND
DGND
CSBGA
www.maximintegrated.com
Maxim Integrated │ 27
MAX2986
Integrated Powerline Digital Transceiver
Package Information
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
PACKAGE OUTLINE,
144 BALL CSBGA, 12x12x1.4mm, 0.8mm PITCH
21-0163
A
1
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
© 2004 Maxim Integrated Products, Inc. │ 28
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