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MAX32652GWE+T

MAX32652GWE+T

  • 厂商:

    AD(亚德诺)

  • 封装:

    140-WFBGA, WLBGA

  • 描述:

    IC MCU 32BIT 3MB FLASH 140WLP

  • 数据手册
  • 价格&库存
MAX32652GWE+T 数据手册
EVALUATION KIT AVAILABLE MAX32650–MAX32652 General Description DARWIN is a new breed of low-power microcontrollers built to thrive in the rapidly evolving Internet of Things (IoT). They are smart, with the biggest memories in their class and a massively scalable memory architecture. They run forever, thanks to wearable-grade power technology. They are also tough enough to withstand the most advanced cyberattacks. DARWIN microcontrollers are designed to run any application imaginable—in places where you would not dream of sending other microcontrollers. Generation UP microcontrollers are designed to handle the increasingly complex applications demanded by today’s advanced battery-powered devices and wireless sensors. The MAX32650–MAX32652 are ultra-low power memory-scalable microcontrollers designed specifically for high-performance, battery-powered applications. They are based on Arm® Cortex®-M4 with FPU CPU with 3MB flash and 1MB SRAM. Memory scalability is supported with multiple memory-expansion interfaces, including a HyperBus™/Xccela™ DDR interface and two SPI execute in place (SPIX) interfaces. A secure digital interface supports external high-speed memory cards, including SD, SDIO, MMC, SDHC, and microSD™. Power management features provide five low power modes for clock, peripheral, and voltage control. Individual SRAM banks of 32KB, 96KB, or 1024KB (full retention) can be retained with reduced power consumption. A SmartDMA performs complex background processing while the CPU is off to dramatically reduces overall power consumption. The MAX32651 is a secure version with a trust protection unit (TPU) that provides a modular arithmetic accelerator (MAA) for fast ECDSA, an AES engine, TRNG, SHA-256 hash, and secure bootloader. A memory decryption integrity unit (MDIU) provides on-the-fly data decryption (plain or executable) stored in external flash. The MAX32652 is a high-density, 0.35mm pitch, 140bump WLP package targeted for tiny form factor products that require high I/O counts. Ultra-Low-Power Arm Cortex-M4 with FPU-Based Microcontroller (MCU) with 3MB Flash and 1MB SRAM Benefits and Features ●● Ultra-Efficient Microcontroller for Battery-Powered Applications • 120MHz Arm Cortex-M4 with FPU • SmartDMA Provides Background Memory Transfers with Programmable Data Processing • 120MHz High-Speed and 40MHz Low-Power Oscillators • 7.3728MHz Low-Power Oscillators • 32.768kHz and RTC Clock (Requires External Crystal) • 8kHz Always-On Ultra-Low Power Oscillator • 3MB Internal Flash, 1MB Internal SRAM • 104μW/MHz Executing from Cache at 1.1V • Five Low Power Modes: Active, Sleep, Background, Deep-Sleep, and Backup • 1.8V and 3.3V I/O with No Level Translators​ ●● Scalable Cached External Memory Interfaces: • 120MB/s HyperBus/Xccela DDR Interface • SPIXF/SPIXR for External Flash/RAM Expansion • 240Mbps SDHC/eMMC/SDIO/microSD Interface ●● Optimal Peripheral Mix Provides Platform Scalability • 16-Channel DMA • Three SPI Master (60MHz)/Slave (48MHz) • One QuadSPI Master (60MHz)/Slave (48MHz) • Up to Three 4Mbaud UARTs with Flow Control • Two 1MHz I2C Master/Slave • I2S Slave • Four-Channel 7.8ksps 10-Bit Delta-Sigma ADC • USB 2.0 Hi-Speed Device Interface with PHY • 16 Pulse Train Generators • Six 32-Bit Timers with 8mA High Drive • 1-Wire Master ●● Trust Protection Unit (TPU) for IP/Data Security • Modular Arithmetic Accelerator (MAA), True Random Number Generator (TRNG) • Secure Nonvolatile Key Storage, SHA-256, AES-128/192/256 • Memory Decryption Integrity Unit, Secure Boot ROM Applications ●● Sports Watches, Fitness Monitors ●● Wearable Medical Patches, Portable Medical Devices ●● Industrial Sensors, IoT Arm and Cortex are registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere. HyperBus is a trademark of Spansion. Xccela is a trademark of Micron Technology, Inc. MicroSD is a trademark of SD-3C, LLC. 19-100220; Rev 3; 12/18 Ordering Information appears at end of data sheet. MAX32650–MAX32652 Ultra-Low-Power Arm Cortex-M4 with FPU-Based Microcontroller (MCU) with 3MB Flash and 1MB SRAM Simplified Block Diagram MAX32650/MAX32651/MAX32652 120MHz 40MHz 32.768kHz 8kHz TCK/SWCLK TMS/SWDIO TDO TDI SECURE DIGITAL INTERFACE HOST ARM CORTEX. M4 WITH FPU CPU 7.3728MHz NVIC JTAG SWD (SERIAL WIRE DEBUG) MEMORY FLASH 3MB VDDIOH VDDIO VCORE VDDA VRTC VSS VSSA 32KOUT 32KIN POR, BROWNOUT MONITOR, SUPPLY VOLTAGE MONITORS SRAM 1MB 16KB CACHE VOLTAGE REGULATION & POWER CONTROL STANDARD DMA SMART DMA RTC BUS MATRIX – AHB, APB, IBUS, DBUS… RSTN 8 BYTE Tx/ Rx FIFOS 2 x I2C MASTER/ SLAVE 32 BYTE Tx/Rx FIFOS 3 x 4-WIRE UART 32 BYTE Tx/Rx FIFOS 3 x SPI MASTER/ SLAVE (4 CS) 32 BYTE Tx/Rx FIFOS QSPI MASTER/ SLAVE (4 CS) 16KB CACHE QSPI FLASH XIP MASTER 32 BYTE Tx/Rx FIFOS I2S SLAVE 1-WIRE MASTER DP DM VDDB USB 2.0 Hi-SPEED CONTROLLER TIMERS/PWM CAPTURE/ COMPARE SDHC HYPERBUS XCCELA BUS I2S SPI QSPI QSPI XIP I2C UART 1-WIRE LCD CONTROLLER 6 x 32-BIT TIMERS 24-BIT LCD CONTROLLER 16KB CACHE UNIQUE ID QSPI SRAM XIP MASTER HYPERBUS /XCCELA BUS HYP_CLKN HYP_CLK AIN0 AIN1 AIN2 AIN3 TRUST PROTECTION UNIT (TPU) (MAX32651 ONLY) MODULAR ARITHMETIC ACCELERATOR (MAA) TRUE RANDOM NUMBER GENERATOR (TRNG) 10-BIT ΣΔ ADC ÷5 ÷5 ÷4 SECURE NV KEY SHA-256 AES-128, -192, -256 SECURE BOOT ROM MEMORY DECRYPTION INTEGRITY UNIT (MDIU) www.maximintegrated.com GPIO /SPECIAL FUNCTION UP TO 105 EXTERNAL INTERRUPTS 16 × PULSE TRAIN ENGINES 2 × WATCHDOG TIMER CRC 16/32 SHARED PAD FUNCTIONS ÷4 ÷4 ÷2 VDDB VDDA VCORE VRTC VDDIO VDDIOH Maxim Integrated │  2 MAX32650–MAX32652 Ultra-Low-Power Arm Cortex-M4 with FPU-Based Microcontroller (MCU) with 3MB Flash and 1MB SRAM Absolute Maximum Ratings (All voltages with respect to VSS, unless otherwise noted.) VCORE...................................................................-0.3V to 1.21V VDDA.....................................................................-0.3V to 1.98V VDDIO....................................................................-0.3V to 1.98V VDDIOH....................................................................-0.3V to 3.6V VRTC......................................................................-0.3V to 1.98V RSTN, GPIO (VDDIO)............................... -0.3V to VDDIO + 0.5V GPIO (VDDIOH)...................................... -0.3V to VDDIOH + 0.5V 32KIN, 32KOUT.........................................-0.3V to VRTC + 0.2V AIN[1:0]...................................................................-0.3V to 5.5V AIN[3:2]..................................................... -0.3V to VDDA + 0.2V VDDB.......................................................................-0.3V to 3.6V DM, DP....................................................................-0.3V to 3.6V HYP_CLK, HYP_CLKN, P1.[21:18], P1.[16:11], P3.0...-0.3V to VDDIO + 0.3V not to exceed 1.98V VDDIO pins (sink)...............................................................100mA VDDIOH pins (sink)............................................................100mA VSSA..................................................................................100mA VSS....................................................................................100mA Output Current (sink) by Any GPIO Pin..............................25mA Output Current (source) by Any GPIO Pin.........................-25mA Continuous Package Power Dissipation TQFP (multilayer board) TA = +70°C (derate 45.5mW/°C above +70°C).....2857.10mW Operating Temperature Range.......................... -40°C to +105°C Storage Temperature Range............................. -65°C to +150°C Soldering Temperature.....................................................+260°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Package Information 140 WLP PACKAGE CODE W1404A4+1 Outline Number 21-100219 Land Pattern Number Refer to Application Note 1891 Thermal Resistance, Four-Layer Board: Junction to Ambient (θJA) 35.13°C/W Junction to Case (θJC) N/A 96 WLP PACKAGE CODE W964A4+1 Outline Number 21-100240 Land Pattern Number Refer to Application Note 1891 Thermal Resistance, Four-Layer Board: Junction to Ambient (θJA) 33.61°C/W Junction to Case (θJC) N/A 144 TQFP PACKAGE CODE C144+1 Outline Number 21-0087 Land Pattern Number 90-0144 Thermal Resistance, Four-Layer Board: Junction to Ambient (θJA) 28°C/W Junction to Case (θJC) 8°C/W For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial. www.maximintegrated.com Maxim Integrated │  3 MAX32650–MAX32652 Ultra-Low-Power Arm Cortex-M4 with FPU-Based Microcontroller (MCU) with 3MB Flash and 1MB SRAM Electrical Characteristics (Limits are 100% tested at TA = +25°C and TA = +105°C. Limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production tested. Specifications to the minimum operating temperature are guaranteed by design and are not production tested. General Purpose I/O are only tested at TA = +105°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS POWER Supply Voltage, Core 0.99 1.1 1.21 V VDDA 1.71 1.8 1.89 V Supply Voltage, RTC VRTC 1.71 1.8 1.89 V Supply Voltage, GPIO VDDIO 1.71 1.8 1.89 V Supply Voltage, GPIO (High) VDDIOH 1.71 1.8 3.6 V Supply Voltage, Analog VCORE fSYS_CLK = 120MHz Monitors VCORE 0.835 Monitors VDDA 1.67 Monitors VRTC 1.67 Power-Fail Reset Voltage VRST Monitors VDDIO 1.67 Power-Fail Reset Voltage VRST Monitors VDDB 2.95 V Power-Fail Reset Voltage VRST Monitors VDDIOH 1.67 V Monitors VCORE 0.594 Monitors VDDA 1.52 Monitors VRTC 1.17 Power-On Reset Voltage RAM Data Retention Voltage VCORE Dynamic Current, Active Mode VCORE Fixed Current, Active Mode VDDA Fixed Current, Active Mode www.maximintegrated.com VPOR VDRV ICORE_DACT ICORE_FACT IDDA_FACT Total current into VCORE pins, fSYS_CLK = 120MHz, VCORE = 1.1V, CPU in Active mode, executing from cache, inputs tied to VSS, VDDIO, or VDDIOH, outputs source/sink 0mA V V 0.81 V 95 μA/MHz 120MHz oscillator enabled, total current into VCORE pins, CPU in Active mode 0MHz execution, inputs tied to VSS, VDDIO, or VDDIOH, outputs source/sink 0mA 1020 7.3728MHz oscillator enabled, total current into VCORE pins, CPU in Active mode 0MHz execution, inputs tied to VSS, VDDIO, or VDDIOH, outputs source/sink 0mA 356 120MHz oscillator enabled, total current into VDDA pins, CPU in Active mode 0MHz execution, inputs tied to VSS, VDDIO, or VDDIOH, outputs source/sink 0mA , VCORE and VDDA voltage monitors enabled 348 7.3728MHz oscillator enabled, total current into VDDA pins, CPU in Active mode 0MHz execution, inputs tied to VSS, VDDIO, or VDDIOH, outputs source/sink 0mA , VCORE and VDDA voltage monitors enabled 39 μA μA Maxim Integrated │  4 MAX32650–MAX32652 Ultra-Low-Power Arm Cortex-M4 with FPU-Based Microcontroller (MCU) with 3MB Flash and 1MB SRAM Electrical Characteristics (continued) (Limits are 100% tested at TA = +25°C and TA = +105°C. Limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production tested. Specifications to the minimum operating temperature are guaranteed by design and are not production tested. General Purpose I/O are only tested at TA = +105°C.) PARAMETER VCORE Dynamic Current, Sleep Mode VCORE Fixed Current, Sleep Mode VDDA Fixed Current, Sleep Mode SYMBOL ICORE_DSLP ICORE_FSLP IDDA_FSLP CONDITIONS MIN TYP Total current into VCORE pins, CPU in Sleep mode, standard DMA with two channels active 114 fSYS_CLK = 120MHz, total current into VCORE pins, CPU in Sleep mode, standard DMA with two channels active 1020 fSYS_CLK = 7.3728MHz, total current into VCORE pins, CPU in Sleep mode, standard DMA with two channels active 356 fSYS_CLK = 120MHz, total current into VDDA pins, CPU in Sleep mode, Standard DMA with two channels active 348 fSYS_CLK = 7.3728MHz, total current into VDDA pins, CPU in Sleep mode, standard DMA with two channels active 49 MAX UNITS μA/MHz μA μA VCORE Dynamic Current, Background Mode ICORE_DBKG fSYS_CLK = 7.3728MHz, total current into VCORE pins, CPU in Deep-sleep mode, SmartDMA active 66 μA/MHz VCORE Fixed Current, Background Mode ICORE_FBGD 7.3728MHz oscillator enabled, total current into VCORE pins, CPU in Deep-sleep mode, SmartDMA active 162 μA VCORE Fixed Current, Deep-Sleep Mode ICORE_FDSL Standby state with full data retention 70 μA Standby state with full data retention, VCORE and VDDA voltage monitors enabled 132 nA VDDA Fixed Current, Deep-Sleep Mode IDDA_FDSL VRTC Fixed Current, Deep-Sleep Mode IDDRTC_FDSL Standby state with full data retention, VRTC = 1.8V, RTC enabled 540 nA VCORE Fixed Current, Backup Mode ICORE_FBKU No SRAM retention (0KB) 30 nA VDDA voltage monitor enabled 132 nA RTC enabled, retention regulator off 540 RTC enabled, 32KB SRAM retained, retention regulator on 720 RTC disabled, retention regulator off 156 VDDA Fixed Current, Backup Mode VRTC Fixed Current, Backup Mode IDDA_FBKU IDDRTC_FBKU Sleep Mode Resume Time tSLP_ON Deep-Sleep Mode Resume Time tDSL_ON Backup Mode Resume Time tBKU_ON www.maximintegrated.com 575 Wake to 40MHz 9 Wake to 120MHz 18 5 nA ns μs ms Maxim Integrated │  5 MAX32650–MAX32652 Ultra-Low-Power Arm Cortex-M4 with FPU-Based Microcontroller (MCU) with 3MB Flash and 1MB SRAM Electrical Characteristics (continued) (Limits are 100% tested at TA = +25°C and TA = +105°C. Limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production tested. Specifications to the minimum operating temperature are guaranteed by design and are not production tested. General-purpose I/O are only tested at TA = +105°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX 3.0 3.3 3.6 UNITS USB USB Supply Voltage D+, D- Pin Capacitance Driver Output Resistance VDDB CIN_USB RDRV Pin to VSS Steady state drive V 8 pF 45 ±10% Ω USB/FULL SPEED Single-Ended Input High Voltage (DP, DM) VIH_USB Single-Ended Input Low Voltage (DP, DM) VIL_USB Output High Voltage (DP, DM) VOH_USB RL = 1.5 kΩ from DP and DM to VSS, IOH = -4mA Output Low Voltage (DP, DM) VOL_USB 2.0 V 0.6 V VDDB 0.4 VDDB V RL = 1.5 kΩ from DP to VDDB, IOL = 4mA VSS 0.4 V Differential Input Sensitivity VDI |DP to DM| 0.2 Common Mode Voltage Range VCM Includes VDI range 0.8 2.5 V Transition Time (Rise/Fall) D+, D- (Note 11) tRF CL = 50pF 4 20 ns Pullup Resistor on Upstream Ports RPU 1.05 1.95 kΩ Hi-Speed Data Signaling Common-Mode Voltage Range VHSCM -50 +500 mV Hi-Speed Squelch Detection Threshold VHSSQ Hi-Speed Idle Level Output Voltage VHSOI -10 +10 mV Hi-Speed Low Level Output Voltage VHSOL -10 +10 mV Hi-Speed High Level Output Voltage VHSOH 400 ± 40 mV Chirp-J Output Voltage (Differential) VCHIRPJ 900 ±200 mV Chirp-K Output Voltage (Differential) VCHIRPK -700 ±200 mV V 1.5 USB/HI-SPEED www.maximintegrated.com Squelch detected 100 No squelch detected 200 mV Maxim Integrated │  6 MAX32650–MAX32652 Ultra-Low-Power Arm Cortex-M4 with FPU-Based Microcontroller (MCU) with 3MB Flash and 1MB SRAM Electrical Characteristics (continued) (Limits are 100% tested at TA = +25°C and TA = +105°C. Limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production tested. Specifications to the minimum operating temperature are guaranteed by design and are not production tested. General Purpose I/O are only tested at TA = +105°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 120,000 kHz CLOCKS System Clock Frequency fSYS_CLK System Clock Period tSYS_CLK High-Speed Oscillator Frequency fHSCLK Low-Power Oscillator Frequency 0.256 1/fSYS_CLK ns 120 ±1 MHz fLPCLK 40 MHz 7MHz Oscillator Frequency f7MCLK 7.3728 MHz Nano-Ring Oscillator Frequency fNANO 8 KHz 32.768 kHz 0.39 μA 250 ms RTC Input Frequency RTC Operating Current RTC Power Up Time f32KIN IRTC_ACTSLP Measured at +25°C, 120MHz 32kHz watch crystal, CL = 6pF, ESR < 70kΩ Sleep or Active mode tRTC_ ON GENERAL-PURPOSE I/O Input Low Voltage for All GPIO VIL_VDDIO Input Low Voltage for All GPIO except P1.[21:18], P1.[16:11], P3.0 VIL_VDDIOH Input Low Voltage for RSTN VIL_RSTN Input High Voltage for All GPIO VIH_VDDIO Input High Voltage for All GPIO except P1.[21:18], P1.[16:11], P3.0 VIH_VDDIOH Input High Voltage for RSTN Output Low Voltage for All GPIO www.maximintegrated.com VDDIO selected as I/O supply VDDIOH selected as I/O supply VDDIO selected as I/O supply VDDIOH selected as I/O supply VIH_RSTN VOL_VDDIO 0.3 × VDDIO V 0.3 × VDDIOH V 0.3 × VDDIO V 0.75 × VDDIO V 0.75 × VDDIOH V 0.75 x VDDIO V VDDIO selected as I/O supply, VDDIO = 1.71V, DS[1:0] = 00, IOL = 1mA 0.2 0.4 VDDIO selected as I/O supply, VDDIO = 1.71V, DS[1:0] = 01, IOL = 2mA 0.2 0.4 VDDIO selected as I/O supply, VDDIO = 1.71V, DS[1:0] = 10, IOL = 4mA 0.2 0.4 VDDIO selected as I/O supply, VDDIO = 1.71V, DS[1:0] = 11, IOL = 8mA 0.2 0.4 V Maxim Integrated │  7 MAX32650–MAX32652 Ultra-Low-Power Arm Cortex-M4 with FPU-Based Microcontroller (MCU) with 3MB Flash and 1MB SRAM Electrical Characteristics (continued) (Limits are 100% tested at TA = +25°C and TA = +105°C. Limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production tested. Specifications to the minimum operating temperature are guaranteed by design and are not production tested. General-purpose I/O are only tested at TA = +105°C.) PARAMETER Output Low Voltage for All GPIO except P1.[21:18], P1.[16:11], P3.0 Combined IOL, All GPIO Output High Voltage for All GPIO Output High Voltage for All GPIO except P1.[21:18], P1.[16:11], P3.0 Combined IOH, All GPIO Input Hysteresis (Schmitt) Input Leakage Current Low Input Leakage Current High SYMBOL VOL_VDDIOH TYP MAX VDDIOH selected as I/O supply, VDDIOH = 1.71V, DS[1:0] = 00, IOL = 1mA CONDITIONS MIN 0.2 0.4 VDDIOH selected as I/O supply, VDDIOH = 1.71V, DS[1:0] = 01, IOL = 2mA 0.2 0.4 VDDIOH selected as I/O supply, VDDIOH = 1.71V, DS[1:0] = 10, IOL = 4mA 0.2 0.4 VDDIOH selected as I/O supply, VDDIOH = 1.71V, DS[1:0] = 11, IOL = 8mA 0.2 0.4 V IOL_TOTAL VOH_VDDIO VOH_VDDIOH UNITS 48 VDDIO selected as I/O supply, VDDIO = 1.71V, DS[1:0] = 00, IOL = -1mA VDDIO - 0.4 VDDIO selected as I/O supply, VDDIO = 1.71V, DS[1:0] = 01, IOL = -2mA VDDIO - 0.4 VDDIO selected as I/O supply, VDDIO = 1.71V, DS[1:0] = 10, IOL = -4mA VDDIO - 0.4 VDDIO selected as I/O supply, VDDIO = 1.71V, DS[1:0] = 00, IOL = -8mA VDDIO - 0.4 VDDIOH selected as I/O supply, VDDIOH = 1.71V, DS[1:0] = 00, IOL = -1mA VDDIOH - 0.4 VDDIOH selected as I/O supply, VDDIOH = 1.71V, DS[1:0] = 01, IOL = -2mA VDDIOH - 0.4 VDDIOH selected as I/O supply, VDDIOH = 1.71V, DS[1:0] = 10, IOL = -8mA VDDIOH - 0.4 VDDIOH selected as I/O supply, VDDIOH = 1.71V, DS[1:0] = 11, IOL = -8mA VDDIOH - 0.4 V V IOH_TOTAL -48 VIHYS mA 300 mA mV IIL VDDIO = 1.89V, VDDIOH = 3.6V, VDDIOH selected as I/O supply, VIN = 0V, internal pullup disabled -1000 +1000 nA IIH VDDIO = 1.89V, VDDIOH = 3.6V, VDDIOH selected as I/O supply, VIN = 3.6V, internal pulldown disabled -1000 +1000 nA IOFF VDDIO = 0V, VDDIOH = 0V, VDDIO selected as I/O supply, VIN < 1.89V -1 +1 IIH3V VDDIO = VDDIOH = 1.71V, VDDIO selected as I/O supply, VIN = 3.6V -2 +2 μA Input Pullup Resistor TMS, TCK, TDI RPU_T 25 kΩ Input Pullup Resistor RSTN RPU_R 1 MΩ www.maximintegrated.com Maxim Integrated │  8 MAX32650–MAX32652 Ultra-Low-Power Arm Cortex-M4 with FPU-Based Microcontroller (MCU) with 3MB Flash and 1MB SRAM Electrical Characteristics (continued) (Limits are 100% tested at TA = +25°C and TA = +105°C. Limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production tested. Specifications to the minimum operating temperature are guaranteed by design and are not production tested. General-purpose I/O are only tested at TA = +105°C.) PARAMETER Input Pullup/Pulldown Resistor for All GPIO SYMBOL CONDITIONS MIN TYP MAX UNITS RPU1 Normal resistance 25 kΩ RPU2 Highest resistance 1 MΩ tM_ERASE Mass erase 30 tP_ERASE Page erase 30 FLASH MEMORY Flash Erase Time Flash Programming Time Per Word tPROG 60 Flash Endurance Data Retention tRET ms TA = +85°C μs 10 kcycles 10 years ADC (DELTA-SIGMA) Resolution 10 ADC Clock Rate fACLK ADC Clock Period tACLK Input Voltage Range Input Impedance Analog Input Capacitance VAIN RAIN CAIN Bits 0.1 8 1/fACLK MHz μs AIN[3:0], ADC_CHSEL = 0-3, ADC_REFSEL = 1 VSSA + 0.05 VBG/2 AIN[3:0], ADC_CHSEL = 0-3, ADC_REFSEL = 0 VSSA + 0.05 VBG AIN[1:0], ADC_CHSEL = 4-5, ADC_REFSEL = 0 VSSA + 0.05 5.5 V AIN[1:0], ADC_CHSEL = 4-5, ADC active 40 kΩ Fixed capacitance to VSSA 1 pF Dynamically switched capacitance 250 fF Integral Nonlinearity INL -2 +2 LSb Differential Nonlinearity DNL -1 +2 LSb Offset Error VOS ±1 LSb Gain Error GE ±2 LSb 210 µA ADC Active Current ADC Setup Time IADC tADC_SU ADC Output Latency tADC ADC Sample Rate fADC ADC Input Leakage www.maximintegrated.com IADC_LEAK ADC active, reference buffer enabled, input buffer disabled Any powerup of: ADC clock or ADC bias to CpuAdcStart 10 1025 tACLK 7.8 AIN0 or AIN1, ADC inactive or channel not selected 0.01 AIN2 or AIN3, ADC inactive or channel not selected 0.01 µs ksps nA Maxim Integrated │  9 MAX32650–MAX32652 Ultra-Low-Power Arm Cortex-M4 with FPU-Based Microcontroller (MCU) with 3MB Flash and 1MB SRAM Electrical Characteristics (continued) (Limits are 100% tested at TA = +25°C and TA = +105°C. Limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production tested. Specifications to the minimum operating temperature are guaranteed by design and are not production tested. General-purpose I/O are only tested at TA = +105°C.) PARAMETER SYMBOL AIN0/AIN1 Resistor Divider Error Full-Scale Voltage Bandgap Temperature Coefficient VFS VTEMPCO CONDITIONS MIN TYP MAX UNITS ADC_CHSEL = 4 or 5, not including ADC offset/ gain error. ±2 LSb ADC code = 0x3FF 1.2 V From +25ºC to +105ºC 15 ppm Electrical Characteristics—SPI (Timing specifications are guaranteed by design and not production tested.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 60 MHz MASTER MODE SPI Master Operating Frequency fMCK fMCK(MAX) = fSYS_CLK/2 SPI Master SCK Period tMCK SCK Output Pulse-Width High/Low tMCH, tMCL tMCK/2 ns MOSI Output Hold Time After SCK Sample Edge tMOH tMCK/2 ns MOSI Output Valid to Sample Edge tMOV tMCK/2 ns MISO Input Valid to SCK Sample Edge Setup tMIS 5 ns MISO Input to SCK Sample Edge Hold tMIH tMCK/2 ns 1/fMCK ns SLAVE MODE SPI Slave Operating Frequency fSCK SPI Slave SCK Period tSCK 1/fSCK SCK Input Pulse-Width High/Low tSCH, tSCL tSCK/2 SSx Active to First Shift Edge tSSE 10 ns MOSI Input to SCK Sample Edge Rise/Fall Setup tSIS 5 ns MOSI Input from SCK Sample Edge Transition Hold tSIH 1 ns MISO Output Valid After SCLK Shift Edge Transition tSOV 5 ns SCK Inactive to SSx Inactive tSSD 10 ns SSx Inactive Time tSSH 1/fSCK μs www.maximintegrated.com 48 MHz ns Maxim Integrated │  10 MAX32650–MAX32652 Ultra-Low-Power Arm Cortex-M4 with FPU-Based Microcontroller (MCU) with 3MB Flash and 1MB SRAM SHIFT SAMPLE SHIFT SAMPLE SSx (SHOWN ACTIVE LOW) tMCK SLK CKPOL/CKPHA 0/1 OR 1/0 SCK CKPOL/CKPHA 0/0 OR 1/1 tMCH tMCL tMOH MOSI/SDIOx (OUTPUT) MSB tMOV tMLH tMIS MISO/SDIOx (INPUT) LSB MSB-1 tMIH MSB LSB MSB-1 Figure 1. SPI Master Mode Timing Diagram SSx (SHOWN ACTIVE LOW) SCK CKPOL/CKPHA 0/1 OR 1/0 tSSE SHIFT SAMPLE SHIFT SAMPLE tSSH tSCH SCK CKPOL/CKPHA 0/0 OR 1/1 MOSI/SDIOx (INPUT) tSSD tSCK tSCL tSIS MSB tSIH MSB-1 LSB tSOV MISOI/SDIOx (OUTPUT) MSB MSB-1 tSLH LSB Figure 2. SPI Slave Mode Timing Diagram www.maximintegrated.com Maxim Integrated │  11 MAX32650–MAX32652 Ultra-Low-Power Arm Cortex-M4 with FPU-Based Microcontroller (MCU) with 3MB Flash and 1MB SRAM Electrical Characteristics—I2C (Timing specifications are guaranteed by design and not production tested.) PARAMETER SYMBOL CONDITIONS tOF Standard mode, from VIH(MIN) to VIL(MAX) MIN TYP MAX UNITS STANDARD MODE Output Fall Time 150 ns SCL Clock Frequency fSCL 0 Low Period SCL Clock tLOW 4.7 100 kHz μs High Time SCL Clock tHIGH 4.0 μs Setup Time for Repeated Start Condition tSU;STA 4.7 μs Hold Time for Repeated Start Condition tHD;STA 4.0 μs Data Setup Time tSU;DAT 300 ns Data Hold Time tHD;DAT 10 ns Rise Time for SDA and SCL tR 800 ns Fall Time for SDA and SCL tF 200 ns Setup Time for a Stop Condition tSU;STO 4.0 μs tBUS 4.7 μs Data Valid Time tVD;DAT 3.45 μs Data Valid Acknowledge Time tVD;ACK 3.45 μs Bus Free Time Between a Stop and Start Condition FAST MODE Output Fall Time tOF Pulse Width Suppressed by Input Filter tSP From VIH(MIN) to VIL(MAX) 150 ns 75 ns SCL Clock Frequency fSCL 0 Low Period SCL Clock tLOW 1.3 400 kHz μs High Time SCL Clock tHIGH 0.6 μs Setup Time for Repeated Start Condition tSU;STA 0.6 μs Hold Time for Repeated Start Condition tHD;STA 0.6 μs Data Setup Time tSU;DAT 125 ns Data Hold Time tHD;DAT 10 ns Rise Time for SDA and SCL tR 30 ns Fall Time for SDA and SCL tF 30 ns Setup Time for a Stop Condition tSU;STO 0.6 μs tBUS 1.3 μs Data Valid Time tVD;DAT 0.9 μs Data Valid Acknowledge Time tVD;ACK 0.9 μs Bus Free Time Between a Stop and Start Condition www.maximintegrated.com Maxim Integrated │  12 MAX32650–MAX32652 Ultra-Low-Power Arm Cortex-M4 with FPU-Based Microcontroller (MCU) with 3MB Flash and 1MB SRAM Electrical Characteristics—I2C (continued) (Timing specifications are guaranteed by design and not production tested.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS FAST MODE PLUS Output Fall Time tOF Pulse Width Suppressed by Input Filter tSP SCL Clock Frequency fSCL From VIH(MIN) to VIL(MAX) 80 ns 75 ns 0 1000 kHz Low Period SCL Clock tLOW 0.5 μs High Time SCL clock tHIGH 0.26 μs Setup Time for Repeated Start Condition tSU;STA 0.26 μs Hold Time for Repeated Start Condition tHD;STA 0.26 μs Data Setup Time tSU;DAT 50 ns Data Hold Time tHD;DAT 10 ns Rise Time for SDA and SCL tR 50 ns Fall Time for SDA and SCL tF 30 ns Setup Time for a Stop Condition tSU;STO 0.26 μs tBUS 0.5 μs Data Valid Time tVD;DAT 0.45 μs Data Valid Acknowledge Time tVD;ACK 0.45 μs Bus Free Time Between a Stop and Start Condition STOP START REPEAT START START tBUS SDA tOF tR tSU;DAT tSU;STO tSP tSU;STA tHIGH SCL tHD;STA tHD;DAT tVD;DAT tVD;ACK tLOW Figure 3. I2C Timing Diagram www.maximintegrated.com Maxim Integrated │  13 MAX32650–MAX32652 Ultra-Low-Power Arm Cortex-M4 with FPU-Based Microcontroller (MCU) with 3MB Flash and 1MB SRAM Electrical Characteristics—I2C Slave (Timing specifications are guaranteed by design and not production tested, TA = -40°C to +105°C.) PARAMETER SYMBOL Bit Clock Frequency fBCLK BCLK High Time CONDITIONS MIN TYP MAX 96kHz LRCLK frequency 3.072 tWBCLKH BCLK Low Time UNITS MHz 0.5 1/fBCLK 0.5 1/fBCLK tLRCLK_BLCK 25 ns tBCLK_SDO 12 ns Setup Time for SD (Input) tSU_SDI 6 ns Hold Time SD (Input) tHD_SDI 3 ns LRCLK Setup Time Delay Time, BCLK to SD (Output) Valid tBLK tWBCLKH tWBCLKL BCLK tLRCLK_BCLK LRCLK tBCLK_SDO SD (OUTPUT) LSB MSB tSU_SDI SD (INPUT) LSB WORD N-1 RIGHT CHANNEL MSB WORD N LEFT CHANNEL LSB MSB LSB MSB tHD_SDI WORD N RIGHT CHANNEL CONDITIONS: I2S_LJ = 0; I2S_MONO = 0; CPOL = 0; CPHA = 0 Figure 4. I2S Timing Diagram www.maximintegrated.com Maxim Integrated │  14 MAX32650–MAX32652 Ultra-Low-Power Arm Cortex-M4 with FPU-Based Microcontroller (MCU) with 3MB Flash and 1MB SRAM Electrical Characteristics—SD/SDIO/SDHC/MMC (TA = -40°C to +105°C ) PARAMETER Clock Frequency in Data Transfer Mode SYMBOL CONDITIONS MIN fSDHC_CLK TYP 0 1/fSDHC_ MAX UNITS fHSCLK/2 MHz Clock Period tCLK Clock Low Time tWCL 7 Clock High Time tWCH 7 Input Setup Time tISU 5 ns Input Hold Time tIHLD 1 ns Output Valid Time tOVLD 5 ns Output Hold Time tOHLD 6 ns CLK ns ns tCLK tWCH tWCL SDHC_CLK tOVLD SDHC_DATx, SDHC_CMD (output) SDHC_DATx, SDHC_CMD (input) tOHLD NOT VALID NOT VALID tISU NOT VALID tIHLD NOT VALID Figure 5. SD/SDIO/SDHC/MMC Timing Diagram www.maximintegrated.com Maxim Integrated │  15 MAX32650–MAX32652 Ultra-Low-Power Arm Cortex-M4 with FPU-Based Microcontroller (MCU) with 3MB Flash and 1MB SRAM Electrical Characteristics—HyperBus (Timing specifications are guaranteed by design and not production tested.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 60 MHz HYP_CLK, HYP_CLKN Frequency fHYP_CLK HYP_CLK, HYP_CLKN Period tHYP_CLK HYP_CLK, HYP_CLKN High Time tWHCKH 7 ns HYP_CLK, HYP_CLKN Low Time tWHCKL 7 ns 1/fHYP_ ns CLK CS Setup to RWDS tCSSU 6 ns RWDS Setup to CK tRWDS_CK 10 ns Dx Output Setup tOSU 5 ns Dx Output Hold tOH 3 ns CS Hold After CK Falling Edge tCSH 5 ns CS High Between Transactions tCHSI 15 ns Dx Input Setup to RWDS tISU 4 ns Dx Input Hold tIHD 2 ns tCHSI CSx tCSSU HYP_CLK, HYP_CLKN RWDS tCSH tWHCKL tWHCKH tRWDS_CK tCK Hi-Z tOH tOSU tOH Dx (output) Dx (input) VALID VALID tOSU VALID VALID VALID VALID VALID VALID VALID VALID HOST DRIVES Dx AND RWDS tIHD COMMAND-ADDRESS HOST DRIVES Dx AND MEMORY DRIVES RWDS VALID VALID VALID VALID tISU MEMORY DRIVES Dx AND RWDS Figure 6. HyperBus/Xccela Bus Timing Diagram www.maximintegrated.com Maxim Integrated │  16 MAX32650–MAX32652 Ultra-Low-Power Arm Cortex-M4 with FPU-Based Microcontroller (MCU) with 3MB Flash and 1MB SRAM Electrical Characteristics—One Wire Master (Timing specifications are guaranteed by design and not production tested.) PARAMETER SYMBOL Write 0 Low Time tW0L Write 1 Low Time tW1L Presence Detect Sample Read Data Value Recovery Time tMSP tMSR tREC0 Reset Time High tRSTH Reset Time Low tRSTL Time Slot tSLOT www.maximintegrated.com CONDITIONS MIN TYP Standard 60 Overdrive 8 Standard 6 Standard, Long Line mode 8 Overdrive 1 Standard 70 Standard, Long Line mode 85 Overdrive 9 Standard 15 Standard, Long Line mode 24 Overdrive 3 Standard 10 Standard, Long Line mode 20 Overdrive 4 Standard 480 Overdrive 58 Standard 600 Overdrive 70 Standard 70 Overdrive 12 MAX UNITS μs μs μs μs μs μs μs μs Maxim Integrated │  17 MAX32650–MAX32652 Ultra-Low-Power Arm Cortex-M4 with FPU-Based Microcontroller (MCU) with 3MB Flash and 1MB SRAM INITIALIZATION RESET AND PRESENCE-DETECT CYCLE tRSTH tMSP OWM_IO tRSTL WRITE TIME SLOTS WRITE 1 SLOT WRITE 0 SLOT tSLOT tSLOT tREC0 tW0L tLOW1 OWM_IO READ TIME SLOTS READ 1 SLOT tSLOT READ 0 SLOT tSLOT tREC0 tW1L tW1L OWM_IO tMSR tMSR LEGEND ONE WIRE MASTER ACTIVE LOW BOTH MASTER AND SLAVE DEVICE ACTIVE LOW SLAVE DEVICE ACTIVE LOW RESISTOR PULLUP Figure 7. One-Wire Master Data Timing Diagram www.maximintegrated.com Maxim Integrated │  18 MAX32650–MAX32652 Ultra-Low-Power Arm Cortex-M4 with FPU-Based Microcontroller (MCU) with 3MB Flash and 1MB SRAM Pin Configurations TOP VIEW (BUMP SIDE DOWN) 1 2 3 4 5 6 7 8 9 10 11 P0.24 P3.0 VSS P1.5 VDDIOH VDDIO VSS HYP_CLKN HYP_CLK P1.14 12 + A B P0.19 P0.21 P0.25 P1.4 P1.6 P1.11 P1.13 P1.16 P1.18 P1.21 VDDB DP C P0.16 P0.17 P0.20 P1.1 P1.3 P1.10 P1.12 P1.15 P1.19 P1.20 VSS DM D VSS P0.15 P0.18 P1.0 P1.2 P1.9 P2.19 P2.23 P2.22 P1.30 VSS VCORE E P0.23 P0.13 P0.14 VDDIO P1.7 P1.8 P2.20 P2.21 P1.17 P1.31 P3.6 P3.9 F VDDIO P0.11 P0.12 VSS P0.0 P2.31 P2.18 P0.31 P1.23 P0.30 P3.5 P3.8 G VDDIOH P0.10 P0.9 VDDIOH P2.29 P2.30 P2.17 P2.0 P1.25 P0.29 P3.4 P3.7 H VCORE P0.8 P0.7 VCORE P2.15 P2.27 P2.24 P2.1 P1.24 P0.27 VDDA VSSA J VSS P0.22 P0.4 P2.16 P2.13 P2.26 P2.8 P2.5 P1.27 P0.26 AIN2 ANI3 K P0.6 P0.5 P0.2 P2.14 P2.28 P2.25 P2.7 P2.4 P1.28 P0.28 AIN1 32KOUT L P0.3 P0.1 P3.2 P2.12 P2.10 P2.9 P2.6 P2.3 P1.29 RSTN AIN0 32KIN P3.3 P3.1 VSS P2.11 VDDIOH VDDIO P2.2 VSS P1.26 VRTC M 140 WLP www.maximintegrated.com Maxim Integrated │  19 MAX32650–MAX32652 Ultra-Low-Power Arm Cortex-M4 with FPU-Based Microcontroller (MCU) with 3MB Flash and 1MB SRAM Pin Configurations (continued) TOP VIEW (BUMP SIDE DOWN) 1 2 3 4 5 6 7 8 9 P0.20 P1.8 P1.10 VDDIO P2.23 D.N.C D.N.C P1.14 10 + A B VDDIO P1.0 P1.9 P1.6 VDDIOH VSS P1.18 P1.21 VDDB DP C VSS P0.21 P1.2 P1.4 P1.15 P1.19 P1.23 VCORE VSS DM D P0.14 P0.18 P1.1 P1.5 P1.16 P1.25 P1.30 VSS P3.6 P3.9 E P0.13 P0.11 P0.17 P1.3 P1.12 P1.20 P1.24 P1.31 P3.5 P3.8 F VDDIOH P2.17 P0.16 P0.19 P1.11 P0.29 P0.26 P0.27 P3.4 P3.7 G VCORE P2.16 P2.13 P0.15 P0.22 P0.28 P0.30 AIN3 VSSA VDDA H P2.15 P2.12 P2.5 P2.4 P2.18 P1.29 P1.27 VRTC AIN2 32KOUT J P2.14 VSS P2.9 P2.6 P2.3 P2.0 P1.28 P1.26 AIN1 32KIN P1.13 P2.11 VDDIOH VDDIO P2.2 VSS RSTN ANI0 K 96 WLP www.maximintegrated.com Maxim Integrated │  20 MAX32650–MAX32652 Ultra-Low-Power Arm Cortex-M4 with FPU-Based Microcontroller (MCU) with 3MB Flash and 1MB SRAM P0.30 VRTC P0.29 AIN0 112 111 110 109 RSTN P0.28 113 115 114 P1.27 P1.26 116 P1.29 P1.28 117 119 118 P2.0 VSS 120 P2.2 P2.1 122 121 P2.4 P2.3 124 125 123 VDDIO P2.5 126 VDDIOH P2.6 128 127 P2.8 P2.7 129 131 130 P2.11 P2.9 132 P2.10 P2.25 135 133 VSS P2.26 136 134 P3.1 P2.12 138 139 137 P2.13 P2.28 140 P3.3 P3.2 141 P2.15 P2.14 144 143 TOP VIEW 142 Pin Configurations (continued) + P2.16 1 108 N.C. P0.1 2 107 32KIN P0.2 3 106 32KOUT P0.3 4 105 N.C. VCORE 5 104 AIN1 P0.4 6 103 P0.5 7 102 P0.26 AIN2 P0.6 8 101 AIN3 VDDIOH 9 100 P0.27 P0.22 10 99 VDDA VSS 11 98 VSSA P0.7 12 97 P3.4 P0.8 13 96 P3.7 VCORE 14 95 P3.5 P0.9 15 94 P3.8 P2.30 16 93 P1.31 P0.10 VDDIOH 17 92 P1.24 18 91 P3.6 P2.17 19 90 P3.9 P2.18 20 89 VSS VDDIO 21 88 VCORE P0.11 22 87 D.N.C P0.12 23 86 D.N.C P0.23 24 85 VSS P0.13 25 84 N.C. P0.14 26 83 DM VSS P0.15 27 82 N.C. 28 81 VSS VSS 29 80 VSS P0.16 30 79 N.C. P0.17 31 78 DP P0.18 32 77 N.C. VDDIO 33 76 VDDB P0.19 34 75 P1.22 P0.20 35 74 N.C. P0.21 36 73 N.C. www.maximintegrated.com 67 68 69 70 71 72 P1.14 P1.17 P1.23 P1.30 P1.25 66 P1.21 65 62 P1.19 P1.20 61 P0.31 HYP_CLK 60 VSS 64 59 P1.16 63 58 P1.15 P1.18 57 P2.23 HYP_CLKN 55 56 VDDIO 54 144 TQFP P1.13 53 P1.12 VDDIOH 51 52 47 VSS P1.9 P1.5 46 P1.8 P1.11 45 P1.4 50 44 P3.0 49 43 P1.3 P1.6 42 P1.2 P1.10 41 P0.25 48 39 40 P1.1 38 P0.24 37 P1.0 P1.7 MAX32650/MAX32651 Maxim Integrated │  21 MAX32650–MAX32652 Ultra-Low-Power Arm Cortex-M4 with FPU-Based Microcontroller (MCU) with 3MB Flash and 1MB SRAM Pin Description PIN 140 WLP NAME FUNCTION 96 WLP 144 TQFP H1, H4, D12 G1, C8 5, 14, 88 VCORE H11 G10 99 VDDA 1.8V Analog Supply Voltage. This pin must be bypassed to VSSA with 1.0μF and 0.01μF capacitors as close as possible to the package. B11 B9 76 VDDB USB Transceiver Supply Voltage. This pin must be bypassed to VSS with a 1.0μF capacitor as close as possible to the package. A7 A5 21 E4, F1 B1, K5 33, 55 M7 — 126 A6 B5 9 G1, G4, M6 F1, K4 18, 54, 128 M11 H8 111 VRTC A4, A8, C11, D1, D11, F4, J1, M4, M9 B6, C1, C9, D8, K7, J2 11, 27, 29, 47, 60, 80, 81, 85, 89, 119, 136 VSS Digital Ground H12 G9 98 VSSA Analog Ground POWER Core Supply Voltage. This pin must be bypassed to VSS with a 1.0μF capacitor as close as possible to the package. GPIO Supply Voltage. This pin must be bypassed to VSS with 1.0μF and 0.01μF capacitors as close as possible to the package. VDDIO GPIO Supply Voltage. This pin must be bypassed to VSS with a 1.0μF and a 0.01μF capacitor as close as possible to the package. GPIO Supply Voltage. This pin must be bypassed to VSS with 1.0μF and 0.01μF capacitors as close as possible to the package. VDDIOH GPIO Supply Voltage, High. VDDIOH ≥ VDDIO . This pin must be bypassed to VSS with 1.0μF and 0.01μF capacitorx as close as possible to the package. GPIO Supply Voltage, High. VDDIOH ≥ VDDIO . This pin must be bypassed to VSS with 1.0μF and 0.01μF capacitors as close as possible to the package. RTC Supply Voltage. This pin must be bypassed to VSS with a 1.0μF capacitor as close as possible to the package. RESET K8 114 RSTN Hardware Power Reset (Active-Low) Input. The device remains in reset while this pin is in its active state. When the pin transitions to its inactive state, the device performs a POR reset (resetting all logic on all supplies except for real-time clock circuitry) and begins execution. This pin has an internal pullup to the VDDIO supply. L12 J10 107 32KIN 32kHz Crystal Oscillator Input. Connect a 32kHz crystal between 32KIN and 32KOUT for RTC operation. Optionally, an external clock source can be driven on 32KIN if the 32KOUT pin is left unconnected. K12 H10 106 32KOUT L10 CLOCK 32kHz Crystal Oscillator Output GPIO AND ALTERNATE FUNCTIONS F5 — — P0.0 General-Purpose I/O, Port 0. Most port pins have multiple special functions. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. L2 — 2 P0.1 General-Purpose I/O, Port 0. Most port pins have multiple special functions. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. www.maximintegrated.com Maxim Integrated │  22 MAX32650–MAX32652 Ultra-Low-Power Arm Cortex-M4 with FPU-Based Microcontroller (MCU) with 3MB Flash and 1MB SRAM Pin Description (continued) PIN NAME FUNCTION 140 WLP 96 WLP 144 TQFP K3 — 3 P0.2 General-Purpose I/O, Port 0. Most port pins have multiple special functions. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. L1 — 4 P0.3 General-Purpose I/O, Port 0. Most port pins have multiple special functions. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. J3 — 6 P0.4 General-Purpose I/O, Port 0. Most port pins have multiple special functions. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. K2 — 7 P0.5 General-Purpose I/O, Port 0. Most port pins have multiple special functions. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. K1 — 8 P0.6 General-Purpose I/O, Port 0. Most port pins have multiple special functions. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. H3 — 12 P0.7 General-Purpose I/O, Port 0. Most port pins have multiple special functions. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. H2 — 13 P0.8 General-Purpose I/O, Port 0. Most port pins have multiple special functions. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. G3 — 15 P0.9 General-Purpose I/O, Port 0. Most port pins have multiple special functions. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. G2 — 17 P0.10 General-Purpose I/O, Port 0. Most port pins have multiple special functions. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. F2 E2 22 P0.11 General-Purpose I/O, Port 0. Most port pins have multiple special functions. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. F3 — 23 P0.12 General-Purpose I/O, Port 0. Most port pins have multiple special functions. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. E2 E1 25 P0.13 General-Purpose I/O, Port 0. Most port pins have multiple special functions. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. E3 D1 26 P0.14 General-Purpose I/O, Port 0. Most port pins have multiple special functions. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. D2 G4 28 P0.15 General-Purpose I/O, Port 0. Most port pins have multiple special functions. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. C1 F3 30 P0.16 General-Purpose I/O, Port 0. Most port pins have multiple special functions. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. www.maximintegrated.com Maxim Integrated │  23 MAX32650–MAX32652 Ultra-Low-Power Arm Cortex-M4 with FPU-Based Microcontroller (MCU) with 3MB Flash and 1MB SRAM Pin Description (continued) PIN NAME FUNCTION 140 WLP 96 WLP 144 TQFP C2 E3 31 P0.17 General-Purpose I/O, Port 0. Most port pins have multiple special functions. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. D3 D2 32 P0.18 General-Purpose I/O, Port 0. Most port pins have multiple special functions. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. B1 F4 34 P0.19 General-Purpose I/O, Port 0. Most port pins have multiple special functions. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. C3 A2 35 P0.20 General-Purpose I/O, Port 0. Most port pins have multiple special functions. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. B2 C2 36 P0.21 General-Purpose I/O, Port 0. Most port pins have multiple special functions. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. J2 G5 10 P0.22 General-Purpose I/O, Port 0. Most port pins have multiple special functions. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. E1 — 24 P0.23 General-Purpose I/O, Port 0. Most port pins have multiple special functions. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. A2 — 40 P0.24 General-Purpose I/O, Port 0. Most port pins have multiple special functions. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. B3 — 41 P0.25 General-Purpose I/O, Port 0. Most port pins have multiple special functions. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. J10 F7 103 P0.26 General-Purpose I/O, Port 0. Most port pins have multiple special functions. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. H10 F8 100 P0.27 General-Purpose I/O, Port 0. Most port pins have multiple special functions. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. K10 G6 113 P0.28 General-Purpose I/O, Port 0. Most port pins have multiple special functions. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. G10 F6 110 P0.29 General-Purpose I/O, Port 0. Most port pins have multiple special functions. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. F10 G7 112 P0.30 General-Purpose I/O, Port 0. Most port pins have multiple special functions. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. F8 — 61 P0.31 General-Purpose I/O, Port 0. Most port pins have multiple special functions. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. www.maximintegrated.com Maxim Integrated │  24 MAX32650–MAX32652 Ultra-Low-Power Arm Cortex-M4 with FPU-Based Microcontroller (MCU) with 3MB Flash and 1MB SRAM Pin Description (continued) PIN NAME FUNCTION 140 WLP 96 WLP 144 TQFP D4 B2 37 P1.0 General-Purpose I/O, Port 1. Most port pins have multiple special functions. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. C4 D3 39 P1.1 General-Purpose I/O, Port 1. Most port pins have multiple special functions. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. D5 C3 42 P1.2 General-Purpose I/O, Port 1. Most port pins have multiple special functions. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. C5 E4 43 P1.3 General-Purpose I/O, Port 1. Most port pins have multiple special functions. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. B4 C4 45 P1.4 General-Purpose I/O, Port 1. Most port pins have multiple special functions. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. A5 D4 51 P1.5 General-Purpose I/O, Port 1. Most port pins have multiple special functions. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. B5 B4 49 P1.6 General-Purpose I/O, Port 1. Most port pins have multiple special functions. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. E5 — 38 P1.7 General-Purpose I/O, Port 1. Most port pins have multiple special functions. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. E6 A3 46 P1.8 General-Purpose I/O, Port 1. Most port pins have multiple special functions. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. D6 B3 48 P1.9 General-Purpose I/O, Port 1. Most port pins have multiple special functions. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. C6 A4 50 P1.10 General-Purpose I/O, Port 1. Most port pins have multiple special functions. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. B6 F5 52 P1.11 General-Purpose I/O, Port 1. Most port pins have multiple special functions. This pin is connected to VDDIO only. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. C7 E5 53 P1.12 General-Purpose I/O, Port 1. Most port pins have multiple special functions. This pin is connected to VDDIO only. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. B7 K2 56 P1.13 General-Purpose I/O, Port 1. Most port pins have multiple special functions. This pin is connected to VDDIO only. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. A11 A9 68 P1.14 General-Purpose I/O, Port 1. Most port pins have multiple special functions. This pin is connected to VDDIO only. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. www.maximintegrated.com Maxim Integrated │  25 MAX32650–MAX32652 Ultra-Low-Power Arm Cortex-M4 with FPU-Based Microcontroller (MCU) with 3MB Flash and 1MB SRAM Pin Description (continued) PIN NAME FUNCTION 140 WLP 96 WLP 144 TQFP C8 C5 58 P1.15 General-Purpose I/O, Port 1. Most port pins have multiple special functions. This pin is connected to VDDIO only. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. B8 D5 59 P1.16 General-Purpose I/O, Port 1. Most port pins have multiple special functions. This pin is connected to VDDIO only. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. E9 — 69 P1.17 General-Purpose I/O, Port 1. Most port pins have multiple special functions. See Table 3, Table 4and Table 5 GPIO and Alternate Function Matrix tables for details. B9 B7 63 P1.18 General-Purpose I/O, Port 1. Most port pins have multiple special functions. This pin is connected to VDDIO only. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. C9 C6 62 P1.19 General-Purpose I/O, Port 1. Most port pins have multiple special functions. This pin is connected to VDDIO only. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. C10 E6 66 P1.20 General-Purpose I/O, Port 1. Most port pins have multiple special functions. This pin is connected to VDDIO only. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. B10 B8 67 P1.21 General-Purpose I/O, Port 1. Most port pins have multiple special functions. This pin is connected to VDDIO only. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. — — 75 P1.22 General-Purpose I/O, Port 1. Most port pins have multiple special functions. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. F9 C7 70 P1.23 General-Purpose I/O, Port 1. Most port pins have multiple special functions. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. H9 E7 92 P1.24 General-Purpose I/O, Port 1. Most port pins have multiple special functions. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. G9 D6 72 P1.25 General-Purpose I/O, Port 1. Most port pins have multiple special functions. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. M10 J8 115 P1.26 General-Purpose I/O, Port 1. Most port pins have multiple special functions. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. J9 H7 116 P1.27 General-Purpose I/O, Port 1. Most port pins have multiple special functions. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. K9 J7 117 P1.28 General-Purpose I/O, Port 1. Most port pins have multiple special functions. See Table 3, Table 4 and TTable 5 GPIO and Alternate Function Matrix tables for details. L9 H6 118 P1.29 General-Purpose I/O, Port 1. Most port pins have multiple special functions. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. www.maximintegrated.com Maxim Integrated │  26 MAX32650–MAX32652 Ultra-Low-Power Arm Cortex-M4 with FPU-Based Microcontroller (MCU) with 3MB Flash and 1MB SRAM Pin Description (continued) PIN NAME FUNCTION 140 WLP 96 WLP 144 TQFP D10 D7 71 P1.30 General-Purpose I/O, Port 1. Most port pins have multiple special functions. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. E10 E8 93 P1.31 General-Purpose I/O, Port 1. Most port pins have multiple special functions. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. G8 J6 120 P2.0 General-Purpose I/O, Port 2. Most port pins have multiple special functions. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. H8 — 121 P2.1 General-Purpose I/O, Port 2. Most port pins have multiple special functions. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. M8 K6 122 P2.2 General-Purpose I/O, Port 2. Most port pins have multiple special functions. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. L8 J5 123 P2.3 General-Purpose I/O, Port 2. Most port pins have multiple special functions. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. K8 H4 124 P2.4 General-Purpose I/O, Port 2. Most port pins have multiple special functions. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. J8 H3 125 P2.5 General-Purpose I/O, Port 2. Most port pins have multiple special functions. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. L7 J4 127 P2.6 General-Purpose I/O, Port 2. Most port pins have multiple special functions. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. K7 — 129 P2.7 General-Purpose I/O, Port 2. Most port pins have multiple special functions. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. J7 — 130 P2.8 General-Purpose I/O, Port 2. Most port pins have multiple special functions. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. L6 J3 131 P2.9 General-Purpose I/O, Port 2. Most port pins have multiple special functions. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. L5 — 134 P2.10 General-Purpose I/O, Port 2. Most port pins have multiple special functions. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. M5 K3 132 P2.11 General-Purpose I/O, Port 2. Most port pins have multiple special functions. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. L4 H2 137 P2.12 General-Purpose I/O, Port 2. Most port pins have multiple special functions. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. www.maximintegrated.com Maxim Integrated │  27 MAX32650–MAX32652 Ultra-Low-Power Arm Cortex-M4 with FPU-Based Microcontroller (MCU) with 3MB Flash and 1MB SRAM Pin Description (continued) PIN NAME FUNCTION 140 WLP 96 WLP 144 TQFP J5 G3 140 P2.13 General-Purpose I/O, Port 2. Most port pins have multiple special functions. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. K4 J1 143 P2.14 General-Purpose I/O, Port 2. Most port pins have multiple special functions. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. H5 H1 144 P2.15 General-Purpose I/O, Port 2. Most port pins have multiple special functions. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. J4 G2 1 P2.16 General-Purpose I/O, Port 2. Most port pins have multiple special functions. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. G7 F2 19 P2.17 General-Purpose I/O, Port 2. Most port pins have multiple special functions. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. F7 H5 20 P2.18 General-Purpose I/O, Port 2. Most port pins have multiple special functions. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. D7 — — P2.19 General-Purpose I/O, Port 2. Most port pins have multiple special functions. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. E7 — — P2.20 General-Purpose I/O, Port 2. Most port pins have multiple special functions. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. E8 — — P2.21 General-Purpose I/O, Port 2. Most port pins have multiple special functions. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. D9 — — P2.22 General-Purpose I/O, Port 2. Most port pins have multiple special functions. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. D8 A6 57 P2.23 General-Purpose I/O, Port 2. Most port pins have multiple special functions. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. H7 — — P2.24 General-Purpose I/O, Port 2. Most port pins have multiple special functions. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. K6 — 133 P2.25 General-Purpose I/O, Port 2. Most port pins have multiple special functions. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. J6 — 135 P2.26 General-Purpose I/O, Port 2. Most port pins have multiple special functions. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. H6 — — P2.27 General-Purpose I/O, Port 2. Most port pins have multiple special functions. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. www.maximintegrated.com Maxim Integrated │  28 MAX32650–MAX32652 Ultra-Low-Power Arm Cortex-M4 with FPU-Based Microcontroller (MCU) with 3MB Flash and 1MB SRAM Pin Description (continued) PIN NAME FUNCTION 140 WLP 96 WLP 144 TQFP K5 — 139 P2.28 General-Purpose I/O, Port 2. Most port pins have multiple special functions. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. G5 — — P2.29 General-Purpose I/O, Port 2. Most port pins have multiple special functions. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. G6 — 16 P2.30 General-Purpose I/O, Port 2. Most port pins have multiple special functions. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. F6 — — P2.31 General-Purpose I/O, Port 2. Most port pins have multiple special functions. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. A3 — 44 P3.0 General-Purpose I/O, Port 3. Most port pins have multiple special functions. This pin is connected to VDDIO only. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. M3 — 138 P3.1 General-Purpose I/O, Port 3. Most port pins have multiple special functions. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. L3 — 141 P3.2 General-Purpose I/O, Port 3. Most port pins have multiple special functions. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. M2 — 142 P3.3 General-Purpose I/O, Port 3. Most port pins have multiple special functions. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. G11 F9 97 P3.4 General-Purpose I/O, Port 3. Most port pins have multiple special functions. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. F11 E9 95 P3.5 General-Purpose I/O, Port 3. Most port pins have multiple special functions. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. E11 D9 91 P3.6 General-Purpose I/O, Port 3. Most port pins have multiple special functions. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. G12 F10 96 P3.7 General-Purpose I/O, Port 3. Most port pins have multiple special functions. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. F12 E10 94 P3.8 General-Purpose I/O, Port 3. Most port pins have multiple special functions. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. E12 D10 90 P3.9 General-Purpose I/O, Port 3. Most port pins have multiple special functions. See Table 3, Table 4 and Table 5 GPIO and Alternate Function Matrix tables for details. www.maximintegrated.com Maxim Integrated │  29 MAX32650–MAX32652 Ultra-Low-Power Arm Cortex-M4 with FPU-Based Microcontroller (MCU) with 3MB Flash and 1MB SRAM Pin Description (continued) PIN 140 WLP 96 WLP 144 TQFP NAME FUNCTION ANALOG INPUT PINS L11 K9 109 AIN0 ADC Input 0. 5V-tolerant input. K11 J9 104 AIN1 ADC Input 1. 5V-tolerant input. J11 H9 102 AIN2 ADC Input 2 J12 G8 101 AIN3 ADC Input 3 HYP_CLK HYPERBUS CLOCKS A10 — 65 HyperBus Positive Clock A9 — 64 C12 C10 83 DM USB DM Signal. This bidirectional pin carries the negative differential data or single-ended data. This pin is weakly pulled high internally when the USB is disabled. B12 B10 78 DP USB DP Signal. This bidirectional pin carries the positive differential data or single-ended data. This pin is weakly pulled high internally when the USB is disabled. A7, A8 — HYP_CLKN HyperBus Negative Clock USB NO CONNECT — 86 Do Not Connect. Internally connected. Do not make any electrical connection to this pin, including power supply grounds. D.N.C. — Do Not Connect. Internally connected. Do not make any electrical connection to this pin, including power supply grounds. 87 — — www.maximintegrated.com 73, 74, 77, 79, 82, 84, 105, 108 Do Not Connect. Internally connected. Do not make any electrical connection to this pin, including power supply grounds. N.C. No Connection. Not internally connected. Maxim Integrated │  30 MAX32650–MAX32652 Ultra-Low-Power Arm Cortex-M4 with FPU-Based Microcontroller (MCU) with 3MB Flash and 1MB SRAM Detailed Description and advanced security features. These features include a modular arithmetic accelerator (MAA) for fast ECDSA and RSA-4096 computation. A hardware AES engine uses 128/192/256-bit keys. A memory decryption integrity unit (MDIU) provides on-the-fly code or data decryption stored in external flash. A hardware TRNG and a hardware SHA256 HASH function are also provided. A secure bootloader authenticates applications before they are allowed to execute and update firmware with confidentiality. The MAX32650–MAX32652 are low-power, mixed signal microcontrollers based on the Arm Cortex-M4 with FPU CPU, operating at a maximum frequency of 120MHz. The devices feature five powerful and flexible power modes. A SmartDMA performs complex background processing on data being transferred, from simple arithmetic to multiply/ accumulate, while the CPU is off. This function dramatically reduces overall power consumption compared to conventional solutions. This allows, for example, an external display to be refreshed while most of the chip is powered off. Built-in dynamic clock gating and firmwarecontrolled power gating allows the user to optimize power for the specific application. Application code executes from an onboard 3MB program flash memory, with 1MB SRAM available for general application use. A 16KB cache improves execution throughput. Additionally, a SPI execute in place (XIP) external memory interface allows application code and data (up to 128MB) to be accessed from an external SPI flash and/or SRAM memory device. A 10-bit delta-sigma ADC is provided with a multiplexer front end for four external input channels (two of which are 5V tolerant) and six internal power supply monitoring channels. Dedicated divided supply input channels allow direct monitoring of internal power supply voltages by the ADC. Built-in limit monitors allow converted input samples to be compared against user-configurable high and low limits, with an option to trigger an interrupt and wake the CPU from a low power mode if attention is required. A wide variety of communications and interface peripherals are provided, including a Hi-Speed USB 2.0 device interface, three master/slave SPI interfaces, one QuadSPI master/slave interface, three UART interfaces with flow control support, two master/slave I2C interfaces, and a I2S bidirectional slave interface. A Cypress Spansion HyperBus interface and a Xccela Bus interface provides support for HyperFLASH, HyperRAM, and Xccela PSRAM operating up to 120MB/s throughput with access up to 512MB. A SD/SDIO/MMC interface running up to 60MB/s supporting media file storage. A 24-bit TFT LCD controller provides color and monochrome display support. The MAX32652 is a high-density, 0.35mm pitch, 140bump WLP targeted for tiny form factor products that require high I/O counts. Arm Cortex-M4 with FPU The Arm Cortex-M4 with FPU combines high-efficiency signal processing functionality with flexible low-power operating modes. The features of this implementation of the familiar Arm Cortex-M4 architecture include: ●● Floating point unit (FPU) ●● Memory protection unit ●● Multilayer, 32-bit AHB matrix ●● Full debug support level • Debug access port (DAP) • Breakpoints • Flash patch • Halting debug • Development and debug interface ●● NVIC support • Programmable IRQ generation for each interrupt source • Unique vectors for each interrupt channel • 8 programmable priority levels support nesting and preemption • External GPIO interrupts grouped by GPIO port ●● DSP supports single instruction multiple data (SIMD) path DSP extensions, providing: • 4 parallel 8-bit add/sub • 2 parallel 16-bit add/sub • 2 parallel MACs • 32- or 64-bit accumulate • Signed, unsigned, data with or without saturation The MAX32651 is a secure version of the MAX32650. It provides a trust protection unit (TPU) with encryption www.maximintegrated.com Maxim Integrated │  31 MAX32650–MAX32652 Ultra-Low-Power Arm Cortex-M4 with FPU-Based Microcontroller (MCU) with 3MB Flash and 1MB SRAM Memory accessing on-chip RAM. Data is transferred over a highspeed, 8-bit bus. Slave memory devices are selected with two chip selects. HyperBus transfers are clocked using a differential clock while Xccela bus transfers use a singleended clock. This interface supports 1.8V operation only. Internal Flash Memory 3MB of internal flash memory provides nonvolatile storage of program and data memory. Flash can be expanded through the SPIXF flash serial interface backed by 16KB of cache. The SPIXF flash interface can address an additional 128MB. Internal SRAM The internal 1MB SRAM provides low-power retention of application information in all power modes except shutdown. The SRAM can be divided into granular banks that create a flexible SRAM retention architecture. This data retention feature is optional and configurable. This granularity allows the application to minimize its power consumption by only retaining the most essential data. SRAM can be expanded through the SPIXR SRAM serial interface backed by 16KB of cache. The SPIXR SRAM interface can address an additional 512MB. Secure Digital Interface The secure digital interface (SDI) provides high-speed, high-density data storage capability for media files and large long-term data logs. This interface supports eMMC, SD, SDHC, and SDXC memory devices up to 4GB at transfer rates up to 30MB/s. The 7-pin interface (4 data, 1 clock, 1 command, 1 write-protect) supports the following specifications: • SD Host Controller Standard Specification Version 3.00 • SDIO Card Specification Version 3.0 • SD Memory Card Specification Version 3.01 • SD Memory Card Security Specification Version 1.01 • MMC Specification Version 4.51 Spansion HyperBus/Xccela Bus The Spansion HyperBus/Xccela bus interface provides access to external Cypress Spansion HyperBus and Xccela bus memory products both SRAM and/or flash. This interface provides a means of high-speed execution from external SRAM or flash allowing system expansion when internal memory resources are insufficient. Up to 8MB SRAM or 512MB flash at a speed of up to 60MHz or 120MBps is supported. It is a high-speed low-pin count interface that is memory-mapped into the CPU memory space making access to this external memory as easy as www.maximintegrated.com Features of the HyperBus/Xccela bus interface include: ●● Master/slave system ●● 120MBps maximum data transfer rate ●● Double data rate (DDR): two data transfers per clock cycle ●● Transparent bus operation to the processor ●● 16KB write-through cache ●● Two chip selects for two memory ports • Each port supports memories up to 512MB ●● Addresses two external memories, one at a time ●● Interfaces to HyperFlash, HyperRAM, and Xccela PSRAM ●● Zero wait state burst mode operation ●● Low-power Half Sleep mode • Puts the external memory device into low power mode while retaining memory contents ●● Configurable timing parameters Clocking Scheme The high-frequency oscillator operates at a maximum frequency of 120MHz. Optionally, 4 other oscillators can be selected depending upon power needs: ●● 40MHz low-power oscillator ●● 8kHz nano-ring oscillator ●● 32.768kHz oscillator (external crystal required) ●● 7.3728MHz oscillator This clock is the primary clock source for the digital logic and peripherals. Select the 7.3728MHz internal oscillator to optimize active power consumption. Using the 7.3727MHz oscillator allows UART communications to meet a ±2% baud rate tolerance. Wakeup is possible from either the 7.3728MHz internal oscillator or the high-frequency oscillator. The device exits power-on reset using the the 40MHz oscillator. An external 32.768kHz timebase is required when using the RTC. Maxim Integrated │  32 MAX32650–MAX32652 Ultra-Low-Power Arm Cortex-M4 with FPU-Based Microcontroller (MCU) with 3MB Flash and 1MB SRAM RTC CALIBRATION OUTPUT 32KCAL ALWAYS-ON DOMAIN XTAL DRIVER OR EXTERNAL CLOCK 32KIN BYPASS 32KIN 32kHz CRYSTAL DIGITAL INTERFACE 32K OSC 4kHz REAL-TIME CLOCK 32.768kHz 32KOUT NANO-RING ~8kHz POWER SEQUENCER 120MHz GCR_CLKCN.clksel HIGH-SPEED OSCILLATOR GCR_CLKCN.psc 40MHz 120MHz PRESCALER CPU 40MHz LOW-POWER OSCILLATOR TPU 7.3728MHz TRUST PROTECTION UNIT CIRCUITRY OSCILLATOR BAUD RATE CLOCK ÷2 APB CLK AHB CLK GCR_PKDIV.sdhcfrq ADC CLOCK SCALER ÷4 < 8MHz UART ADC SMART DMA CTRL PHY HI-SPEED USB 2.0 ÷2, 4 SD/SDIO/ MMC Figure 8. Clocking Scheme Diagram www.maximintegrated.com Maxim Integrated │  33 MAX32650–MAX32652 Ultra-Low-Power Arm Cortex-M4 with FPU-Based Microcontroller (MCU) with 3MB Flash and 1MB SRAM General-Purpose I/O and Special Function Pins All DMA transactions consist of an AHB burst read into the DMA FIFO followed immediately by an AHB burst write from the FIFO. Most general-purpose I/O (GPIO) pins share both a firmware-controlled I/O function and one or more special function signals associated with peripheral modules. Pins can be individually enabled for GPIO or peripheral special function use. Configuring a pin as a special function usually supersedes its use as a firmware-controlled I/O. Though this multiplexing between peripheral and GPIO functions is usually static, it can also be done dynamically. The electrical characteristics of a GPIO pin are identical whether the pin is configured as an I/O or special function, except where explicitly noted in the electrical characteristics tables. In GPIO mode, pins are logically divided into ports of 32 pins. Each pin of a port has an interrupt function that can be independently enabled, and configured as a level- or edge-sensitive interrupt. All GPIOs of a given port share the same interrupt vector. Some packages do not have all of the GPIOs available. When configured as GPIO, the following features are provided. The features can be independently enabled or disabled on a per-pin basis. ●● Configurable as input, output, bidirectional, or high impedance ●● Optional internal pullup resistor or internal pulldown resistor when configured as input ●● Exit from low-power modes on rising or falling edge ●● Selectable standard- or high-drive modes The MAX32650/MAX32651/MAX32652 provides up to 105 GPIO (140 WLP), 97 GPIO (144 TQFP), and 67 GPIO (96 WLP). GPIOs, which have any HyperBus alternate functionality (P1.[21:18], P1.[16:11], P3.0), can only be used with the VDDIO supply, whether used as a GPIO or any alternate function. Standard DMA Controller The standard DMA (direct memory access) controller provides a means to off-load the CPU for memory/peripheral data transfer leading to a more power-efficient system. It allows automatic one-way data transfer between two entities. These entities can be either memories or peripherals. The transfers are done without using CPU resources. The following transfer modes are supported: ●● ●● ●● ●● ●● 16 channel Peripheral to data memory Data memory to peripheral Data memory to data memory Event support www.maximintegrated.com SmartDMA Controller The SmartDMA controller provides low-power memory/ peripheral access control that can run data collection tasks and perform complex background processing on data being transferred, from simple arithmetic to multiply/accumulate, while the CPU is off, significantly reducing power consumption (Background mode). The SmartDMA controller allows peripherals on the AHB to access main system memory (SRAM) independent of the CPU. It is configured through the APB and can configure itself through the AHB-to-APB bridge. The SmartDMA engine runs code from system SRAM. If desired, custom SmartDMA algorithms supporting data post-processing can be developed by the user. Key features: ●● Dedicated 32-bit controller with general-purpose timer ●● APB read access to the SmartDMA registers ●● Configurable start IP address ●● Selects 32 interrupts from peripherals from a total of 80 available interrupts to initiate DMA operations ●● Global enable (SDMA_EN) keeps SmartDMA in reset except APB interface ●● Synchronous interrupt output to CPU Analog-to-Digital Converter The 10-bit delta-sigma ADC provides an integrated reference generator and a single-ended input multiplexer. The multiplexer selects an input channel from either the external analog input signals (AIN0, AIN1, AIN2, and AIN3) or the internal power supply inputs. AIN0 and AIN1 are 5V tolerant, making them suitable for monitoring batteries. An internal 1.22V bandgap or the VDDA analog supply can be chosen as the ADC reference. An optional feature allows samples captured by the ADC to be automatically compared against user-programmable high and low limits. Up to four channel limit pairs can be configured in this way. The comparison allows the ADC to trigger an interrupt (and potentially wake the CPU from a low-power sleep mode) when a captured sample goes outside the preprogrammed limit range. Since this comparison is performed directly by the sample limit monitors, it can be performed even while the main CPU is suspended in a low power mode. Maxim Integrated │  34 MAX32650–MAX32652 Ultra-Low-Power Arm Cortex-M4 with FPU-Based Microcontroller (MCU) with 3MB Flash and 1MB SRAM ​The ADC measures: ●● AIN[3:2] (up to 3.3V) UARTS, I2C, 1-Wire, timers, pulse train engines, and the secure digital interface as well as SRAM. The transition from Background to Active mode is faster than the transition from Backup mode because system initialization is not required. There are four sources from which Background mode can be exited to return to Active mode: RTC interrupt, GPIO interrupt, USB interrupt, or RSTN assertion. ●● AIN[1:0] (up to 5.5V) ●● VCORE ●● VDD18 ●● VDDB ●● VRTC ●● VDDIO ●● VDDIOH Power Management Power Management Unit The power management unit (PMU) provides high-performance operation while minimizing power consumption. It exercises intelligent, precise control of power distribution to the CPU and peripheral circuitry. The PMU provides the following features: ●● User-configurable system clock ●● Automatic enabling and disabling of crystal oscillators based on power mode ●● Multiple clock domains ●● Fast wakeup of powered-down peripherals when activity detected Active Mode In this mode, the CPU is executing application code, and all digital and analog peripherals are available on demand. Dynamic clocking disables peripherals not in use, providing the optimal mix of high performance and low power consumption. Sleep Mode This mode allows for low power consumption, but a faster wakeup because the clocks can optionally be enabled. The CPU is asleep, peripherals are on, and the standard and SmartDMA blocks are available for optional use. The GPIO or any active peripheral interrupt can be configured to interrupt and cause transition to the Active mode. Background Mode This mode is suitable for running the SmartDMA engine to collect and move data from enabled peripherals. The CPU is in its Deep-sleep mode. Memory retention is configurable. The SmartDMA engine can access the SPI, www.maximintegrated.com Deep-Sleep Mode This mode corresponds to the Arm Cortex-M4 with FPU Deep-sleep mode. In this mode, the register settings and all volatile memory is preserved. The GPIO pins retain their state in this mode. The transition from Deep-sleep to Active mode is faster than the transition from Backup mode because system initialization is not required. The high-speed oscillator that generates the 120MHz system clock can be shut down to provide additional power savings over Sleep or Background modes. There are four sources from which Background mode can be exited to return to Active mode: RTC interrupt, GPIO interrupt, USB interrupt, or RSTN assertion. Backup Mode This mode places the CPU in a static, low-power state that supports a fast wake-up to Active mode feature. In Backup mode, all of the SRAM can be retained with restrictions depending upon which supply is used to support this mode. Data retention in this mode can be maintained using only the VCORE or VRTC supplies. Optionally, the VCORE voltage input can be turned off at its source and an internal retention regulator can be enabled to power the state so that the VRTC voltage input is all that is required for mode operation including the RTC. If the VRTC supply is used, then either 32KB or 96KB of SRAM can be retained and all GPIO can be retained. If the VCORE supply is subsequently turned on then the power mode will wake to the Active state. If the VCORE supply is used, then either 32KB, 96KB, or 1024KB of SRAM can be retained and all GPIO can be retained. There are four sources from which Background mode can be exited to return to Active mode: RTC interrupt, GPIO interrupt, USB interrupt, or RSTN assertion. Maxim Integrated │  35 MAX32650–MAX32652 Ultra-Low-Power Arm Cortex-M4 with FPU-Based Microcontroller (MCU) with 3MB Flash and 1MB SRAM Real-Time Clock CRC Module A real-time clock (RTC) keeps the time of day in absolute seconds. The 32-bit seconds register can count up to approximately 136 years and be translated to calendar format by application software. The RTC provides a time-of-day alarm that can be programmed to any future value between 1 second and 12 days. When configured for long intervals, the time-of-day alarm can be used as a power-saving timer, allowing the device to remain in an extremely low-power mode but still awaken periodically to perform assigned tasks. A second independent 32-bit 1/256 subsecond alarm can be programmed between 244μs and 256 seconds. Both can be configured as recurring alarms. When enabled, either alarm can cause an interrupt or wake the device from most low power modes. The time base is generated by a 32.768kHz crystal or an external clock source that must meet the electrical/timing requirements in the Electrical Characteristics table. The RTC calibration feature provides the ability for user software to compensate for minor variations in the RTC oscillator, crystal, temperature, and board layout. Enabling the 32KCAL alternate function outputs a timing signal derived from the RTC. External hardware can measure the frequency and adjust the RTC frequency in increments of ±127ppm with 1ppm resolution. Under most circumstances, the oscillator does not require any calibration. A cyclic redundancy check (CRC) hardware module provides fast calculations and data integrity checks by application software. The CRC module supports the following polynomials: ●● CRC-16-CCITT ●● CRC-32 (X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 + X4 + X2 + X + 1) Programmable Timers 32-Bit Timer/Counter/PWM (TMR) General-purpose, 32-bit timers provide timing, capture/ compare, or generation of pulse-width modulated (PWM) signals with minimal software interaction. Each of the 32-bit timers can also be split into two 16-bit timers. The timer provides the following features: ●● 32-bit up/down autoreload ●● Programmable prescaler ●● PWM output generation ●● Capture, compare, and capture/compare capability ●● External pin multiplexed with GPIO for timer input, clock gating or capture ●● Timer output pin ●● Configurable as 2 × 16-bit general-purpose timers ●● Timer interrupt The MAX32650–MAX32652 provides six instances of the general-purpose 32-bit timer (TMR0–TMR5). 32-BIT TIMER BLOCK APB BUS TIMER CONTROL REGISTER 32-BIT COMPARE REGISTER APB CLOCK TIME INTERRUPT REGISTER COMPARE INTERRUPT PWM AND TIMER OUTPUT CONTROL 32-BIT TIMER (WITH PRESCALER) 32-BIT PWM/COMPARE COMPARE TIMER INTERRUPT TIMER OUTPUT TIMER INPUT Figure 9. 32-Bit Timer www.maximintegrated.com Maxim Integrated │  36 MAX32650–MAX32652 Ultra-Low-Power Arm Cortex-M4 with FPU-Based Microcontroller (MCU) with 3MB Flash and 1MB SRAM Pulse Train Engine (PT) target device. The SPI operates independently and requires minimal processor overhead. Multiple, independent pulse train generators can provide either a square wave or a repeating pattern from 2 to 32 bits in length. Any single pulse train generator or any desired group of pulse train generators can be synchronized at the bit level allowing for multibit patterns. Each pulse train generator is independently configurable. The provided SPI peripherals can operate in either slave or master mode and provide the following features: ●● SPI modes 0, 1, 2, 3 for single-bit communication ●● 3- or 4-wire mode for single-bit slave device communication The pulse train generators provide the following features: ●● Independently enabled ●● Full-duplex operation in single-bit, 4-wire mode ●● Dual and quad data modes supported ●● Safe enable and disable for pulse trains without bit banding ●● Multiple slave select lines on some instances ●● Multiple pin configurations allow for flexible layout ●● Multimaster mode fault detection ●● Pulse trains can be started/synchronized independently or as a group ●● Programmable interface timing ●● Programmable SCK frequency and duty cycle ●● Frequency of each enabled pulse train generator is also set separately, based on a divide down (divide by 2, divide by 4, divide by 8, and so on) of the input pulse train module clock ●● 32-byte transmit and receive FIFOs ●● Slave select assertion and deassertion timing with respect to leading/trailing SCK edge The MAX32650–MAX32652 provide four instances of the SPI peripheral (SPI0, SPI1 and SPI2, SPI3) in accordance with the specifications shown in Table 1: ●● Multiple repetition options • Single shot (nonrepeating pattern of 2 to 32 bits) • Pattern repeats user-configurable number of times or indefinitely • Termination of one pulse train loop count can restart one or more other pulse trains I2S Interface The I2S interface is a bidirectional, three-wire serial bus that provides serial communications for codecs and audio amplifiers compliant with the I2S Bus Specification, June 5, 1996. It provides the following features: The pulse train engine feature is an alternate function associated with a GPIO pin. In most cases, enabling the pulse train engine function supersedes the GPIO function. ●● Slave mode operation The MAX32650–MAX32652 provide up to 16 instances of the pulse train engine peripheral (PT[15:0]). ●● Normal and left-justified data alignment Serial Peripherals ●● Wakeup on FIFO status (full/empty/threshold) Serial Peripheral Interface ●● Interrupts generated for FIFO status​ The serial peripheral interface (SPI) is a highly configurable, flexible, and efficient synchronous interface between multiple SPI devices on a single bus. The bus uses a single clock signal and multiple data signals, and one or more slave select lines to address only the intended ●● Receiver FIFO depth of 32 bytes ●● 16-bit audio transfer ●● Transmitter FIFO depth of 32 bytes The MAX32650–MAX32652 provide one instance of the I2S peripheral that is multiplexed with the SPI2 peripheral. Table 1. SPI Configuration Options SLAVE SELECT LINES 144 TQFP 140 WLP 96 WLP MAXIMUM FREQUENCY (MASTER MODE) (MHz) MAXIMUM FREQUENCY (SLAVE MODE) (MHz) 3-wire, 4-wire 1 1 0 60 48 SPI1 3-wire, 4-wire 4 4 4 60 48 SPI2 3-wire, 4-wire 4 4 3 60 48 SPI3 3-wire, 4-wire, dual, or quad data support 4 4 4 60 48 INSTANCE DATA SPI0 www.maximintegrated.com Maxim Integrated │  37 MAX32650–MAX32652 Ultra-Low-Power Arm Cortex-M4 with FPU-Based Microcontroller (MCU) with 3MB Flash and 1MB SRAM USB Controller UART The integrated USB device controller is compliant with the Hi-Speed (480Mbps) USB 2.0 specification. The integrated USB physical interface (PHY) reduces board space and system cost. An integrated voltage regulator enables smart switching between the main supply and VDDB when connected to a USB host controller. The universal asynchronous receiver-transmitter (UART) interface supports full-duplex asynchronous communication with optional hardware flow control (HFC) modes to prevent data overruns. If HFC mode is enabled on a given port, the system uses two extra pins to implement the industry standard request to send (RTS) and clear to send (CTS) flow control signaling. Each UART is individually programmable. ●● Supports DMA for the endpoint buffers. A total of 12 endpoint buffers are supported with configurable selection of IN or OUT in addition to endpoint 0. ●● 2-wire interface or 4-wire interface with flow control ●● Isochronous, bulk, interrupt, and control transfers ●● 32-byte send/receive FIFO ●● Automatic packet splitting and combining ●● Full-duplex operation for asynchronous data transfers ●● FIFOs up to 4096 bytes deep ●● Interrupts available for frame error, parity error, CTS, Rx FIFO overrun and FIFO full/partially full conditions ●● Double packet buffering ●● USB 2.0 test mode support I2C Interface ●● Automatic parity and frame error detection ●● Independent baud-rate generator The I2C interface is a bidirectional, two-wire serial bus that provides a medium-speed communications network. It can operate as a one-to-one, one-to-many or many-tomany communications medium. Two I2C master/slave interface to a wide variety of I2C-compatible peripherals. These engines support standard mode, fast mode, and fast mode plus I2C speeds. It provides the following features: ●● Programmable 9th bit parity support ●● Master or slave mode operation ●● Supports standard 7-bit addressing or 10-bit addressing ●● Two DMA channels can be connected (read and write FIFOs) ●● RESTART condition ●● Programmable word size (5 bits to 8 bits) ●● Interactive Receive mode The MAX32650–MAX32652 provide three instances of the UART peripheral (UART0, UART1, and UART2) according to the specifications in Table 2. ●● Tx FIFO preloading ●● Support for clock stretching to allow slower slave devices to operate on higher speed busses ●● Multiple transfer rates • Standard mode: 100kbps • Fast mode: 400kbps • Fast mode plus: 1000kbps ●● Internal filter to reject noise spikes ●● Receiver FIFO depth of 8 bytes ●● Transmitter FIFO depth of 8 bytes The MAX32650–MAX32652 provide two instances of the I2C peripheral (I2C0 and I2C1). www.maximintegrated.com ●● Multidrop support ●● Start/stop bit support ●● Hardware flow control using RTS/CTS ●● Baud rate generation with ±2% optionally utilizing the 7.3727MHz relaxation oscillator ●● Maximum baud rate 4000kB Serial Peripheral Interface Execute in Place (SPIX) Master There are two SPI execute-in-place master interfaces. One for SRAM (SPIXR) and one for flash (SPIXF) with dedicated slave selects. This feature allows the CPU to transparently execute instructions stored in an external SPI memory device. Instructions fetched through the SPI master are cached like instructions fetched from internal program memory. The SPI SRAM master provides writeback capability. These two SPI execute in place master interfaces can also be used to access large amounts of external static data that would otherwise reside in internal data memory. Maxim Integrated │  38 MAX32650–MAX32652 Ultra-Low-Power Arm Cortex-M4 with FPU-Based Microcontroller (MCU) with 3MB Flash and 1MB SRAM Table 2. UART Configuration Options INSTANCE FLOW CONTROL 96 WLP MAXIMUM BAUD RATE (KB) YES NO 4000 YES YES 4000 YES NO 4000 144 TQFP 140 WLP UART0 YES UART1 YES UART2 YES 1-Wire Master ●● 320 x 200, 320 x 240, Maxim's 1-wire bus consists of a single line to provide both power and data communications and a ground return. The bus supports a serial, multidrop communication protocol between a master and one or more slave devices with the minimum amount of interconnection. ●● 640 x 200, 640 x 240, 640 x 480 Maxim's 1-wire bus consists of one signal that carries data and also supplies power to the slave devices, and a ground return. The bus master communicates serially with one or more slave devices through the bidirectional, multidrop 1-Wire bus. The single contact serial interface is ideal for communication networks requiring minimal interconnection. ●● 4096 x 4096 The provided 1-Wire master supports the following features: ●● 800 x 600 ●● 1024 x 768 ●● 2048 x 2048 Debug and Development Interface (SWD/JTAG) Special versions of the device are available with a serial wire debug or JTAG interface that is used only during application development and debugging. The interface is used for code loading, ICE debug activities, and control of boundary scan activities. ●● Single contact for control and operation Trust Protection Unit (MAX32651 Only) ●● Unique factory identifier for any 1-Wire device True Random Number Generator ●● Multiple device capability on a single line The MAX32650–MAX32652 1-Wire master supports both the standard (15.6kbps) and overdrive (110kbps) speeds. 24-Bit Color TFT Controller The 24-bit color TFT controller is controlled by the CPU through the APB and fed graphic data through the AHB. The controller supports the following display types: ●● Active matrix TFT panels with up to 24-bit bus interface ●● Single/dual-panel monochrome STN panels (4-bit and 8-bit bus interface) ●● Single/dual-panel color STN panels, 8-bit bus interface ●● TFT panels up to 24bpp, direct 8:8:8 RGB ●● Color STN panels up to 16bpp, direct 5:5:5 with one bit not being used ●● Mono STN panels up to 4bpp, pelletized, 16 gray scales selected from 16 Random numbers are a vital part of a secure application, providing random numbers that can be used for cryptographic seeds or strong encryption keys to ensure data privacy. Software can use random numbers to trigger asynchronous events that result in nondeterministic behavior. This is helpful in thwarting replay attacks or key search approaches. An effective true random number generator (TRNG) must be continuously updated by a high-entropy source. The provided TRNG is continuously driven by a physicallyunpredictable entropy source. It generates a 128-bit true random number in 128 system clock cycles. The TRNG can support the system-level validation of many security standards such as FIPS 140-2, PCI-PED, and Common Criteria. Contact Maxim for details of compliance with specific standards. The controller can be programmed to operate a wide range of panel resolutions (including, but not limited to the following settings): www.maximintegrated.com Maxim Integrated │  39 MAX32650–MAX32652 Ultra-Low-Power Arm Cortex-M4 with FPU-Based Microcontroller (MCU) with 3MB Flash and 1MB SRAM MAA Additional Documentation and Technical Support The provided high-speed, hardware-based modulo arithmetic accelerator (MAA) performs mathematical computations that support strong cryptographic algorithms. These include:​ ●● 2048-bit DSA ●● 4096-bit RSA ●● Elliptic curve public key infrastructure AES The dedicated hardware-based AES engine supports the following algorithms: ●● AES-128 ●● AES-192 ●● AES-256 The AES keys are automatically generated by the engine and stored in dedicated flash to protect against tampering. Key generation and storage is transparent to the user. Designers must have the following documents to use all the features of this device: ●● This data sheet, which contains electrical/timing specifications, package information, and pin descriptions ●● The corresponding revision-specific errata sheet ●● The corresponding user guide, which contains detailed information and programming guidelines for core features and peripherals Applications Information GPIO and Alternate Function Matrix, 140 WLP Table 3. GPIO and Alternate Function Matrix, 140 WLP GPIO ALTERNATE FUNCTION 1 ALTERNATE FUNCTION 2 P0.0 PT3 SPIXF_SDIO2** P0.1 SPIXR_SDIO0** ― P0.2 SPIXR_SDIO2** ― P0.3 SPIXR_SCK** ― The device provides a hardware SHA-256 engine for fast computation of 256-bit digests. P0.4 SPIXR_SDIO3** ― P0.5 SPIXR_SDIO1** ― Memory Decryption Integrity Unit P0.6 SPIXR_SS0** ― P0.7 SPIXF_SS0** ― P0.8 SPIXF_SCK** ― SHA-256 SHA-256 is a cryptographic hash function part of the SHA-2 family of algorithms. It authenticates user data and verifies its integrity. It is used for digital signatures. The external SPI flash can optionally be encrypted for additional security. Data can be transparently encrypted when it is loaded and decrypted on-the-fly. Encryption keys are stored in the always-on domain and preserved as long as VRTC is present. Secure Bootloader The secure bootloader provides a secure, authenticated communication channel with a system host. The secure communication protocol (SCP) allows the programming of internal and external memory. The secure bootloader provides the following features: ●● Life cycle management ●● Authentications using ECDSA P-256, with 256-bit ECC key pairs and SHA-256 secure hash function ●● Preprogrammed Maxim manufacturer root key (MRK) ●● Programmable customer root key (CRK) ●● Support for 2048- or 4096-bit RSA digital signature www.maximintegrated.com P0.9 SPIXF_SDIO1** ― P0.10 SPIXF_SDIO0** ― P0.11 SPIXF_SDIO2** ― P0.12 SPIXF_SDIO3** ― P0.13 SPI3_SS1 CLCD_G0 P0.14 SPI3_SS2 CLCD_G1 P0.15 SPI3_SDIO3 CLCD_G2 P0.16 SPI3_SCK CLCD_G3 P0.17 SPI3_SDIO2 CLCD_G4 P0.18 SPI3_SS3 CLCD_G5 P0.19 SPI3_SS0 CLCD_G6 P0.20 SPI3_SDIO1 CLCD_G7 P0.21 SPI3_SDIO0 — P0.22 SPI0_SS0 CLCD_VDEN P0.23 PT15 CLCD_CLK Maxim Integrated │  40 MAX32650–MAX32652 Ultra-Low-Power Arm Cortex-M4 with FPU-Based Microcontroller (MCU) with 3MB Flash and 1MB SRAM Table 3. GPIO and Alternate Function Matrix, 140 WLP (continued) GPIO ALTERNATE FUNCTION 1 ALTERNATE FUNCTION 2 GPIO ALTERNATE FUNCTION 1 ALTERNATE FUNCTION 2 P0.24 RXEV CLCD_HSYNC P1.30 OWM_PUPEN CLCD_R0 P0.25 TXEV CLCD_B0 P1.31 OWM_IO CLCD_R1 P0.26 TDI TDI P2.0 SPI2_SS2 PT9 P0.27 TDO TDO P2.1 SPI2_SS1 PT10 P0.28 TMS (SWDIO)†† TMS (SWDIO)†† P2.2 SPI2_SCK (I2S_BCLK)† CLCD_LEND P0.29 TCK (SWDCLK)†† TCK (SWDCLK)†† P2.3 SPI2_MISO (I2S_SDI)† CLCD_PWREN P0.30 — CLCD_B0 P2.4 SPI2_MOSI (I2S_SDO)† ― P0.31 32KCAL SDHC_CDN P2.5 SPI2_SS0 (I2S_LRCLK)† PT11 P1.0 SDHC_CMD SPIXF_SDIO3** P2.6 SPI2_SS3 CLCD_VSYNC P1.1 SDHC_DAT2 SPIXF_SDIO1** P2.7 I2C0_SDA ― P1.2 SDHC_WP SPIXF_SS0** P2.8 I2C0_SCL ― P1.3 SDHC_DAT3 CLCD_CLK P2.9 UART0_CTS PT12 P1.4 SDHC_DAT0 SPIXF_SDIO0** P2.10 UART0_RTS PT14 P1.5 SDHC_CLK SPIXF_SCK** P2.11 UART0_RX PT13 P1.6 SDHC_DAT1 PT0 P2.12 UART0_TX PT15 P1.7 UART2_CTS PT1 P2.13 UART1_CTS CLCD_R2 P1.8 UART2_RTS PT2 P2.14 UART1_RX CLCD_R3 P1.9 UART2_RX PT3 P2.15 UART1_RTS CLCD_R4 P1.10 UART2_TX PT4 P2.16 UART1_TX CLCD_R5 P1.11 HYP_CS0N SPIXR_SDIO0** P2.17 I2C1_SDA CLCD_R6 P1.12 HYP_D0 SPIXR_SDIO1** P2.18 I2C1_SCL CLCD_R7 P1.13 HYP_D4 SPIXR_SS0** P2.19 PT4 ― P1.14 HYP_RWDS PT5 P2.20 PT5 ― P1.15 HYP_D1 SPIXR_SDIO2** P2.21 PT7 ― P1.16 HYP_D5 SPIXR_SCK** P2.22 PT8 ― P1.17 PT9 ― P2.23 PT6 SPIXR_SDIO3** P1.18 HYP_D6 PT6 P2.24 PT10 ― P1.19 HYP_D2 PT7 P2.25 PT11 ― P1.20 HYP_D3 CLCD_HSYNC P2.26 PT12 ― P1.21 HYP_D7 PT8 P2.27 PT13 ― P1.22* ― ― P2.28 PT14 ― P1.23 SPI1_SS0 CLCD_B1 P2.29 PT0 ― P1.24 SPI1_SS2 CLCD_B2 P2.30 PT1 ― P1.25 SPI1_SS1 CLCD_B3 P2.31 PT2 ― P1.26 SPI1_SCK CLCD_B4 P3.0 PDOWN HYP_CS1N P1.27 SPI1_SS3 CLCD_B5 P3.1 SPI0_MISO ― P1.28 SPI1_MISO CLCD_B6 P3.2 SPI0_MOSI ― P1.29 SPI1_MOSI CLCD_B7 P3.3 SPI0_SCK ― www.maximintegrated.com Maxim Integrated │  41 MAX32650–MAX32652 Ultra-Low-Power Arm Cortex-M4 with FPU-Based Microcontroller (MCU) with 3MB Flash and 1MB SRAM Table 3. GPIO and Alternate Function Matrix, 140 WLP (continued) GPIO ALTERNATE FUNCTION 1 ALTERNATE FUNCTION 2 GPIO ALTERNATE FUNCTION 1 ALTERNATE FUNCTION 2 P3.4 TMR0 ― P3.7 TMR1 ― P3.5 TMR2 ― P3.8 TMR3 ― P3.6 TMR4 ― P3.9 TMR5 ― *GPIO not pinned out. **This signal can be mapped to more than one GPIO, but there is only one instance of this peripheral. †I2S_BCLK, I2S_LRCLK, I2S_SDI, and I2S_SDO when enabled. ††Single-wire debug when enabled. GPIO and Alternate Function Matrix, 96 WLP Table 4. GPIO and Alternate Function Matrix, 96 WLP ALTERNATE FUNCTION 1 ALTERNATE FUNCTION 2 P0.27 TDO — P0.28 TMS (SWDIO)†† — — P0.29 TCK (SWDCLK)†† — — P0.30 — CLCD_B0 — — P0.31* — — P0.5* — — P1.0 SDHC_CMD SPIXF_SDIO3** P0.6* — — P1.1 SDHC_DAT2 SPIXF_SDIO1** P0.7* — — P1.2 SDHC_WP SPIXF_SS0** P0.8* — — P1.3 SDHC_DAT3 CLCD_CLK GPIO ALTERNATE FUNCTION 1 ALTERNATE FUNCTION 2 GPIO P0.0* — — P0.1* — — P0.2* — P0.3* — P0.4* P0.9* — — P1.4 SDHC_DAT0 SPIXF_SDIO0** P0.10* — — P1.5 SDHC_CLK SPIXF_SCK** P0.11 SPIXF_SDIO2** P0.11 P1.6 SDHC_DAT1 PT0 P0.12* — — P1.7* — — P0.13 SPI3_SS1 CLCD_G0 P1.8 UART2_RTS PT2 P0.14 SPI3_SS2 CLCD_G1 P1.9 UART2_RX PT3 P0.15 SPI3_SDIO3 CLCD_G2 P1.10 UART2_TX PT4 P0.16 SPI3_SCK CLCD_G3 P1.11 — SPIXR_SDIO0** P0.17 SPI3_SDIO2 CLCD_G4 P1.12 — SPIXR_SDIO1** P0.18 SPI3_SS3 CLCD_G5 P1.13 — SPIXR_SS0** P0.19 SPI3_SS0 CLCD_G6 P1.14 — PT5 P0.20 SPI3_SDIO1 CLCD_G7 P1.15 — SPIXR_SDIO2** P0.21 SPI3_SDIO0 — P1.16 — SPIXR_SCK** P0.22 SPI0_SS0 CLCD_VDEN P1.17* — — P0.23* — — P1.18 — PT6 P0.24* — — P1.19 — PT7 P0.25* — — P1.20 — CLCD_HSYNC P0.26 TDI — P1.21 — PT8 www.maximintegrated.com Maxim Integrated │  42 MAX32650–MAX32652 Ultra-Low-Power Arm Cortex-M4 with FPU-Based Microcontroller (MCU) with 3MB Flash and 1MB SRAM Table 4. GPIO and Alternate Function Matrix, 96 WLP (continued) GPIO ALTERNATE FUNCTION 1 ALTERNATE FUNCTION 2 GPIO ALTERNATE FUNCTION 1 ALTERNATE FUNCTION 2 P1.22* — — P2.15 UART1_RTS CLCD_R4 P1.23 SPI1_SS0 CLCD_B1 P2.16 UART1_TX CLCD_R5 P1.24 SPI1_SS2 CLCD_B2 P2.17 I2C1_SDA CLCD_R6 P1.25 SPI1_SS1 CLCD_B3 P2.18 I2C1_SCL CLCD_R7 P1.26 SPI1_SCK CLCD_B4 P2.19* — — P1.27 SPI1_SS3 CLCD_B5 P2.20* — — P1.28 SPI1_MISO CLCD_B6 P2.21* — — P1.29 SPI1_MOSI CLCD_B7 P2.22* — — P1.30 OWM_PUPEN CLCD_R0 P2.23 PT6 SPIXR_SDIO3** P1.31 OWM_IO CLCD_R1 P2.24* — — P2.0 SPI2_SS2 PT9 P2.25* — — P2.1* — — P2.26* — — P2.2 SPI2_SCK (I2SBCLK)† CLCD_LEND P2.27* — — P2.3 SPI2_MISO (I2S-SDI)† CLCD_PWREN P2.28* — — — — P2.4 SPI2_MOSI (I2SSDO)† P2.29* — P2.30* — — — — P2.5 SPI2_SS0 (I2S_LRCLK)† P2.31* PT11 P3.0* — — P2.6 SPI2_SS3 CLCD_VSYNC P3.1* — — P2.7* — — P3.2* — — P2.8* — — P3.3* — — P2.9 UART0_CTS PT12 P3.4 TMR0 — P2.10* — — P3.5 TMR2 — P2.11 UART0_RX PT13 P3.6 TMR4 — P2.12 UART0_TX PT15 P3.7 TMR1 — P2.13 UART1_CTS CLCD_R2 P3.8 TMR3 — P2.14 UART1_RX CLCD_R3 P3.9 TMR5 — *GPIO not pinned out. **This signal can be mapped to more than one GPIO, but there is only one instance of this peripheral. †I2S_BCLK, I2S_LRCLK, I2S_SDI, I2S_SDO when enabled. ††Single-wire debug when enabled. www.maximintegrated.com Maxim Integrated │  43 MAX32650–MAX32652 Ultra-Low-Power Arm Cortex-M4 with FPU-Based Microcontroller (MCU) with 3MB Flash and 1MB SRAM GPIO and Alternate Function Matrix, 144 TQFP Table 5. GPIO and Alternate Function Matrix, 144 TQFP GPIO ALTERNATE FUNCTION 1 ALTERNATE FUNCTION 2 GPIO ALTERNATE FUNCTION 1 ALTERNATE FUNCTION 2 P0.0* — — P1.2 SDHC_WP SPIXF_SS0** P0.1 SPIXR_SDIO0** — P1.3 SDHC_DAT3 CLCD_CLK P0.2 SPIXR_SDIO2** — P1.4 SDHC_DAT0 SPIXF_SDIO0** P0.3 SPIXR_SCK** — P1.5 SDHC_CLK SPIXF_SCK** P0.4 SPIXR_SDIO3** — P1.6 SDHC_DAT1 PT0 P0.5 SPIXR_SDIO1** — P1.7 UART2_CTS PT1 P0.6 SPIXR_SS0** — P1.8 UART2_RTS PT2 P0.7 SPIXF_SS0** — P1.9 UART2_RX PT3 P0.8 SPIXF_SCK** — P1.10 UART2_TX PT4 P0.9 SPIXF_SDIO1** — P1.11 HYP_CS0N SPIXR_SDIO0** P0.10 SPIXF_SDIO0** — P1.12 HYP_D0 SPIXR_SDIO1** P0.11 SPIXF_SDIO2** — P1.13 HYP_D4 SPIXR_SS0** P0.12 SPIXF_SDIO3** — P1.14 HYP_RWDS PT5 P0.13 SPI3_SS1 CLCD_G0 P1.15 HYP_D1 SPIXR_SDIO2** P0.14 SPI3_SS2 CLCD_G1 P1.16 HYP_D5 SPIXR_SCK** P0.15 SPI3_SDIO3 CLCD_G2 P1.17 PT9 — P0.16 SPI3_SCK CLCD_G3 P1.18 HYP_D6 PT6 P0.17 SPI3_SDIO2 CLCD_G4 P1.19 HYP_D2 PT7 P0.18 SPI3_SS3 CLCD_G5 P1.20 HYP_D3 CLCD_HSYNC P0.19 SPI3_SS0 CLCD_G6 P1.21 HYP_D7 PT8 P0.20 SPI3_SDIO1 CLCD_G7 P1.22 — — P0.21 SPI3_SDIO0 — P1.23 SPI1_SS0 CLCD_B1 P0.22 SPI0_SS0 CLCD_VDEN P1.24 SPI1_SS2 CLCD_B2 P0.23 PT15 CLCD_CLK P1.25 SPI1_SS1 CLCD_B3 P0.24 RXEV CLCD_HSYNC P1.26 SPI1_SCK CLCD_B4 P0.25 TXEV CLCD_B0 P1.27 SPI1_SS3 CLCD_B5 P0.26 TDI — P1.28 SPI1_MISO CLCD_B6 P0.27 TDO — P1.29 SPI1_MOSI CLCD_B7 P0.28 TMS (SWDIO)††† — P1.30 OWM_PUPEN CLCD_R0 P0.29 TCK (SWDCLK)††† — P1.31 OWM_IO CLCD_R1 P0.30 — CLCD_B0 P2.0 SPI2_SS2 PT9 P0.31 32KCAL SDHC_CDN P2.1 SPI2_SS1 PT10 P1.0 SDHC_CMD SPIXF_SDIO3** P1.1 SDHC_DAT2 SPIXF_SDIO1** P2.2 SPI2_SCK (I2S-BCLK)† CLCD_LEND www.maximintegrated.com Maxim Integrated │  44 MAX32650–MAX32652 Ultra-Low-Power Arm Cortex-M4 with FPU-Based Microcontroller (MCU) with 3MB Flash and 1MB SRAM Table 5. GPIO and Alternate Function Matrix, 144 TQFP (continued) GPIO ALTERNATE FUNCTION 1 ALTERNATE FUNCTION 2 GPIO ALTERNATE FUNCTION 1 ALTERNATE FUNCTION 2 P2.3 SPI2_MISO (I2S-SDI)† CLCD_PWREN P2.22* — — P2.4 SPI2_MOSI (I2S-SDO)† — P2.23 PT6 SPIXR_SDIO3** — — P2.5 SPI2_SS0 (I2S_LRCLK)† P2.24* PT11 P2.25 PT11 — P2.6 SPI2_SS3 CLCD_VSYNC P2.26 PT12 — P2.7 I2C0_SDA — P2.27* — — P2.8 I2C0_SCL — P2.28 PT14 — P2.9 UART0_CTS PT12 P2.29* — — P2.10 UART0_RTS PT14 P2.30 PT1 — P2.11 UART0_RX PT13 P2.31* — — P2.12 UART0_TX PT15 P3.0 PDOWN HYP_CS1N P2.13 UART1_CTS CLCD_R2 P3.1 SPI0_MISO — P2.14 UART1_RX CLCD_R3 P3.2 SPI0_MOSI — P2.15 UART1_RTS CLCD_R4 P3.3 SPI0_SCK — P2.16 UART1_TX CLCD_R5 P3.4 TMR0 — P2.17 I2C1_SDA CLCD_R6 P3.5 TMR2 — P2.18 I2C1_SCL CLCD_R7 P3.6 TMR4 — P2.19* — — P3.7 TMR1 — P2.20* — — P3.8 TMR3 — P2.21* — — P3.9 TMR5 — *GPIO not pinned out. **This signal can be mapped to more than one GPIO, but there is only one instance of this peripheral. †I2S_BCLK, I2S_LRCLK, I2S_SDI, I2S_SDO when enabled. ††PBM Interface signal when enabled. †††Single-wire debug when enabled. www.maximintegrated.com Maxim Integrated │  45 MAX32650–MAX32652 Ultra-Low-Power Arm Cortex-M4 with FPU-Based Microcontroller (MCU) with 3MB Flash and 1MB SRAM Typical Application Circuit Pulse Oximeter and Heart Rate Monitor with BLE and GPS Location VDD VDD VDD ACCELEROMETER SDA SCL VDD VDD POWER MANAGEMENT VBAT GPS SCL RPU_SCL0 VDD RPU_SDA0 RPU_SCL1 RPU_SDA1 VBAT SCL GPIO1 GND RSTN DRIVEP VDD M 1.8V 1.8V BUCK DRIVEN 1.1V 1.1V BUCK HV 1.8V 1.8V LDO MAX32650 MAX32651 MAX32652 3.3V LED0 USB 2.0 HI-SPEED LED1 VDD INT HIGH-SENSITIVITY PULSE OXIMETER AND HEART RATE SENSOR FOR WEARABLE HEALTH VDD VDDIO VCORE SPI BLUETOOTH™ LOW ENERGY VRTC TFT CONTROLLER 3.3V LDO SDA VLED+ MAX30101 RTC RST VDD SDA1 SCL1 BAT Li+ 2.7 TO 5.5V VDD SDA SCL SDA0 SCL0 VIBRATION MOTOR SDA VDD 24-BIT COLOR TFT DISPLAY VDD VDDB DP DM SDHC CONTROLLER SECURE DIGITAL HIGH CAPACITY STORAGE PIEZO BUZZER The Bluetooth word mark and logos are registered trademarks owned by Bluetooth SIG, Inc. and any use of such marks by Maxim is under license. Ordering Information PART TRUST PROTECTION UNIT WITH SECURE PIN-PACKAGE BOOTLOADER MAX32650GWQ+* No 96 WLP (0.4mm pitch) MAX32650GWQ+T* No 96 WLP (0.4mm pitch) MAX32650GCE+* No 144 TQFP MAX32651GWQ+ Yes 96 WLP (0.4mm pitch) PART TRUST PROTECTION UNIT WITH SECURE PIN-PACKAGE BOOTLOADER MAX32651GWQ+T Yes 96 WLP (0.4mm pitch) MAX32651GCE+* Yes 144 TQFP MAX32652GWE+ No 140 WLP (0.35mm pitch) MAX32652GWE+T No 140 WLP (0.35mm pitch) +Denotes a lead(Pb)-free/RoHS-compliant package. T = Tape and reel. *Future product—contact factory for availability. www.maximintegrated.com Maxim Integrated │  46 MAX32650–MAX32652 Ultra-Low-Power Arm Cortex-M4 with FPU-Based Microcontroller (MCU) with 3MB Flash and 1MB SRAM Revision History REVISION NUMBER REVISION DATE PAGES CHANGED 0 12/17 Initial release — 1 3/18 Updated General Description and Benefits and Features sections 1 2 10/18 Updated title, Absolute Maximum Ratings, Debug and Development Interface (SWD/ JTAG), and Ordering Information sections 3 12/18 Updated Debug and Development Interface (SWD/JTAG) section and Ordering Information DESCRIPTION 1, 2, 39, 46 39, 46 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com. Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc. © 2018 Maxim Integrated Products, Inc. │  47
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