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MAX32672
High-Reliability, Tiny, Ultra-Low-Power
Arm Cortex-M4F Microcontroller
with 12-Bit, 1Msps ADC
General Description
Benefits and Features
In the DARWIN family, the MAX32672 is an ultra-lowpower, cost-effective, highly integrated, and highly reliable
32-bit microcontroller enabling designs with complex sensor processing without compromising battery life. It combines a flexible and versatile power management unit with
the powerful Arm® Cortex®-M4 processor with a floatingpoint unit (FPU). The MAX32672 also offers legacy designs an easy and cost-optimal upgrade path from 8- or
16-bit microcontrollers.
● High-Efficiency Microcontroller for Low-Power HighReliability Devices
• Arm Cortex-M4 Processor with FPU up to 100MHz
• 1MB Dual-Bank Flash with Error Correction
• 200KB SRAM (160KB with ECC Enabled),
Optionally Preserved in Lowest Power Modes
• EEPROM Emulation on Flash
• 16KB Unified Cache with ECC
• Resource Protection Unit (RPU) and Memory
Protection Unit (MPU)
• Dual- or Single-Supply Operation, 1.7V to 3.6V
• Wide Operating Temperature: -40°C to +105°C
The device integrates 1MB of flash and 200KB of SRAM
to accommodate application and sensor code. Error correction coding (ECC) is implemented on the entire flash,
RAM, and cache to ensure extremely reliable code execution even in the harshest of environments. Brownout detection ensures proper operation during power-down and
power-up events and unexpected supply transients. The
flash is organized into two equal-size physical banks to allow execute-while-write and facilitate "live upgrades."
Multiple high-speed peripherals such as 3.4MHz I2C,
50MHz SPI, and UART are included to maximize communication bandwidth. In addition, a low-power UART
(LPUART) is available for operation in the lowest power
sleep modes to facilitate wake-up activity without any loss
of data. A total of six timers with I/O capability are provided, including two low-power timers to enable pulse counting, capture/compare, and pulse-width modulation (PWM)
generation, even in the lowest power sleep modes. An incremental/quadrature encoder interface with multiple diagnostics is included specifically for motor control applications. A 1Msps, 12-channel, 12-bit successive approximation register (SAR) ADC is integrated for the digitization
of analog sensor signals or other analog measurements.
Two low-power comparators, available in all low-power
modes, allow energy-efficient monitoring and wake-up on
external analog signals. An Elliptic Curve Digital Signature Algorithm (ECDSA)-based cryptographic secure bootloader is available in ROM. The device is available in a
5mm x 5mm, 40-pin TQFN-EP or 7mm x 7mm, 56-pin
TQFN.
Applications
● Motion/Motor Control, Industrial Sensors
● Optical Communication Modules, Secure Radio
Modem Controller
● Battery-Powered Medical Devices
● Flexible Clocking Schemes
• Internal High-Speed 100MHz Oscillator
• Internal Low-Power 7.3728MHz and Ultra-LowPower 80kHz Oscillators
• 16MHz–32MHz Oscillator, 32.768kHz Oscillator
(External Crystal Required)
• External Clock Input for CPU, LPUART, LPTMR
● Power Management Maximizes Uptime for Battery
Applications
• 59.8μA/MHz ACTIVE at 0.9V up to 12MHz
(CoreMark®)
• 56.6μA/MHz ACTIVE at 1.1V up to 100MHz
(While(1))
• 3.09μA Full Memory Retention Power in BACKUP
Mode at VDD = 1.8V
• 350nA Ultra-Low-Power RTC at VDD = 1.8V
• Wake from LPUART or LPTMR
● Optimal Peripheral Mix Provides Platform Scalability
• Up to 42 General-Purpose I/O Pins
• Up to Three SPI Master/Slave (up to 50Mbps)
• Up to Three 4-Wire UART
• Up to Three I2C Master/Slave 3.4Mbps High Speed
• Up to Four 32-Bit Timers (TMR)
• Up to Two Low-Power 32-Bit Timers (LPTMR)
• One I2S Master/Slave for Digital Audio Interface
• 12-Channel, 12-Bit, 1Msps SAR ADC with On-Die
Temperature Sensor
● Security and Integrity
• Optional ECDSA-Based Cryptographic Secure
Bootloader in ROM
• Secure Cryptographic Accelerator for Elliptic Curve
• AES-128/192/256 Hardware Acceleration Engine
Arm and Cortex are registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
CoreMark is a registered trademark of EEMBC.
Ordering Information appears at end of data sheet.
19-101210; Rev 2; 5/23
© 2023 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.
One Analog Way, Wilmington, MA 01887 U.S.A. | Tel: 781.329.4700 | © 2023 Analog Devices, Inc. All rights reserved.
MAX32672
High-Reliability, Tiny, Ultra-Low-Power
Arm Cortex-M4F Microcontroller
with 12-Bit, 1Msps ADC
Simplified Block Diagram
MAX32672
100MHz (IPO)
HFXOUT
HFXIN
16MHz– 32MHz (ERFO)
7.3728MHz (IBRO)
EXTERNAL CLOCK
32KOUT
32KIN
32.768kHz (ERTCO)
HOST
Arm Cortex-M4 WITH
FPU CPU
SERIAL WIRE DEBUG (SWD)
*4 x 32-BIT TIMER
NVIC
80kHz (INRO)
GPIO AND
SHARED PAD
FUNCTIONS
*2 x 32-BIT LOW POWER TIMER
MEMORY
VCORE
VDD
VSS
VREG1
VREF
VDDA
VSSA
32KIN
SRAM 200KB
(160KB WITH
ECC)
16KB CACHE
(WITH ECC)
REGULATOR/
POWER CONTROL
12-CHANNEL
STANDARD DMA
QUADRATURE DECODER
INTERFACE
*3 x I2C MASTER/SLAVE
I2S MASTER/SLAVE
*3 x 4-WIRE UART
1 x 4-WIRE LOW POWER UART
VCORE
12-BIT
1Msps ADC
(SAR)
12
EXTERNAL
CHANNELS
VDDA
2 COMPARATORS
12
2 x WINDOWED
WATCHDOG TIMER
RTC
32KOUT
TIMER
LOW-POWER TIMER
ADC
COMPARATORS
SPI
I2 C
UART
LPUART
I2 S
32kHz OUTPUT
SINGLE-WIRE
DEBUG
EXT CLK INPUT/
OUTPUT
ADC TRIGGER
*3 x SPI MASTER/SLAVE
BUS MATRIX – AHB, APB, IBUS, DBUS…
RSTN
POR,
BROWNOUT
MONITOR,
SUPPLY VOLTAGE
MONITORS
FLASH 1MB
DUAL BANK
(WITH ECC)
GPIO/
ALTERNATE
FUNCTION
VDD
TEMP
SENSOR
2
EXTERNAL
INTERRUPTS
12
2
SECURITY
32-BIT CRC
ACCELERATOR
SECURE CRYPTO
SHA-2
ACCELERATOR (SCA)
SECURE NV KEY
SECURE BOOTLOADER
TRUE RANDOM NUMBER GENERATOR (TRNG)
AES-128/192/256
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*NOT ALL PACKAGES
PROVIDE THE FULL
COMPLEMENT OF HIS
PERIPHERAL. SEE ORDERING
INFORMATION FOR DETAILS.
Analog Devices | 2
MAX32672
High-Reliability, Tiny, Ultra-Low-Power
Arm Cortex-M4F Microcontroller
with 12-Bit, 1Msps ADC
TABLE OF CONTENTS
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Benefits and Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Simplified Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
40 TQFN-EP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
56 TQFN-EP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Electrical Characteristics—SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Electrical Characteristics—I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Electrical Characteristics—I2S Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Electrical Characteristics—Quadrature Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
40 TQFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
56 TQFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Arm Cortex-M4 Processor with FPU Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Internal Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Internal SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Clocking Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
General-Purpose I/O and Special Function Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Standard DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Power Management Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
ACTIVE Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
SLEEP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
DEEPSLEEP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
BACKUP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
STORAGE Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Real-Time Clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Windowed Watchdog Timer (WDT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
32-Bit Timer/Counter/PWM (TMR, LPTMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Serial Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
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Analog Devices | 3
MAX32672
High-Reliability, Tiny, Ultra-Low-Power
Arm Cortex-M4F Microcontroller
with 12-Bit, 1Msps ADC
TABLE OF CONTENTS (CONTINUED)
Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
I2S Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Quadrature Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Analog-to-Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
AES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Secure Cryptographic Accelerator (SCA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
True Random Number Generator (TRNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
CRC Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
SHA-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Software Integrity and Root of Trust . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Root of Trust . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Secure Communications Protocol Bootloader (SCPBL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Secure Boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Debug and Development Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Bypass Capacitor Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Bootloader Activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Single Supply Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
ACTIVE Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
SLEEP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
ACTIVE Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
SLEEP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
DEEPSLEEP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
BACKUP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
STORAGE Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Dual Supply Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
ACTIVE Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
ACTIVE Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
SLEEP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
SLEEP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
ACTIVE Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
ACTIVE Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
SLEEP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
SLEEP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
DEEPSLEEP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
DEEPSLEEP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
BACKUP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
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Analog Devices | 4
MAX32672
High-Reliability, Tiny, Ultra-Low-Power
Arm Cortex-M4F Microcontroller
with 12-Bit, 1Msps ADC
TABLE OF CONTENTS (CONTINUED)
BACKUP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
STORAGE Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
STORAGE Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
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Analog Devices | 5
MAX32672
High-Reliability, Tiny, Ultra-Low-Power
Arm Cortex-M4F Microcontroller
with 12-Bit, 1Msps ADC
LIST OF FIGURES
Figure 1. Power Supply Operational Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 2. SPI Master Mode Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 3. SPI Slave Mode Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 4. I2C Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 5. I2S Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 6. Quadrature Decoder Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 7. Clocking Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
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Analog Devices | 6
MAX32672
High-Reliability, Tiny, Ultra-Low-Power
Arm Cortex-M4F Microcontroller
with 12-Bit, 1Msps ADC
LIST OF TABLES
Table 1. BACKUP Mode RAM Retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 2. MAX32672 Watchdog Timer Instances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 3. MAX32672 Timer Instances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 4. MAX32672 I2C Instances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 5. MAX32672 SPI Instances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 6. MAX32672 UART Instances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 7. Common CRC Polynomials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 8. Bootloader Activation Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 9. Fixed VDD Current Consumption ACTIVE Mode, IPO, Single Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 10. Fixed VDD Current Consumption SLEEP Mode, IPO, Single Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 11. Fixed VDD Current Consumption ACTIVE Mode, IBRO, Single Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 12. Fixed VDD Current Consumption SLEEP Mode, IBRO, Single Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 13. Fixed VDD Current Consumption DEEPSLEEP Mode, Single Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 14. Fixed VDD Current Consumption BACKUP Mode, Single Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 15. Fixed VDD Current Consumption STORAGE Mode, Single Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 16. Fixed VCORE Current Consumption ACTIVE Mode, IPO, Dual Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 17. Fixed VDD Current Consumption ACTIVE Mode, IPO, Dual Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 18. Fixed VCORE Current Consumption SLEEP Mode, IPO, Dual Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 19. Fixed VDD Current Consumption SLEEP Mode, IPO, Dual Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 20. Fixed VCORE Current Consumption ACTIVE Mode, IBRO, Dual Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 21. Fixed VDD Current Consumption ACTIVE Mode, IBRO, Dual Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 22. Fixed VCORE Current Consumption SLEEP Mode, IBRO, Dual Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 23. Fixed VDD Current Consumption SLEEP Mode, IBRO, Dual Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 24. Fixed VCORE Current Consumption DEEPSLEEP Mode, Dual Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 25. Fixed VDD Current Consumption DEEPSLEEP Mode, Dual Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 26. Fixed VCORE Current Consumption BACKUP Mode, Dual Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 27. Fixed VDD Current Consumption BACKUP Mode, Dual Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 28. Fixed VCORE Current Consumption STORAGE Mode, Dual Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 29. Fixed VDD Current Consumption STORAGE Mode, Dual Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
www.analog.com
Analog Devices | 7
MAX32672
High-Reliability, Tiny, Ultra-Low-Power
Arm Cortex-M4F Microcontroller
with 12-Bit, 1Msps ADC
Absolute Maximum Ratings
VCORE, HFXIN, HFXOUT ................................... -0.3V to +1.21V
VDD, VDDA .......................................................... -0.3V to +3.63V
VREF ........................................................... -0.3V to VDDA + 0.3V
32KIN, 32KOUT ........................................... -0.3V to VDD + 0.3V
RSTN, GPIO ................................................. -0.3V to VDD + 0.3V
Total Current into All GPIO Combined (sink) .................... 100mA
VSS .................................................................................... 100mA
Output Current (sink) by Any GPIO Pin ............................... 25mA
Output Current (source) by Any GPIO Pin ......................... -25mA
Continuous Package Power Dissipation 40 TQFN-EP (multilayer
board)
TA
=
+70°C
(derate
35.7mW/°C
above
+70°C) ........................................................................2857.10mW
Continuous Package Power Dissipation 56 TQFN-EP (multilayer
board) TA = +70°C (derate 40mW/°C above +70°C) ......3200mW
Operating Temperature Range ...........................-40°C to +105°C
Storage Temperature Range ..............................-65°C to +125°C
Soldering Temperature (reflow) ........................................ +260°C
Note: No device pins can exceed 3.63V. All voltages with respect to VSS, unless otherwise noted.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the
device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Package Information
40 TQFN-EP
Package Code
T4055+1
Outline Number
21-0140
Land Pattern Number
90-0016
Thermal Resistance, Single-Layer Board:
Junction to Ambient (θJA)
45°C/W
Junction to Case (θJC)
2°C/W
Thermal Resistance, Four-Layer Board:
Junction to Ambient (θJA)
28°C/W
Junction to Case (θJC)
2°C/W
56 TQFN-EP
Package Code
T5677+1
Outline Number
21-0144
Land Pattern Number
90-0042
Thermal Resistance, Single-Layer Board:
Junction to Ambient (θJA)
36°C/W
Junction to Case (θJC)
1°C/W
Thermal Resistance, Four-Layer Board:
Junction to Ambient (θJA)
25°C/W
Junction to Case (θJC)
1°C/W
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates
RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal
considerations, refer to www.maximintegrated.com/thermal-tutorial.
www.analog.com
Analog Devices | 8
MAX32672
High-Reliability, Tiny, Ultra-Low-Power
Arm Cortex-M4F Microcontroller
with 12-Bit, 1Msps ADC
Electrical Characteristics
(All specifications and characteristics apply across the entire operating conditions range unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
POWER / BOTH SINGLE-SUPPLY OPERATION AND DUAL-SUPPLY OPERATION
Supply Voltage
Supply Voltage, Core
VDD
VCORE
Dual-supply
operation
1.71
1.8
3.63
0.855
0.9
0.945
OVR = [01]
0.95
1.0
1.05
Default OVR = [10]
1.045
1.1
1.155
OVR = [00]
No power supply connection for singlesupply operation
Supply Voltage, Analog
VDDA
Power-Fail Reset
Voltage
VRST
Power-On Reset
Voltage
VPOR
www.analog.com
V
—
VDDA must be connected to VDD
1.71
3.63
Monitors VDD
1.58
1.71
Monitors VCORE during dual-supply
operation
0.74
0.845
Monitors VDD
1.4
Monitors VCORE during dual-supply
operation
0.6
V
V
V
Analog Devices | 9
MAX32672
High-Reliability, Tiny, Ultra-Low-Power
Arm Cortex-M4F Microcontroller
with 12-Bit, 1Msps ADC
Electrical Characteristics (continued)
(All specifications and characteristics apply across the entire operating conditions range unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER / SINGLE-SUPPLY OPERATION (VDD ONLY); fSYS_OSC = IPO
Dynamic, IPO
enabled, total
current into VDD
pin, VDD = 3.3V,
CPU in ACTIVE
mode, executing
CoreMark, ECC
disabled, inputs
tied to VSS or VDD,
outputs source/sink
0mA
VDD Current ACTIVE
Mode
IDD_DACTS
Dynamic, IPO
enabled, total
current into VDD
pin, VDD = 1.8V,
CPU in ACTIVE
mode, executing
CoreMark, ECC
disabled, inputs
tied to VSS or VDD,
outputs source/sink
0mA
Dynamic, IPO
enabled, total
current into VDD
pin, VDD = 3.3V,
CPU in ACTIVE
mode, executing
While(1), ECC
disabled, inputs
tied to VSS or VDD,
outputs source/sink
0mA
www.analog.com
OVR = [10],
internal regulator
set to 1.1V,
fSYS_CLK(MAX) =
100MHz
70
OVR = [01],
internal regulator
set to 1.0V,
fSYS_CLK(MAX) =
50MHz
68.4
OVR = [00],
internal regulator
set to 0.9V,
fSYS_CLK(MAX) =
12MHz
66.8
OVR = [10],
internal regulator
set to 1.1V,
fSYS_CLK(MAX) =
100MHz
69.4
OVR = [01],
internal regulator
set to 1.0V,
fSYS_CLK(MAX) =
50MHz
67.5
OVR = [00],
internal regulator
set to 0.9V,
fSYS_CLK(MAX) =
12MHz
65.9
OVR = [10],
internal regulator
set to 1.1V,
fSYS_CLK(MAX) =
100MHz
56.6
OVR = [01],
internal regulator
set to 1.0V,
fSYS_CLK(MAX) =
50MHz
54.3
OVR = [00],
internal regulator
set to 0.9V,
fSYS_CLK(MAX) =
12MHz
53.1
μA/MHz
Analog Devices | 10
MAX32672
High-Reliability, Tiny, Ultra-Low-Power
Arm Cortex-M4F Microcontroller
with 12-Bit, 1Msps ADC
Electrical Characteristics (continued)
(All specifications and characteristics apply across the entire operating conditions range unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
www.analog.com
TYP
56
OVR = [01],
internal regulator
set to 1.0V,
fSYS_CLK(MAX) =
50MHz
53.7
OVR = [00],
internal regulator
set to 0.9V,
fSYS_CLK(MAX) =
12MHz
52.5
Fixed, IPO
enabled, total
current into VDD
pin, VDD = 3.3V,
CPU in ACTIVE
mode 0MHz
execution, ECC
disabled, inputs
tied to VSS or VDD,
outputs source/sink
0mA.
See Table 9 for
temperature
variance.
OVR = [10],
internal regulator
set to 1.1V
893
OVR = [01],
internal regulator
set to 1.0V
732
OVR = [00],
internal regulator
set to 0.9V
618
Fixed, IPO
enabled, total
current into VDD
pin, VDD = 1.8V,
CPU in ACTIVE
mode 0MHz
execution, ECC
disabled, inputs
tied to VSS or VDD,
outputs source/sink
0mA.
See Table 9 for
temperature
variance.
OVR = [10],
internal regulator
set to 1.1V
865
OVR = [01],
internal regulator
set to 1.0V
708
OVR = [00],
internal regulator
set to 0.9V
594
Dynamic, IPO
enabled, total
current into VDD
pin, VDD = 1.8V,
CPU in ACTIVE
mode, executing
While(1), ECC
disabled, inputs
tied to VSS or VDD,
outputs source/sink
0mA
IDD_FACTS
MIN
OVR = [10],
internal regulator
set to 1.1V,
fSYS_CLK(MAX) =
100MHz
MAX
UNITS
μA
Analog Devices | 11
MAX32672
High-Reliability, Tiny, Ultra-Low-Power
Arm Cortex-M4F Microcontroller
with 12-Bit, 1Msps ADC
Electrical Characteristics (continued)
(All specifications and characteristics apply across the entire operating conditions range unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
Dynamic, IPO
enabled, total
current into VDD
pin, VDD = 3.3V,
CPU in SLEEP
mode, ECC
disabled, standard
DMA with two
channels active,
inputs tied to VSS
or VDD, outputs
source/sink 0mA
VDD Current SLEEP
Mode
IDD_DSLPS
Dynamic, IPO
enabled, total
current into VDD
pin, VDD = 1.8V,
CPU in SLEEP
mode, ECC
disabled, standard
DMA with two
channels active,
inputs tied to VSS
or VDD, outputs
source/sink 0mA
Dynamic, IPO
enabled, total
current into VDD
pin, VDD = 3.3V,
CPU in SLEEP
mode, ECC
disabled, DMA
disabled, inputs
tied to VSS or VDD,
outputs source/sink
0mA
www.analog.com
MIN
TYP
OVR = [10],
internal regulator
set to 1.1V,
fSYS_CLK(MAX) =
100MHz
44.9
OVR = [01],
internal regulator
set to 1.0V,
fSYS_CLK(MAX) =
50MHz
43.6
OVR = [00],
internal regulator
set to 0.9V,
fSYS_CLK(MAX) =
12MHz
43.8
OVR = [10],
internal regulator
set to 1.1V,
fSYS_CLK(MAX) =
100MHz
44.7
OVR = [01],
internal regulator
set to 1.0V,
fSYS_CLK(MAX) =
50MHz
43.3
OVR = [00],
internal regulator
set to 0.9V,
fSYS_CLK(MAX) =
12MHz
43.5
OVR = [10],
internal regulator
set to 1.1V,
fSYS_CLK(MAX) =
100MHz
21.4
OVR = [01],
internal regulator
set to 1.0V,
fSYS_CLK(MAX) =
50MHz
19.8
OVR = [00],
internal regulator
set to 0.9V,
fSYS_CLK(MAX) =
12MHz
19.8
MAX
UNITS
μA/MHz
Analog Devices | 12
MAX32672
High-Reliability, Tiny, Ultra-Low-Power
Arm Cortex-M4F Microcontroller
with 12-Bit, 1Msps ADC
Electrical Characteristics (continued)
(All specifications and characteristics apply across the entire operating conditions range unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
www.analog.com
TYP
21.4
OVR = [01],
internal regulator
set to 1.0V,
fSYS_CLK(MAX) =
50MHz
19.8
OVR = [00],
internal regulator
set to 0.9V,
fSYS_CLK(MAX) =
12MHz
19.7
Fixed, IPO
enabled, total
current into VDD
pin, VDD = 3.3V,
CPU in SLEEP
mode, ECC
disabled, inputs
tied to VSS or VDD,
outputs source/sink
0mA.
See Table 10 for
temperature
variance.
OVR = [10],
internal regulator
set to 1.1V
893
OVR = [01],
internal regulator
set to 1.0V
732
OVR = [00],
internal regulator
set to 0.9V
618
Fixed, IPO
enabled, total
current into VDD
pin, VDD = 1.8V,
CPU in SLEEP
mode, ECC
disabled, inputs
tied to VSS or VDD,
outputs source/sink
0mA.
See Table 10 for
temperature
variance.
OVR = [10],
internal regulator
set to 1.1V
865
OVR = [01],
internal regulator
set to 1.0V
708
OVR = [00],
internal regulator
set to 0.9V
594
Dynamic, IPO
enabled, total
current into VDD
pin, VDD = 1.8V,
CPU in SLEEP
mode, ECC
disabled, DMA
disabled, inputs
tied to VSS or VDD,
outputs source/sink
0mA
IDD_FSLPS
MIN
OVR = [10],
internal regulator
set to 1.1V,
fSYS_CLK(MAX) =
100MHz
MAX
UNITS
μA
Analog Devices | 13
MAX32672
High-Reliability, Tiny, Ultra-Low-Power
Arm Cortex-M4F Microcontroller
with 12-Bit, 1Msps ADC
Electrical Characteristics (continued)
(All specifications and characteristics apply across the entire operating conditions range unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER / SINGLE-SUPPLY OPERATION (VDD ONLY); fSYS_OSC = IBRO
Dynamic, IBRO
enabled, total
current into VDD
pin, VDD = 3.3V,
CPU in ACTIVE
mode, executing
CoreMark, ECC
disabled, inputs
tied to VSS or VDD,
outputs source/sink
0mA
VDD Current ACTIVE
Mode
IDD_DACTS
Dynamic, IBRO
enabled, total
current into VDD
pin, VDD = 1.8V,
CPU in ACTIVE
mode, executing
CoreMark, ECC
disabled, inputs
tied to VSS or VDD,
outputs source/sink
0mA
Dynamic, IBRO
enabled, total
current into VDD
pin, VDD = 3.3V,
CPU in ACTIVE
mode, executing
While(1), ECC
disabled, inputs
tied to VSS or VDD,
outputs source/sink
0mA
www.analog.com
OVR = [10],
internal regulator
set to 1.1V,
fSYS_CLK(MAX) =
7.3728MHz
70.8
OVR = [01],
internal regulator
set to 1.0V,
fSYS_CLK(MAX) =
7.3728MHz
68.1
OVR = [00],
internal regulator
set to 0.9V,
fSYS_CLK(MAX) =
7.3728MHz
64.2
OVR = [10],
internal regulator
set to 1.1V,
fSYS_CLK(MAX) =
7.3728MHz
70.1
OVR = [01],
internal regulator
set to 1.0V,
fSYS_CLK(MAX) =
7.3728MHz
67.4
OVR = [00],
internal regulator
set to 0.9V,
fSYS_CLK(MAX) =
7.3728MHz
63.4
OVR = [10],
internal regulator
set to 1.1V,
fSYS_CLK(MAX) =
7.3728MHz
56.5
OVR = [01],
internal regulator
set to 1.0V,
fSYS_CLK(MAX) =
7.3728MHz
53.5
OVR = [00],
internal regulator
set to 0.9V,
fSYS_CLK(MAX) =
7.3728MHz
50.1
μA/MHz
Analog Devices | 14
MAX32672
High-Reliability, Tiny, Ultra-Low-Power
Arm Cortex-M4F Microcontroller
with 12-Bit, 1Msps ADC
Electrical Characteristics (continued)
(All specifications and characteristics apply across the entire operating conditions range unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
www.analog.com
TYP
55.8
OVR = [01],
internal regulator
set to 1.0V,
fSYS_CLK(MAX) =
7.3728MHz
52.8
OVR = [00],
internal regulator
set to 0.9V,
fSYS_CLK(MAX) =
7.3728MHz
49.4
Fixed, IBRO
enabled, total
current into VDD
pin, VDD = 3.3V,
CPU in ACTIVE
mode 0MHz
execution, ECC
disabled, inputs
tied to VSS or VDD,
outputs source/sink
0mA.
See Table 11 for
temperature
variance.
OVR = [10],
internal regulator
set to 1.1V
446
OVR = [01],
internal regulator
set to 1.0V
385
OVR = [00],
internal regulator
set to 0.9V
341
Fixed, IBRO
enabled, total
current into VDD
pin, VDD = 1.8V,
CPU in ACTIVE
mode 0MHz
execution, ECC
disabled, inputs
tied to VSS or VDD,
outputs source/sink
0mA.
See Table 11 for
temperature
variance.
OVR = [10],
internal regulator
set to 1.1V
413
OVR = [01],
internal regulator
set to 1.0V
353
OVR = [00],
internal regulator
set to 0.9V
309
Dynamic, IBRO
enabled, total
current into VDD
pin, VDD = 1.8V,
CPU in ACTIVE
mode, executing
While(1), ECC
disabled, inputs
tied to VSS or VDD,
outputs source/sink
0mA
IDD_FACTS
MIN
OVR = [10],
internal regulator
set to 1.1V,
fSYS_CLK(MAX) =
7.3728MHz
MAX
UNITS
μA
Analog Devices | 15
MAX32672
High-Reliability, Tiny, Ultra-Low-Power
Arm Cortex-M4F Microcontroller
with 12-Bit, 1Msps ADC
Electrical Characteristics (continued)
(All specifications and characteristics apply across the entire operating conditions range unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
Dynamic, IBRO
enabled, total
current into VDD
pin, VDD = 3.3V,
CPU in SLEEP
mode, ECC
disabled, standard
DMA with two
channels active,
inputs tied to VSS
or VDD, outputs
source/sink 0mA
VDD Current SLEEP
Mode
IDD_DSLPS
Dynamic, IBRO
enabled, total
current into VDD
pin, VDD = 1.8V,
CPU in SLEEP
mode, ECC
disabled, standard
DMA with two
channels active,
inputs tied to VSS
or VDD, outputs
source/sink 0mA
Dynamic, IBRO
enabled, total
current into VDD
pin, VDD = 3.3V,
CPU in SLEEP
mode, ECC
disabled, DMA
disabled, inputs
tied to VSS or VDD,
outputs source/sink
0mA
www.analog.com
MIN
TYP
OVR = [10],
internal regulator
set to 1.1V,
fSYS_CLK(MAX) =
7.3728MHz
44
OVR = [01],
internal regulator
set to 1.0V,
fSYS_CLK(MAX) =
7.3728MHz
42.6
OVR = [00],
internal regulator
set to 0.9V,
fSYS_CLK(MAX) =
7.3728MHz
40.9
OVR = [10],
internal regulator
set to 1.1V,
fSYS_CLK(MAX) =
7.3728MHz
43.8
OVR = [01],
internal regulator
set to 1.0V,
fSYS_CLK(MAX) =
7.3728MHz
42.4
OVR = [00],
internal regulator
set to 0.9V,
fSYS_CLK(MAX) =
7.3728MHz
40.6
OVR = [10],
internal regulator
set to 1.1V,
fSYS_CLK(MAX) =
7.3728MHz
20.6
OVR = [01],
internal regulator
set to 1.0V,
fSYS_CLK(MAX) =
7.3728MHz
19.1
OVR = [00],
internal regulator
set to 0.9V,
fSYS_CLK(MAX) =
7.3728MHz
17.2
MAX
UNITS
μA/MHz
Analog Devices | 16
MAX32672
High-Reliability, Tiny, Ultra-Low-Power
Arm Cortex-M4F Microcontroller
with 12-Bit, 1Msps ADC
Electrical Characteristics (continued)
(All specifications and characteristics apply across the entire operating conditions range unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
TYP
20.6
OVR = [01],
internal regulator
set to 1.0V,
fSYS_CLK(MAX) =
7.3728MHz
19.1
OVR = [00],
internal regulator
set to 0.9V,
fSYS_CLK(MAX) =
7.3728MHz
17.1
Fixed, IBRO
enabled, total
current into VDD
pin, VDD = 3.3V,
CPU in SLEEP
mode, ECC
disabled, inputs
tied to VSS or VDD,
outputs source/sink
0mA.
See Table 12 for
temperature
variance.
OVR = [10],
internal regulator
set to 1.1V
446
OVR = [01],
internal regulator
set to 1.0V
385
OVR = [00],
internal regulator
set to 0.9V
341
Fixed, IBRO
enabled, total
current into VDD
pin, VDD = 1.8V,
CPU in SLEEP
mode, ECC
disabled, inputs
tied to VSS or VDD,
outputs source/sink
0mA.
See Table 12 for
temperature
variance.
OVR = [10],
internal regulator
set to 1.1V
413
OVR = [01],
internal regulator
set to 1.0V
353
OVR = [00],
internal regulator
set to 0.9V
309
VDD = 3.3V
5.3
VDD = 1.8V
5
Dynamic, IBRO
enabled, total
current into VDD
pin, VDD = 1.8V,
CPU in SLEEP
mode, ECC
disabled, DMA
disabled, inputs
tied to VSS or VDD,
outputs source/sink
0mA
IDD_FSLPS
MIN
OVR = [10],
internal regulator
set to 1.1V,
fSYS_CLK(MAX) =
7.3728MHz
MAX
UNITS
μA
POWER / SINGLE-SUPPLY OPERATION (VDD ONLY)
VDD Fixed Current,
DEEPSLEEP Mode
www.analog.com
IDD_FDSLS
Standby state with
full data retention
and 200KB SRAM
retained.
See Table 13 for
temperature
variance.
μA
Analog Devices | 17
MAX32672
High-Reliability, Tiny, Ultra-Low-Power
Arm Cortex-M4F Microcontroller
with 12-Bit, 1Msps ADC
Electrical Characteristics (continued)
(All specifications and characteristics apply across the entire operating conditions range unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
VDD = 3.3V, RTC
disabled.
See Table 14 for
temperature
variance.
VDD Fixed Current,
BACKUP Mode
IDD_FBKUS
VDD = 1.8V, RTC
disabled.
See Table 14 for
temperature
variance.
VDD Fixed Current,
STORAGE Mode
IDD_FSTOS
See Table 15 for
temperature
variance.
MIN
TYP
0KB SRAM
retained, retention
regulator disabled
0.35
20KB SRAM
retained
1.14
40KB SRAM
retained
1.56
120KB SRAM
retained
2.69
200KB SRAM
retained
3.78
0KB SRAM
retained, retention
regulator disabled
0.08
20KB SRAM
retained
0.86
40KB SRAM
retained
1.3
120KB SRAM
retained
2.4
200KB SRAM
retained
3.5
VDD = 3.3V
0.34
VDD = 1.8V
0.083
MAX
UNITS
μA
μA
POWER / SINGLE-SUPPLY OPERATION (VDD ONLY) RESUME TIMES
SLEEP Mode Resume
Time
DEEPSLEEP Mode
Resume Time
BACKUP Mode Resume
Time
STORAGE Mode
Resume Time
www.analog.com
tSLP_ONS
fSYS_OSC = IPO
0.1
fSYS_OSC = IBRO
1.1
fSYS_OSC = IPO
tDSL_ONS
fSYS_OSC = IBRO
tBKU_ONS
tSTO_ONS
Time from power
mode exit to
execution of
application code
Time from power
mode exit to
execution of
application code
fast_wk_en = 1
74
fast_wk_en = 0
210
fast_wk_en = 1
182
fast_wk_en = 0
319
Parts without
SCPBL
1.08
Parts with SCPBL
performing
signature
verification over
512KB of flash
264
Parts without
SCPBL
1.08
Parts with SCPBL
performing
signature
verification over
512KB of flash
264
μs
μs
μs
ms
ms
Analog Devices | 18
MAX32672
High-Reliability, Tiny, Ultra-Low-Power
Arm Cortex-M4F Microcontroller
with 12-Bit, 1Msps ADC
Electrical Characteristics (continued)
(All specifications and characteristics apply across the entire operating conditions range unless otherwise noted.)
PARAMETER
Cold Boot Startup Time
SYMBOL
tCB_STS
CONDITIONS
Time from VDD =
VDD(MIN) to
execution of
application code
MIN
TYP
Parts without
SCPBL
1.08
Parts with SCPBL
performing
signature
verification over
512KB of flash
264
MAX
UNITS
ms
POWER / DUAL-SUPPLY OPERATION (VDD AND VCORE); fSYS_OSC = IPO
Dynamic, IPO
enabled, total
current into VCORE
pin, CPU in
ACTIVE mode,
executing
CoreMark, ECC
disabled, inputs
tied to VSS or VDD,
outputs source/sink
0mA
ICORE_DACTD
Dynamic, IPO
enabled, total
current into VCORE
pin, CPU in
ACTIVE mode,
executing While(1),
ECC disabled,
inputs tied to VSS
or VDD, outputs
source/sink 0mA
VCORE Current,
ACTIVE Mode
ICORE_FACTD
www.analog.com
Fixed, IPO
enabled, total
current into VCORE
pin, CPU in
ACTIVE mode
0MHz execution,
ECC disabled,
inputs tied to VSS
or VDD, outputs
source/sink 0mA.
See Table 16 for
temperature
variance.
OVR = [10], VCORE
= 1.1V,
fSYS_CLK(MAX) =
100MHz
69
OVR = [01], VCORE
= 1.0V,
fSYS_CLK(MAX) =
50MHz
67
OVR = [00], VCORE
= 0.9V,
fSYS_CLK(MAX) =
12MHz
59.8
OVR = [10], VCORE
= 1.1V,
fSYS_CLK(MAX) =
100MHz
55.5
OVR = [01], VCORE
= 1.0V,
fSYS_CLK(MAX) =
50MHz
53
OVR = [00], VCORE
= 0.9V,
fSYS_CLK(MAX) =
12MHz
47.4
OVR = [10], VCORE
= 1.1V
417
OVR = [01], VCORE
= 1.0V
261
μA/MHz
μA
OVR = [00], VCORE
= 0.9V
137
Analog Devices | 19
MAX32672
High-Reliability, Tiny, Ultra-Low-Power
Arm Cortex-M4F Microcontroller
with 12-Bit, 1Msps ADC
Electrical Characteristics (continued)
(All specifications and characteristics apply across the entire operating conditions range unless otherwise noted.)
PARAMETER
VDD Current, ACTIVE
Mode
www.analog.com
SYMBOL
IDD_DACTD
CONDITIONS
MIN
TYP
Dynamic, IPO
enabled, total
current into VDD
pin, VDD = 3.3V,
CPU in ACTIVE
mode, executing
CoreMark, ECC
disabled, inputs
tied to VSS or VDD,
outputs source/sink
0mA
OVR = [10],
fSYS_CLK(MAX) =
100MHz
0.67
OVR = [01],
fSYS_CLK(MAX) =
50MHz
0.67
OVR = [00],
fSYS_CLK(MAX) =
12MHz
0.67
Dynamic, IPO
enabled, total
current into VDD
pin, VDD = 1.8V,
CPU in ACTIVE
mode, executing
CoreMark, ECC
disabled, inputs
tied to VSS or VDD,
outputs source/sink
0mA
OVR = [10],
fSYS_CLK(MAX) =
100MHz
0.30
OVR = [01],
fSYS_CLK(MAX) =
50MHz
0.30
OVR = [00],
fSYS_CLK(MAX) =
12MHz
0.30
Dynamic, IPO
enabled, total
current into VDD
pin, VDD = 3.3V,
CPU in ACTIVE
mode, executing
While(1), ECC
disabled, inputs
tied to VSS or VDD,
outputs source/sink
0mA
OVR = [10],
fSYS_CLK(MAX) =
100MHz
0.67
OVR = [01],
fSYS_CLK(MAX) =
50MHz
0.67
OVR = [00],
fSYS_CLK(MAX) =
12MHz
0.67
Dynamic, IPO
enabled, total
current into VDD
pin, VDD = 1.8V,
CPU in ACTIVE
mode, executing
While(1), ECC
disabled, inputs
tied to VSS or VDD,
outputs source/sink
0mA
OVR = [10],
fSYS_CLK(MAX) =
100MHz
0.30
OVR = [01],
fSYS_CLK(MAX) =
50MHz
0.30
OVR = [00],
fSYS_CLK(MAX) =
12MHz
0.30
MAX
UNITS
μA/MHz
Analog Devices | 20
MAX32672
High-Reliability, Tiny, Ultra-Low-Power
Arm Cortex-M4F Microcontroller
with 12-Bit, 1Msps ADC
Electrical Characteristics (continued)
(All specifications and characteristics apply across the entire operating conditions range unless otherwise noted.)
PARAMETER
SYMBOL
IDD_FACTD
www.analog.com
CONDITIONS
MIN
TYP
Fixed, IPO
enabled, total
current into VDD
pin, VDD = 3.3V,
CPU in ACTIVE
mode 0MHz
execution, ECC
disabled, inputs
tied to VSS or VDD,
outputs source/sink
0mA.
See Table 17 for
temperature
variance.
OVR = [10], VCORE
= 1.1V
430
OVR = [01], VCORE
= 1.0V
430
OVR = [00], VCORE
= 0.9V
430
Fixed, IPO
enabled, total
current into VDD
pin, VDD = 1.8V,
CPU in ACTIVE
mode 0MHz
execution, ECC
disabled, inputs
tied to VSS or VDD,
outputs source/sink
0mA.
See Table 17 for
temperature
variance.
OVR = [10], VCORE
= 1.1V
410
OVR = [01], VCORE
= 1.0V
410
OVR = [00], VCORE
= 0.9V
410
MAX
UNITS
μA
Analog Devices | 21
MAX32672
High-Reliability, Tiny, Ultra-Low-Power
Arm Cortex-M4F Microcontroller
with 12-Bit, 1Msps ADC
Electrical Characteristics (continued)
(All specifications and characteristics apply across the entire operating conditions range unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
Dynamic, IPO
enabled, total
current into VCORE
pin, CPU in SLEEP
mode, ECC
disabled, standard
DMA with two
channels active,
inputs tied to VSS
or VDD, outputs
source/sink 0mA
ICORE_DSLPD
Dynamic, IPO
enabled, total
current into VCORE
pin, CPU in SLEEP
mode, ECC
disabled, DMA
disabled, inputs
tied to VSS or VDD,
outputs source/sink
0mA
VCORE Current, SLEEP
Mode
ICORE_FSLPD
www.analog.com
Fixed, IPO
enabled, total
current into VCORE
pin, CPU in SLEEP
mode, ECC
disabled, inputs
tied to VSS or VDD,
outputs source/sink
0mA.
See Table 18 for
temperature
variance.
MIN
TYP
OVR = [10], VCORE
= 1.1V,
fSYS_CLK(MAX) =
100MHz
44.5
OVR = [01], VCORE
= 1.0V,
fSYS_CLK(MAX) =
50MHz
42.9
OVR = [00], VCORE
= 0.9V,
fSYS_CLK(MAX) =
12MHz
39.2
OVR = [10], VCORE
= 1.1V,
fSYS_CLK(MAX) =
100MHz
21.1
OVR = [01], VCORE
= 1.0V,
fSYS_CLK(MAX) =
50MHz
19.3
OVR = [00], VCORE
= 0.9V,
fSYS_CLK(MAX) =
12MHz
16.5
OVR [10], VCORE =
1.1V
417
OVR [01], VCORE =
1.0V
261
MAX
UNITS
μA/MHz
μA
OVR [00], VCORE =
0.9V
137
Analog Devices | 22
MAX32672
High-Reliability, Tiny, Ultra-Low-Power
Arm Cortex-M4F Microcontroller
with 12-Bit, 1Msps ADC
Electrical Characteristics (continued)
(All specifications and characteristics apply across the entire operating conditions range unless otherwise noted.)
PARAMETER
SYMBOL
IDD_DSLPD
VDD Current, SLEEP
Mode
IDD_FSLPD
www.analog.com
CONDITIONS
MIN
TYP
Dynamic, IPO
enabled, total
current into VDD
pin, VDD = 3.3V,
CPU in SLEEP
mode, ECC
disabled, standard
DMA with two
channels active,
inputs tied to VSS
or VDD, outputs
source/sink 0mA
OVR = [10], VCORE
= 1.1V,
fSYS_CLK(MAX) =
100MHz
0.002
OVR = [01], VCORE
= 1.0V,
fSYS_CLK(MAX) =
50MHz
0.002
OVR = [00], VCORE
= 0.9V,
fSYS_CLK(MAX) =
12MHz
0.002
Dynamic, IPO
enabled, total
current into VDD
pin, VDD = 1.8V,
CPU in SLEEP
mode, ECC
disabled, standard
DMA with two
channels active,
inputs tied to VSS
or VDD, outputs
source/sink 0mA
OVR = [10], VCORE
= 1.1V,
fSYS_CLK(MAX) =
100MHz
0.001
OVR = [01], VCORE
= 1.0V,
fSYS_CLK(MAX) =
50MHz
0.001
OVR = [00], VCORE
= 0.9V,
fSYS_CLK(MAX) =
12MHz
0.001
Fixed, IPO
enabled, total
current into VDD
pin, VDD = 3.3V,
CPU in SLEEP
mode, ECC
disabled, inputs
tied to VSS or VDD,
outputs source/sink
0mA.
See Table 19 for
temperature
variance.
OVR = [10], VCORE
= 1.1V
430
OVR = [01], VCORE
= 1.0V
430
OVR = [00], VCORE
= 0.9V
430
Fixed, IPO
enabled, total
current into VDD
pin, VDD = 1.8V,
CPU in SLEEP
mode, ECC
disabled, inputs
tied to VSS or VDD,
outputs source/sink
0mA.
See Table 19 for
temperature
variance.
OVR = [10], VCORE
= 1.1V
410
OVR = [01], VCORE
= 1.0V
410
OVR = [00], VCORE
= 0.9V
410
MAX
UNITS
μA/MHz
μA
Analog Devices | 23
MAX32672
High-Reliability, Tiny, Ultra-Low-Power
Arm Cortex-M4F Microcontroller
with 12-Bit, 1Msps ADC
Electrical Characteristics (continued)
(All specifications and characteristics apply across the entire operating conditions range unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER / DUAL-SUPPLY OPERATION (VDD AND VCORE); fSYS_OSC = IBRO
Dynamic, IBRO
enabled, total
current into VCORE
pin, CPU in
ACTIVE mode,
executing
CoreMark, ECC
disabled, inputs
tied to VSS or VDD,
outputs source/sink
0mA
ICORE_DACTD
Dynamic, IBRO
enabled, total
current into VCORE
pin, CPU in
ACTIVE mode,
executing While(1),
ECC disabled,
inputs tied to VSS
or VDD, outputs
source/sink 0mA
VCORE Current,
ACTIVE Mode
ICORE_FACTD
www.analog.com
Fixed, IBRO
enabled, total
current into VCORE
pin, CPU in
ACTIVE mode
0MHz execution,
ECC disabled,
inputs tied to VSS
or VDD, outputs
source/sink 0mA.
See Table 20 for
temperature
variance.
OVR = [10], VCORE
= 1.1V,
fSYS_CLK(MAX) =
7.3728MHz
70.4
OVR = [01], VCORE
= 1.0V,
fSYS_CLK(MAX) =
7.3728MHz
67
OVR = [00], VCORE
= 0.9V,
fSYS_CLK(MAX) =
7.3728MHz
60
OVR = [10], VCORE
= 1.1V,
fSYS_CLK(MAX) =
7.3728MHz
55.9
OVR = [01], VCORE
= 1.0V,
fSYS_CLK(MAX) =
7.3728MHz
52.9
OVR = [00], VCORE
= 0.9V,
fSYS_CLK(MAX) =
7.3728MHz
46.9
OVR = [10], VCORE
= 1.1V
238
OVR = [01], VCORE
= 1.0V
179
μA/MHz
μA
OVR = [00], VCORE
= 0.9V
122
Analog Devices | 24
MAX32672
High-Reliability, Tiny, Ultra-Low-Power
Arm Cortex-M4F Microcontroller
with 12-Bit, 1Msps ADC
Electrical Characteristics (continued)
(All specifications and characteristics apply across the entire operating conditions range unless otherwise noted.)
PARAMETER
VDD Current, ACTIVE
Mode
www.analog.com
SYMBOL
IDD_DACTD
CONDITIONS
MIN
TYP
Dynamic, IBRO
enabled, total
current into VDD
pin, VDD = 3.3V,
CPU in ACTIVE
mode, executing
CoreMark, ECC
disabled, inputs
tied to VSS or VDD,
outputs source/sink
0mA
OVR = [10],
fSYS_CLK(MAX) =
7.3728MHz
0.05
OVR = [01],
fSYS_CLK(MAX) =
7.3728MHz
0.01
OVR = [00],
fSYS_CLK(MAX) =
7.3728MHz
0.42
Dynamic, IBRO
enabled, total
current into VDD
pin, VDD = 1.8V,
CPU in ACTIVE
mode, executing
CoreMark, ECC
disabled, inputs
tied to VSS or VDD,
outputs source/sink
0mA
OVR = [10],
fSYS_CLK(MAX) =
7.3728MHz
0.022
OVR = [01],
fSYS_CLK(MAX) =
7.3728MHz
0.045
OVR = [00],
fSYS_CLK(MAX) =
7.3728MHz
0.18
Dynamic, IBRO
enabled, total
current into VDD
pin, VDD = 3.3V,
CPU in ACTIVE
mode, executing
While(1), ECC
disabled, inputs
tied to VSS or VDD,
outputs source/sink
0mA
OVR = [10],
fSYS_CLK(MAX) =
7.3728MHz
0.05
OVR = [01],
fSYS_CLK(MAX) =
7.3728MHz
0.1
OVR = [00],
fSYS_CLK(MAX) =
7.3728MHz
0.42
Dynamic, IBRO
enabled, total
current into VDD
pin, VDD = 1.8V,
CPU in ACTIVE
mode, executing
While(1), ECC
disabled, inputs
tied to VSS or VDD,
outputs source/sink
0mA
OVR = [10],
fSYS_CLK(MAX) =
7.3728MHz
0.02
OVR = [01],
fSYS_CLK(MAX) =
7.3728MHz
0.04
OVR = [00],
fSYS_CLK(MAX) =
7.3728MHz
0.18
MAX
UNITS
μA/MHz
Analog Devices | 25
MAX32672
High-Reliability, Tiny, Ultra-Low-Power
Arm Cortex-M4F Microcontroller
with 12-Bit, 1Msps ADC
Electrical Characteristics (continued)
(All specifications and characteristics apply across the entire operating conditions range unless otherwise noted.)
PARAMETER
SYMBOL
IDD_FACTD
www.analog.com
CONDITIONS
MIN
TYP
Fixed, IBRO
enabled, total
current into VDD
pin, VDD = 3.3V,
CPU in ACTIVE
mode 0MHz
execution, ECC
disabled, inputs
tied to VSS or VDD,
outputs source/sink
0mA.
See Table 21 for
temperature
variance.
OVR = [10], VCORE
= 1.1V
165
OVR = [01], VCORE
= 1.0V
165
OVR = [00], VCORE
= 0.9V
165
Fixed, IBRO
enabled, total
current into VDD
pin, VDD = 1.8V,
CPU in ACTIVE
mode 0MHz
execution, ECC
disabled, inputs
tied to VSS or VDD,
outputs source/sink
0mA.
See Table 21 for
temperature
variance.
OVR = [10], VCORE
= 1.1V
136
OVR = [01], VCORE
= 1.0V
136
OVR = [00], VCORE
= 0.9V
136
MAX
UNITS
μA
Analog Devices | 26
MAX32672
High-Reliability, Tiny, Ultra-Low-Power
Arm Cortex-M4F Microcontroller
with 12-Bit, 1Msps ADC
Electrical Characteristics (continued)
(All specifications and characteristics apply across the entire operating conditions range unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
Dynamic, IBRO
enabled, total
current into VCORE
pin, CPU in SLEEP
mode, ECC
disabled, standard
DMA with two
channels active,
inputs tied to VSS
or VDD, outputs
source/sink 0mA
ICORE_DSLPD
Dynamic, IBRO
enabled, total
current into VCORE
pin, CPU in SLEEP
mode, ECC
disabled, DMA
disabled, inputs
tied to VSS or VDD,
outputs source/sink
0mA
VCORE Current, SLEEP
Mode
ICORE_FSLPD
www.analog.com
Fixed, IBRO
enabled, total
current into VCORE
pin, CPU in SLEEP
mode, ECC
disabled, inputs
tied to VSS or VDD,
outputs source/sink
0mA.
See Table 22 for
temperature
variance.
MIN
TYP
OVR = [10], VCORE
= 1.1V,
fSYS_CLK(MAX) =
7.3728MHz
0.04
OVR = [01], VCORE
= 1.0V,
fSYS_CLK(MAX) =
7.3728MHz
0.04
OVR = [00], VCORE
= 0.9V,
fSYS_CLK(MAX) =
7.3728MHz
0.04
OVR = [10], VCORE
= 1.1V,
fSYS_CLK(MAX) =
7.3728MHz
0.02
OVR = [01], VCORE
= 1.0V,
fSYS_CLK(MAX) =
7.3728MHz
0.02
OVR = [00], VCORE
= 0.9V,
fSYS_CLK(MAX) =
7.3728MHz
0.02
OVR [10], VCORE =
1.1V
238
OVR [01], VCORE =
1.0V
179
MAX
UNITS
μA/MHz
μA
OVR [00], VCORE =
0.9V
122
Analog Devices | 27
MAX32672
High-Reliability, Tiny, Ultra-Low-Power
Arm Cortex-M4F Microcontroller
with 12-Bit, 1Msps ADC
Electrical Characteristics (continued)
(All specifications and characteristics apply across the entire operating conditions range unless otherwise noted.)
PARAMETER
SYMBOL
IDD_DSLPD
VDD Current, SLEEP
Mode
IDD_FSLPD
www.analog.com
CONDITIONS
MIN
TYP
Dynamic, IBRO
enabled, total
current into VDD
pin, VDD = 3.3V,
CPU in SLEEP
mode, ECC
disabled, standard
DMA with two
channels active,
inputs tied to VSS
or VDD, outputs
source/sink 0mA
OVR = [10], VCORE
= 1.1V,
fSYS_CLK(MAX) =
7.3728MHz
0.001
OVR = [01], VCORE
= 1.0V,
fSYS_CLK(MAX) =
7.3728MHz
0.001
OVR = [00], VCORE
= 0.9V,
fSYS_CLK(MAX) =
7.3728MHz
0.001
Dynamic, IBRO
enabled, total
current into VDD
pin, VDD = 1.8V,
CPU in SLEEP
mode, ECC
disabled, standard
DMA with two
channels active,
inputs tied to VSS
or VDD, outputs
source/sink 0mA
OVR = [10], VCORE
= 1.1V,
fSYS_CLK(MAX) =
7.3728MHz
0.001
OVR = [01], VCORE
= 1.0V,
fSYS_CLK(MAX) =
7.3728MHz
0.001
OVR = [00], VCORE
= 0.9V,
fSYS_CLK(MAX) =
7.3728MHz
0.001
Fixed, IBRO
enabled, total
current into VDD
pin, VDD = 3.3V,
CPU in SLEEP
mode, ECC
disabled, inputs
tied to VSS or VDD,
outputs source/sink
0mA.
See Table 23 for
temperature
variance.
OVR = [10], VCORE
= 1.1V
165
OVR = [01], VCORE
= 1.0V
165
OVR = [00], VCORE
= 0.9V
165
Fixed, IBRO
enabled, total
current into VDD
pin, VDD = 1.8V,
CPU in SLEEP
mode, ECC
disabled, inputs
tied to VSS or VDD,
outputs source/sink
0mA.
See Table 23 for
temperature
variance.
OVR = [10], VCORE
= 1.1V
136
OVR = [01], VCORE
= 1.0V
136
OVR = [00], VCORE
= 0.9V
136
MAX
UNITS
μA/MHz
μA
Analog Devices | 28
MAX32672
High-Reliability, Tiny, Ultra-Low-Power
Arm Cortex-M4F Microcontroller
with 12-Bit, 1Msps ADC
Electrical Characteristics (continued)
(All specifications and characteristics apply across the entire operating conditions range unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER / DUAL-SUPPLY OPERATION (VDD AND VCORE)
VCORE Fixed Current,
DEEPSLEEP Mode
VDD Fixed Current,
DEEPSLEEP Mode
www.analog.com
ICORE_FDSLP
D
IDD_FDSLPD
See Table 24 for
temperature
variance.
See Table 25 for
temperature
variance.
VDD = 3.3V,
VCORE = 1.1V
12.2
VDD = 3.3V,
VCORE = 0.855V
4.6
VDD = 1.8V,
VCORE = 1.1V
12.2
VDD = 1.8V,
VCORE = 0.855V
4.6
VDD = 3.3V,
VCORE = 1.1V
0.37
VDD = 3.3V,
VCORE = 0.855V
0.37
VDD = 1.8V,
VCORE = 1.1V
0.15
VDD = 1.8V,
VCORE = 0.855V
0.15
μA
μA
Analog Devices | 29
MAX32672
High-Reliability, Tiny, Ultra-Low-Power
Arm Cortex-M4F Microcontroller
with 12-Bit, 1Msps ADC
Electrical Characteristics (continued)
(All specifications and characteristics apply across the entire operating conditions range unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
0KB SRAM
retained, RTC
disabled, retention
regulator disabled.
See Table 26 for
temperature
variance.
20KB SRAM
retained with RTC
disabled.
See Table 26 for
temperature
variance.
VCORE Fixed Current,
BACKUP Mode
ICORE_FBKUD
40KB SRAM
retained with RTC
disabled.
See Table 26 for
temperature
variance.
120KB SRAM
retained with RTC
disabled.
See Table 26 for
temperature
variance.
200KB SRAM
retained with RTC
disabled.
See Table 26 for
temperature
variance.
www.analog.com
MIN
TYP
VDD = 3.3V,
VCORE = 1.1V
0.28
VDD = 3.3V,
VCORE = 0.855V
0.14
VDD = 1.8V,
VCORE = 1.1V
0.28
VDD = 1.8V,
VCORE = 0.855V
0.14
VDD = 3.3V,
VCORE = 1.1V
1.31
VDD = 3.3V,
VCORE = 0.855V
0.54
VDD = 1.8V,
VCORE = 1.1V
1.31
VDD = 1.8V,
VCORE = 0.855V
0.54
VDD = 3.3V,
VCORE = 1.1V
2.35
VDD = 3.3V,
VCORE = 0.855V
0.94
VDD = 1.8V,
VCORE = 1.1V
2.35
VDD = 1.8V,
VCORE = 0.855V
0.94
VDD = 3.3V,
VCORE = 1.1V
5.46
VDD = 3.3V,
VCORE = 0.855V
2.02
VDD = 1.8V,
VCORE = 1.1V
5.46
VDD = 1.8V,
VCORE = 0.855V
2.02
VDD = 3.3V,
VCORE = 1.1V
8.55
VDD = 3.3V,
VCORE = 0.855V
3.09
VDD = 1.8V,
VCORE = 1.1V
8.55
VDD = 1.8V,
VCORE = 0.855V
3.09
MAX
UNITS
μA
Analog Devices | 30
MAX32672
High-Reliability, Tiny, Ultra-Low-Power
Arm Cortex-M4F Microcontroller
with 12-Bit, 1Msps ADC
Electrical Characteristics (continued)
(All specifications and characteristics apply across the entire operating conditions range unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
0KB SRAM
retained with RTC
disabled, retention
regulator disabled.
See Table 27 for
temperature
variance.
20KB SRAM
retained with RTC
disabled.
See Table 27 for
temperature
variance.
VDD Fixed Current,
BACKUP Mode
IDD_FBKUD
40KB SRAM
retained with RTC
disabled.
See Table 27 for
temperature
variance.
120KB SRAM
retained with RTC
disabled.
See Table 27 for
temperature
variance.
200KB SRAM
retained with RTC
disabled.
See Table 27 for
temperature
variance.
www.analog.com
MIN
TYP
VDD = 3.3V,
VCORE = 1.1V
0.37
VDD = 3.3V,
VCORE = 0.855V
0.37
VDD = 1.8V,
VCORE = 1.1V
0.16
VDD = 1.8V,
VCORE = 0.855V
0.16
VDD = 3.3V,
VCORE = 1.1V
0.37
VDD = 3.3V,
VCORE = 0.855V
0.37
VDD = 1.8V,
VCORE = 1.1V
0.16
VDD = 1.8V,
VCORE = 0.855V
0.16
VDD = 3.3V,
VCORE = 1.1V
0.37
VDD = 3.3V,
VCORE = 0.855V
0.37
VDD = 1.8V,
VCORE = 1.1V
0.16
VDD = 1.8V,
VCORE = 0.855V
0.16
VDD = 3.3V,
VCORE = 1.1V
0.37
VDD = 3.3V,
VCORE = 0.855V
0.37
VDD = 1.8V,
VCORE = 1.1V
0.16
VDD = 1.8V,
VCORE = 0.855V
0.16
VDD = 3.3V,
VCORE = 1.1V
0.37
VDD = 3.3V,
VCORE = 0.855V
0.37
VDD = 1.8V,
VCORE = 1.1V
0.16
VDD = 1.8V,
VCORE = 0.855V
0.16
MAX
UNITS
μA
Analog Devices | 31
MAX32672
High-Reliability, Tiny, Ultra-Low-Power
Arm Cortex-M4F Microcontroller
with 12-Bit, 1Msps ADC
Electrical Characteristics (continued)
(All specifications and characteristics apply across the entire operating conditions range unless otherwise noted.)
PARAMETER
VCORE Fixed Current,
STORAGE Mode
VDD Fixed Current,
STORAGE Mode
SYMBOL
ICORE_FSTOD
IDD_FSTOD
CONDITIONS
See Table 28 for
temperature
variance.
See Table 29 for
temperature
variance.
MIN
TYP
VDD = 3.3V,
VCORE = 1.1V
0.29
VDD = 3.3V,
VCORE = 0.855V
0.15
VDD = 1.8V,
VCORE = 1.1V
0.29
VDD = 1.8V,
VCORE = 0.855V
0.15
VDD = 3.3V;
VCORE = 1.1V
0.4
VDD = 3.3V;
VCORE = 0.855V
0.4
VDD = 1.8V;
VCORE = 1.1V
0.16
VDD = 1.8V;
VCORE = 0.855V
0.16
MAX
UNITS
μA
μA
POWER / DUAL-SUPPLY OPERATION (VDD AND VCORE) RESUME TIMES
SLEEP Mode Resume
Time
DEEPSLEEP Mode
Resume Time
BACKUP Mode Resume
Time
STORAGE Mode
Resume Time
Cold Boot Startup Time
tSLP_OND
tDSL_OND
tBKU_OND
tSTO_OND
tCB_STD
fSYS_OSC = IPO; OVR = [11]
0.1
fSYS_OSC = IBRO; OVR = [11]
1.1
fSYS_OSC = IPO;
OVR = [11]
fast_wk_en = 1
37
fast_wk_en = 0
184
fSYS_OSC = IBRO;
OVR = [11]
fast_wk_en = 1
146
fast_wk_en = 0
295
Parts without
SCPBL
1.05
Parts with SCPBL
performing
signature
verification over
512KB of flash
264
Parts without
SCPBL
1.05
Parts with SCPBL
performing
signature
verification over
512KB of flash
264
Parts without
SCPBL
1.05
Time from power
mode exit to
execution of
application code;
OVR = [11]
Time from power
mode exit to
execution of
application code
Time from VDD =
VDD(MIN) and
VCORE =
VCORE(MIN) to
execution of
application code
μs
μs
ms
ms
ms
CLOCKS
System Clock
Frequency
www.analog.com
fSYS_CLK
100
MHz
Analog Devices | 32
MAX32672
High-Reliability, Tiny, Ultra-Low-Power
Arm Cortex-M4F Microcontroller
with 12-Bit, 1Msps ADC
Electrical Characteristics (continued)
(All specifications and characteristics apply across the entire operating conditions range unless otherwise noted.)
PARAMETER
System Clock Period
Internal Primary
Oscillator (IPO)
SYMBOL
fIPO
fERFO
Internal Baud Rate
Oscillator (IBRO)
fIBRO
Internal Nanoring
Oscillator (INRO)
fINRO
RTC Operating Current
MIN
fERTCO
IRTC
RTC Power-Up Time
tRTC_ ON
External Clock Input
Frequency
fEXT_CLK
TYP
MAX
1/fSYS_C
tSYS_CLK
External RF Oscillator
(ERFO)
External RTC Oscillator
(ERTCO)
CONDITIONS
μs
LK
Default OVR = [10]
100
Required crystal characteristics: CL =
12pF, ESR ≤ 50Ω, C0 ≤ 7pF, temperature
stability ±20ppm, initial tolerance ±20ppm
16
Measured at VDD = 1.8V
32.768kHz watch crystal, CL = 6pF, ESR
< 90kΩ, C0 < 2pF
All power modes, RTC enabled
UNITS
MHz
32
MHz
7.3728
MHz
70
kHz
32.768
kHz
0.35
μA
250
ms
EXT_CLK1 selected
50
EXT_CLK2 selected
1
MHz
12-BIT SAR ADC
Resolution
Effective Number of Bits
ENOB
ADC_CLKCTRL.clkdiv = 0bX00. AINx
input pk--pk = VREF – 10mV
External Reference
Voltage
VREF
VREF ≤ VDDA
Internal Reference
Voltage
12
bits
10
bits
2.048
VDDA
VINT_REF
MCR_ADC_CFG0.ext_ref = 0,
MCR_ADC_CFG0.ref_sel = 0
1.25
VINT_REF
MCR_ADC_CFG0.ext_ref = 0,
MCR_ADC_CFG0.ref_sel = 1
2.048
V
V
ADC Clock Rate
fACLK
1
MHz
ADC Clock Period
tACLK
1/fACLK
μs
Input Voltage Range
VAIN
Input Impedance
RAIN
Analog Input
Capacitance
CAIN
AIN[11:0],
ADC_DATA.chan =
[11:0]
ADC_CLKCTRL.clk
div = 0bX00
VSSA +
0.05
VREF
ADC_CLKCTRL.clk
div = 0bX01
VSSA +
0.05
min(2 x
VREF,VD
DA)
ADC_CLKCTRL.clk
div = 0bX10
VSSA +
0.05
min(2 x
VREF,VD
DA)
ADC_CLKCTRL.clkdiv = 0bX01
5
ADC_CLKCTRL.clkdiv = 0bX10
50
Fixed capacitance to VSSA
Dynamically switched capacitance
V
kΩ
2
pF
1.2
pF
Integral Nonlinearity
INL
±1.5
LSb
Differential Nonlinearity
DNL
±0.75
LSb
www.analog.com
Analog Devices | 33
MAX32672
High-Reliability, Tiny, Ultra-Low-Power
Arm Cortex-M4F Microcontroller
with 12-Bit, 1Msps ADC
Electrical Characteristics (continued)
(All specifications and characteristics apply across the entire operating conditions range unless otherwise noted.)
PARAMETER
Offset Error
SYMBOL
VOS
CONDITIONS
IADC
Chopping enabled
±0.2
ADC active,
reference buffer
enabled,
ADC_CLKCTRL.clk
div = 0bX01
ADC active,
reference buffer
enabled,
ADC_CLKCTRL.clk
div = 0bX10
ADC Sample Rate
ADC Setup Time
fADC
tADC_SU
TYP
±9
ADC active,
reference buffer
enabled,
ADC_CLKCTRL.clk
div = 0bX00
ADC Active Current
MIN
Chopping disabled
MCR_ADC_CFG0.
ext_ref = 0,
MCR_ADC_CFG0.
ref_sel = 0, VDDA =
1.8V
500
MCR_ADC_CFG0.
ext_ref = 0,
MCR_ADC_CFG0.
ref_sel = 1, VDDA =
3.3V
788
MCR_ADC_CFG0.
ext_ref = 0,
MCR_ADC_CFG0.
ref_sel = 0, VDDA =
1.8V
440
MCR_ADC_CFG0.
ext_ref = 0,
MCR_ADC_CFG0.
ref_sel = 1, VDDA =
3.3V
670
MCR_ADC_CFG0.
ext_ref = 0,
MCR_ADC_CFG0.
ref_sel = 0, VDDA =
1.8V
366
MCR_ADC_CFG0.
ext_ref = 0,
MCR_ADC_CFG0.
ref_sel = 1, VDDA =
3.3V
512
MAX
UNITS
LSb
µA
ADC_CLKCTRL.clkdiv = 0bX00
1
ADC_CLKCTRL.clkdiv = 0bX01
0.625
ADC_CLKCTRL.clkdiv = 0bX10
0.125
Any power-up of ADC clock or ADC bias
to CpuAdcStart
500
Msps
µs
ADC Input Leakage
IADC_LEAK
ADC inactive or channel not selected
0.4
nA
Bandgap Temperature
Coefficient
VTEMPCO
Box method
45
ppm
Includes linearity and calibration error
±3
°C
Includes integration and ADC conversion
time
300
μs
0.5
°C
12-BIT SAR ADC / TEMPERATURE SENSOR
Accuracy
TACC
Conversion Time
tT_CONV
Integration Noise
1-Sigma
TINTN
www.analog.com
Reduce by
1
√N integrations
Analog Devices | 34
MAX32672
High-Reliability, Tiny, Ultra-Low-Power
Arm Cortex-M4F Microcontroller
with 12-Bit, 1Msps ADC
Electrical Characteristics (continued)
(All specifications and characteristics apply across the entire operating conditions range unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
COMPARATORS
Input Offset Voltage
Input Hysteresis
Input Voltage Range
VOFFSET
VHYST
±3
AINCOMPHYST[1:0] = 00
22
AINCOMPHYST[1:0] = 01
50
AINCOMPHYST[1:0] = 10
2
AINCOMPHYST[1:0] = 11
7
VIN_CMP
Common-mode range
Input Low Voltage for All
GPIO, RSTN
VIL_GPIO
Pin configured as GPIO
Input High Voltage for
All GPIO, RSTN
VIH_GPIO
Pin configured as GPIO
0.6
mV
mV
1.35
V
0.3 ×
VDD
V
GENERAL-PURPOSE I/O
Output Low Voltage for
All GPIO Except P0.6,
P0.7, P0.12, P0.13,
P0.18, and P0.19
Output Low Voltage for
GPIO P0.6, P0.7, P0.12,
P0.13, P0.18, P0.19
Output High Voltage for
All GPIO Except P0.6,
P0.7, P0.12, P0.13,
P0.18, and P0.19
VOL_GPIO
VOL_I2C
VOH_GPIO
Output High Voltage for
GPIO P0.6, P0.7, P0.12,
P0.13, P0.18, and P0.19
VOH_I2C
Combined IOL, All GPIO
IOL_TOTAL
Combined IOH, All GPIO
IOH_TOTAL
Input Hysteresis
(Schmitt)
Input/Output Pin
Capacitance for All Pins
Input Leakage Current
Low
www.analog.com
0.7 ×
VDD
V
VDD = 1.71V, IOL = 1mA, DS[1:0] = 00
(Note 1)
0.2
0.4
VDD = 1.71V, IOL = 2mA, DS[1:0] = 10
(Note 1)
0.2
0.4
VDD = 1.71V, IOL = 4mA, DS[1:0] = 01
(Note 1)
0.2
0.4
VDD = 1.71V, IOL = 6mA, DS[1:0] = 11
(Note 1)
0.2
0.4
VDD = 1.71V, IOL = 2mA, DS = 0 (Note 1)
0.2
0.4
VDD = 1.71V, IOL = 8mA, DS = 1 (Note 1)
0.2
0.4
V
VDD = 1.71V, IOH = 1mA, DS[1:0] = 00
(Note 1)
VDD 0.4
VDD = 1.71V, IOH = 2mA, DS[1:0] = 10
(Note 1)
VDD 0.4
VDD = 1.71V, IOH = 4mA, DS[1:0] = 01
(Note 1)
VDD 0.4
VDD = 1.71V, IOH = 6mA, DS[1:0] = 11
(Note 1)
VDD 0.4
VDD = 1.71V, IOH = 2mA, DS = 0 (Note
1)
VDD 0.4
VDD = 1.71V, IOH = 8mA, DS = 1 (Note
1)
VDD 0.4
V
V
V
100
-100
mA
mA
VIHYS
300
mV
CIO
4
pF
IIL
VIN = 0V, internal pullup disabled
-500
+500
nA
Analog Devices | 35
MAX32672
High-Reliability, Tiny, Ultra-Low-Power
Arm Cortex-M4F Microcontroller
with 12-Bit, 1Msps ADC
Electrical Characteristics (continued)
(All specifications and characteristics apply across the entire operating conditions range unless otherwise noted.)
PARAMETER
SYMBOL
Input Leakage Current
High
IIH
RSTN Assertion Time
tRSTN
Input Pullup Resistor to
RSTN
Input Pullup Resistor for
All GPIO
Input Pulldown Resistor
for All GPIO
CONDITIONS
VIN = 3.6V, internal pulldown disabled
MIN
TYP
-500
Device in ACTIVE mode, RSTN device
pin assertion duration to entry into device
reset state
Pullup to VDD = 3.63V, RSTN at VIH
10.0
Device pin configured as GPIO, pullup to
VDD = VRST, device pin at VIH
18.7
Device pin configured as GPIO, pullup to
VDD = 3.63V, device pin at VIH
10.0
Device pin configured as GPIO, pulldown
to VSS, VDD = VRST, device pin at VIL
17.6
Device pin configured as GPIO, pulldown
to VSS, VDD = 3.63V, device pin at VIL
8.8
tM_ERASE
Mass erase
30
tP_ERASE
Page erase
30
32-bit programming mode,
fFLC_CLK = 1MHz
42
RPD
+500
nA
μs
K
18.7
RPU
UNITS
6x
tSYS_CL
Pullup to VDD = VRST, RSTN at VIH
RPU_VDD
MAX
kΩ
kΩ
kΩ
FLASH MEMORY
Flash Erase Time
Flash Programming
Time per Word
tPROG
Flash Endurance
Data Retention
Current Consumption
During Flash
Programming
tRET
IPROG
TA = +125°C
Single-supply
operation; current
required for flash
write/erase
Dual-supply
operation; current
required for flash
write/erase
ms
μs
10
kcycles
10
years
VDD
6.5
VCORE
0.5
VDD
mA
6
Electrical Characteristics—SPI
(Timing specifications are guaranteed by design and not production tested. All specifications and characteristics apply across the entire
operating conditions range unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
50
MHz
MASTER MODE
SPI Master Operating
Frequency
fMCK
SPI Master SCK Period
tMCK
SCK Output PulseWidth High/Low
MOSI Output Hold Time
After SCK Sample Edge
www.analog.com
fSYS_CLK = 100MHz,
fMCK(MAX) = fSYS_CLK/2
1/fMCK
ns
tMCH, tMCL
tMCK/2
ns
tMOH
tMCK/2
ns
Analog Devices | 36
MAX32672
High-Reliability, Tiny, Ultra-Low-Power
Arm Cortex-M4F Microcontroller
with 12-Bit, 1Msps ADC
Electrical Characteristics—SPI (continued)
(Timing specifications are guaranteed by design and not production tested. All specifications and characteristics apply across the entire
operating conditions range unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MOSI Output Valid to
Sample Edge
tMOV
MOSI Output Hold Time
After SCK Low Idle
tMLH
tMCK/2
ns
MISO Input Valid to
SCK Sample Edge
Setup
tMIS
5
ns
MISO Input to SCK
Sample Edge Hold
tMIH
tMCK/2
ns
tMCK/2
ns
SLAVE MODE
SPI Slave Operating
Frequency
fSCK
SPI Slave SCK Period
tSCK
1/fSCK
SCK Input Pulse-Width
High/Low
tSCH, tSCL
tSCK/2
SSx Active to First Shift
Edge
tSSE
10
ns
MOSI Input to SCK
Sample Edge Rise/Fall
Setup
tSIS
5
ns
MOSI Input from SCK
Sample Edge Transition
Hold
tSIH
1
ns
MISO Output Valid after
SCLK Shift Edge
Transition
tSOV
5
ns
SCK Inactive to SSx
Inactive
tSSD
10
ns
SSx Inactive Time
tSSH
1/fSCK
μs
MISO Hold Time after
SSx Deassertion
tSLH
10
ns
50
MHz
ns
Electrical Characteristics—I2C
(Timing specifications are guaranteed by design and not production tested. All specifications and characteristics apply across the entire
operating conditions range unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
STANDARD MODE
Output Fall Time
tOF
Standard mode, from VIH(MIN) to
VIL(MAX)
150
ns
SCL Clock Frequency
fSCL
0
Low-Period SCL Clock
tLOW
4.7
μs
High-Time SCL Clock
tHIGH
4.0
μs
www.analog.com
100
kHz
Analog Devices | 37
MAX32672
High-Reliability, Tiny, Ultra-Low-Power
Arm Cortex-M4F Microcontroller
with 12-Bit, 1Msps ADC
Electrical Characteristics—I2C (continued)
(Timing specifications are guaranteed by design and not production tested. All specifications and characteristics apply across the entire
operating conditions range unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Setup Time for
Repeated Start
Condition
tSU;STA
4.7
μs
Hold Time for Repeated
Start Condition
tHD;STA
4.0
μs
Data Setup Time
tSU;DAT
300
ns
Data Hold Time
tHD;DAT
10
ns
Rise Time for SDA and
SCL
tR
800
ns
Fall Time for SDA and
SCL
tF
200
ns
Setup Time for a Stop
Condition
tSU;STO
4.0
μs
tBUS
4.7
μs
Data Valid Time
tVD;DAT
3.45
μs
Data Valid Acknowledge
Time
tVD;ACK
3.45
μs
Bus Free Time Between
a Stop and Start
Condition
FAST MODE
Output Fall Time
tOF
Pulse Width Suppressed
by Input Filter
tSP
From VIH(MIN) to VIL(MAX)
150
ns
75
ns
SCL Clock Frequency
fSCL
0
Low-Period SCL Clock
tLOW
1.3
400
kHz
μs
High-Time SCL Clock
tHIGH
0.6
μs
Setup Time for
Repeated Start
Condition
tSU;STA
0.6
μs
Hold Time for Repeated
Start Condition
tHD;STA
0.6
μs
Data Setup Time
tSU;DAT
125
ns
Data Hold Time
tHD;DAT
10
ns
Rise Time for SDA and
SCL
tR
30
ns
Fall Time for SDA and
SCL
tF
30
ns
Setup Time for a Stop
Condition
tSU;STO
0.6
μs
tBUS
1.3
μs
tVD;DAT
0.9
μs
Bus Free Time Between
a Stop and Start
Condition
Data Valid Time
www.analog.com
Analog Devices | 38
MAX32672
High-Reliability, Tiny, Ultra-Low-Power
Arm Cortex-M4F Microcontroller
with 12-Bit, 1Msps ADC
Electrical Characteristics—I2C (continued)
(Timing specifications are guaranteed by design and not production tested. All specifications and characteristics apply across the entire
operating conditions range unless otherwise noted.)
PARAMETER
SYMBOL
Data Valid Acknowledge
Time
tVD;ACK
CONDITIONS
MIN
TYP
MAX
0.9
UNITS
μs
FAST-MODE PLUS
Output Fall Time
tOF
Pulse Width Suppressed
by Input Filter
tSP
SCL Clock Frequency
fSCL
From VIH(MIN) to VIL(MAX)
80
ns
75
ns
0
1000
kHz
Low-Period SCL Clock
tLOW
0.5
μs
High-Time SCL Clock
tHIGH
0.26
μs
Setup Time for
Repeated Start
Condition
tSU;STA
0.26
μs
Hold Time for Repeated
Start Condition
tHD;STA
0.26
μs
Data Setup Time
tSU;DAT
50
ns
Data Hold Time
tHD;DAT
10
ns
Rise Time for SDA and
SCL
tR
50
ns
Fall Time for SDA and
SCL
tF
30
ns
Setup Time for a Stop
Condition
tSU;STO
Bus Free Time Between
a Stop and Start
Condition
0.26
μs
0.5
tBUS
μs
Data Valid Time
tVD;DAT
0.45
μs
Data Valid Acknowledge
Time
tVD;ACK
0.45
μs
Electrical Characteristics—I2S Slave
(Timing specifications are guaranteed by design and not production tested. All specifications and characteristics apply across the entire
operating conditions range unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
25
MHz
Bit Clock Frequency
fBCLKS
Bit Clock Period
tBCLKS
BCLK High Time
tWBCLKHS
0.5
1/fBCLKS
BCLK Low Time
tWBCLKLS
0.5
1/fBCLKS
tLRCLK_BCLKS
25
ns
tBCLK_SDOS
12
ns
tSU_SDIS
6
ns
LRCLK Setup Time
Delay Time, BCLK to
SD (Output) Valid
Setup Time for SD
(Input)
www.analog.com
1/fBCLKS
ns
Analog Devices | 39
MAX32672
High-Reliability, Tiny, Ultra-Low-Power
Arm Cortex-M4F Microcontroller
with 12-Bit, 1Msps ADC
Electrical Characteristics—I2S Slave (continued)
(Timing specifications are guaranteed by design and not production tested. All specifications and characteristics apply across the entire
operating conditions range unless otherwise noted.)
PARAMETER
Hold Time SD (Input)
SYMBOL
CONDITIONS
MIN
tHD_SDIS
TYP
MAX
3
UNITS
ns
Electrical Characteristics—Quadrature Decoder
(Timing specifications are guaranteed by design and not production tested. All specifications and characteristics apply across the entire
operating conditions range unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
4
8
tPCLK
Encoder Period
tEP
Ensure at least one sample in each
encoder state
Encoder Pulse Width
tE
Ensure at least one sample in each
encoder state
2
4
tPCLK
Encoder State Period
tES
Ensure at least one sample in each
encoder state
1
2
tPCLK
Index Signal Width
tIND
1
1/4 x tEP
Expected Glitch Time
Window
tGL
QDEC_CTRL.filter = 0b00
0
tEP
tPCLK
tPCLK
QDEC_CTRL.filter = 0b01
1
tQDIR
After either QEA or QEB transition
4
tPCLK
Q MATCH
tQM
After either QEA or QEB transition
4
tPCLK
Q MATCH Pulse Width
tQMP
Until next state transition
1
tES
Q DIRECTION
Q ERROR
tER
After either a faulty QEA or QEB
transition
4
tPCLK
Q ERROR Pulse Width
tERP
Until next state transition
1
tES
Note 1: When using a GPIO bias voltage of 2.97V, the drive current capability of the GPIO is 2x that of its drive strength when using a
GPIO bias voltage of 1.62V.
www.analog.com
Analog Devices | 40
MAX32672
High-Reliability, Tiny, Ultra-Low-Power
Arm Cortex-M4F Microcontroller
with 12-Bit, 1Msps ADC
VBAT
1.71V TO 3.63V
VDD
4.7µF
Li+
2.7V TO 5.5V
MAX32672
VDDA
POWER
MANAGEMENT
1µF
0.855V TO 1.155V
VCORE
1µF
VREG1
4.7nF
VSS
DUAL-SUPPLY OPERATION
VBAT
1.71V TO 3.63V
STANDARD
CELL
VDD
4.7µF
MAX32672
VDDA
1µF
VCORE
1µF
VREG1
4.7nF
VSS
SINGLE-SUPPLY OPERATION
Figure 1. Power Supply Operational Modes
www.analog.com
Analog Devices | 41
MAX32672
High-Reliability, Tiny, Ultra-Low-Power
Arm Cortex-M4F Microcontroller
with 12-Bit, 1Msps ADC
SHIFT SAMPLE SHIFT SAMPLE
SSx
(SHOWN ACTIVE LOW)
tMCK
SCK
CKPOL/CKPHA
0/1 OR 1/0
SCK
CKPOL/CKPHA
0/0 OR 1/1
tMCH
tMCL
tMOH
MOSI/SDIOx
(OUTPUT)
MSB
tMOV
tMLH
tMIS
MISO/SDIOx
(INPUT)
LSB
MSB-1
tMIH
MSB
MSB-1
LSB
Figure 2. SPI Master Mode Timing Diagram
SHIFT SAMPLE SHIFT SAMPLE
SSx
(SHOWN ACTIVE LOW)
tSSE
SCK
CKPOL/CKPHA
0/1 OR 1/0
tSSH
tSSD
tSCK
tSCH
tSCL
SCK
CKPOL/CKPHA
0/0 OR 1/1
MOSI/SDIOx
(INPUT)
tSIS
MSB
tSIH
MSB-1
LSB
tSOV
MISO/SDIOx
(OUTPUT)
MSB
MSB-1
tSLH
LSB
Figure 3. SPI Slave Mode Timing Diagram
www.analog.com
Analog Devices | 42
MAX32672
High-Reliability, Tiny, Ultra-Low-Power
Arm Cortex-M4F Microcontroller
with 12-Bit, 1Msps ADC
STOP
START
REPEAT
START
START
tBUS
SDA
tOF
tR
tSU;STO
tSP
tSU;STA
tSU;DAT
tHIGH
SCL
tHD;STA
tHD;DAT
tLOW
tVD;ACK
tVD;DAT
Figure 4. I2C Timing Diagram
tBCLKS
tWBCLKHS tWBCLKLS
BCLK
(INPUT)
tLRCLK_BCLKS
LRCLK
(INPUT)
tBCLK_SDOS
SDO
(OUTPUT)
LSB
MSB
LSB
tSU_SDIS
SDI
(INPUT)
LSB
WORD N-1 RIGHT CHANNEL
MSB
LSB
WORD N LEFT CHANNEL
MSB
tHD_SDIS
MSB
WORD N RIGHT CHANNEL
CONDITIONS: I2S_CTRL0CH0.ws_pol = 0; I2S_CTRL0CH0.ch_mode = 3; I2S_CTRL0CH0.lsb_first = 0; I2S_CTRL0CH0.stereo = 0; I2S_CTRL1CH0.en = 1
Figure 5. I2S Timing Diagram
www.analog.com
Analog Devices | 43
MAX32672
High-Reliability, Tiny, Ultra-Low-Power
Arm Cortex-M4F Microcontroller
with 12-Bit, 1Msps ADC
tEP
tE
QEA
tES
tGL
tES
QEB
NOISE SPIKE
tIND
QEI
tQM
QMATCH
tQM
tQMP
tQDIR
QDIR
QERR
tQDIR
tER
tER
tERP
Figure 6. Quadrature Decoder Timing Diagram
www.analog.com
Analog Devices | 44
MAX32672
High-Reliability, Tiny, Ultra-Low-Power
Arm Cortex-M4F Microcontroller
with 12-Bit, 1Msps ADC
Pin Configuration
P0.11
P0.10
P0.12
P0.13
29 28 27
P0.14
30
P0.15
P0.16
P0.17
P0.18
TOP VIEW
P0.19
40 TQFN
26 25 24 23 22
21
VDDA 31
20 P0.9
VSSA 32
19 P0.8
VREF 33
18 P0.29
VREG1 34
17 P0.28
RSTN 35
16 P0.27
MAX32672
HFXIN 36
15 P0.26
HFXOUT 37
14 P0.25
VSS 38
13 P0.24
+
VDD 39
32KOUT 40
12 P0.23
VCORE
P0.22
P0.0
P0.1
6
7
8
9
10
P0.6
5
P0.5
4
P0.4
3
P0.3
2
P0.2
1
32KIN
11 P0.7
TQFN
5mm x 5mm
Pin Description
FUNCTION MODE
PIN
NAME
Primary
Signal
(Default)
Alternate
Function 1
Alternate
Function 2
Alternate
Function 3
Alternate
Function 4
FUNCTION
POWER AND SYSTEM PINS (See Bypass Capacitor Recommendations)
2
VCORE
—
—
—
—
—
Digital Supply Voltage. Bypass with
1.0μF to VSS.
34
VREG1
—
—
—
—
—
Bypass with 4.7nF to VSS. Do not
connect this device pin to any other
external circuitry.
39
VDD
—
—
—
—
—
GPIO Supply Voltage. Bypass with
4.7μF to VSS.
EP,
38
VSS
—
—
—
—
—
Digital Ground. Exposed pad (TQFN
only). This pad must be connected to
VSS. Refer to Application Note 3273:
Exposed Pads: A Brief Introduction
for additional information.
33
VREF
—
—
—
—
—
ADC External Reference Input. This
is the reference input for the ADC.
Bypass with 1.0μF to VSS.
www.analog.com
Analog Devices | 45
MAX32672
High-Reliability, Tiny, Ultra-Low-Power
Arm Cortex-M4F Microcontroller
with 12-Bit, 1Msps ADC
40 TQFN
FUNCTION MODE
PIN
NAME
Primary
Signal
(Default)
Alternate
Function 1
Alternate
Function 2
Alternate
Function 3
Alternate
Function 4
FUNCTION
31
VDDA
—
—
—
—
—
Analog Supply Voltage. This pin
must always be connected to the
VDD device pin at the PCB level.
Bypass this pin to VSSA with 1.0μF
as close as possible to the package.
32
VSSA
—
—
—
—
—
Analog Ground
—
Hardware Power Reset (Active-Low)
Input. The device remains in reset
while this pin is in its active state.
When the pin transitions to its
inactive state, the device performs a
POR reset (resetting all logic on all
supplies except for real-time clock
circuitry) and begins execution. This
pin has an internal pullup to the VDD
supply.
—
32kHz Crystal Oscillator Output.
Refer to the MAX32672 User Guide
for determination of the required
external stability capacitors.
—
32kHz Crystal Oscillator Input.
Connect a 32kHz crystal between
32KIN and 32KOUT for RTC
operation. Refer to the MAX32672
User Guide for determination of the
required external stability capacitors.
Optionally, this pin can be configured
as the input for an external CMOSlevel clock source.
—
RF Crystal Oscillator Input. Connect
the crystal between HFXIN and
HFXOUT. Optionally, this pin can be
configured as the input for an
external square-wave source. See
the Electrical Characteristics table for
details of the crystal requirements.
Refer to the MAX32672 User Guide
for determination of the required
external stability capacitors.
—
RF Crystal Oscillator Output.
Connect the crystal between HFXIN
and HFXOUT. See the Electrical
Characteristics table for details of the
crystal requirements. Refer to the
MAX32672 User Guide for
determination of the required
external stability capacitors.
35
RSTN
—
—
—
—
CLOCK PINS
40
1
36
37
32KOUT
32KIN
HFXIN
HFXOUT
www.analog.com
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Analog Devices | 46
MAX32672
High-Reliability, Tiny, Ultra-Low-Power
Arm Cortex-M4F Microcontroller
with 12-Bit, 1Msps ADC
40 TQFN
FUNCTION MODE
PIN
NAME
Primary
Signal
(Default)
Alternate
Function 1
Alternate
Function 2
Alternate
Function 3
Alternate
Function 4
FUNCTION
GPIO AND ALTERNATE FUNCTION
4
P0.0
P0.0
SWDIO
—
TMR0C_IA
—
Single-Wire Debug I/O; Timer0 Port
Map C Input 32 Bits or Lower 16 Bits
5
P0.1
P0.1
SWDCLK
—
TMR0C_OA
—
Single-Wire Debug Clock; Timer0
Port Map C Output 32 Bits or Lower
16 Bits
6
P0.2
P0.2
SPI0A_MIS
O
UART1B_R
X
TMR1C_IA
—
SPI0 Master In Slave Out; UART1
Port Map B RX; Timer1 Port Map C
Input 32 Bits or Lower 16 Bits
7
P0.3
P0.3
SPI0A_MO
SI
UART1B_T
X
TMR1C_OA
—
SPI0 Master Out Slave In; UART1
Port Map B Tx; Timer1 Port Map C
Output 32 Bits or Lower 16 Bits
8
P0.4
P0.4
SPI0A_SCK
UART1B_C
TS
TMR2C_IA
—
SPI0 Serial Clock; UART1 Port Map
B CTS; Timer2 Port Map C Input 32
Bits or Lower 16 Bits
SPI0A_SS0
UART1B_R
TS
TMR2C_OA
HFX_CLK_
OUT
I2C0A_SCL
LPTMR0B_I
A
9
10
P0.5
P0.6
P0.5
P0.6
QEA
I2C0 Serial Clock; Low-Power
Timer0 Port Map A Input 32 Bits or
Lower 16 Bits; SPI0 Slave Select 1;
Quadrature Decoder Phase A Input
SPI0C_SS2
QEB
I2C0 Serial Data; Low-Power Timer0
Port Map A Output 32 Bits or Lower
16 Bits; SPI0 Slave Select 2;
Quadrature Decoder Phase B Input
TMR0C_IA
AIN0/
AIN_C0_N/
AIN_C1_N
UART0 Port Map A Rx; I2S0 Serial
Data Output; Timer0 Port Map C
Input 32 Bits or Lower 16 Bits;
Comparator Negative Input
TMR0C_OA
AIN1/
AIN_C0_N/
AIN_C1_N
UART0 Port Map A Tx; I2S0 Left/
Right Clock; Timer0 Port Map C
Output 32 Bits or Lower 16 Bits;
Comparator Negative Input
TMR1C_IA
AIN2/
AIN_C0_N/
AIN_C1_N
UART0 Port Map A CTS; I2S0 Bit
Clock; Timer Port Map C Input 32
Bits or Lower 16 Bits; Comparator
Negative Input
UART0 Port Map A RTS; I2S0 Serial
Data Input; Timer1 Port Map C
Output 32 Bits or Lower 16 Bits;
Comparator Negative Input
I2C1 Serial Clock; Low-Power
External Clock Input; Timer2 Port
Map C Input 32 Bits or Lower 16 Bits;
Comparator Positive Input
SPI0C_SS1
11
P0.7
P0.7
I2C0A_SDA
LPTMR0B_
OA
19
P0.8
P0.8
UART0A_R
X
I2S0A_SDO
P0.9
UART0A_T
X
I2S0A_LRC
LK
P0.10
UART0A_C
TS
I2S0A_BCL
K
I2S0A_SDI
TMR1C_OA
AIN3/
AIN_C0_N/
AIN_C1_N
EXT_CLK2
TMR2C_IA
AIN4/
AIN_C0_P/
AIN_C1_P
20
21
P0.9
P0.10
22
P0.11
P0.11
UART0A_R
TS
23
P0.12
P0.12
I2C1A_SCL
www.analog.com
SPI0 Slave Select 0; UART1 Port
Map B RTS; Timer2 Port Map C
Output; ERFO Buffered Output 32
Bits or Lower 16 Bits
Analog Devices | 47
MAX32672
High-Reliability, Tiny, Ultra-Low-Power
Arm Cortex-M4F Microcontroller
with 12-Bit, 1Msps ADC
40 TQFN
FUNCTION MODE
PIN
NAME
Primary
Signal
(Default)
Alternate
Function 1
Alternate
Function 2
FUNCTION
Alternate
Function 3
Alternate
Function 4
I2C1 Serial Data; 32.768kHz
Calibration Output; Timer2 Port Map
C Output 32 Bits or Lower 16 Bits;
Comparator Positive Input
24
P0.13
P0.13
I2C1A_SDA
32KCAL
TMR2C_OA
AIN5/
AIN_C0_P/
AIN_C1_P
25
P0.14
P0.14
SPI1A_MIS
O
UART2B_R
X
TMR3C_IA
AIN6/
AIN_C0_P/
AIN_C1_P
SPI1 Master In Slave Out; UART2
Port Map B Rx; Timer3 Port Map C
Input 32 Bits or Lower 16 Bits;
Comparator Positive Input
UART2B_T
X
TMR3C_OA
AIN7/
AIN_C0_P/
AIN_C1_P
SPI1 Master Out Slave In; UART2
Port Map B Tx; Timer3 Port Map C
Output 32 Bits or Lower 16 Bits; ADC
Input 7/Comparator Positive Input
TMR0C_IA
AIN8
SPI1 Serial Clock; UART2 Port Map
B CTS; Timer0 Port Map C Input 32
Bits or Lower 16 Bits; ADC Input 8
26
P0.15
P0.15
SPI1A_MO
SI
27
P0.16
P0.16
SPI1A_SCK
UART2B_C
TS
TMR0C_OA
AIN9
SPI1 Slave Select 0; UART2 Port
Map B RTS; Timer0 Port Map C
Output 32 Bits or Lower 16 Bits; ADC
Input 9
28
P0.17
P0.17
SPI1A_SS0
UART2B_R
TS
29
P0.18
P0.18
I2C2A_SCL
—
TMR1C_IA
AIN10
I2C2 Serial Clock; Timer1 Port Map
C Input 32 Bits or Lower 16 Bits;
ADC Input 10
30
P0.19
P0.19
I2C2A_SDA
—
TMR1C_OA
AIN11
I2C2 Serial Data; Timer1 Port Map C
Output 32 Bits or Lower 16 Bits; ADC
Input 11
3
P0.22
P0.22
LPTMR1A_I
A
ADC_TRIG
_B
TMR0C_IA
—
Low-Power Timer1 Port Map A Input;
ADC Trigger Port Map B; Timer0
Port Map C Input 32 Bits or Lower 16
Bits
12
P0.23
P0.23
LPTMR1A_
OA
—
SPI0C_SS3
QEI
Low-Power Timer1 Port Map A
Output; SPI0 Slave Select 3;
Quadrature Decoder Index Input
UART0B_R
X
I2S0A_SD0
QES
Low-Power UART0 CTS; UART0
Port Map B Rx; I2S0 Serial Data
Output; Quadrature Decoder Capture
Input
QMATCH
13
P0.24
P0.24
LPUART0A
_CTS
14
P0.25
P0.25
LPUART0A
_RTS
UART0B_T
X
I2S0A_LRC
LK
P0.26
LPUART0A
_RX
UART0B_C
TS
I2S0C_BCL
K
P0.27
LPUART0A
_TX
UART0B_R
TS
15
16
P0.26
P0.27
www.analog.com
I2S0C_SDI
Low-Power UART0 RTS; UART0
Port Map B Tx; I2S0 Left/Right
Clock; Quadrature Decoder Match
Output
QDIR
Low-Power UART0 Rx; UART0 Port
Map B CTS; I2S0 Bit Clock;
Quadrature Decoder Direction
Output
QERR
Low-Power UART0 Port Map A Tx;
UART0 Port Map B Request to Send;
I2S 0 Port Map C Serial Data Input;
Quadrature Decoder Error Output
Analog Devices | 48
MAX32672
High-Reliability, Tiny, Ultra-Low-Power
Arm Cortex-M4F Microcontroller
with 12-Bit, 1Msps ADC
40 TQFN
FUNCTION MODE
PIN
NAME
Primary
Signal
(Default)
Alternate
Function 1
Alternate
Function 2
Alternate
Function 3
Alternate
Function 4
17
P0.28
P0.28
UART1A_R
X
EXT_CLK1
TMR3C_IA
—
P0.29
UART1A_T
X
TMR3C_OA
ADC_TRIG
_D
18
P0.29
SPI1_SS0
FUNCTION
UART1 Port Map A Receive; Timer3
Port Map C Input 32 Bits or Lower 16
Bits; External Clock Input
UART1 Port Map A Transmit; SPI1
Port Map B Slave Select 0; Timer3
Port Map C Output 32 Bits or Lower
16 Bits; ADC Trigger Port Map D
Pin Configuration
56 TQFN
P0.9
34 33
P0.10
35
P0.11
37 36
P0.12
P0.14
P0.13
P0.15
39 38
P0.16
P1.7
40
P1.5
P1.8
42 41
P1.6
P0.17
P0.18
TOP VIEW
32 31
30
29
P0.19
43
28 P0.8
P0.31
44
27 VSS
VDDA
45
26 P0.30
VSSA
46
25 P0.29
VREF
47
24 P0.28
VREG1
48
RSTN
49
HFXIN
50
21 P1.4
HFXOUT
51
20 P1.1
VSS
52
19 P1.2
VDD
53
18 P0.26
32KOUT
54
32KIN
55
VCORE
56
23 P0.27
MAX32672
22 P1.3
17 P0.25
EP
+
16 P0.24
5
6
7
8
9
10
P0.21
P0.22
P1.0
P1.9
P0.0
P0.1
P0.2
P0.3
P0.4
11 12 13 14
VDD
4
P0.7
3
P0.6
2
P0.5
1
P0.20
15 P0.23
TQFN
7mm x 7mm
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Analog Devices | 49
MAX32672
High-Reliability, Tiny, Ultra-Low-Power
Arm Cortex-M4F Microcontroller
with 12-Bit, 1Msps ADC
Pin Description
FUNCTION MODE
PIN
NAME
Primary
Signal
(Default)
Alternate
Function 1
Alternate
Function 2
Alternate
Function 3
Alternate
Function 4
FUNCTION
POWER AND SYSTEM PINS (See Bypass Capacitor Recommendations)
56
VCORE
—
—
—
—
—
Digital Supply Voltage. Bypass with
1.0μF to VSS.
48
VREG1
—
—
—
—
—
Bypass with 4.7nF to VSS. Do not
connect this device pin to any other
external circuitry.
14,
53
VDD
—
—
—
—
—
GPIO Supply Voltage. Bypass with
4.7μF to VSS.
EP,
27,
52
VSS
—
—
—
—
—
Digital Ground. Exposed pad (TQFN
only). This pad must be connected to
VSS. Refer to Application Note 3273:
Exposed Pads: A Brief Introduction
for additional information.
47
VREF
—
—
—
—
—
ADC External Reference Input. This
is the reference input for the ADC
converter. Bypass with 1.0μF to VSS.
45
VDDA
—
—
—
—
—
Analog Supply Voltage. This pin
must always be connected to the
VDD device pin at the PCB level.
Bypass this pin to VSSA with 1.0μF
as close as possible to the package.
46
VSSA
—
—
—
—
—
Analog Ground
—
Hardware Power Reset (Active-Low)
Input. The device remains in reset
while this pin is in its active state.
When the pin transitions to its
inactive state, the device performs a
POR reset (resetting all logic on all
supplies except for real-time clock
circuitry) and begins execution. This
pin has an internal pullup to the VDD
supply.
—
32kHz Crystal Oscillator Output.
Refer to the MAX32672 User Guide
for determination of the required
external stability capacitors.
—
32kHz Crystal Oscillator Input.
Connect a 32kHz crystal between
32KIN and 32KOUT for RTC
operation. Refer to the MAX32672
User Guide for determination of the
required external stability capacitors
Optionally, this pin can be configured
as the input for an external CMOSlevel clock source.
49
RSTN
—
—
—
—
CLOCK PINS
54
55
32KOUT
32KIN
www.analog.com
—
—
—
—
—
—
—
—
Analog Devices | 50
MAX32672
High-Reliability, Tiny, Ultra-Low-Power
Arm Cortex-M4F Microcontroller
with 12-Bit, 1Msps ADC
56 TQFN
FUNCTION MODE
PIN
50
51
NAME
HFXIN
HFXOUT
Primary
Signal
(Default)
Alternate
Function 1
—
—
—
Alternate
Function 2
—
Alternate
Function 3
—
Alternate
Function 4
FUNCTION
—
RF Crystal Oscillator Input. Connect
the crystal between HFXIN and
HFXOUT. Optionally, this pin can be
configured as the input for an
external square-wave source. See
the Electrical Characteristics table for
details of the crystal requirements.
Refer to the MAX32672 User Guide
for determination of the required
external stability capacitors.
—
—
—
—
RF Crystal Oscillator Output.
Connect the crystal between HFXIN
and HFXOUT. See Electrical
Characteristics for details of the
crystal requirements. Refer to the
MAX32672 User Guide for
determination of the required
external stability capacitors.
GPIO AND ALTERNATE FUNCTION
6
P0.0
P0.0
SWDIO
—
TMR0C_IA
—
Single-Wire Debug I/O; Timer0 Port
Map C Input 32 Bits or Lower 16 Bits
7
P0.1
P0.1
SWDCLK
—
TMR0C_OA
—
Single-Wire Debug Clock; Timer0
Port Map C Output 32 Bits or Lower
16 Bits
UART1B_R
X
TMR1C_IA
—
SPI0 Port Map A Master In Slave
Out; UART1 Port Map B Rx; Timer1
Port Map C Input 32 Bits or Lower 16
Bits
8
P0.2
P0.2
SPI0A_MIS
O
9
P0.3
P0.3
SPI0A_MO
SI
UART1B_T
X
TMR1C_OA
—
SPI0 Master Out Slave In; UART1
Port Map B Tx; Timer1 Port Map C
Output 32 Bits or Lower 16 Bits
10
P0.4
P0.4
SPI0A_SCK
UART1B_C
TS
TMR2C_IA
—
SPI0 Serial Clock; UART1 Port Map
B CTS; Timer2 Port Map C Input 32
Bits or Lower 16 Bits
11
P0.5
P0.5
SPI0A_SS0
UART1B_R
TS
TMR2C_OA
HFX_CLK_
OUT
12
P0.6
P0.6
I2C0A_SCL
LPTMR0B_I
A
SPI0C_SS1
QEA
I2C0 Serial Clock; Low-Power
Timer0 Port Map A Input 32 Bits or
Lower 16 Bits; SPI0 Slave Select 1;
Quadrature Decoder Phase A Input
I2C0A_SDA
LPTMR0B_
OA
QEB
I2C0 Serial Data; Low-Power Timer0
Port Map A Output 32 Bits or Lower
16 Bits; SPI0 Slave Select 2;
Quadrature Decoder Phase B Input
13
P0.7
www.analog.com
P0.7
SPI0C_SS2
SPI0 Slave Select 0; UART1 Port
Map B RTS; Timer2 Port Map C
Output 32 Bits or Lower 16 Bits;
ERFO Buffered Output
Analog Devices | 51
MAX32672
High-Reliability, Tiny, Ultra-Low-Power
Arm Cortex-M4F Microcontroller
with 12-Bit, 1Msps ADC
56 TQFN
FUNCTION MODE
PIN
NAME
Primary
Signal
(Default)
Alternate
Function 1
Alternate
Function 2
Alternate
Function 4
I2S0A_SDO
TMR0C_IA
AIN0/
AIN_C0_N/
AIN_C1_N
UART0 Port Map A Rx; I2S0 Serial
Data Output; Timer0 Port Map C
Input 32 Bits or Lower 16 Bits;
Comparator Negative Input
TMR0C_OA
AIN1/
AIN_C0_N/
AIN_C1_N
UART0 Port Map A Tx; I2S0 Left/
Right Clock; Timer0 Port Map C
Output 32 Bits or Lower 16 Bits;
Comparator Negative Input
TMR1C_IA
AIN2/
AIN_C0_N/
AIN_C1_N
UART0 Port Map A CTS; I2S0 Bit
Clock; Timer1 Port Map C Input 32
Bits or Lower 16 Bits; Comparator
Negative Input
TMR1C_OA
AIN3/
AIN_C0_N/
AIN_C1_N
UART0 Port Map A RTS; I2S0 Serial
Data Input; Timer1 Port Map C
Output 32 Bits or Lower 16 Bits;
Comparator Negative Input
I2C1 Serial Clock; Low-Power
External Clock Input; Timer2 Port
Map C Input 32 Bits or Lower 16 Bits;
Comparator Positive Input
28
P0.8
P0.8
UART0A_R
X
29
P0.9
P0.9
UART0A_T
X
I2S0A_LRC
LK
P0.10
UART0A_C
TS
I2S0A_BCL
K
P0.11
UART0A_R
TS
30
31
P0.10
P0.11
FUNCTION
Alternate
Function 3
I2S0A_SDI
32
P0.12
P0.12
I2C1A_SCL
EXT_CLK2
TMR2C_IA
AIN4/
AIN_C0_P/
AIN_C1_P
33
P0.13
P0.13
I2C1A_SDA
32KCAL
TMR2C_OA
AIN5/
AIN_C0_P/
AIN_C1_P
I2C1 Serial Data; 32.768kHz
Calibration Output; Timer2 Port Map
C Output 32 Bits or Lower 16 Bits;
Comparator Positive Input
P0.14
SPI1A_MIS
O
UART2B_R
X
TMR3C_IA
AIN6/
AIN_C0_P/
AIN_C1_P
SPI1 Master In Slave Out; UART2
Port Map B Rx; Timer3 Port Map C
Input 32 Bits or Lower 16 Bits;
Comparator Positive Input
UART2B_T
X
TMR3C_OA
AIN7/
AIN_C0_P/
AIN_C1_P
SPI1 Master Out Slave In; UART2
Port Map B Tx; Timer3 Port Map C
Output 32 Bits or Lower 16 Bits; ADC
Input 7/Comparator Positive Input
TMR0C_IA
AIN8
SPI1 Serial Clock; UART2 Port Map
B CTS; Timer0 Port Map C Input 32
Bits or Lower 16 Bits; ADC Input 8
34
P0.14
35
P0.15
P0.15
SPI1A_MO
SI
36
P0.16
P0.16
SPI1A_SCK
UART2B_C
TS
TMR0C_OA
AIN9
SPI1 Slave Select 0; UART2 Port
Map B RTS; Timer0 Port Map C
Output 32 Bits or Lower 16 Bits; ADC
Input 9
41
P0.17
P0.17
SPI1A_SS0
UART2B_R
TS
42
P0.18
P0.18
I2C2A_SCL
—
TMR1C_IA
AIN10
I2C2 Serial Clock; Timer1 Port Map
C Input 32 Bits or Lower 16 Bits;
ADC Input 10
43
P0.19
P0.19
I2C2A_SDA
—
TMR1C_OA
AIN11
I2C2 Serial Data; Timer1 Port Map C
Output 32 Bits or Lower 16 Bits; ADC
Input 11
1
P0.20
P0.20
CM4_RX
—
TMR2C_IA
—
CM4 Rx Event Input; Timer2 Port
Map C Input 32 Bits or Lower 16 Bits
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Analog Devices | 52
MAX32672
High-Reliability, Tiny, Ultra-Low-Power
Arm Cortex-M4F Microcontroller
with 12-Bit, 1Msps ADC
56 TQFN
FUNCTION MODE
PIN
NAME
Primary
Signal
(Default)
Alternate
Function 1
Alternate
Function 2
Alternate
Function 3
Alternate
Function 4
2
P0.21
P0.21
CM4_TX
—
TMR2C_OA
—
CM4 Tx Event Output; Timer2 Port
Map C Output 32 Bits or Lower 16
Bits
ADC_TRIG
_B
TMR0C_IA
—
Low-Power Timer1 Port Map A Input;
ADC Trigger Port Map B; Timer0
Port Map C Input 32 Bits or Lower 16
Bits
SPI0C_SS3
QEI
Low-Power Timer1 Port Map A
Output; SPI0 Slave Select 3;
Quadrature Decoder Index Input
QES
Low-Power UART0 CTS; UART0
Port Map B Rx; I2S0 Serial Data
Output; Quadrature Decoder Capture
Input
3
P0.22
P0.22
LPTMR1A_I
A
15
P0.23
P0.23
LPTMR1A_
OA
—
P0.24
LPUART0A
_CTS
UART0B_R
X
I2S0A_SD0
UART0B_T
X
I2S0A_LRC
LK
QMATCH
16
P0.24
FUNCTION
Low-Power UART0 RTS; UART0
Port Map B Tx; I2S0 Left/Right
Clock; Quadrature Decoder Match
Output
17
P0.25
P0.25
LPUART0A
_RTS
18
P0.26
P0.26
LPUART0A
_RX
UART0B_C
TS
I2S0C_BCL
K
QDIR
Low-Power UART0 Rx; UART0 Port
Map B CTS; I2S0 Bit Clock;
Quadrature Decoder Direction
Output
23
P0.27
P0.27
LPUART0A
_TX
UART0B_R
TS
I2S0C_SDI
QERR
Low-Power UART0 Port Map A Tx;
UART0 Port Map B Request to Send;
I2S0 Port Map C Serial Data Input;
Quadrature Decoder Error Output
24
P0.28
P0.28
UART1A_R
X
EXT_CLK1
TMR3C_IA
—
UART1 Port Map A Receive; Timer3
Port Map C Input 32 Bits or Lower 16
Bits; External Clock Input
25
P0.29
P0.29
UART1A_T
X
SPI1_SS0
TMR3C_OA
ADC_TRIG
_D
UART1 Port Map A Transmit; SPI1
Port Map B Slave Select 0;Timer3
Port Map C Output 32 Bits or Lower
16 Bits; ADC Trigger Port Map D
26
P0.30
P0.30
UART1A_C
TS
—
TMR3C_IA
—
UART1 Port Map A Clear to Send;
Timer3 Port Map C Input 32 Bits or
Lower 16 Bits
44
P0.31
P0.31
UART1A_R
TS
—
TMR3C_OA
—
UART1 Port Map A Request to Send;
Timer3 Port Map C Output 32 Bits or
Lower 16 Bits
4
P1.0
P1.0
—
—
TMR1C_IA
—
Timer1 Port Map C Input 32 Bits or
Lower 16 Bits
20
P1.1
P1.1
SPI2A_MIS
O
UART0B_R
X
TMR3C_OA
—
SPI2 Port Map A Master In Slave
Out; UART0 Port Map B Receive;
Timer3 Port Map C Output 32 Bits or
Lower 16 Bits
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Analog Devices | 53
MAX32672
High-Reliability, Tiny, Ultra-Low-Power
Arm Cortex-M4F Microcontroller
with 12-Bit, 1Msps ADC
56 TQFN
FUNCTION MODE
PIN
NAME
Primary
Signal
(Default)
Alternate
Function 1
Alternate
Function 2
Alternate
Function 3
Alternate
Function 4
UART0B_T
X
TMR3C_IA
DIV_CLK_
OUT
—
—
19
P1.2
P1.2
SPI2A_MO
SI
22
P1.3
P1.3
SPI2A_SCK
UART0B_C
TS
TMR0C_OA
ADC_TRIG
_D
FUNCTION
SPI2 Port Map A Master Out Slave
In; UART0 Port Map B Transmit;
Timer3 Port Map C Input 32 Bits or
Lower 16 Bits; Divided_Clock_Output
SPI2 Port Map A Serial Clock;
UART0 Port Map B Clear to Send
SPI2 Port Map A Slave Select 0;
UART0 Port Map B Request to Send;
Timer0 Port Map C Output 32 Bits or
Lower 16 Bits; ADC Trigger Port Map
D
21
P1.4
P1.4
SPI2A_SS0
UART0B_R
TS
37
P1.5
P1.5
UART2A_R
X
—
—
—
UART2 Port Map A Receive
38
P1.6
P1.6
UART2A_T
X
—
—
—
UART2 Port Map A Transmit
39
P1.7
P1.7
UART2A_C
TS
—
—
—
UART2 Port Map A Clear to Send
40
P1.8
P1.8
UART2A_R
TS
—
—
—
UART2 Port Map A Request to Send
5
P1.9
P1.9
—
—
TMR1C_OA
—
Timer1 Port Map C Output 32 Bits or
Lower 16 Bits
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Analog Devices | 54
MAX32672
High-Reliability, Tiny, Ultra-Low-Power
Arm Cortex-M4F Microcontroller
with 12-Bit, 1Msps ADC
Detailed Description
The MAX32672 is an ultra-low-power, cost-effective, highly integrated microcontroller designed for battery-powered
devices and wireless sensors. It combines a flexible and versatile power management unit with the powerful Arm CortexM4 processor with FPU. The device enables designs with complex sensor processing without compromising battery life.
It also offers legacy designs an easy and cost-optimal upgrade path from 8- or 16-bit microcontrollers. Error correction
coding (single error correction, double error detection, or SEC-DED) for flash and SRAM provides extremely reliable code
execution. The device integrates 1MB of dual-bank flash memory and 200KB (160KB with ECC enabled) of SRAM to
accommodate application and sensor code. A 1Msps, 12-channel, 12-bit SAR ADC is integrated for the digitization of
analog sensor signals or other analog measurements.
The device features five powerful and flexible power modes. It can operate from a single-supply battery or a dual-supply
typically provided by a PMIC. The I2C ports support Standard, Fast, Fast-mode Plus, and High Speed modes, operating
up to 3400kbps. The SPI ports can run up to 50MHz in both master and slave mode. Four general-purpose 32-bit timers,
two low-power 32-bit timers, two windowed watchdog timers, and a real-time clock (RTC) are also provided. An I2S
interface provides digital audio streaming to a codec.
Arm Cortex-M4 Processor with FPU Engine
The Arm Cortex-M4 with FPU processor combines high-efficiency signal processing functionality with low power, low
cost, and ease of use.
The Arm Cortex-M4 with FPU DSP supports single instruction, multiple data (SIMD) path DSP extensions, providing:
●
●
●
●
●
●
Four parallel 8-bit add/sub
Floating point single precision
Two parallel 16-bit add/sub
Two parallel MACs
32- or 64-bit accumulate
Signed, unsigned, data with or without saturation
Memory
Internal Flash Memory
The 1MB internal flash memory with error correction provides nonvolatile storage of program and data memory. The
flash is organized in two equal sizes, physically separate banks (dual bank) to allow execute-while-write operation and
facilitate "live FW upgrades."
Internal SRAM
The internal 200KB SRAM provides low-power retention of application information in all power modes except STORAGE.
The SRAM can be configured as 160KB with Error Correction Coded (ECC) SEC-DED for enhanced system reliability.
The SRAM can be divided into granular banks that create a flexible SRAM retention architecture. This data retention
feature is optional and is configurable. This granularity allows the application to minimize its power consumption by only
retaining the essential data.
Clocking Scheme
The internal primary oscillator (IPO) operates at a nominal frequency of 100MHz.
Optionally, the software can select one of five other oscillators depending upon power needs:
●
●
●
●
●
80kHz oscillator (INRO)
32.768kHz oscillator (external crystal required) (ERTC0)
7.3728MHz oscillator (IBRO)
16MHz–32MHz oscillator (external crystal required) (ERFO)
External square-wave clocks up to 50MHz
This clock is the primary clock source for digital logic and peripherals.
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Analog Devices | 55
MAX32672
High-Reliability, Tiny, Ultra-Low-Power
Arm Cortex-M4F Microcontroller
with 12-Bit, 1Msps ADC
An external 32.768kHz timebase is required when using the RTC. A separate external square-wave clock can be used
as a source for LPTMR0/1 and LPUART0 in the Always-On domain.
RTC/CALIBRATION
OUTPUT
32KCAL
(P0.13)
ALWAYS-ON DOMAIN
XTAL DRIVER OR
EXTERNAL CLOCK
32KIN BYPASS
32KIN
32.768kHz
CRYSTAL
4096Hz
DIGITAL
INTERFACE
32.768kHz
OSC
LPTMR0
32-BIT
32KOUT
RTC_OSCCTRL.bypass
1Hz 512Hz 4096Hz 32768Hz
32.768kHz
LPTMR1
32-BIT
REAL-TIME CLOCK
LPUART0
POWER SEQUENCER
NANORING (INRO)
~80kHz
AUTO-CAL
GCR_CLKCTRL.ipo_div
100MHz
100MHz
INTERNAL
PRIMARY
OSCILLATOR
(IPO)
80kHz
INTERNAL
PRIMARY
OSCILLATOR
PRESCALER
Arm Cortex-M4
GCR_PCLKDIV.aon_clkdiv
32.768kHz
7.3728MHz
ALWAYS-ON
DOMAIN CLOCK
(AOD_CLK)
GCR_CLKCTRL.sysclk_sel
÷2
PCLK
SYS_CLK
GCR_PCLKDIV.div_clk_out_ctrl
7.3728MHz
SYS_OSC
INTERNAL BAUD
RATE OCILLATOR
(IBRO)
÷2
DIV_CLK_OUT (P1.2 56 TQFN
PACKAGE ONLY)
÷4
÷8
HFX_CLK_OUT (P0.5)
GCR_CLKCTRL.sysclk_div
HFXIN
BYPASS
16MHz–32MHz
CRYSTAL
XTAL DRIVER OR
EXTERNAL CLOCK
EXT_CLK1 (P0.28)
EXT_CLK2 (P0.12)
TMR0
DUAL
16-BIT
TMR1
DUAL
16-BIT
AES/CRC/
TRNG
PRESCALER
12-BIT SAR ADC
16MHz–
32MHz
ADC
OSC
(ERFO)
SAR_CLKCTRL.clkdiv
HFXOUT
GCR_PM.erfo_bp
CLOCK
SCALER
SAR_CLKCTRL.clksel
EXT_CLK1 (AF2)
EXT_CLK2 (AF2)
TMR2
DUAL
16-BIT
TMR3
DUAL
16-BIT
UART0
UART1
UART2
WDT1
WDT0
3x
I2 C
I2 S
12-CH
DMA
3x
SPI
QUAD
DEC
Figure 7. Clocking Scheme
General-Purpose I/O and Special Function Pins
Most general-purpose I/O (GPIO) pins share a firmware-controlled I/O function and one or more special function signals
associated with peripheral modules. The software can individually enable pins for GPIO or peripheral special function
use. Configuring a pin as a special function usually supersedes its use as a software-controlled I/O. Multiplexing
between peripheral and GPIO functions is usually static but can also be done dynamically by software. The electrical
characteristics of a GPIO pin are identical whether the pin is configured as an I/O or special function, except where
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Analog Devices | 56
MAX32672
High-Reliability, Tiny, Ultra-Low-Power
Arm Cortex-M4F Microcontroller
with 12-Bit, 1Msps ADC
explicitly noted in the Electrical Characteristics tables.
In GPIO mode, each port pin has an interrupt function that can be independently enabled by software and configured
as a level- or edge-sensitive interrupt. All GPIOs share the same interrupt vector. Some packages do not have all of the
GPIOs available.
When configured as GPIOs, the following features are provided. These features can be independently enabled or
disabled on a per-pin basis.
●
●
●
●
Configurable as input, output, bidirectional, or high-impedance
Optional internal pullup resistor or internal pulldown resistor when configured as input
Exit from low-power modes on rising or falling edge
Selectable standard- or high-drive modes
The MAX32672 provides up to 42 GPIOs. See the Ordering Information table for the specific number of GPIOs by part
number.
Standard DMA Controller
The standard direct memory access (DMA) controller provides a means to offload the CPU for memory/peripheral data
transfer leading to a more power-efficient system. It allows automatic one-way data transfer between two entities. These
entities can be either memories (flash or SRAM) or peripherals. The transfers are done without using CPU resources.
The following transfer modes are supported:
●
●
●
●
●
12 channel
Peripheral to memory
Memory to peripheral
Memory to memory
Event support
All DMA transactions consist of an AHB burst read into the DMA FIFO followed immediately by an AHB burst write from
the FIFO.
Power Management
Power Management Unit
The power management unit (PMU) provides the optimal mix of high-performance and low-power consumption. It
exercises intelligent, precise control of power distribution to the CPU and peripheral circuitry.
The PMU provides the following features:
●
●
●
●
User-configurable system clock
Automatic enabling and disabling of crystal oscillators based on power mode
Multiple clock domains
Fast wakeup of powered-down peripherals when activity detected
ACTIVE Mode
In this mode, the CPU executes software and all digital and analog peripherals are available on demand. Dynamic
clocking disables local clocks in peripherals that are not in use. This mode corresponds to the Arm Cortex-M4 processor
with FPU ACTIVE mode.
SLEEP Mode
This mode allows for lower power consumption operations than ACTIVE mode. The CPU is asleep, peripherals are on,
and the standard DMA block is available. The GPIO or any active peripheral can be configured to interrupt and cause a
transition to the ACTIVE mode. This mode corresponds to the Arm Cortex-M4 processor with FPU SLEEP mode.
DEEPSLEEP Mode
In this mode, CPU and critical peripheral configuration settings and all volatile memory are preserved.
The device status is as follows:
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Analog Devices | 57
MAX32672
High-Reliability, Tiny, Ultra-Low-Power
Arm Cortex-M4F Microcontroller
with 12-Bit, 1Msps ADC
● CPU is powered down. System state and all SRAM is retained.
● The GPIO pins retain their state.
● The transition from DEEPSLEEP to ACTIVE mode is faster than the transition from BACKUP mode because system
initialization is not required.
● The system oscillators are all disabled to provide additional power savings over SLEEP mode.
● LPUART0 and LPTMR0/1 can be active and are optional wake-up sources.
This mode corresponds to the Arm Cortex-M4 with FPU DEEPSLEEP mode.
BACKUP Mode
This mode places the CPU in a static, low-power state. BACKUP mode supports the same wake-up sources as
DEEPSLEEP mode.
The device status is as follows:
● CPU is powered down.
● SRAM retention as per Table 1.
● LPUART0 and LPTMR0/1 can be active and are optional wake-up sources.
Table 1. BACKUP Mode RAM Retention
RAM BLOCK
SRAM SIZE
RETAINED SRAM
TYPE
SYSRAM0
20KB
18KB
16KB + 4KB ECC
SYSRAM1
20KB
14KB
16KB + 4KB ECC
SYSRAM2
80KB
80KB
64KB + 16KB ECC
SYSRAM3
80KB
80KB
64KB + 16KB ECC
Note: The boot ROM uses certain ranges of SRAM during a system reset, watchdog timer reset, an external reset, and
exiting from BACKUP. The devices uses this RAM to perform system checks. As a result, not all of each RAM can be
retained during an exit from BACKUP.
STORAGE Mode
The device status is as follows:
●
●
●
●
●
CPU is powered off.
All peripherals are powered off.
Wake-up from GPIO interrupt.
The RTC can be enabled by software before entering STORAGE mode.
No SRAM retention.
Real-Time Clock (RTC)
An RTC keeps the time of day in absolute seconds. The 32-bit seconds register can count up to approximately 136 years
and be translated to calendar format by application software.
The RTC provides a time-of-day alarm programmed by software to any future value between 1 second and 12 days.
When configured for long intervals, the time-of-day alarm can be used as a power-saving timer, allowing the device to
remain in an extremely low-power mode but still awaken periodically to perform assigned tasks. Software can program a
second independent 32-bit 1/4096 sub-second alarm between 244μs and 12 days. Both can be configured as recurring
alarms. When enabled, either alarm can cause an interrupt or wake the device from most low-power modes.
The time base is generated by a 32.768kHz crystal or an external clock source that must meet the electrical/timing
requirements in the Electrical Characteristics table.
An RTC calibration feature allows the software to compensate for minor variations in the RTC oscillator, crystal,
temperature, and board layout. Enabling the 32KCAL alternate function outputs a timing signal derived from the RTC.
External hardware can measure the frequency and adjust the RTC frequency in increments of ±127ppm with a 1ppm
resolution. Under most circumstances, the oscillator does not require any calibration.
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Analog Devices | 58
MAX32672
High-Reliability, Tiny, Ultra-Low-Power
Arm Cortex-M4F Microcontroller
with 12-Bit, 1Msps ADC
Windowed Watchdog Timer (WDT)
Microcontrollers are often used in harsh environments where electrical noise and electromagnetic interference (EMI) are
abundant. Without proper safeguards, these hazards can disturb device operation and corrupt program execution. One
of the most effective countermeasures is the windowed WDT, which detects runaway code or system unresponsiveness.
The WDT is a 32-bit, free-running counter with a configurable prescaler. When enabled, the WDT must be periodically
reset by the application software. Failure to reset the WDT within the user-configurable timeout period indicates that the
application software is not operating correctly and results in a WDT timeout. A WDT timeout can trigger an interrupt,
system reset, or both. Either response forces the instruction pointer to a known good location before resuming instruction
execution. The windowed timeout period feature provides more detailed monitoring of system operation, requiring the
WDT to be reset within a specific time window.
One or more instances of the peripheral are provided, as shown in Table 2. See the Ordering Information table for the
specific instances available by part number.
Table 2. MAX32672 Watchdog Timer Instances
INSTANCE
OPERATING MODES
WDT0
WDT1
CLOCK SOURCE
PCLK
IPO
IBRO
ERFO
INRO
ERTCO
EXT_CLK1
EXT_CLK2
ACTIVE
SLEEP
YES
YES
YES
YES
YES
YES
YES
NO
ACTIVE
SLEEP
YES
YES
YES
YES
YES
YES
YES
NO
32-Bit Timer/Counter/PWM (TMR, LPTMR)
General-purpose, 32-bit timers provide timing, capture/compare, or generate pulse-width modulated (PWM) signals with
minimal software interaction.
The timer provides the following features:
●
●
●
●
●
●
●
●
32-bit up/down auto-reload
Programmable prescaler
PWM output generation
Capture, compare, and capture/compare capability
External pin multiplexed with GPIO for timer input, clock gating, or capture
Timer output pin
TMR0-TMR3 configurable as 2 × 16-bit general-purpose timers
Timer interrupt
The MAX32672 provides six 32-bit timers (TMR0, TMR1, TMR2, TMR3, LPTMR0, LPTMR1). The LPTMR0 and LPTMR1
are capable of operation in the SLEEP, DEEPSLEEP, and BACKUP low-power modes.
The I/O functionality is supported for all of the timers. Note that the function of a port can be multiplexed with other
functions on the GPIO pins, so it might not be possible to use all the ports depending on the device configuration. One or
more instances of the peripheral are provided, as shown in Table 3.
See the Ordering Information table for the specific instances available by part number.
Table 3. MAX32672 Timer Instances
CLOCK SOURCE
INSTANCE
SINGLE
32-BIT
DUAL
16-BIT
OPERATING
MODES
PCLK
IBRO
ERFO
INRO
ERTCO
EXT_CLK1
EXT_CLK2
TMR0
YES
YES
ACTIVE
YES
YES
YES
NO
NO
YES
NO
TMR1
YES
YES
ACTIVE
YES
YES
YES
NO
NO
YES
NO
TMR2
YES
YES
ACTIVE
YES
YES
YES
NO
NO
YES
NO
TMR3
YES
YES
ACTIVE
YES
YES
YES
NO
NO
YES
NO
LPTMR0
YES
NO
AOD_CLK
NO
NO
YES
YES
NO
YES
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ACTIVE
SLEEP
Analog Devices | 59
MAX32672
High-Reliability, Tiny, Ultra-Low-Power
Arm Cortex-M4F Microcontroller
with 12-Bit, 1Msps ADC
Table 3. MAX32672 Timer Instances (continued)
INSTANCE
SINGLE
32-BIT
DUAL
16-BIT
OPERATING
MODES
CLOCK SOURCE
PCLK
DEEPSLEEP
YES
NO
ERFO
INRO
ERTCO
EXT_CLK1
EXT_CLK2
NO
NO
YES
YES
NO
YES
NO
BACKUP
LPTMR1
IBRO
ACTIVE
SLEEP
AOD_CLK
DEEPSLEEP
BACKUP
NO
Serial Peripherals
I2C Interface
The I2C interface is a bidirectional, two-wire serial bus that provides a medium-speed communications network. It can
operate as a one-to-one, one-to-many, or many-to-many communications medium. The I2C master/slave interfaces to a
wide variety of I2C-compatible peripherals. These engines support standard-mode, fast-mode, fast-mode plus, and highspeed mode I2C speeds. It provides the following features:
● Master or slave mode operation
• Supports up to four different slave addresses in slave mode
●
●
●
●
●
●
Supports standard 7-bit addressing or 10-bit addressing
RESTART condition
Interactive receive mode
Transmit FIFO preloading
Support for clock stretching to allow slower slave devices to operate on higher speed busses
Multiple transfer rates
• Standard mode: 100kbps
• Fast mode: 400kbps
• Fast mode plus: 1000kbps
• High-speed mode: 3400kbps
● Internal filter to reject noise spikes
● Receive FIFO depth of 8 bytes
● Transmit FIFO depth of 8 bytes
One or more instances of the peripheral are provided, as shown in Table 4. See the Ordering Information table for the
specific instances available by part number.
Table 4. MAX32672 I2C Instances
INSTANCE
POWER MODES
I2C0
ACTIVE
SLEEP
I2C1
ACTIVE
SLEEP
I2C2
ACTIVE
SLEEP
Serial Peripheral Interface (SPI)
The SPI is a highly configurable, flexible, and efficient synchronous interface between multiple SPI devices on a single
bus. The bus uses a single clock signal and multiple data signals and one or more slave select lines to address only the
intended target device. The SPI operates independently and requires minimal processor overhead.
The provided SPI peripherals can operate in either slave or master mode and provide the following features:
● SPI modes 0, 1, 2, and 3 for single-bit communication
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Analog Devices | 60
MAX32672
●
●
●
●
●
●
●
High-Reliability, Tiny, Ultra-Low-Power
Arm Cortex-M4F Microcontroller
with 12-Bit, 1Msps ADC
3- or 4-wire mode for single-bit slave device communication
Full-duplex operation in single-bit, 4-wire mode
Multimaster mode fault detection
Programmable interface timing
Programmable SCK frequency and duty cycle
32-byte transmit and receive FIFOs
Slave select assertion and deassertion timing relative to leading/trailing SCK edge
One or more instances of the peripheral are provided, as shown in Table 5. See the Ordering Information table for the
specific instances available by part number.
Table 5. MAX32672 SPI Instances
INSTANCE
DATA
SLAVE SELECT
LINES
MAXIMUM FREQUENCY (MASTER
MODE) (MHz)
MAXIMUM FREQUENCY (SLAVE
MODE) (MHz)
SPI0
3 wire,
4 wire
4
50
50
SPI1
3 wire,
4 wire
1
50
50
SPI2
3 wire, 4
wire
1
50
50
I2S Interface
The I2S interface is a bidirectional, 4-wire serial bus that provides serial communications for codecs and audio amplifiers
compliant with the I2S Bus Specification, June 5, 1996. It provides the following features:
●
●
●
●
●
●
●
●
●
●
Slave mode operation
8-, 16-, 24-, and 32-bit frames
Receive and transmit DMA support
Wakeup on FIFO status (full/empty/threshold)
Pulse density modulation support for the receive channel
Word select polarity control
First-bit position selection
Interrupts generated for FIFO status
Receiver FIFO depth of 32 bytes
Transmitter FIFO depth of 32 bytes
The MAX32672 provides one instance of the I2S peripheral (I2S0).
UART
The universal asynchronous receiver-transmitter (UART, LPUART) interface supports full-duplex asynchronous
communication with optional hardware flow control (HFC) modes to prevent data overruns. If HFC mode is enabled on a
given port, the system uses two extra pins to implement the industry-standard request-to-send (RTS) and clear-to-send
(CTS) flow control signaling. Each LPUART is individually programmable.
●
●
●
●
●
●
●
●
●
●
●
●
2-wire interface or 4-wire interface with flow control
8-byte send/receive FIFO
Full-duplex operation for asynchronous data transfers
Interrupts available for frame error, parity error, CTS, receive FIFO overrun, and FIFO full/partially full conditions
Automatic parity and frame error detection
Independent baud-rate generator
Programmable 9th-bit parity support
Multidrop support
Start/stop bit support
Hardware flow control using RTS/CTS
Two DMA channels can be connected (read and write FIFOs)
Programmable word size (5 bits to 8 bits)
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Analog Devices | 61
MAX32672
High-Reliability, Tiny, Ultra-Low-Power
Arm Cortex-M4F Microcontroller
with 12-Bit, 1Msps ADC
LPUART0 is capable of operation in SLEEP, DEEPSLEEP, and BACKUP low-power modes.
One or more instances of the peripheral are provided, as shown in Table 6. See the Ordering Information table for the
specific instances available by part number.
Table 6. MAX32672 UART Instances
INSTANCE
MODE
UART0
CLOCK SOURCE
PCLK
IBRO
ERFO
INRO
ERTCO
EXT_CLK1
EXT_CLK2
ACTIVE
YES
YES
YES
NO
NO
YES
NO
UART1
ACTIVE
YES
YES
YES
NO
NO
YES
NO
UART2
ACTIVE
YES
YES
YES
NO
NO
YES
NO
ACTIVE
SLEEP
AOD_CLK
DEEPSLEEP
BACKUP
NO
NO
YES
YES
NO
YES
NO
LPUART0
Quadrature Decoder
The quadrature decoder converts rotational information derived from optical or magnetic encoders to counts representing
a shaft's angle and rotational velocity.
The following features are provided:
●
●
●
●
●
x1, x2, and x4 mode selection
32-bit counter
Index input
Rotational direction and error outputs
On-chip deglitch filters
The MAX32672 provides one instance of the quadrature decoder (QDEC).
Analog-to-Digital Converter (ADC)
The 12-bit SAR ADC provides an integrated reference generator and a single-ended input multiplexer. The multiplexer
selects an input channel from one of the 12 external analog input signals (AIN0–AIN11), the internal power supply inputs,
or an internal temperature sensor.
The reference for the ADC can be:
● External VREF input
● VDDA analog supply
The ADC measures the following voltages:
●
●
●
●
●
AIN[11:0] up to 3.3V
VDD
VCORE
VDDA
Internal die temperature sensor input
Security
AES
The dedicated hardware-based AES engine supports the following algorithms:
● AES-128
● AES-192
● AES-256
AES keys can be generated by the TRNG, and software can store the keys in a dedicated protected flash region. If keys
are stored in the dedicated protected flash region, the keys are automatically loaded to the AES system key registers on
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Analog Devices | 62
MAX32672
High-Reliability, Tiny, Ultra-Low-Power
Arm Cortex-M4F Microcontroller
with 12-Bit, 1Msps ADC
power-on reset and system reset. The AES key registers can not be read by software.
Secure Cryptographic Accelerator (SCA)
This hardware accelerator is dedicated to asymmetrical cryptographic operations, specially optimized ECDSA P-256
curve cryptographic operations such as signatures and verifications. It also accelerates low-level operations such as
modular addition, subtraction, multiplication, division, and scalar operations.
The following features are provided:
●
●
●
●
●
●
●
ECC operations of 256, 384, and 521 bits
Pointer-based architecture to easily access SCA memory without memory transfer overhead
Support for Jacobian and affine coordinates
SPA, DPA, and fault attack countermeasures
Precalculated point support to speed ECC processing (ECDSA P-256)
EdDSA algorithms such as Ed25519 and Ed448 can also be implemented (supported in TLS 1.3), as well as X25519
Dedicated input for the private key
True Random Number Generator (TRNG)
Random numbers are a vital part of a secure application, providing random numbers useable for cryptographic seeds or
strong cryptography keys to ensure data privacy. Software can use random numbers to trigger asynchronous events that
result in nondeterministic behavior. Random strings can be added to to messages to make encryption indeterministic and
therefore avoid replay attacks.
The TRNG is continuously updated by a high-quality, physically-unpredictable entropy source. It generates one random
bit per cryptographic clock cycle.
The TRNG can support the system-level validation of many security standards. Contact Analog Devices for details of
compliance with specific standards.
CRC Module
A cyclic redundancy check (CRC) hardware module provides fast calculations and data integrity checks by application
software. The CRC polynomial is programmable to support custom CRC algorithms, as well as the common algorithms
shown in Table 7.
Table 7. Common CRC Polynomials
ALGORITHM
POLYNOMIAL EXPRESSION
CRC-32-ETHERNET
x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x1 + x0
CRC-CCITT
x16 + x12 + x5 + x0
CRC-16
x16 + x15 + x2 + x0
USB DATA
x16 + x15 + x2 + x0
PARITY
x1 + x0
SHA-2
SHA-2 is a cryptographic hash function. It authenticates user data and verifies its integrity. It is used for digital signatures.
The device provides a hardware SHA-2 engine for fast computation of digests supporting:
●
●
●
●
SHA-224
SHA-256
SHA-384
SHA-512
Software Integrity and Root of Trust
Root of Trust
On devices that support SCPBL, the root of trust starts with trusted software and the microcontroller's complement of
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Analog Devices | 63
MAX32672
High-Reliability, Tiny, Ultra-Low-Power
Arm Cortex-M4F Microcontroller
with 12-Bit, 1Msps ADC
security features. Communications between a host and the device must be secure and authenticated, and program
integrity must be verified each time before execution to ensure the device's trustworthiness. The device's root of trust is
based on a secret Analog Devices root verification key and a signed customer verification key (CVK). Customers submit
their public CVK, which is then signed, and a certificate is sent back to the customer. This process is quick and required
only once, before the software is released for the first time, and is unnecessary during the software development. A
customer can then load their own key and download their signed binary executable code.
Secure Communications Protocol Bootloader (SCPBL)
On devices that support SCPBL, communication between a host system and the device uses a system of ECDSA-256
digitally signed packets. This guarantees the integrity and authenticity of all communication before executing
configuration commands and loading or verifying program memory. One or more serial interfaces are available for
communication. This also enables the assembly and programming of the customer's final product by third-party assembly
houses without the required cost and complexity of ensuring that the assembly house implements and maintains a secure
production facility. It also allows in-field software upgrades to deployed products, thus eliminating the costly need to
return a product to the manufacturer for any software changes. The serial interfaces available for SCPBL communication
are shown in Table 8. Following any reset or exit from certain low-power modes, the device tests the assigned stimulus
pin and, if active, begins an SCPBL session. The stimulus pin can be reassigned once an SCPBL session begins. The
host can disable the bootloader interface before deployment to prevent any changes to program memory.
See the Ordering Information table for availability.
Secure Boot
On devices that support SCPBL, the device performs a secure boot to confirm that the root of trust has not been
compromised. Following every reset and exit from certain low-power modes, the secure boot verifies the digital signature
of the program memory to confirm it has not been modified or corrupted, ensuring the trustworthiness of the application
software. Failure to verify the digital signature transitions the device to safe mode, which prevents execution of the
customer code. During the development phase, the bootloader can be reactivated and a new, trusted program memory
loaded.
Debug and Development Interface
The device provides an Arm Debug Access Port (DAP) that supports debugging during application development. The
DAP enables an external debugger to access the device. The DAP is a standard Arm CoreSight™ serial wire debug
(SWD) port and uses a two-pin serial interface (SWDCLK and SWDIO).
Coresight is a trademark of Arm Limited.
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Analog Devices | 64
MAX32672
High-Reliability, Tiny, Ultra-Low-Power
Arm Cortex-M4F Microcontroller
with 12-Bit, 1Msps ADC
Applications Information
Bypass Capacitor Recommendations
The proper use of bypass capacitors reduces noise generated by the IC into the ground plane. The Pin Descriptions table
indicates which pins should be connected to bypass capacitors and the appropriate ground plane.
It is recommended that one instance of a bypass capacitor should be connected to each pin/ball of the IC package. For
example, if the Pin Descriptions table shows four device pins associated with voltage supply A, a separate capacitor
should be connected to each pin for a total of four capacitors.
Place capacitors as close as possible to their corresponding device pins. When more than one value of capacitor is
recommended per pin, the capacitors should be placed in parallel starting with the lowest value capacitor closest to the
pin.
Bootloader Activation
The SCPBL can use the interfaces shown in Table 8.
Table 8. Bootloader Activation Summary
BOOTLOADER INTERFACE
PART NUMBERS
DEFAULT STIMULUS PIN
UART
MAX32672GTLBL
MAX32672GTNBL
UART0A_RX/UART0A_TX
P0.10 (Active Low)
On devices that support SCPBL, the SCPBL is activated following any reset or existing certain low-power modes if the
assigned stimulus pin is asserted. The design must ensure that the desired bootloader interface and stimulus pin is
accessible by the host or the SCPBL cannot be activated. A different stimulus pin can be assigned once an SCPBL
session has been started.
The RSTN signal must also be accessible by the host for initial synchronization with the SCPBL.
Single Supply Operation
ACTIVE Mode
Table 9. Fixed VDD Current Consumption ACTIVE Mode, IPO, Single Supply
PARAMETER
VDD Current,
ACTIVE
Mode
www.analog.com
SYMBOL
IDD_FACTS
TYPICAL
CONDITIONS
Fixed, IPO enabled, total current into
VDD pin, VDD = 3.3V, CPU in
ACTIVE mode 0MHz execution, ECC
disabled, inputs tied to VSS or VDD,
outputs source/sink 0mA
-40°C
+25°C
+55°C
+85°C
+105°C
OVR =
[10],
internal
regulator
set to
1.1V
700
890
1260
1930
2770
OVR =
[01],
internal
regulator
set to
1.0V
580
730
1020
1560
2260
OVR =
[00],
internal
regulator
set to
0.9V
500
620
850
1280
1860
UNITS
μA
Analog Devices | 65
MAX32672
High-Reliability, Tiny, Ultra-Low-Power
Arm Cortex-M4F Microcontroller
with 12-Bit, 1Msps ADC
Table 9. Fixed VDD Current Consumption ACTIVE Mode, IPO, Single Supply
(continued)
PARAMETER
SYMBOL
TYPICAL
CONDITIONS
Fixed, IPO enabled, total current into
VDD pin, VDD = 1.8V, CPU in
ACTIVE mode 0MHz execution, ECC
disabled, inputs tied to VSS or VDD,
outputs source/sink 0mA
-40°C
+25°C
+55°C
+85°C
+105°C
OVR =
[10],
internal
regulator
set to
1.1V
670
860
1230
1890
2870
OVR =
[01],
internal
regulator
set to
1.0V
560
710
1000
1530
2210
OVR =
[00],
internal
regulator
set to
0.9V
480
590
820
1250
1820
UNITS
SLEEP Mode
Table 10. Fixed VDD Current Consumption SLEEP Mode, IPO, Single Supply
PARAMETER
VDD Current,
SLEEP Mode
SYMBOL
Fixed, IPO enabled, total current into
VDD pin, VDD = 3.3V, CPU in SLEEP
mode, ECC disabled, inputs tied to
VSS or VDD, outputs source/sink
0mA
IDD_FSLPS
Fixed, IPO enabled, total current into
VDD pin, VDD = 1.8V, CPU in SLEEP
mode, ECC disabled, inputs tied to
VSS or VDD, outputs source/sink
0mA
www.analog.com
TYPICAL
CONDITIONS
-40°C
+25°C
+55°C
+85°C
+105°C
OVR =
[10],
internal
regulator
set to
1.1V
700
890
1260
1930
2770
OVR =
[01],
internal
regulator
set to
1.0V
580
730
1020
1560
2260
OVR =
[00],
internal
regulator
set to
0.9V
500
620
850
1280
1860
OVR =
[10],
internal
regulator
set to
1.1V
670
860
1230
1890
2870
UNITS
μA
Analog Devices | 66
MAX32672
High-Reliability, Tiny, Ultra-Low-Power
Arm Cortex-M4F Microcontroller
with 12-Bit, 1Msps ADC
Table 10. Fixed VDD Current Consumption SLEEP Mode, IPO, Single Supply
(continued)
PARAMETER
SYMBOL
TYPICAL
CONDITIONS
-40°C
+25°C
+55°C
+85°C
+105°C
OVR =
[01],
internal
regulator
set to
1.0V
560
710
1000
1530
2210
OVR =
[00],
internal
regulator
set to
0.9V
480
590
820
1250
1820
UNITS
ACTIVE Mode
Table 11. Fixed VDD Current Consumption ACTIVE Mode, IBRO, Single Supply
PARAMETER
SYMBOL
Fixed, IBRO enabled, total current
into VDD pin, VDD = 3.3V, CPU in
ACTIVE mode 0MHz execution, ECC
disabled, inputs tied to VSS or VDD,
outputs source/sink 0mA
VDD Current,
ACTIVE
Mode
IDD_FACTS
Fixed, IBRO enabled, total current
into VDD pin, VDD = 1.8V, CPU in
ACTIVE mode 0MHz execution, ECC
disabled, inputs tied to VSS or VDD,
outputs source/sink 0mA
www.analog.com
TYPICAL
CONDITIONS
-40°C
+25°C
+55°C
+85°C
+105°C
OVR =
[10],
internal
regulator
set to
1.1V
170
450
800
1450
2280
OVR =
[01],
internal
regulator
set to
1.0V
260
390
660
1180
1870
OVR =
[00],
internal
regulator
set to
0.9V
240
340
550
980
1540
OVR =
[10],
internal
regulator
set to
1.1V
240
410
760
1400
2220
OVR =
[01],
internal
regulator
set to
1.0V
230
350
620
1140
1810
UNITS
μA
Analog Devices | 67
MAX32672
High-Reliability, Tiny, Ultra-Low-Power
Arm Cortex-M4F Microcontroller
with 12-Bit, 1Msps ADC
Table 11. Fixed VDD Current Consumption ACTIVE Mode, IBRO, Single Supply
(continued)
PARAMETER
SYMBOL
TYPICAL
CONDITIONS
OVR =
[00],
internal
regulator
set to
0.9V
-40°C
+25°C
+55°C
+85°C
+105°C
210
310
520
940
1490
UNITS
SLEEP Mode
Table 12. Fixed VDD Current Consumption SLEEP Mode, IBRO, Single Supply
PARAMETER
SYMBOL
Fixed, IBRO enabled, total current
into VDD pin, VDD = 3.3V, CPU in
SLEEP mode, ECC disabled, inputs
tied to VSS or VDD, outputs source/
sink 0mA
VDD Current,
SLEEP Mode
IDD_FSLPS
Fixed, IBRO enabled, total current
into VDD pin, VDD = 1.8V, CPU in
SLEEP mode, inputs tied to VSS or
VDD, outputs source/sink 0mA
www.analog.com
TYPICAL
CONDITIONS
-40°C
+25°C
+55°C
+85°C
+105°C
OVR =
[10],
internal
regulator
set to
1.1V
270
450
800
1450
2280
OVR =
[01],
internal
regulator
set to
1.0V
260
390
660
1180
1870
OVR =
[00],
internal
regulator
set to
0.9V
240
340
550
980
1540
OVR =
[10],
internal
regulator
set to
1.1V
240
410
760
1400
2220
OVR =
[01],
internal
regulator
set to
1.0V
230
350
620
1140
1810
OVR =
[00],
internal
regulator
set to
0.9V
210
310
520
940
1490
UNITS
μA
Analog Devices | 68
MAX32672
High-Reliability, Tiny, Ultra-Low-Power
Arm Cortex-M4F Microcontroller
with 12-Bit, 1Msps ADC
DEEPSLEEP Mode
Table 13. Fixed VDD Current Consumption DEEPSLEEP Mode, Single Supply
PARAMETER
VDD Fixed Current,
DEEPSLEEP Mode
SYMBOL
IDD_FDSLS
TYPICAL
CONDITIONS
-40°C
+25°C
+55°C
+85°C
105°C
5.3
16.2
43.9
89
Standby state with full data
retention and 200KB SRAM
retained
VDD
=
3.3V
2
Standby state with full data
retention and 200KB SRAM
retained
VDD
=
1.8V
1.8
UNITS
μA
5
15.7
43.3
87.9
BACKUP Mode
Table 14. Fixed VDD Current Consumption BACKUP Mode, Single Supply
PARAMETER
SYMBOL
CONDITIONS
VDD = 3.3V,
RTC disabled
VDD Fixed Current,
BACKUP Mode
IDD_FBKUS
VDD = 1.8V,
RTC disabled
TYPICAL
-40°C
+25°C
+55°C
+85°C
+105°C
0KB SRAM retained,
retention regulator
disabled
0.3
0.35
0.75
1.7
3.2
20KB SRAM retained
0.65
1.14
2.7
6.7
13.2
40KB SRAM retained
0.8
1.6
4.1
10.5
21
120KB SRAM retained
1.2
2.7
7.3
19.2
38.7
200KB SRAM retained
1.6
3.8
10.5
27.9
56.4
0KB SRAM retained,
retention regulator
disabled
0.06
0.09
0.33
0.96
2.2
20KB SRAM retained
0.5
0.9
2.3
6
12.2
40KB SRAM retained
0.65
1.3
3.7
9.8
19.9
120KB SRAM retained
1
2.4
6.9
18.4
37.4
200KB SRAM retained
1.5
3.5
10.1
26.9
54.7
UNITS
μA
STORAGE Mode
Table 15. Fixed VDD Current Consumption STORAGE Mode, Single Supply
PARAMETER
VDD Fixed Current, STORAGE Mode
SYMBOL
IDD_FSTOS
CONDITIONS
TYPICAL
-40°C
+25°C
+55°C
+85°C
105°C
VDD = 3.3V
0.27
0.4
0.74
1.6
3.2
VDD = 1.8V
0.06
0.09
0.34
0.97
2.2
UNITS
μA
Dual Supply Operation
www.analog.com
Analog Devices | 69
MAX32672
High-Reliability, Tiny, Ultra-Low-Power
Arm Cortex-M4F Microcontroller
with 12-Bit, 1Msps ADC
ACTIVE Mode
Table 16. Fixed VCORE Current Consumption ACTIVE Mode, IPO, Dual Supply
PARAMETER
VCORE Fixed
Current,
ACTIVE
Mode
SYMBOL
TYPICAL
CONDITIONS
ICORE_FACTD
Fixed, IPO enabled, total current
into VCORE pin, CPU in ACTIVE
mode 0MHz execution, ECC
disabled, inputs tied to VSS or VDD,
outputs source/sink 0mA
-40°C
+25°C
+55°C
+85°C
+105°C
OVR =
[10],
VCORE
set to
1.1V
240
420
750
1370
2170
OVR =
[01],
VCORE
set to
1.0V
120
260
510
1010
1660
OVR =
[00],
VCORE
set to
0.9V
44
140
300
670
1150
UNITS
μA
ACTIVE Mode
Table 17. Fixed VDD Current Consumption ACTIVE Mode, IPO, Dual Supply
PARAMETER
SYMBOL
Fixed, IPO enabled, total current into
VDD pin, VDD = 3.3V, CPU in ACTIVE
mode 0MHz execution, ECC disabled,
inputs tied to VSS or VDD, outputs
source/sink 0mA
VDD Current,
ACTIVE
Mode
IDD_FACTD
Fixed, IPO enabled, total current into
VDD pin, VDD = 1.8V, CPU in ACTIVE
mode 0MHz execution, ECC disabled,
inputs tied to VSS or VDD, outputs
source/sink 0mA
www.analog.com
TYPICAL
CONDITIONS
-40°C
+25°C
+55°C
+85°C
+105°C
OVR =
[10],
VCORE
= 1.1V
400
430
450
480
510
OVR =
[01],
VCORE
= 1.0V
400
430
450
480
510
OVR =
[00],
VCORE
= 0.9V
400
430
450
480
510
OVR =
[10],
VCORE
= 1.1V
380
410
430
460
490
OVR =
[01],
VCORE
= 1.0V
380
410
430
460
490
OVR =
[00],
VCORE
= 0.9V
380
410
430
460
490
UNITS
μA
Analog Devices | 70
MAX32672
High-Reliability, Tiny, Ultra-Low-Power
Arm Cortex-M4F Microcontroller
with 12-Bit, 1Msps ADC
SLEEP Mode
Table 18. Fixed VCORE Current Consumption SLEEP Mode, IPO, Dual Supply
PARAMETER
VCORE
Current,
SLEEP Mode
SYMBOL
TYPICAL
CONDITIONS
ICORE_FSLPD
Fixed, IPO enabled, total current
into VCORE pin, CPU in SLEEP
mode, ECC disabled, inputs tied to
VSS or VDD, outputs source/sink
0mA
-40°C
+25°C
+55°C
+85°C
+105°C
OVR =
[10],
VCORE
= 1.1V
240
420
750
1370
2170
OVR =
[01],
VCORE
= 1.0V
120
260
510
1010
1660
OVR =
[00],
VCORE
= 0.9V
44
140
300
670
1150
UNITS
μA
SLEEP Mode
Table 19. Fixed VDD Current Consumption SLEEP Mode, IPO, Dual Supply
PARAMETER
SYMBOL
Fixed, IPO enabled, total current into
VDD pin, VDD = 3.3V, CPU in SLEEP
mode, ECC disabled, inputs tied to
VSS or VDD, outputs source/sink 0mA
VDD Current,
SLEEP Mode
IDD_FSLPD
Fixed, IPO enabled, total current into
VDD pin, VDD = 1.8V, CPU in SLEEP
mode, ECC disabled, inputs tied to
VSS or VDD, outputs source/sink 0mA
www.analog.com
TYPICAL
CONDITIONS
-40°C
+25°C
+55°C
+85°C
+105°C
OVR =
[10],
VCORE
= 1.1V
400
430
450
480
510
OVR =
[01],
VCORE
= 1.0V
400
430
450
480
510
OVR =
[00],
VCORE
= 0.9V
400
430
450
480
510
OVR =
[10],
VCORE
= 1.1V
380
410
430
460
490
OVR =
[01],
VCORE
= 1.0V
380
410
430
460
490
OVR =
[00],
VCORE
= 0.9V
380
410
430
460
490
UNITS
μA
Analog Devices | 71
MAX32672
High-Reliability, Tiny, Ultra-Low-Power
Arm Cortex-M4F Microcontroller
with 12-Bit, 1Msps ADC
ACTIVE Mode
Table 20. Fixed VCORE Current Consumption ACTIVE Mode, IBRO, Dual Supply
PARAMETER
VCORE
Current,
ACTIVE
Mode
SYMBOL
TYPICAL
CONDITIONS
ICORE_FACTD
Fixed, IBRO enabled, total current
into VCORE pin, CPU in ACTIVE
mode 0MHz execution, ECC
disabled, inputs tied to VSS or VDD,
outputs source/sink 0mA
-40°C
+25°C
+55°C
+85°C
+105°C
OVR =
[10],
VCORE
= 1.1V
60
240
570
1210
1910
OVR =
[01],
VCORE
= 1.0V
40
180
430
940
1600
OVR =
[00],
VCORE
= 0.9V
30
120
290
660
1150
UNITS
μA
ACTIVE Mode
Table 21. Fixed VDD Current Consumption ACTIVE Mode, IBRO, Dual Supply
PARAMETER
SYMBOL
Fixed, IBRO enabled, total current into
VDD pin, VDD = 3.3V, CPU in ACTIVE
mode 0MHz execution, ECC disabled,
inputs tied to VSS or VDD, outputs
source/sink 0mA
VDD Current,
ACTIVE
Mode
IDD_FACTD
Fixed, IBRO enabled, total current into
VDD pin, VDD = 1.8V, CPU in ACTIVE
mode 0MHz execution, ECC disabled,
inputs tied to VSS or VDD, outputs
source/sink 0mA
www.analog.com
TYPICAL
CONDITIONS
-40°C
+25°C
+55°C
+85°C
+105°C
OVR =
[10],
VCORE
= 1.1V
155
165
175
190
210
OVR =
[01],
VCORE
= 1.0V
155
165
175
190
210
OVR =
[00],
VCORE
= 0.9V
155
165
175
190
210
OVR =
[10],
VCORE
= 1.1V
128
136
144
158
179
OVR =
[01],
VCORE
= 1.0V
128
136
144
158
179
OVR =
[00],
VCORE
= 0.9V
128
136
144
158
179
UNITS
μA
Analog Devices | 72
MAX32672
High-Reliability, Tiny, Ultra-Low-Power
Arm Cortex-M4F Microcontroller
with 12-Bit, 1Msps ADC
SLEEP Mode
Table 22. Fixed VCORE Current Consumption SLEEP Mode, IBRO, Dual Supply
PARAMETER
VCORE
Current,
SLEEP Mode
SYMBOL
TYPICAL
CONDITIONS
ICORE_FSLPD
Fixed, IBRO enabled, total current
into VCORE pin, CPU in SLEEP
mode, ECC disabled, inputs tied to
VSS or VDD, outputs source/sink
0mA
-40°C
+25°C
+55°C
+85°C
+105°C
OVR =
[10],
VCORE
= 1.1V
60
240
570
1210
1910
OVR =
[01],
VCORE
= 1.0V
40
180
430
940
1600
OVR =
[00],
VCORE
= 0.9V
30
120
290
660
1150
UNITS
μA
SLEEP Mode
Table 23. Fixed VDD Current Consumption SLEEP Mode, IBRO, Dual Supply
PARAMETER
SYMBOL
Fixed, IBRO enabled, total current into
VDD pin, VDD = 3.3V, CPU in SLEEP
mode, ECC disabled, inputs tied to
VSS or VDD, outputs source/sink 0mA
VDD Current,
SLEEP Mode
IDD_FSLPD
Fixed, IBRO enabled, total current into
VDD pin, VDD = 1.8V, CPU in SLEEP
mode, ECC disabled, inputs tied to
VSS or VDD, outputs source/sink 0mA
www.analog.com
TYPICAL
CONDITIONS
-40°C
+25°C
+55°C
+85°C
+105°C
OVR =
[10],
VCORE
= 1.1V
155
165
175
190
210
OVR =
[01],
VCORE
= 1.0V
155
165
175
190
210
OVR =
[00],
VCORE
= 0.9V
155
165
175
190
210
OVR =
[10],
VCORE
= 1.1V
128
136
144
158
179
OVR =
[01],
VCORE
= 1.0V
128
136
144
158
179
OVR =
[00],
VCORE
= 0.9V
128
136
144
158
179
UNITS
μA
Analog Devices | 73
MAX32672
High-Reliability, Tiny, Ultra-Low-Power
Arm Cortex-M4F Microcontroller
with 12-Bit, 1Msps ADC
DEEPSLEEP Mode
Table 24. Fixed VCORE Current Consumption DEEPSLEEP Mode, Dual Supply
PARAMETER
VCORE Fixed Current,
DEEPSLEEP Mode
SYMBOL
CONDITIONS
ICORE_FDSLD
TYPICAL
-40°C
+25°C
+55°C
+85°C
105°C
VDD = 3.3V, VCORE =
1.1V
5.8
12.2
29
68
126
VDD = 3.3V, VCORE =
0.855V
1.5
4.6
14.7
40
79.5
VDD = 1.8V, VCORE =
1.1V
5.8
12.2
29
68
126
VDD = 1.8V, VCORE =
0.855V
1.5
4.6
14.7
40
79.5
UNITS
μA
DEEPSLEEP Mode
Table 25. Fixed VDD Current Consumption DEEPSLEEP Mode, Dual Supply
PARAMETER
VDD Fixed Current, DEEPSLEEP
Mode
SYMBOL
CONDITIONS
IDD_FDSLD
TYPICAL
-40°C
+25°C
+55°C
+85°C
105°C
VDD = 3.3V, VCORE = 1.1V
0.34
0.4
0.77
1.66
3.2
VDD = 3.3V, VCORE =
0.855V
0.34
0.4
0.77
1.66
3.2
VDD = 1.8V, VCORE = 1.1V
0.14
0.15
0.33
0.96
2.2
VDD = 1.8V, VCORE =
0.855V
0.14
0.15
0.33
0.96
2.2
UNITS
μA
BACKUP Mode
Table 26. Fixed VCORE Current Consumption BACKUP Mode, Dual Supply
PARAMETER
SYMBOL
0KB SRAM retained with
RTC disabled, retention
regulator disabled
Fixed VCORE
Current,
BACKUP Mode
ICORE_FBKUD
20KB SRAM retained with
RTC disabled
www.analog.com
TYPICAL
CONDITIONS
-40°C
+25°C
+55°C
+85°C
+105°C
VDD = 3.3V,
VCORE =
1.1V
0.22
0.3
1.1
3.5
7.8
VDD = 3.3V,
VCORE =
0.855V
0.03
0.14
0.78
2.7
6.2
VDD = 1.8V,
VCORE =
1.1V
0.22
0.3
1.1
3.5
7.8
VDD = 1.8V,
VCORE =
0.855V
0.03
0.14
0.78
2.7
6.2
VDD = 3.3V,
VCORE =
1.1V
0.65
1.4
3.7
9.4
18.6
VDD = 3.3V,
VCORE =
0.855V
0.15
0.55
2.1
6.2
13
VDD = 1.8V,
VCORE =
1.1V
0.65
1.4
3.7
9.4
18.6
UNITS
μA
Analog Devices | 74
MAX32672
High-Reliability, Tiny, Ultra-Low-Power
Arm Cortex-M4F Microcontroller
with 12-Bit, 1Msps ADC
Table 26. Fixed VCORE Current Consumption BACKUP Mode, Dual Supply
(continued)
PARAMETER
SYMBOL
TYPICAL
CONDITIONS
40KB SRAM retained with
RTC disabled
120KB SRAM retained with
RTC disabled
200KB SRAM retained with
RTC disabled
-40°C
+25°C
+55°C
+85°C
+105°C
VDD = 1.8V,
VCORE =
0.855V
0.15
0.55
2.1
6.2
13
VDD = 3.3V,
VCORE =
1.1V
1.1
2.35
6.2
15.3
29.4
VDD = 3.3V,
VCORE =
0.855V
0.3
0.95
3.4
9.6
19.8
VDD = 1.8V,
VCORE =
1.8V
1.1
2.35
6.2
15.3
29.4
VDD = 1.8V,
VCORE =
0.855V
0.3
0.95
3.4
9.6
19.8
VDD = 3.3V,
VCORE =
1.1V
2.9
5.5
12.5
28.9
54
VDD = 3.3V,
VCORE =
0.855V
0.69
2
6.3
17.5
35.4
VDD = 1.8V,
VCORE =
1.1V
2.9
5.5
12.5
28.9
54
VDD = 1.8V,
VCORE =
0.855V
0.69
2
6.3
17.5
35.4
VDD = 3.3V,
VCORE =
1.1V
4.6
8.6
18.8
42.4
79
VDD = 3.3V,
VCORE =
0.855V
1.1
3.1
9.3
25.3
51
VDD = 1.8V,
VCORE =
1.1V
4.6
8.6
18.8
42.4
79
VDD = 1.8V,
VCORE =
0.855V
1.1
3.1
9.3
25.3
51
UNITS
BACKUP Mode
Table 27. Fixed VDD Current Consumption BACKUP Mode, Dual Supply
PARAMETER
SYMBOL
Fixed VDD
Current,
BACKUP Mode
IDD_FBKUD
www.analog.com
TYPICAL
CONDITIONS
0KB SRAM retained with RTC
disabled, retention regulator
disabled
VDD = 3.3V,
VCORE =
1.1V
-40°C
+25°C
+55°C
+85°C
+105°C
0.32
0.4
0.76
1.7
3.2
UNITS
μA
Analog Devices | 75
MAX32672
High-Reliability, Tiny, Ultra-Low-Power
Arm Cortex-M4F Microcontroller
with 12-Bit, 1Msps ADC
Table 27. Fixed VDD Current Consumption BACKUP Mode, Dual Supply (continued)
PARAMETER
SYMBOL
20KB SRAM retained with RTC
disabled
40KB SRAM retained with RTC
disabled
120KB SRAM retained with
RTC disabled
200KB SRAM retained with
RTC disabled
www.analog.com
TYPICAL
CONDITIONS
-40°C
+25°C
+55°C
+85°C
+105°C
VDD = 3.3V,
VCORE =
0.855V
0.32
0.4
0.76
1.7
3.2
VDD = 1.8V,
VCORE =
1.1V
0.14
0.16
0.34
0.97
2.2
VDD = 1.8V,
VCORE =
0.855V
0.14
0.16
0.34
0.97
2.2
VDD = 3.3V,
VCORE =
1.1V
0.32
0.4
0.76
1.7
3.2
VDD = 3.3V,
VCORE =
0.855V
0.32
0.4
0.76
1.7
3.2
VDD = 1.8V,
VCORE =
1.1V
0.14
0.16
0.34
0.97
2.2
VDD = 1.8V,
VCORE =
0.855V
0.14
0.16
0.34
0.97
2.2
VDD = 3.3V,
VCORE =
1.1V
0.32
0.4
0.76
1.7
3.2
VDD = 3.3V,
VCORE =
0.855V
0.32
0.4
0.76
1.7
3.2
VDD = 1.8V,
VCORE =
1.8V
0.14
0.16
0.34
0.97
2.2
VDD = 1.8V,
VCORE =
0.855V
0.14
0.16
0.34
0.97
2.2
VDD = 3.3V,
VCORE =
1.1V
0.32
0.4
0.76
1.7
3.2
VDD = 3.3V,
VCORE =
0.855V
0.32
0.4
0.76
1.7
3.2
VDD = 1.8V,
VCORE =
1.1V
0.14
0.16
0.34
0.97
2.2
VDD = 1.8V,
VCORE =
0.855V
0.14
0.16
0.34
0.97
2.2
VDD = 3.3V,
VCORE =
1.1V
0.32
0.4
0.76
1.7
3.2
UNITS
Analog Devices | 76
MAX32672
High-Reliability, Tiny, Ultra-Low-Power
Arm Cortex-M4F Microcontroller
with 12-Bit, 1Msps ADC
Table 27. Fixed VDD Current Consumption BACKUP Mode, Dual Supply (continued)
PARAMETER
SYMBOL
TYPICAL
CONDITIONS
-40°C
+25°C
+55°C
+85°C
+105°C
VDD = 3.3V,
VCORE =
0.855V
0.32
0.4
0.76
1.7
3.2
VDD = 1.8V,
VCORE =
1.1V
0.14
0.16
0.34
0.97
2.2
VDD = 1.8V,
VCORE =
0.855V
0.14
0.16
0.34
0.97
2.2
UNITS
STORAGE Mode
Table 28. Fixed VCORE Current Consumption STORAGE Mode, Dual Supply
PARAMETER
VCORE Fixed Current, STORAGE
Mode
SYMBOL
IDD_FSTOD
CONDITIONS
TYPICAL
-40°C
+25°C
+55°C
+85°C
105°C
VDD = 3.3V, VCORE =
1.1V
0.21
0.29
1.1
3.5
7.8
VDD = 3.3V, VCORE =
0.855V
0.03
0.15
0.78
2.7
6.2
VDD = 1.8V, VCORE =
1.1V
0.21
0.29
1.1
3.5
7.8
VDD = 1.8V, VCORE =
0.855V
0.03
0.15
0.78
2.7
6.2
UNITS
μA
STORAGE Mode
Table 29. Fixed VDD Current Consumption STORAGE Mode, Dual Supply
PARAMETER
VDD Fixed Current, STORAGE
Mode
www.analog.com
SYMBOL
IDD_FSTOD
CONDITIONS
TYPICAL
-40°C
+25°C
+55°C
+85°C
105°C
VDD = 3.3V, VCORE = 1.1V
0.3
0.4
0.74
1.6
3.2
VDD = 1.8V, VCORE =
0.855V
0.3
0.4
0.74
1.6
3.2
VDD = 3.3V, VCORE = 1.1V
0.15
0.16
0.34
0.97
2.2
VDD = 1.8V, VCORE =
0.855V
0.15
0.16
0.34
0.97
2.2
UNITS
μA
Analog Devices | 77
MAX32672
High-Reliability, Tiny, Ultra-Low-Power
Arm Cortex-M4F Microcontroller
with 12-Bit, 1Msps ADC
Ordering Information
PART NUMBER
TMR LPTMR
I2C SPI
UART
LPUART
CMP
ADC
INPUTS
SCPBL
GPIO
PACKAGE
MAX32672GTL+
3
2
3
2
3
1
2
12
N
28
40 TQFN-EP
5mm x 5mm
0.4mm pitch
MAX32672GTL+T
3
2
3
2
3
1
2
12
N
28
40 TQFN-EP
5mm x 5mm
0.4mm pitch
MAX32672GTLBL+
3
2
3
2
3
1
2
12
Y
28
40 TQFN-EP
5mm x 5mm
0.4mm pitch
MAX32672GTLBL+T
3
2
3
2
3
1
2
12
Y
28
40 TQFN-EP
5mm x 5mm
0.4mm pitch
MAX32672GTNBL+
3
2
3
3
3
1
2
12
Y
42
56 TQFN-EP
7mm x 7mm
0.4mm pitch
MAX32672GTNBL+T
3
2
3
3
3
1
2
12
Y
42
56 TQFN-EP
7mm x 7mm
0.4mm pitch
All packages contain Quadrature Decoder (QDEC), 12-Channel DMA, I2S, SWD, 1024KB Flash with ECC, 160KB SRAM with ECC.
TMR = Timer; LPTMR = Low-Power Timer; LPUART = Low-Power UART; CMP = Comparator; SCPBL = Secure Communications
Protocol Bootloader
+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel. Full reel.
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Analog Devices | 78
MAX32672
High-Reliability, Tiny, Ultra-Low-Power
Arm Cortex-M4F Microcontroller
with 12-Bit, 1Msps ADC
Revision History
REVISION
NUMBER
REVISION
DATE
0
8/21
Release for Market Intro
1/22
Updated the General Description, Benefits and Features, and Simplified Block
Diagram. Added Continuous Package Power Dissipation and Package Information
for the 56 TQFN-EP. Added Pin Configurations and Pin Descriptions for the 56
TQFN-EP. Updated the Clocking Scheme. Updated the Secure Communications
Protocol Bootloader (SCPBL) section. Updated Bootloader Activation Table 5.
Added the 56 TQFN part numbers to the Ordering Information.
5/23
Updated Benefits and Features, Simplified Block Diagram, Absolute Maximum
Ratings, Electrical Characteristics, Pin Configuration, Pin Descriptions, Detailed
Description, Applications Information, Ordering Information
1
2
DESCRIPTION
PAGES
CHANGED
—
1–2, 7, 47–52,
54, 61–62
1, 2, 8, 9–32, 34,
36, 37, 39, 45,
46, 50, 56–64,
65–77, 78
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