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MAX3375EEBL+T

MAX3375EEBL+T

  • 厂商:

    AD(亚德诺)

  • 封装:

    9-WFBGA,CSPBGA

  • 描述:

    IC POWER MANAGEMENT

  • 数据手册
  • 价格&库存
MAX3375EEBL+T 数据手册
MAX3372E–MAX3379E/ MAX3390E–MAX3393E ±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad Low-Voltage Level Translators in UCSP General Description The MAX3372E–MAX3379E and MAX3390E–MAX3393E ±15kV ESD-protected level translators provide the level shifting necessary to allow data transfer in a multivoltage system. Externally applied voltages, VCC and VL, set the logic levels on either side of the device. A low-voltage logic signal present on the VL side of the device appears as a high-voltage logic signal on the VCC side of the device, and vice-versa. The MAX3374E/MAX3375E/ MAX3376E/MAX3379E and MAX3390E–MAX3393E unidirectional level translators level shift data in one direction (VL → VCC or VCC → VL) on any single data line. The MAX3372E/MAX3373E and MAX3377E/MAX3378E bidirectional level translators utilize a transmission-gatebased design (Figure 2) to allow data translation in either direction (V L ↔ V CC ) on any single data line. The MAX3372E–MAX3379E and MAX3390E–MAX3393E accept VL from +1.2V to +5.5V and VCC from +1.65V to +5.5V, making them ideal for data transfer between lowvoltage ASICs/PLDs and higher voltage systems. All devices in the MAX3372E–MAX3379E, MAX3390E– MAX3393E family feature a three-state output mode that reduces supply current to less than 1µA, thermal shortcircuit protection, and ±15kV ESD protection on the VCC side for greater protection in applications that route signals externally. The MAX3372E/MAX3377E operate at a guaranteed data rate of 230kbps. Slew-rate limiting reduces EMI emissions in all 230kbps devices. The MAX3373E–MAX3376E/MAX3378E/MAX3379E and MAX3390E–MAX3393E operate at a guaranteed data rate of 8Mbps over the entire specified operating voltage range. Within specific voltage domains, higher data rates are possible. (See the Timing Characteristics table.) The MAX3372E–MAX3376E are dual level shifters available in 3 x 3 UCSP™, 8-pin TDFN, and 8-pin SOT23-8 packages. The MAX3377E/MAX3378E/ MAX3379E and MAX3390E–MAX3393E are quad level shifters available in 3 x 4 UCSP, 14-pin TDFN, and 14pin TSSOP packages. ________________________Applications MICROWIRE®, I2C SPI, and Level Translation Low-Voltage ASIC Level Translation Smart Card Readers Cell-Phone Cradles Portable POS Systems Portable Communication Devices Low-Cost Serial Interfaces Cell Phones GPS Telecommunications Equipment Features o Guaranteed Data Rate Options 230kbps 8Mbps (+1.2V ≤ VL ≤ VCC ≤ +5.5V) 10Mbps (+1.2V ≤ VL ≤ VCC ≤ +3.3V) 16Mbps (+1.8V ≤ VL ≤ VCC ≤ +2.5V and +2.5V ≤ VL ≤ VCC +3.3V) o Bidirectional Level Translation (MAX3372E/MAX3373E and MAX3377E/MAX3378E) o Operation Down to +1.2V on VL o ±15kV ESD Protection on I/O VCC Lines o Ultra-Low 1µA Supply Current in Three-State Output Mode o Low-Quiescent Current (130µA typ) o UCSP, TDFN, SOT23, and TSSOP Packages o Thermal Short-Circuit Protection Ordering Information PART TEMP RANGE PINPACKAGE MAX3372EEKA+T -40°C to +85°C 8 SOT23 +Denotes a lead-free package. T = Tape and reel. Ordering Information continued at end of data sheet. Selector Guide appears at end of data sheet. UCSP is a trademark of Maxim Integrated Products, Inc. MICROWIRE is a registered trademark of National Semiconductor Corp. Pin Configurations TOP VIEW + I/O VL1 1 14 VCC I/O VL2 2 13 I/0 VCC1 MAX3377E/ MAX3378E THREE-STATE 3 12 I/0 VCC2 N.C. 4 11 N.C. I/O VL3 5 10 VL I/O VL4 6 9 I/0 VCC3 GND 7 8 I/0 VCC4 TDFN-14 (3mm x 3mm) Pin Configurations continued at end of data sheet. For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com. 19-2328; Rev 3; 1/13 MAX3372E–MAX3379E/MAX3390E–MAX3393E ±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad Low-Voltage Level Translators in UCSP ABSOLUTE MAXIMUM RATINGS (All voltages referenced to GND.) VCC ...........................................................................-0.3V to +6V I/O VCC_......................................................-0.3V to (VCC + 0.3V) I/O VL_ ...........................................................-0.3V to (VL + 0.3V) THREE-STATE...............................................-0.3V to (VL + 0.3V) Short-Circuit Duration I/O VL, I/O VCC to GND...........Continuous Short-Circuit Duration I/O VL or I/O VCC to GND Driven from 40mA Source (except MAX3372E and MAX3377E) .....................Continuous Continuous Power Dissipation (TA = +70°C) 8-Pin SOT23 (derate 5.6mW/°C above +70°C)........444.4mW 8-Pin TDFN (derate 18.5mW/°C above +70°C) ........1482mW 3 x 3 UCSP (derate 4.7mW/°C above +70°C) ............379mW 3 x 4 UCSP (derate 6.5mW/°C above +70°C) ............520mW 14-Pin TSSOP (derate 9.1mW/°C above +70°C) ........727mW 14-Pin TDFN (derate 18.5mW/°C above +70°C) ......1482mW Operating Temperature Range ...........................-40°C to +85°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Soldering Temperature (reflow) .......................................+260°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VCC = +1.65V to +5.5V, VL = +1.2V to (VCC + 0.3V), GND = 0, I/O VL_ and I/O VCC_ unconnected, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VCC = +3.3V, VL = +1.8V, TA = +25°C.) (Notes 1, 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS POWER SUPPLIES VL Supply Range VCC Supply Range Supply Current from VCC Supply Current from VL VCC Three-State Output Mode Supply Current VL Three-State Output Mode Supply Current Three-State Output Mode Leakage Current I/O VL_ and I/O VCC_ VL 1.2 5.5 V VCC 1.65 5.50 V IQVCC 130 300 µA IQVL 16 100 µA ITHREE-STATE-VCC TA = +25°C, THREE-STATE = GND 0.03 1 µA ITHREE-STATE-VL TA = +25°C, THREE-STATE = GND 0.03 1 µA ITHREE-STATE-LKG TA = +25°C, THREE-STATE = GND 0.02 1 µA TA = +25°C 0.02 1 µA THREE-STATE Pin Input Leakage ESD PROTECTION IEC 1000-4-2 Air-Gap Discharge I/O VCC (Note 3) ±8 IEC 1000-4-2 Contact Discharge ±8 Human Body Model ±15 kV LOGIC-LEVEL THRESHOLDS (MAX3372E/MAX3377E) 2 I/O VL_ Input-Voltage High VIHL I/O VL_ Input-Voltage Low VILL VL - 0.2 V 0.15 V Maxim Integrated MAX3372E–MAX3379E/MAX3390E–MAX3393E ±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad Low-Voltage Level Translators in UCSP ELECTRICAL CHARACTERISTICS (continued) (VCC = +1.65V to +5.5V, VL = +1.2V to (VCC + 0.3V), GND = 0, I/O VL_ and I/O VCC_ unconnected, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VCC = +3.3V, VL = +1.8V, TA = +25°C.) (Notes 1, 2) PARAMETER SYMBOL CONDITIONS I/O VCC_ Input-Voltage High VIHC I/O VCC_ Input-Voltage Low VILC I/O VL_ Output-Voltage High VOHL I/O VL_ source current = 20µA, I/O VCC_ > VCC - 0.4V I/O VL_ Output-Voltage Low VOLL I/O VL_ sink current = 20µA, I/O VCC_ < 0.15V I/O VCC_ Output-Voltage High VOHC I/O VCC_ source current = 20µA, I/O VL _ > VL - 0.2V I/O VCC_ Output-Voltage Low VOLC I/O VCC_ sink current = 20µA, I/O VL_ < 0.15V THREE-STATE Input-Voltage High VIL-THREE-STATE THREE-STATE Input-Voltage Low VIL-THREE-STATE MIN TYP MAX UNITS 0.15 V VCC - 0.4 V 0.67 ✕ VL V 0.4 0.67 ✕ VCC V V 0.4 VL - 0.2 V V 0.15 V LOGIC-LEVEL THRESHOLDS (MAX3373E–MAX3376E/MAX3378E/MAX3379E and MAX3390E–MAX3393E) I/O VL_ Input-Voltage High VIHL I/O VL_ Input-Voltage Low VILL I/O VCC_ Input-Voltage High VIHC I/O VCC_ Input-Voltage Low VILC I/O VL_ Output-Voltage High VOHL I/O VL_ source current = 20µA, I/O VCC_ ≥ VCC - 0.4V I/O VL_ Output-Voltage Low VOLL I/O VL_ sink current = 1mA, I/O VCC_ ≤ 0.15V I/O VCC_ Output-Voltage High VOHC I/O VCC_ source current = 20µA, I/O VL_ ≥ VL - 0.2V I/O VCC_ Output-Voltage Low VOLC I/O VCC_ sink current = 1mA, I/O VL_ ≤ 0.15V THREE-STATE Input-Voltage High VIH-THREE-STATE THREE-STATE Input-Voltage Low VIL-THREE-STATE Maxim Integrated VL - 0.2 V 0.15 V 0.15 V VCC - 0.4 V 0.67 ✕ VL V 0.4 0.67 ✕ VCC V V 0.4 VL - 0.2 V V 0.15 V 3 MAX3372E–MAX3379E/MAX3390E–MAX3393E ±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad Low-Voltage Level Translators in UCSP TIMING CHARACTERISTICS (VCC = +1.65V to +5.5V, VL = +1.2V to (VCC + 0.3V), GND = 0, RLOAD = 1MΩ, I/O test signal of Figure 1, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VCC = +3.3V, VL = +1.8V, TA = +25°C, unless otherwise noted.) (Notes 1, 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS MAX3372E/MAX3377E (CLOAD = 50pF) I/O VCC_ Rise Time (Note 4) tRVCC 1100 I/O VCC_ Fall Time (Note 5) tFVCC 1000 ns I/O VL _ Rise Time (Note 4) tRVL 600 ns I/O VL _ Fall Time (Note 5) tFVL 1100 ns Propagation Delay Channel-to-Channel Skew ns I/OVL-VCC Driving I/O VL _ 1.6 I/OVCC-VL Driving I/O VCC_ 1.6 Each translator equally loaded 500 tSKEW Maximum Data Rate CL = 25pF 230 µs ns kbps MAX3373E–MAX3376E/MAX3378E/MAX3379E and MAX3390E–MAX3393E (CLOAD = 15pF, Driver Output Impedance ≤ 50Ω) +1.2V ≤ VL ≤ VCC ≤ +5.5V I/O VCC_ Rise Time (Note 4) tRVCC I/O VCC_ Fall Time (Note 5) tFVCC I/O VL _ Rise Time (Note 4) tRVL I/O VL _ Fall Time (Note 5) tLFV I/OVL-VCC 7 25 170 400 6 37 Open-drain driving 20 50 8 30 Open-drain driving 180 400 3 30 Open-drain driving 30 60 5 30 210 1000 4 30 190 1000 Open-drain driving Driving I/O VL _ Propagation Delay I/OVCC-VL Channel-to-Channel Skew Maximum Data Rate 4 tSKEW Driving I/O VCC_ Each translator equally loaded Open-drain driving Open-drain driving Open-drain driving 20 Open-drain driving 50 ns ns ns ns ns ns 8 Mbps 500 kbps Maxim Integrated MAX3372E–MAX3379E/MAX3390E–MAX3393E ±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad Low-Voltage Level Translators in UCSP TIMING CHARACTERISTICS (continued) (VCC = +1.65V to +5.5V, VL = +1.2V to (VCC + 0.3V), GND = 0, RLOAD = 1MΩ, I/O test signal of Figure 1, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VCC = +3.3V, VL = +1.8V, TA = +25°C, unless otherwise noted.) (Notes 1, 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS +1.2V ≤ VL ≤ VCC ≤ +3.3V I/O VCC_ Rise Time (Note 4) tRVCC 25 ns I/O VCC_ Fall Time (Note 5) tFVCC 30 ns I/O VL _ Rise Time (Note 4) tRVL 30 ns I/O VL _ Fall Time (Note 5) tFVL 30 ns Propagation Delay Channel-to-Channel Skew I/OVL-VCC Driving I/O VL _ 20 I/OVCC-VL Driving I/O VCC_ Each translator equally loaded 20 tSKEW Maximum Data Rate 10 10 ns ns Mbps +2.5V ≤ VL ≤ VCC ≤ +3.3V I/O VCC_ Rise Time (Note 4) tRVCC 15 ns I/O VCC_ Fall Time (Note 5) tFVCC 15 ns I/O VL _ Rise Time (Note 4) tRVL 15 ns I/O VL _ Fall Time (Note 5) tFVL 15 ns Propagation Delay Channel-to-Channel Skew I/OVL-VCC Driving I/O VL _ 15 I/OVCC-VL Driving I/O VCC_ 15 Each translator equally loaded 10 tSKEW Maximum Data Rate 16 ns ns Mbps +1.8V ≤ VL ≤ VCC ≤ +2.5V I/O VCC_ Rise Time (Note 4) tRVCC 15 ns I/O VCC_ Fall Time (Note 5) tFVCC 15 ns I/O VL _ Rise Time (Note 4) tRVL 15 ns I/O VL _ Fall Time (Note 5) tFVL 15 ns Propagation Delay Channel-to-Channel Skew Maximum Data Rate I/OVL-VCC Driving I/O VL _ 15 I/OVCC-VL Driving I/O VCC_ 15 Each translator equally loaded 10 tSKEW 16 ns ns Mbps Note 1: All units are 100% production tested at TA = +25°C. Limits over the operating temperature range are guaranteed by design and not production tested. Note 2: For normal operation, ensure VL < (VCC + 0.3V). During power-up, VL > (VCC + 0.3V) will not damage the device. Note 3: To ensure maximum ESD protection, place a 1µF capacitor between VCC and GND. See Applications Circuits. Note 4: 10% to 90% Note 5: 90% to 10% Maxim Integrated 5 MAX3372E–MAX3379E/MAX3390E–MAX3393E ±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad Low-Voltage Level Translators in UCSP Typical Operating Characteristics (RLOAD = 1MΩ, TA = +25°C, unless otherwise noted. All 230kbps TOCs apply to MAX3372E/MAX3377E only. All 8Mbps and 500kbps TOCs apply to MAX3373E–MAX3376E/MAX3378E/MAX3379E and MAX3390E–MAX3393E only.) VCC SUPPLY CURRENT vs. SUPPLY VOLTAGE (DRIVING I/O VL, VCC = +3.3V, VL = +1.8V) 300 500kbps, OPEN-DRAIN, CLOAD = 15pF 230kbps, CLOAD = 50pF 100 500kbps, OPEN-DRAIN, CLOAD = 15pF 2.5 2.0 8Mbps, CLOAD = 15pF 1.5 1.0 230kbps, CLOAD = 50pF 150 3.30 3.85 4.40 4.95 0 1.65 5.50 2.20 2.75 3.30 4.40 4.95 5.50 -40 350 300 SUPPLY CURRENT (μA) 1200 8Mbps, CLOAD = 15pF 1000 500kbps, OPEN-DRAIN, CLOAD = 15pF 600 8Mbps 250 200 150 500kbps, OPEN-DRAIN 100 230kbps, CLOAD = 50pF 0 35 85 60 25 40 55 70 85 16 DATA RATE = 230kbps tLH 10 8 tHL 6 4 500 40 50 70 100 85 tLH 200 150 DATA RATE = 500kbps, OPEN-DRAIN 100 tHL 50 DATA RATE = 8Mbps 0 0 30 55 2 tHL 0 20 40 250 RISE/FALL TIME (ns) RISE/FALL TIME (ns) 14 12 25 RISE/FALL TIME vs. CAPACITIVE LOAD (DRIVING I/O VL, VCC = +3.3V, VL = +1.8V) MAX3372E toc08 18 MAX3372E toc07 1000 10 CAPACITIVE LOAD (pF) RISE/FALL TIME vs. CAPACITIVE LOAD (DRIVING I/O VL, VCC = +3.3V, VL = +1.8V) tLH 230kbps 100 RISE/FALL TIME vs. CAPACITIVE LOAD (DRIVING I/O VL, VCC = +3.3V, VL = +1.8V) 1500 500kbps, OPEN-DRAIN 1000 0 10 CAPACITIVE LOAD (pF) 2000 8Mbps 1500 500 TEMPERATURE (°C) 2500 85 60 2000 0 10 35 2500 230kbps 50 200 -15 10 VCC SUPPLY CURRENT vs. CAPACITIVE LOAD (DRIVING I/O VL, VCC = +3.3V, VL = +1.8V) MAX3372E toc05 1400 -40 -15 TEMPERATURE (°C) VL SUPPLY CURRENT vs. CAPACITIVE LOAD (DRIVING I/O VL, VCC = +3.3V, VL = +1.8V) MAX3372E toc04 1600 400 3.85 VCC (V) VCC SUPPLY CURRENT vs. TEMPERATURE (DRIVING I/O VCC, VCC = +3.3V, VL = +1.8V) 800 230kbps, CLOAD = 50pF MAX3372E toc06 2.75 SUPPLY CURRENT (μA) 2.20 500kbps, OPEN-DRAIN, CLOAD = 15pF 200 50 VCC (V) SUPPLY CURRENT (μA) 8Mbps, CLOAD = 15pF 250 0 1.65 RISE/FALL TIME (ns) 300 100 0.5 0 60 70 80 CAPACITIVE LOAD (pF) 6 350 MAX3372E toc09 200 3.0 SUPPLY CURRENT (μA) 400 400 MAX3372E toc02 8Mbps, CLOAD = 15pF SUPPLY CURRENT (mA) SUPPLY CURRENT (μA) 500 3.5 MAX3372E toc01 600 VL SUPPLY CURRENT vs. TEMPERATURE (DRIVING I/O VCC, VCC = +3.3V, VL = +1.8V) MAX3372E toc03 VL SUPPLY CURRENT vs. SUPPLY VOLTAGE (DRIVING I/O VL, VCC = +3.3V, VL = +1.8V) 90 100 10 15 20 25 30 35 40 CAPACITIVE LOAD (pF) 45 50 10 15 20 25 30 35 40 45 50 CAPACITIVE LOAD (pF) Maxim Integrated MAX3372E–MAX3379E/MAX3390E–MAX3393E ±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad Low-Voltage Level Translators in UCSP Typical Operating Characteristics (continued) (RLOAD = 1MΩ, TA = +25°C, unless otherwise noted. All 230kbps TOCs apply to MAX3372E/MAX3377E only. All 8Mbps and 500kbps TOCs apply to MAX3373E–MAX3376E/MAX3378E/MAX3379E and MAX3390E–MAX3393E only.) tPHL 500 400 300 tPLH 200 DATA RATE = 230kbps tPHL 9 6 300 200 DATA RATE = 500kbps, OPEN-DRAIN 150 100 tPHL 50 tPLH 0 0 20 30 40 50 60 70 80 90 0 100 10 15 20 25 30 35 40 45 50 10 15 20 25 30 35 40 45 50 CAPACITIVE LOAD (pF) CAPACITIVE LOAD (pF) CAPACITIVE LOAD (pF) RISE/FALL TIME vs. CAPACITIVE LOAD (DRIVING I/O VL, VCC = +2.5V, VL = +1.8V) RISE/FALL TIME vs. CAPACITIVE LOAD (DRIVING I/O VL, VCC = +2.5V, VL = +1.8V) RISE/FALL TIME vs. CAPACITIVE LOAD (DRIVING I/O VCC, VCC = +2.5V, VL = +1.8V) 12 tLH 1500 1000 DATA RATE = 230kbps 10 tLH 8 6 tHL 4 300 tLH 250 RISE/FALL TIME (ns) RISE/FALL TIME (ns) 2000 DATA RATE = 8Mbps MAX3372E toc15 14 MAX3372E toc13 2500 200 DATA RATE = 500kbps, OPEN-DRAIN 150 100 tHL 500 50 2 tHL 0 0 0 20 30 40 50 60 70 80 90 100 10 15 20 25 30 35 40 45 10 50 15 20 25 30 35 40 45 50 CAPACITIVE LOAD (pF) CAPACITIVE LOAD (pF) CAPACITIVE LOAD (pF) RISE/FALL TIME vs. CAPACITIVE LOAD (DRIVING I/O VCC, VCC = +3.3V, VL = +1.8V) RISE/FALL TIME vs. CAPACITIVE LOAD (DRIVING I/O VCC, VCC = +3.3V, VL = +1.8V) RISE/FALL TIME vs. CAPACITIVE LOAD (DRIVING I/O VCC, VCC = +3.3V, VL = +1.8V) tHL 1000 8 tLH 6 250 RISE/FALL TIME (ns) 10 4 MAX3372E toc18 DATA RATE = 8Mbps RISE/FALL TIME (ns) 2000 300 MAX3372E toc17 DATA RATE = 230kbps 1500 12 MAX3372E toc16 2500 RISE/FALL TIME (ns) tPLH 250 3 MAX3372E toc12 12 100 RISE/FALL TIME (ns) MAX3372E toc11 DATA RATE = 8Mbps PROPAGATION DELAY vs. CAPACITIVE LOAD (DRIVING I/O VL, VCC = +3.3V, VL = +1.8V) MAX3372E toc14 PROPAGATION DELAY (ns) 600 15 PROPAGATION DELAY (ns) MAX3372E toc10 700 PROPAGATION DELAY vs. CAPACITIVE LOAD (DRIVING I/O VL, VCC = +3.3V, VL = +1.8V) PROPAGATION DELAY (ns) PROPAGATION DELAY vs. CAPACITIVE LOAD (DRIVING I/O VL, VCC = +3.3V, VL = +1.8V) tLH 200 DATA RATE = 500kbps, OPEN-DRAIN 150 100 tHL 500 tHL 2 tLH 0 20 30 40 50 60 0 0 70 80 CAPACITIVE LOAD (pF) Maxim Integrated 50 90 100 10 15 20 25 30 35 40 CAPACITIVE LOAD (pF) 45 50 10 15 20 25 30 35 40 45 50 CAPACITIVE LOAD (pF) 7 MAX3372E–MAX3379E/MAX3390E–MAX3393E ±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad Low-Voltage Level Translators in UCSP Typical Operating Characteristics (continued) (RLOAD = 1MΩ, TA = +25°C, unless otherwise noted. All 230kbps TOCs apply to MAX3372E/MAX3377E only. All 8Mbps and 500kbps TOCs apply to MAX3373E–MAX3376E/MAX3378E/MAX3379E and MAX3390E–MAX3393E only.) tPHL 400 300 200 100 tPHL 4 3 2 tPLH 300 250 30 40 50 60 70 80 90 10 100 200 DATA RATE = 500kbps, OPEN-DRAIN 150 100 tPHL 0 0 20 tPLH 50 1 tPHL 15 20 25 30 35 40 45 10 50 15 20 25 30 35 40 45 50 CAPACITIVE LOAD (pF) CAPACITIVE LOAD (pF) CAPACITIVE LOAD (pF) RISE/FALL TIME vs. CAPACITIVE LOAD (DRIVING I/O VCC, VCC = +2.5V, VL = +1.8V) RISE/FALL TIME vs. CAPACITIVE LOAD (DRIVING I/O VCC, VCC = +2.5V, VL = +1.8V) RISE/FALL TIME vs. CAPACITIVE LOAD (DRIVING I/O VCC, VCC = +2.5V, VL = +1.8V) tHL 1000 500 8 tLH 6 4 40 50 60 70 80 90 100 tLH 150 DATA RATE = 500kbps, OPEN-DRAIN tHL 50 0 30 200 100 tLH 20 250 tHL 2 0 300 RISE/FALl TIME (ns) 10 MAX3373E toc24 DATA RATE = 8Mbps RISE/FALL TIME (ns) 2000 350 MAX3372E toc23 DATA RATE = 230kbps 1500 12 MAX3372E toc22 2500 0 10 20 30 40 50 10 CAPACITIVE LOAD (pF) CAPACITIVE LOAD (pF) 20 30 40 MAX3372E toc26 RAIL-TO-RAIL DRIVING (DRIVING I/O VL, VCC = +3.3V, VL = +1.8V, CLOAD = 15pF, DATA RATE = 8Mbps) I/O VL_ 1V/div I/O VL_ 1V/div I/O VCC_ 2V/div I/O VCC_ 2V/div 1μs/div 50 CAPACITIVE LOAD (pF) MAX3372E toc25 RAIL-TO-RAIL DRIVING (DRIVING I/O VL, VCC = +3.3V, VL = +1.8V, CLOAD = 50pF, DATA RATE = 230kbps) 8 MAX3372E toc21 5 0 RISE/FALL TIME (ns) MAX3372E toc20 DATA RATE = 8Mbps PROPAGATION DELAY (ns) 500 6 PROPAGATION DELAY (ns) DATA RATE = 230kbps 600 PROPAGATION DELAY (ns) MAX3372E toc19 700 PROPAGATION DELAY vs. CAPACITIVE LOAD (DRIVING I/O VCC, VCC = +3.3V, VL = +1.8V) PROPAGATION DELAY vs. CAPACITIVE LOAD (DRIVING I/O VCC, VCC = +3.3V, VL = +1.8V) PROPAGATION DELAY vs. CAPACITIVE LOAD (DRIVING I/O VCC, VCC = +3.3V, VL = +1.8V) 200ns/div Maxim Integrated MAX3372E–MAX3379E/MAX3390E–MAX3393E ±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad Low-Voltage Level Translators in UCSP Typical Operating Characteristics (continued) (RLOAD = 1MΩ, TA = +25°C, unless otherwise noted. All 230kbps TOCs apply to MAX3372E/MAX3377E only. All 8Mbps and 500kbps TOCs apply to MAX3373E–MAX3376E/MAX3378E/MAX3379E and MAX3390E–MAX3393E only.) OPEN-DRAIN DRIVING (DRIVING I/O VL, VCC = +3.3V, VL = +1.8V, CLOAD = 15pF, DATA RATE = 500kbps) EXITING THREE-STATE OUTPUT MODE (VCC = +3.3V, VL = +1.8V, CLOAD = 50pF) MAX3372E toc27 MAX3372E toc28 2V/div I/O VCC_ I/O VL_ 1V/div 1V/div I/O VL_ I/O VCC_ 2V/div 1V/div THREE-STATE 2μs/div 200ns/div Pin Description PIN 3x4 UCSP 14 SOT23-8 TSSOP A1 2 A2 A3 3x3 UCSP 5 C2 3 4 4 — A4 5 — B1 14 B2 1 B3 8 TDFN- 14 TDFNEP EP NAME FUNCTION 6 1 I/O VL1 Input/Output 1. Referenced to VL. (Note 6) C3 8 2 I/O VL2 Input/Output 2. Referenced to VL. (Note 6) — — 5 I/O VL3 Input/Output 3. Referenced to VL. (Note 6) — — 6 I/O VL4 Input/Output 4. Referenced to VL. (Note 6) 7 A1 4 14 VCC VCC Input Voltage +1.65V ≤ VCC ≤ +5.5V. 3 C1 7 10 VL 8 6 B1 5 3 THREESTATE Logic Input Voltage +1.2V ≤ VL ≤ (VCC + 0.3V) Three-State Output Mode Enable. Pull THREE-STATE low to place device in three-state output mode. I/O VCC_ and I/O VL_ are high impedance in three-state output mode. Note: Logic referenced to VL (for logic thresholds see the Electrical Characteristics table). B4 7 2 B3 2 7 GND C1 13 8 A2 3 13 I/O VCC1 Ground Input/Output 1. Referenced to VCC. (Note 6) C2 12 1 A3 1 12 I/O VCC2 Input/Output 2. Referenced to VCC. (Note 6) C3 11 — — — 9 I/O VCC3 Input/Output 3. Referenced to VCC. (Note 6) C4 10 — — — 8 I/O VCC4 Input/Output 4. Referenced to VCC. (Note 6) — 6, 9 — B2 — 4, 11 N.C. — — — — — — EP No Connection. Not internally connected. Exposed Pad. Connect EP to ground. Note 6: For unidirectional devices (MAX3374E/MAX3375E/MAX3376E/MAX3379E and MAX3390E–MAX3393E) see the Pin Configurations for input/output configurations. Maxim Integrated 9 MAX3372E–MAX3379E/MAX3390E–MAX3393E ±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad Low-Voltage Level Translators in UCSP Detailed Description The MAX3372E–MAX3379E and MAX3390E–MAX3393E ESD-protected level translators provide the level shifting necessary to allow data transfer in a multivoltage system. Externally applied voltages, VCC and VL, set the logic levels on either side of the device. A low-voltage logic signal present on the VL side of the device appears as a highvoltage logic signal on the VCC side of the device, and vice-versa. The MAX3374E/MAX3375E/MAX3376E/ MAX3379E and MAX3390E–MAX3393E unidirectional level translators level shift data in one direction (VL → V CC or V CC → V L ) on any single data line. The MAX3372E/MAX3373E and MAX3377E/MAX3378E bidirectional level translators utilize a transmission-gatebased design (see Figure 2) to allow data translation in either direction (VL ↔ VCC) on any single data line. The MAX3372E–MAX3379E and MAX3390E–MAX3393E VL accept VL from +1.2V to +5.5V and VCC from +1.65V to +5.5V, making them ideal for data transfer between lowvoltage ASICs/PLDs and higher voltage systems. All devices in the MAX3372E–MAX3379E, MAX3390E– MAX3393E family feature a three-state output mode that reduces supply current to less than 1µA, thermal shortcircuit protection, and ±15kV ESD protection on the VCC side for greater protection in applications that route signals externally. The MAX3372E/MAX3377E operate at a guaranteed data rate of 230kbps. Slew-rate limiting reduces EMI emissions in all 230kbps devices. The MAX3373E–MAX3376E/MAX3378E/MAX3379E and MAX3390E–MAX3393E operate at a guaranteed data rate of 8Mbps over the entire specified operating voltage range. Within specific voltage domains, higher data rates are possible. (See the Timing Characteristics table.) VL VCC VL VCC VL VCC MAX3372E–MAX3379E AND MAX3390E–MAX3393E MAX3372E–MAX3379E AND MAX3390E–MAX3393E DATA DATA GND RLOAD I/O VL_ (tRISE, tFALL < 10ns) CLOAD CLOAD RLOAD GND I/O VCC_ (tRISE, tFALL < 10ns) tPD-VCC-LH tPD-VCC-HL tRVCC tFVCC I/O VCC_ tPD-VL-LH tPD-VL-HL tRVL tFVL I/O VL _ Figure 1a. Rail-to-Rail Driving I/O VL 10 I/O VCC_ I/O VL _ I/O VCC_ I/O VL _ VCC Figure 1b. Rail-to-Rail Driving I/O VCC Maxim Integrated MAX3372E–MAX3379E/MAX3390E–MAX3393E ±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad Low-Voltage Level Translators in UCSP Level Translation For proper operation ensure that +1.65V ≤ V CC ≤ +5.5V, +1.2V ≤ VL ≤ +5.5V, and VL ≤ (VCC + 0.3V). During power-up sequencing, VL ≥ (VCC + 0.3V) will not damage the device. During power-supply sequencing, when VCC is floating and VL is powering up, a current may be sourced, yet the device will not latch up. The speed-up circuitry limits the maximum data rate for devices in the MAX3372E–MAX3379E, MAX3390E– MAX3393E family to 16Mbps. The maximum data rate also depends heavily on the load capacitance (see the Typical Operating Characteristics), output impedance of the driver, and the operational voltage range (see the Timing Characteristics table). Speed-Up Circuitry The MAX3373E–MAX3376E/MAX3378E/MAX3379E and MAX3390E–MAX3393E feature a one-shot generator that decreases the rise time of the output. When triggered, MOSFETs PU1 and PU2 turn on for a short time to pull up VL I/O VL_ and I/O VCC_ to their respective supplies (see Figure 2b). This greatly reduces the rise time and propagation delay for the low-to-high transition. The scope photo of Rail-to-Rail Driving for 8Mbps Operation in the Typical Operating Characteristics shows the speed-up circuitry in operation. Rise-Time Accelerators The MAX3373E–MAX3376E/MAX3378E/MAX3379E and the MAX3390E–MAX3393E have internal rise-time accelerators allowing operation up to 16Mbps. The rise-time accelerators are present on both sides of the device and act to speed up the rise time of the input and output of the device, regardless of the direction of the data. The triggering mechanism for these accelerators is both level and edge sensitive. To prevent false triggering of the rise-time accelerators, signal fall times of less than 20ns/V are recommended for both the inputs and outputs of the device. Under less noisy conditions, longer signal fall times may be acceptable. VL VCC VL VCC VL VCC MAX3373E–MAX3376E, MAX3378E/MAX3379E AND MAX3390E–MAX3393E MAX3372E–MAX3379E AND MAX3390E–MAX3393E DATA DATA CLOAD GND I/O VCC_ I/O VL_ I/O VCC_ I/O VL_ VCC CLOAD GND RLOAD RLOAD I/O VCC_ I/O VL_ tPD-VCC-HL tPD-VL-LH tPD-VCC-LH tPD-VL-HL I/O VL_ I/O VCC_ tRVCC Figure 1c. Open-Drain Driving I/O VCC Maxim Integrated tFVCC tRVL tFVL Figure 1d. Open-Drain Driving I/O VL 11 MAX3372E–MAX3379E/MAX3390E–MAX3393E ±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad Low-Voltage Level Translators in UCSP Three-State Output Mode at I/O VL_ to exceed (VL + 0.3V), or the voltage at I/O VCC_ to exceed (VCC + 0.3V). Pull THREE-STATE low to place the MAX3372E– MAX3379E and MAX3390E–MAX3393E in three-state output mode. Connect THREE-STATE to VL (logic-high) for normal operation. Activating the three-state output mode disconnects the internal 10kΩ pullup resistors on the I/O VCC and I/O VL lines. This forces the I/O lines to a highimpedance state, and decreases the supply current to less than 1µA. The high-impedance I/O lines in threestate output mode allow for use in a multidrop network. When in three-state output mode, do not allow the voltage Thermal Short-Circuit Protection Thermal overload detection protects the MAX3372E– MAX3379E and MAX3390E–MAX3393E from short-circuit fault conditions. In the event of a short-circuit fault, when the junction temperature (TJ) reaches +152°C, a thermal sensor signals the three-state output mode logic to force the device into three-state output mode. When TJ has cooled to +142°C, normal operation resumes. VCC VL P P GATE BIAS I/O VL I/O VCC N Figure 2a. Functional Diagram, MAX3372E/MAX3377E (1 I/O line) VCC VL PU1 ONE-SHOT BLOCK ONE-SHOT BLOCK PU2 GATE BIAS I/O VL_ N I/O VCC_ Figure 2b. Functional Diagram, MAX3373E/MAX3378E (1 I/O line) 12 Maxim Integrated MAX3372E–MAX3379E/MAX3390E–MAX3393E ±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad Low-Voltage Level Translators in UCSP ±15kV ESD Protection As with all Maxim devices, ESD-protection structures are incorporated on all pins to protect against electrostatic discharges encountered during handling and assembly. The I/O VCC lines have extra protection against static electricity. Maxim’s engineers have developed state-ofthe-art structures to protect these pins against ESD of ±15kV without damage. The ESD structures withstand high ESD in all states: normal operation, three-state output mode, and powered down. After an ESD event, Maxim’s E versions keep working without latchup, whereas competing products can latch and must be powered down to remove latchup. ESD protection can be tested in various ways. The I/O VCC lines of this product family are characterized for protection to the following limits: 1) ±15kV using the Human Body Model 2) ±8kV using the Contact Discharge method specified in IEC 1000-4-2 3) ±10kV using IEC 1000-4-2’s Air-Gap Discharge method ESD Test Conditions ESD performance depends on a variety of conditions. Contact Maxim for a reliability report that documents test setup, test methodology, and test results. Human Body Model Figure 3a shows the Human Body Model and Figure 3b shows the current waveform it generates when discharged into a low impedance. This model consists of a 100pF capacitor charged to the ESD voltage of interest, which is then discharged into the test device through a 1.5kΩ resistor. RC 1MΩ CHARGE-CURRENTLIMIT RESISTOR IEC 1000-4-2 The IEC 1000-4-2 standard covers ESD testing and performance of finished equipment; it does not specifically refer to integrated circuits. The MAX3372E– MAX3379E and MAX3390E–MAX3393E help to design equipment that meets Level 3 of IEC 1000-4-2, without the need for additional ESD-protection components. The major difference between tests done using the Human Body Model and IEC 1000-4-2 is higher peak current in IEC 1000-4-2, because series resistance is lower in the IEC 1000-4-2 model. Hence, the ESD withstand voltage measured to IEC 1000-4-2 is generally lower than that measured using the Human Body Model. Figure 4a shows the IEC 1000-4-2 model, and Figure 4b shows the current waveform for the ±8kV, IEC 1000-4-2, Level 4, ESD contact-discharge test. The air-gap test involves approaching the device with a charged probe. The contact-discharge method connects the probe to the device before the probe is energized. Machine Model The Machine Model for ESD tests all pins using a 200pF storage capacitor and zero discharge resistance. Its objective is to emulate the stress caused by contact that occurs with handling and assembly during manufacturing. Of course, all pins require this protection during manufacturing, not just inputs and outputs. Therefore, after PCB assembly, the Machine Model is less relevant to I/O ports. RD 1500Ω IP 100% 90% DISCHARGE RESISTANCE Ir PEAK-TO-PEAK RINGING (NOT DRAWN TO SCALE) AMPERES HIGHVOLTAGE DC SOURCE Cs 100pF STORAGE CAPACITOR DEVICEUNDERTEST 36.8% 10% 0 0 Figure 3a. Human Body ESD Test Model Maxim Integrated tRL TIME tDL CURRENT WAVEFORM Figure 3b. Human Body Current Waveform 13 MAX3372E–MAX3379E/MAX3390E–MAX3393E ±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad Low-Voltage Level Translators in UCSP I 100% 90% CHARGE-CURRENTLIMIT RESISTOR HIGHVOLTAGE DC SOURCE Cs 150pF RD 330Ω DISCHARGE RESISTANCE I PEAK RC 50MΩ to 100MΩ DEVICEUNDERTEST STORAGE CAPACITOR 10% t t r = 0.7ns to 1ns 30ns 60ns Figure 4a. IEC 1000-4-2 ESD Test Model Figure 4b. IEC 1000-4-2 ESD Generator Current Waveform Applications Information ASIC and an I2C device. A typical application involves interfacing a low-voltage microprocessor to a 3V or 5V D/A converter, such as the MAX517. Power-Supply Decoupling To reduce ripple and the chance of transmitting incorrect data, bypass VL and VCC to ground with a 0.1µF capacitor. See the Typical Operating Circuit. To ensure full ±15kV ESD protection, bypass VCC to ground with a 1µF capacitor. Place all capacitors as close to the power-supply inputs as possible. Push-Pull vs. Open-Drain Driving All devices in the MAX3372E–MAX3379E and MAX3390E–MAX3393E family may be driven in a pushpull configuration. The MAX3373E–MAX3376E/ MAX3378E/MAX3379E and MAX3390E–MAX3393E include internal 10kΩ resistors that pull up I/O VL_ and I/O VCC_ to their respective power supplies, allowing operation of the I/O lines with open-drain devices. See the Timing Characteristics table for maximum data rates when using open-drain drivers. I2C Level Translation The MAX3373E–MAX3376E, MAX3378E/MAX3379E and MAX3390E–MAX3393E level-shift the data present on the I/O lines between +1.2V and +5.5V, making them ideal for level translation between a low-voltage Typical Operating Circuit +1.8V +3.3V 0.1µF 0.1µF VL 1µF VCC THREE-STATE +1.8V SYSTEM CONTROLLER DATA 14 +3.3V SYSTEM MAX3378E–MAX3383E I/O VL_ I/O VCC_ DATA Maxim Integrated MAX3372E–MAX3379E/MAX3390E–MAX3393E ±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad Low-Voltage Level Translators in UCSP Applications Circuits +1.8V +3.3V 0.1µF 0.1µF VL 1µF VCC THREE-STATE +1.8V SYSTEM CONTROLLER +3.3V SYSTEM MAX3372E/MAX3373E DATA I/O VL1 I/O VCC1 I/O VL2 I/O VCC2 DATA +1.8V +3.3V 0.1µF 0.1µF VL 1µF VCC THREE-STATE +1.8V SYSTEM CONTROLLER +3.3V SYSTEM MAX3374E I VL1 DATA Maxim Integrated I VL2 O VCC1 O VCC2 DATA 15 MAX3372E–MAX3379E/MAX3390E–MAX3393E ±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad Low-Voltage Level Translators in UCSP Applications Circuits (continued) +1.8V +3.3V 0.1µF 0.1µF VL 1µF VCC THREE-STATE +1.8V SYSTEM CONTROLLER +3.3V SYSTEM MAX3375E DATA O VL1 I VCC1 I VL2 O VCC2 DATA +1.8V +3.3V 0.1µF 0.1µF VL 1µF VCC THREE-STATE +1.8V SYSTEM CONTROLLER +3.3V SYSTEM MAX3376E DATA 16 O VL1 I VCC1 O VL2 I VCC2 DATA Maxim Integrated MAX3372E–MAX3379E/MAX3390E–MAX3393E ±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad Low-Voltage Level Translators in UCSP Applications Circuits (continued) +1.8V +3.3V 0.1µF 0.1µF VL 1µF VCC THREE-STATE +1.8V SYSTEM CONTROLLER +3.3V SYSTEM MAX3377E/MAX3378E DATA I/O VL1 I/O VCC1 I/O VL2 I/O VL3 I/O VL4 I/O VCC2 I/O VCC3 I/O VCC4 DATA +1.8V +3.3V 0.1µF 0.1µF VL 1µF VCC THREE-STATE +1.8V SYSTEM CONTROLLER +3.3V SYSTEM MAX3379E DATA Maxim Integrated I VL1 O VCC1 I VL2 O VCC2 I VL3 I VL4 O VCC3 O VCC4 DATA 17 MAX3372E–MAX3379E/MAX3390E–MAX3393E ±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad Low-Voltage Level Translators in UCSP Applications Circuits (continued) +1.8V +3.3V 0.1µF 0.1µF VL 1µF VCC THREE-STATE +1.8V SYSTEM CONTROLLER +3.3V SYSTEM MAX3390E I VL1 O VL1 DATA I VL2 O VCC2 I VL3 I VL4 O VCC3 O VCC4 DATA +1.8V +3.3V 0.1µF 0.1µF VL 1µF VCC THREE-STATE +1.8V SYSTEM CONTROLLER +3.3V SYSTEM MAX3391E DATA O VL1 O VL2 I VL3 I VL4 18 I VCC1 I VCC2 O VCC3 O VCC4 DATA Maxim Integrated MAX3372E–MAX3379E/MAX3390E–MAX3393E ±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad Low-Voltage Level Translators in UCSP Applications Circuits (continued) +1.8V +3.3V 0.1µF 0.1µF VL 1µF VCC THREE-STATE +1.8V SYSTEM CONTROLLER +3.3V SYSTEM MAX3392E DATA O VL1 I VCC1 O VL2 I VCC2 O VL3 I VL4 I VCC3 O VCC4 DATA +1.8V +3.3V 0.1µF 0.1µF VL 1µF VCC THREE-STATE +1.8V SYSTEM CONTROLLER +3.3V SYSTEM MAX3393E DATA O VL1 O VL2 O VL3 I VL4 Maxim Integrated I VCC1 I VCC2 I VCC3 I VCC4 DATA 19 MAX3372E–MAX3379E/MAX3390E–MAX3393E ±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad Low-Voltage Level Translators in UCSP Ordering Information (continued) PART TEMP RANGE PINPACKAGE PART TEMP RANGE PINPACKAGE MAX3372EEBL+T -40°C to +85°C 9 UCSP (1.5mm x 1.5mm) MAX3378EEBC+T -40°C to +85°C 12 UCSP (1.5mm x 2.0mm) MAX3372EETA+T -40°C to +85°C 8 TDFN-EP** (3mm x 3mm) MAX3378EETD+T -40°C to +85°C 14 TDFN-EP** (3mm x 3mm) MAX3373EEKA+T -40°C to +85°C 8 SOT23 MAX3379EEUD+ -40°C to +85°C 14 TSSOP MAX3373EEBL+T -40°C to +85°C 9 UCSP (1.5mm x 1.5mm) MAX3379EEBC+T -40°C to +85°C 12 UCSP (1.5mm x 2.0mm) MAX3373EETA+T -40°C to +85°C 8 TDFN-EP** (3mm x 3mm) MAX3379EETD+T -40°C to +85°C 14 TDFN-EP** (3mm x 3mm) MAX3374EEKA+T -40°C to +85°C 8 SOT23 MAX3390EEUD+ -40°C to +85°C 14 TSSOP MAX3374EEBL+T -40°C to +85°C 9 UCSP (1.5mm x 1.5mm) MAX3390EEBC+T -40°C to +85°C 12 UCSP (1.5mm x 2.0mm) MAX3374EETA+T -40°C to +85°C 8 TDFN-EP** (3mm x 3mm) MAX3390EETD+T -40°C to +85°C 14 TDFN-EP** (3mm x 3mm) MAX3375EEKA+T -40°C to +85°C 8 SOT23 MAX3391EEUD+ -40°C to +85°C 14 TSSOP MAX3375EEBL+T -40°C to +85°C 9 UCSP (1.5mm x 1.5mm) MAX3391EEBC+T -40°C to +85°C 12 UCSP (1.5mm x 2.0mm) MAX3375EETA+T -40°C to +85°C 8 TDFN-EP** (3mm x 3mm) MAX3391EETD+T -40°C to +85°C 14 TDFN-EP** (3mm x 3mm) MAX3376EEKA+T -40°C to +85°C 8 SOT23 MAX3392EEUD+ -40°C to +85°C 14 TSSOP MAX3376EEBL+T -40°C to +85°C 9 UCSP (1.5mm x 1.5mm) MAX3392EEBC+T -40°C to +85°C 12 UCSP (1.5mm x 2.0mm) MAX3376EETA+T -40°C to +85°C 8 TDFN-EP** (3mm x 3mm) MAX3392EETD+T -40°C to +85°C 14 TDFN-EP** (3mm x 3mm) MAX3377EEUD+ -40°C to +85°C 14 TSSOP MAX3393EEUD+ -40°C to +85°C 14 TSSOP MAX3377EEBC+T -40°C to +85°C 9 UCSP (1.5mm x 1.5mm) MAX3393EEBC+T -40°C to +85°C 12 UCSP (1.5mm x 2.0mm) MAX3377EETD+T -40°C to +85°C 14 TDFN-EP** (3mm x 3mm) MAX3393EETD+T -40°C to +85°C 14 TDFN-EP** (3mm x 3mm) MAX3378EEUD+ -40°C to +85°C 14 TSSOP +Denotes a lead-free package. **EP = Exposed pad. T = Tape and reel. 20 Maxim Integrated MAX3372E–MAX3379E/MAX3390E–MAX3393E ±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad Low-Voltage Level Translators in UCSP Selector Guide LEVEL TRANSLATION Tx/ Rx† MAX3372EEKA+T  Bi 2/2 MAX3372EEBL+T  Bi 2/2 MAX3372EETA+T  Bi 2/2 MAX3373EEKA+T  Bi 2/2 MAX3373EEBL+T  Bi MAX3373EETA+T  Bi PART DATA RATE TOP MARK PART LEVEL TRANSLATION Tx/ Rx† DATA RATE TOP MARK AAKO MAX3378EEUD+  Bi 4/4 AAR MAX3378EEBC+T  Bi 4/4 AAY AQG MAX3378EETD+T  Bi 4/4 AAH AAKS MAX3379EEUD+ Uni 4/0 — 2/2 AAZ MAX3379EEBC+T Uni 4/0 AAZ 2/2 AQH MAX3379EETD+T Uni 4/0 AAI Uni 3/1 — ABA 230kbps MAX3374EEKA+T Uni 2/0 AALH MAX3390EEUD+ MAX3374EEBL+T Uni 2/0 ABA MAX3390EEBC+T Uni 3/1 MAX3374EETA+T Uni 2/0 AQI MAX3390EETD+T Uni 3/1 AALI MAX3391EEUD+ Uni 2/2 8Mbps* — 8Mbps* AAJ — MAX3375EEKA+T Uni 1/1 MAX3375EEBL+T Uni 1/1 ABB MAX3391EEBC+T Uni 2/2 ABB MAX3375EETA+T Uni 1/1 AQJ MAX3391EETD+T Uni 2/2 AAK AALG MAX3392EEUD+ Uni 1/3 — MAX3376EEKA+T Uni 0/2 MAX3376EEBL+T Uni 0/2 AAV MAX3392EEBC+T Uni 1/3 ABC MAX3376EETA+T Uni 0/2 AQK MAX3392EETD+T Uni 1/3 AAL MAX3377EEUD+  Bi 4/4 — MAX3393EEUD+ Uni 0/4 — MAX3377EEBC+T  Bi 4/4 AAX MAX3393EEBC+T Uni 0/4 ABD MAX3377EETD+T  Bi 4/4 AAG MAX3393EETD+T Uni 0/4 AAM 230kbps Tx = VL → VCC, Rx = VCC → VL † *Higher data rates are possible (see the Timing Characteristics table). Maxim Integrated 21 MAX3372E–MAX3379E/MAX3390E–MAX3393E ±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad Low-Voltage Level Translators in UCSP Pin Configurations (continued) A B C + I/O VCC2 1 VCC THREE-STATE VL MAX3372E MAX3373E 2 I/O VCC1 N.C. I/O VL1 + 8 I/O VCC1 1 GND 2 VL 7 VCC 3 6 THREE-STATE I/O VL2 4 3 I/O VCC2 GND 5 I/O VL1 B 8 I/O VL2 GND 2 I/O VCC1 7 VL 6 I/O VL1 3 VCC 4 *EP SOT23-8 TOP VIEW TDFN-8 (3mm x 3mm) TOP VIEW *CONNECT EP TO GND C + + O VCC2 1 VCC THREE-STATE VL O VCC1 N.C. I VL1 MAX3374E 2 1 8 O VCC1 GND 2 VL 7 VCC 3 6 THREE-STATE I VL2 4 5 I VL1 O VCC2 1 8 I V L2 GND 2 O VCC1 7 VL 6 I VL1 3 VCC 4 *EP 3 O VCC2 GND I VL2 B *CONNECT EP TO GND C + + O VCC2 1 VCC THREE-STATE VL O VCC1 N.C. I VL1 MAX3375E 2 1 8 I VCC1 GND 2 VL 7 VCC 3 6 THREE-STATE I VL2 4 5 O VL1 O VCC2 1 8 I VL2 GND 2 I VCC1 7 VL 6 O VL1 3 VCC 4 *EP 3 I VCC2 GND O VL2 B *CONNECT EP TO GND C + + I VCC2 1 VCC THREE-STATE VL I VCC1 N.C. O V L1 2 GND 8 I VCC1 GND 2 VL 7 VCC 3 6 THREE-STATE 5 O VL1 I VCC2 1 8 O VL2 GND 2 I VCC1 7 VL 6 O VL1 3 VCC 4 *EP 5 THREE-STATE O VL2 9 UCSP (1.5mm x 1.5mm) BOTTOM VIEW 22 MAX3376E 1 O VL2 4 3 I VCC2 5 THREE-STATE TDFN-8 (3mm x 3mm) TOP VIEW SOT23-8 TOP VIEW 9 UCSP (1.5mm x 1.5mm) BOTTOM VIEW A 5 THREE-STATE TDFN-8 (3mm x 3mm) TOP VIEW SOT23-8 TOP VIEW 9 UCSP (1.5mm x 1.5mm) BOTTOM VIEW A 5 THREE-STATE I/O VL2 9 UCSP (1.5mm x 1.5mm) BOTTOM VIEW A I/O VCC2 1 SOT23-8 TOP VIEW TDFN-8 (3mm x 3mm) TOP VIEW *CONNECT EP TO GND Maxim Integrated MAX3372E–MAX3379E/MAX3390E–MAX3393E ±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad Low-Voltage Level Translators in UCSP Pin Configurations (continued) B A C + + 1 VCC I/O VL1 I/O VCC1 MAX3377E MAX3378E 2 VL I/O VL2 I/O VCC2 3 I/O VL3 THREE-STATE I/O VCC3 4 I/O VL4 GND VL 1 14 VCC I/O VL1 1 14 VCC I/O VL1 2 13 I/0 VCC1 I/O VL2 2 13 I/0 VCC1 I/O VL2 3 12 I/0 VCC2 THREE-STATE 3 12 I/0 VCC2 I/O VL3 4 11 I/0 VCC3 N.C. 4 11 N.C. I/O VL4 5 10 I/0 VCC4 I/O VL3 5 10 VL N.C. 6 9 N.C. I/O VL4 6 9 I/0 VCC3 GND 7 8 THREE-STATE GND 7 8 I/0 VCC4 B TDFN-14 (3mm x 3mm) TOP VIEW TSSOP-14 TOP VIEW 12 UCSP (1.5mm x 2.0mm) BOTTOM VIEW A *CONNECT EP TO GND C + + 1 VCC I VL1 O VCC1 MAX3379E 2 VL I VL2 O VCC2 3 I VL3 THREE-STATE O VCC3 4 I VL4 GND B 1 14 13 O VCC1 I VL2 2 13 0 VCC1 12 O VCC2 THREE-STATE 3 12 0 VCC2 11 O VCC3 N.C. 4 11 N.C. 5 10 VL 9 0 VCC3 8 0 VCC4 1 14 VCC I VL1 2 I VL2 3 I VL3 4 I VL4 5 10 O VCC4 I VL3 N.C. 6 9 N.C. I VL4 6 GND 7 8 THREE-STATE GND 7 TDFN-14 (3mm x 3mm) TOP VIEW TSSOP-14 TOP VIEW *CONNECT EP TO GND C 1 VCC I VCC1 MAX3390E 2 VL I VL2 O VCC2 3 I VL3 THREE-STATE O VCC3 4 I VL4 GND + VL 1 14 VCC O VL1 2 13 I VCC1 I VL2 3 12 O VCC2 VCC O VL1 1 14 I V L2 2 13 I VCC1 THREE-STATE 3 12 0 VCC2 I VL3 4 11 O VCC3 N.C. 4 11 N.C. I VL4 5 10 O VCC4 I VL3 5 10 VL N.C. 6 9 N.C. I V L4 6 9 0 VCC3 GND 7 8 THREE-STATE GND 7 8 0 VCC4 O VCC4 12 UCSP (1.5mm x 2.0mm) BOTTOM VIEW Maxim Integrated *EP O VCC4 + O VL1 VCC I VL1 VL 12 UCSP (1.5mm x 2.0mm) BOTTOM VIEW A *EP I/O VCC4 TSSOP-14 TOP VIEW *EP TDFN-14 (3mm x 3mm) TOP VIEW *CONNECT EP TO GND 23 MAX3372E–MAX3379E/MAX3390E–MAX3393E ±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad Low-Voltage Level Translators in UCSP Pin Configurations (continued) A B C + + 14 VCC O VL1 2 13 I VCC1 O VL2 2 13 I VCC1 O VL2 3 12 I VCC2 THREE-STATE 3 12 I VCC2 VL 1 1 O VL1 VCC I VCC1 MAX3391E 2 O VL2 VL I VCC2 3 I VL3 THREE-STATE O VCC3 I VL4 GND B 1 I VL3 4 11 O VCC3 N.C. 4 11 N.C. 10 O VCC4 I VL3 5 10 VL N.C. 6 9 I VL4 6 9 0 VCC3 8 0 VCC4 8 N.C. THREE-STATE GND 7 TDFN-14 (3mm x 3mm) TOP VIEW TSSOP-14 TOP VIEW *CONNECT EP TO GND C + + 14 VCC VL 1 1 O VL1 VCC I VCC1 MAX3392E 2 O VL2 VL I VCC2 3 O VL3 THREE-STATE I VCC3 4 I VL4 GND *EP O VCC4 12 UCSP (1.5mm x 2.0mm) BOTTOM VIEW A O VL1 I VL4 5 GND 7 4 14 VCC O VL1 1 14 VCC O VL1 2 13 I VCC1 O V L2 2 13 I VCC1 O VL2 3 12 I VCC2 THREE-STATE 3 12 I VCC2 O VL3 4 11 I VCC3 N.C. 4 11 N.C. I V L4 5 10 O VCC4 O VL3 5 10 VL N.C. 6 9 N.C. I VL4 6 9 I VCC3 GND 7 8 THREE-STATE GND 7 8 0 VCC4 *EP O VCC4 TDFN-14 (3mm x 3mm) TOP VIEW TSSOP-14 TOP VIEW 12 UCSP (1.5mm x 2.0mm) BOTTOM VIEW *CONNECT EP TO GND A B C + + 1 O VL1 VCC I VCC1 MAX3393E 2 O VL2 VL I VCC2 3 O VL3 THREE-STATE I VCC3 4 O VL4 GND O VL1 1 14 VCC O VL1 2 13 I VCC1 O VL2 2 13 I VCC1 O VL2 3 12 I VCC2 THREE-STATE 3 12 I VCC2 O VL3 4 11 I VCC3 N.C. 4 11 N.C. O V L4 5 10 I VCC4 O VL3 5 10 VL N.C. 6 9 N.C. O VL4 6 9 I VCC3 GND 7 8 THREE-STATE GND 7 8 I VCC4 I VCC4 12 UCSP (1.5mm x 2.0mm) BOTTOM VIEW 24 14 VCC VL 1 TSSOP-14 TOP VIEW TDFN-14 (3mm x 3mm) TOP VIEW *CONNECT EP TO GND Maxim Integrated MAX3372E–MAX3379E/MAX3390E–MAX3393E ±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad Low-Voltage Level Translators in UCSP Package Information Chip Information PROCESS: BiCMOS Maxim Integrated For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 8 SOT23 K8SN+1 21-0078 90-0176 9 UCSP B9+2 21-0093 12 UCSP B12+1 21-0104 Refer to Application Note 1891 Refer to Application Note 1891 8 TDFN T833+2 21-0137 90-0059 14 TDFN T1433+2 21-0137 90-0063 14 TSSOP U14+1 21-0066 90-0113 25 MAX3372E–MAX3379E/MAX3390E–MAX3393E ±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad Low-Voltage Level Translators in UCSP Revision History REVISION NUMBER REVISION DATE 0 1/02 Initial Release 1 12/06 Addition of 12-bump ECSP packaging 2 11/07 Addition of lead-free options 3 1/13 Updated packaging information; updated Absolute Maximum Ratings DESCRIPTION PAGES CHANGED — – 1, 20–31 1, 2, 9, 20–23 Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. 26 ________________________________Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 © 2013 Maxim Integrated Products, Inc. Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
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