MAX3681EAG+T

19-1091; Rev 1; 5/04 KIT ATION EVALU E L B AVAILA +3.3V, 622Mbps, SDH/SONET 1:4 Deserializer with LVDS Outputs ______________________________Features The MAX3681 deserializer is ideal for converting 622Mbps serial data to 4-bit-wide, 155Mbps parallel data in ATM and SDH/SONET applications. Operating from a single +3.3V supply, this device accepts PECL serial clock and data inputs, and delivers low-voltage differential-signal (LVDS) clock and data outputs for interfacing with high-speed digital circuitry. It also provides an LVDS synchronization input that enables data realignment and reframing. The MAX3681 is available in the extended-industrial temperature range (-40°C to +85°C), in a 24-pin SSOP package. ♦ Single +3.3V Supply __________________________Applications ________________Ordering Information ♦ 622Mbps Serial to 155Mbps Parallel Conversion ♦ 265mW Power ♦ LVDS Data Outputs and Synchronization Inputs ♦ Synchronization Input for Data Realignment and Reframing ♦ Differential 3.3V PECL Clock and Data Inputs 622Mbps SDH/SONET Transmission Systems PART MAX3681EAG MAX3681EAG+ 622Mbps ATM/SONET Access Nodes Add/Drop Multiplexers TEMP RANGE -40°C to +85°C -40°C to +85°C PIN-PACKAGE 24 SSOP 24 SSOP +Denotes Lead Free Package Digital Cross Connects Pin Configuration appears at end of data sheet. ___________________________________________________________________Typical Operating Circuit VCC = +3.3V VCC PD3+ 100Ω* VCC = +3.3V VCC = +3.3V MAX3681 130Ω PD3PD2+ 130Ω 100Ω* PHOTODIODE MAX3675 82Ω PREAMP 100Ω LIMITING AMP DATA AND CLOCK RECOVERY SD+ PD2- SD- PD1+ 82Ω OVERHEAD TERMINATION 100Ω* PD1PD0+ VCC = +3.3V 100Ω* MAX3664 130Ω 130Ω PD0PCLK+ SCLK+ 100Ω* SCLKPCLK82Ω 82Ω SYNC+ *REQUIRED ONLY IF OVERHEAD CIRCUIT DOES NOT INCLUDE INTERNAL INPUT TERMINATION. GND SYNC- THIS SYMBOL REPRESENTS A TRANSMISSION LINE OF CHARACTERISTIC IMPEDANCE Z0 = 50Ω. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX3681 _________________General Description MAX3681 +3.3V, 622Mbps, SDH/SONET 1:4 Deserializer with LVDS Outputs ABSOLUTE MAXIMUM RATINGS Terminal Voltage (with respect to GND) VCC ...........................................................................-0.5V to 5V PECL Inputs (SD+/-, SCLK+/-).................................VCC + 0.5V LVDS Inputs (SYNC+/-)............................................VCC + 0.5V Output Current, LVDS Outputs (PCLK+/-, PD_+/-) .............10mA Continuous Power Dissipation (TA = +85°C) SSOP (derate 8.00mW/°C above +85°C) ......................520mW Operating Temperature Range ...........................-40°C to +85°C Storage Temperature Range .............................-65°C to +160°C Lead Temperature (soldering, 10sec) .............................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +3.6V, differential loads = 100Ω, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25°C.) PARAMETER MIN TYP MAX UNITS ICC 55 80 120 mA Input High Voltage VIH VCC - 1.16 VCC - 0.88 V Input Low Voltage VIL VCC - 1.81 VCC - 1.48 V Input High Current IIH VIN = VIH(MAX) -10 10 µA Input Low Current IIL VIN = VIL(MAX) -10 10 µA Supply Current SYMBOL CONDITIONS PECL INPUTS (SD+/-, SCLK+/-) LVDS INPUTS AND OUTPUTS (SYNC+/-, PCLK+/-, PD_+/-) Input Voltage Range VI Differential Input Threshold VIDTH Threshold Hysteresis VHYST Differential input voltage = 100mV Common-mode voltage = 50mV 0 2.4 V -100 100 mV 70 Differential Input Resistance RIN Output High Voltage VOH Output Low Voltage VOL 0.925 Differential Output Voltage VOD 250 Change in Magnitude of Differential Output Voltage for Complementary States Output Offset Voltage 85 Ω 1.475 V 400 mV 25 mV 1.275 V 25 mV 70 140 Ω ±1 ±10 % TYP MAX UNITS V ΔVOD VOS Change in Magnitude of Output Offset Voltage for Complementary States ΔVOS Single-Ended Output Resistance RO Change in Magnitude of SingleEnded Output Resistance for Complementary States ΔRO TA = +25°C 1.125 40 mV 115 100 AC ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +3.6V, differential loads = 100Ω, TA = +25°C, unless otherwise noted.) (Note 1) PARAMETER Maximum Serial Clock Frequency SYMBOL CONDITIONS MIN fSCLK 622 MHz Serial Data Setup Time tSU 800 ps Serial Data Hold Time tH 50 tCLK-Q 200 Parallel Clock to Data Output Delay ps 550 Note 1: AC Characteristics guaranteed by design and characterization. 2 _______________________________________________________________________________________ 900 ps +3.3V, 622Mbps, SDH/SONET 1:4 Deserializer with LVDS Outputs SERIAL DATA-SETUP TIME vs. TEMPERATURE 1.6 VCC = 3.0V 1.4 1.2 MAX3681-03 360 320 280 240 200 1.0 25 50 75 -180 -220 -260 -300 -50 100 -140 0 -25 25 50 75 100 -50 -25 TEMPERATURE (°C) TEMPERATURE (°C) 25 50 75 100 TEMPERATURE (°C) PARALLEL CLOCK TO DATA OUTPUT PROPAGATION DELAY vs. TEMPERATURE SUPPLY CURRENT vs. TEMPERATURE 120 100 0 700 VCC = +3.6V VCC = +3.3V 80 VCC = +3.0V 60 MAX3681-05 0 PARALLEL CLOCK TO DATA PROPAGATION DELAY (ps) -25 MAX3681-02 -50 -100 SERIAL DATA-HOLD TIME (ps) VCC = 3.6V 400 SERIAL DATA-SETUP TIME (ps) MAX3681-01 1.8 SUPPLY CURRENT (mA) MAX SERIAL CLOCK FREQUENCY (GHz) 2.0 SERIAL DATA-HOLD TIME vs. TEMPERATURE MAX3681-04 MAXIMUM SERIAL CLOCK FREQUENCY vs. TEMPERATURE 650 600 550 500 450 40 -50 -25 0 25 50 TEMPERATURE (°C) 75 100 -50 -25 0 25 50 75 100 TEMPERATURE (°C) _______________________________________________________________________________________ 3 MAX3681 __________________________________________Typical Operating Characteristics (VCC = +3.0V to +3.6V, differential loads = 100Ω, unless otherwise noted.) MAX3681 +3.3V, 622Mbps, SDH/SONET 1:4 Deserializer with LVDS Outputs ______________________________________________________________Pin Description PIN NAME FUNCTION 1, 2, 5, 8, 12 VCC +3.3V Supply Voltage 3 SD+ Noninverting PECL Serial Data Input. Data is clocked on the SCLK signal’s positive transition. 4 SD- Inverting PECL Serial Data Input. Data is clocked on the SCLK signal’s positive transition. 6 SCLK+ Noninverting PECL Serial Clock Input 7 SCLK- Inverting PECL Serial Clock Input 9, 15, 22 GND 10 SYNC+ Noninverting LVDS Synchronizing Pulse Input. Pulse the SYNC signal high for at least two SCLK periods to shift the data alignment by dropping one bit. 11 SYNC- Inverting LVDS Synchronizing Pulse Input. Pulse the SYNC signal high for at least two SCLK periods to shift the data alignment by dropping one bit. 13 PCLK- Inverting LVDS Parallel Clock Output 14 PCLK+ Noninverting LVDS Parallel Clock Output 16, 18, 20, 23 PD0- to PD3- 17, 19, 21, 24 PD0+ to PD3+ Ground Inverting LVDS Parallel Data Outputs. Data is updated on the positive transition of the PCLK signal. See Figure 2 for the relationship between serial-data-bit position and output-data-bit assignment. Noninverting LVDS Parallel Data Outputs. Data is updated on the positive transition of the PCLK signal. See Figure 2 for the relationship between serial-data-bit position and output-data-bit assignment. _______________Detailed Description The MAX3681 deserializer uses a 4-bit shift register, 4-bit parallel output register, 2-bit counter, PECL input buffers, and low-voltage differential-signal (LVDS) input/output buffers to convert 622Mbps serial data to 4-bit-wide, 155Mbps parallel data (Figure 1). The input shift register continuously clocks incoming data on the positive transition of the serial clock (SCLK) input signal. The 2-bit counter generates a parallel output clock (PCLK) by dividing down the serial clock frequency. The PCLK signal is used to clock the parallel output register. During normal operation, the counter divides the SCLK frequency by four, causing the output register to latch every four bits of incoming serial data. The synchronization inputs (SYNC+, SYNC-) are used for data realignment and reframing. When the SYNC signal is pulsed high for at least two SCLK cycles, the parallel output data is delayed by one SCLK cycle. This realignment is guaranteed to occur within two PCLK cycles of the SYNC signal’s positive transition. As a result, the first incoming bit of data during that PCLK cycle is dropped, shifting the alignment between PCLK and data by one bit. See Figure 2 for the functional timing diagram and Figure 3 for the timing parameters diagram. 4 PD3+ SD+ SD- PECL 4-BIT SHIFT REGISTER SCLK+ SCLK- 4-BIT PARALLEL OUTPUT REGISTER LVDS PD2+ LVDS PECL PD3- PD2PD1+ LVDS MAX3681 PD1PD0+ LVDS SYNC+ SYNC- 100Ω LVDS 2-BIT COUNTER Figure 1. Functional Diagram _______________________________________________________________________________________ PD0PCLK+ LVDS PCLK- +3.3V, 622Mbps, SDH/SONET 1:4 Deserializer with LVDS Outputs MAX3681 SCLK SD D1- D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 SYNC PCLK PD3 D4- D0 D5 PD2 D3- D1 D6 PD1 D2- D2 D7 PD0 D1- D3 D8 NOTE: SIGNALS SHOWN ARE DIFFERENTIAL. FOR EXAMPLE, SCLK = (SCLK+) - (SCLK-). Figure 2. Functional Timing Diagram tSCLK = 1 / fSCLK SCLK tSU tH SD PCLK tCLK-Q PD0–PD3 NOTE: SIGNALS SHOWN ARE DIFFERENTIAL. FOR EXAMPLE, SCLK = (SCLK+) - (SCLK-). Figure 3. Timing Parameters _______________________________________________________________________________________ 5 MAX3681 +3.3V, 622Mbps, SDH/SONET 1:4 Deserializer with LVDS Outputs Low-Voltage Differential-Signal (LVDS) Inputs and Outputs The MAX3681 features LVDS inputs and outputs for interfacing with high-speed digital circuitry. The LVDS standard is based on the IEEE 1596.3 LVDS specification. This technology uses 250mVp-p to 400mVp-p, differential low-voltage swings to achieve fast transition times, minimized power dissipation, and noise immunity. The parallel clock and data LVDS outputs (PCLK+, PCLK-, PD_+, PD_-) require 100Ω differential DC termination between the inverting and noninverting outputs for proper operation. Do not terminate these outputs to ground. The synchronization LVDS inputs (SYNC+, SYNC-) are internally terminated with 100Ω of differential input resistance, and therefore do not require external termination. THEVENIN-EQUIVALENT TERMINATION +3.3V 130Ω __________Applications Information PECL INPUTS 82Ω 82Ω ECL AC-COUPLING TERMINATION +3.3V 1.6k 1.6k ZO = 50Ω MAX3681 50Ω ZO = 50Ω PECL INPUTS -2V Alternative PECL Input Termination Figure 4 shows alternative PECL input-termination methods. Use Thevenin-equivalent termination when a (VCC - 2V) termination voltage is not available. If AC coupling is necessary, such as when interfacing with an ECL-output device, use the ECL AC-coupling termination. MAX3681 ZO = 50Ω PECL Inputs The serial data and clock PECL inputs (SD+, SD-, SCLK+, SCLK-) require 50Ω termination to (VCC - 2V) when interfacing with a PECL source (see the Alternative PECL Input Termination section). 130Ω ZO = 50Ω 50Ω 2.7k 2.7k -2V Figure 4. Alternative PECL Input Termination Layout Techniques For best performance, use good high-frequency layout techniques. Filter voltage supplies and keep ground connections short. Use multiple vias where possible. Also, use controlled impedance transmission lines to interface with the MAX3681 data inputs and outputs. 6 _______________________________________________________________________________________ +3.3V, 622Mbps, SDH/SONET 1:4 Deserializer with LVDS Outputs TOP VIEW ___________________Chip Information TRANSISTOR COUNT: 724 VCC 1 24 PD3+ VCC 2 23 PD3- SD+ 3 22 GND SD- 4 21 PD2+ VCC 5 MAX3681 20 PD2- SCLK+ 6 19 PD1+ SCLK- 7 18 PD1- VCC 8 17 PD0+ GND 9 16 PD0- SYNC+ 10 15 GND SYNC- 11 14 PCLK+ VCC 12 13 PCLK- SSOP _______________________________________________________________________________________ 7 MAX3681 __________________Pin Configuration Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) 2 SSOP.EPS MAX3681 +3.3V, 622Mbps, SDH/SONET 1:4 Deserializer with LVDS Outputs 1 INCHES E H MILLIMETERS DIM MIN MAX MIN MAX A 0.068 0.078 1.73 1.99 A1 0.002 0.008 0.05 0.21 B 0.010 0.015 0.25 0.38 C 0.09 0.20 0.004 0.008 SEE VARIATIONS D E e 0.205 0.212 0.0256 BSC 5.20 MILLIMETERS INCHES D D D D D 5.38 MIN MAX MIN MAX 0.239 0.239 0.278 0.249 0.249 0.289 6.07 6.07 7.07 6.33 6.33 7.33 0.317 0.397 0.328 0.407 8.07 10.07 8.33 10.33 N 14L 16L 20L 24L 28L 0.65 BSC H 0.301 0.311 7.65 7.90 L 0.025 0∞ 0.037 8∞ 0.63 0∞ 0.95 8∞ N A C B e L A1 D NOTES: 1. D&E DO NOT INCLUDE MOLD FLASH. 2. MOLD FLASH OR PROTRUSIONS NOT TO EXCEED .15 MM (.006"). 3. CONTROLLING DIMENSION: MILLIMETERS. 4. MEETS JEDEC MO150. 5. LEADS TO BE COPLANAR WITHIN 0.10 MM. PROPRIETARY INFORMATION TITLE: PACKAGE OUTLINE, SSOP, 5.3 MM APPROVAL DOCUMENT CONTROL NO. 21-0056 REV. C 1 1 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 8 ___________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600 © 1996 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.