EVALUATION KIT AVAILABLE
MAX3747A/MAX3747B
155Mbps to 3.2Gbps, Low-Power SFP
Limiting Amplifiers
General Description
Features
The MAX3747A/MAX3747B multirate limiting amplifiers
function as data quantizers for OC-3 through OC-48 synchronous optical network (SONET), Fibre-Channel, and
Gigabit Ethernet optical receivers. They are pin-for-pin
compatible with the SY88993V from Micrel
Semiconductor, Inc. The amplifiers accept a wide range
of input voltages and provide constant-level, currentmode logic (CML) output voltages with controlled edge
speeds. The MAX3747A/MAX3747B output voltages are
800mVP-P. The MAX3747B has enhanced LOS operation
under overload conditions.
o Pin Compatible with Micrel SY88993V
o 155Mbps to 3.2Gbps Operation
o > 57dB of Gain
o < 10-12 BER with 2mVP-P Input Amplitude
o 18mA Supply Current
o Chatter-Free LOS with Programmable Threshold
o Output DISABLE Function
o PECL-Compatible Inputs
The MAX3747A/MAX3747B limiting amplifiers feature a
programmable loss-of-signal detect (LOS) and an
optional disable function (DISABLE) that can be combined to implement squelch.
The MAX3747A/MAX3747B are available in a 3mm, 10pin µMAX® package ideal for small formfactor receivers.
Ordering Information
PART
Applications
TEMP RANGE
PIN-PACKAGE
MAX3747AEUB+
-40°C to +85°C
10 µMAX
MAX3747BEUB+
-40°C to +85°C
10 µMAX
+Denotes a lead(Pb)-free/RoHS-compliant package.
Gigabit Ethernet SFP/SFF Optical Transceiver Modules
1G/2G Fibre-Channel SFP/SFF Optical Transceiver
Modules
Multirate OC-3 to OC-48 FEC SFP/SFF Optical
Transceiver Modules
10G LX4 Transceiver Modules
µMAX is a registered trademark of Maxim Integrated Products, Inc.
Pin Configuration appears at end of data sheet.
Typical Application Circuit
SFP OPTICAL RECEIVER
3-INPUT
DIAGNOSTIC
MONITOR
VCC
DS1859
MAX4004
HOST BOARD
SUPPLY FILTER
HOST FILTER
VCC_RX
VCC
MAX3747A
MAX3747B
0.1µF
MAX3745
0.1µF
IN+
OUT+
IN-
OUT-
0.1µF
50Ω
SERDES
0.1µF
50Ω
5-PIN TO-HEADER
50Ω
VREF
50Ω
TH
GND LOS
DISABLE
4.7kΩ TO 10kΩ
VCC_HOST
LOS
RTH1
0.1µF
0.1µF
RTH2
VCC
RTH1 + RTH2 ≥ 5kΩ
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.
19-0281; Rev 2; 8/12
MAX3747A/MAX3747B
155Mbps to 3.2Gbps, Low-Power SFP
Limiting Amplifiers
ABSOLUTE MAXIMUM RATINGS
Power-Supply Voltage (VCC) .................................-0.5V to +4.5V
Voltage at IN+, IN- ..........................(VCC - 2.4V) to (VCC + 0.5V)
Voltage at DISABLE, LOS, TH, VREF ..........-0.5V to (VCC + 0.5V)
Current into LOS ...................................................-1mA to +9mA
Current into VREF ..................................................................2mA
Differential Input Voltage (IN+ - IN-) .....................................2.5V
Continuous Current at CML Outputs
(OUT+, OUT-) ..............................................-25mA to +25mA
Continuous Power Dissipation (TA = +70°C)
10-Pin µMAX (derate 6.9mW/°C above +70°C) ...........552mW
Operating Junction Temperature Range (TJ) .......-55°C to +150°C
Storage Ambient Temperature Range (TS)...........-55°C to +150°C
Lead Temperature (soldering, 10s)......................................+300°C
Soldering Temperature (reflow)............................................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = +2.97V to +3.63V, CML output load is 50Ω to VCC, TA = -40°C to +85°C. Typical values are at VCC = +3.3V and TA = +25°C,
unless otherwise specified.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
MAX3747A including the CML output current
36
41
MAX3747B including the CML output current
38
43
MAX3747A excluding the CML output
current
18
24
MAX3747B excluding the CML output
current
20
26
PSNR
f < 2MHz
30
Input Sensitivity
VIN-MIN
(Note 3)
Input Overload
VIN-MAX
(Note 3)
1200
(Note 4)
42
UNITS
POWER SUPPLY
Supply Current (Note 2)
Power-Supply Noise Rejection
ICC
mA
dB
INPUT SPECIFICATION
4
mVP-P
mVP-P
OUTPUT SPECIFICATION
Output Resistance
ROUT
Differential Output Return Loss
DUT is powered on, f < 3GHz
CML Differential Output Voltage
MAX3747A/MAX3747B
4mVP-P ≤ VIN ≤ 1200mVP-P
Differential Output Signal When
Disabled
AC-coupled outputs, VIN-MAX applied to the
input (Note 4)
Data-Output Transition Time
20% to 80% (Note 4)
50
58
15
600
800
Ω
dB
1000
mVP-P
15
mVP-P
70
120
ps
TRANSFER CHARACTERISTIC
K28.5 pattern at 3.2Gbps
Deterministic Jitter (Notes 4, 5)
Random Jitter
2
DJ
13.2
19
PRBS 223 - 1 equivalent pattern at 2.7Gbps
(Note 6)
14
25
K28.5 pattern at 2.1Gbps
12
17
PRBS 223 - 1 equivalent pattern at 155Mbps
(Note 6)
85
150
VIN = 4mVP-P (Notes 4, 7)
3.5
5
psP-P
psRMS
Maxim Integrated
MAX3747A/MAX3747B
155Mbps to 3.2Gbps, Low-Power SFP
Limiting Amplifiers
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +2.97V to +3.63V, CML output load is 50Ω to VCC, TA = -40°C to +85°C. Typical values are at VCC = +3.3V and TA = +25°C,
unless otherwise specified.) (Note 1)
PARAMETER
SYMBOL
Input-Referred Noise
CONDITIONS
MIN
VIN = 4mVP-P (Note 4)
Low-Frequency Cutoff
TYP
MAX
UNITS
120
150
µVRMS
6.4
LOS Hysteresis
10log(VDEASSERT / VASSERT) (Note 4)
MAX3747A (Notes 4, 8)
LOS Assert/Deassert Time
MAX3747B (Notes 4, 8, 9)
Low LOS Assert Level
VTH = -1.3V (Notes 4, 10)
Low LOS Deassert Level
VTH = -1.3V (Notes 4, 10)
Medium LOS Assert Level
VTH = -0.68V (Notes 4, 10)
Medium LOS Deassert Level
VTH = -0.68V (Notes 4, 10)
High LOS Assert Level
VTH = -0.114V (Notes 4, 10)
High LOS Deassert Level
VTH = -0.114V (Notes 4, 10)
kHz
1.25
dB
2.3
40.0
µs
5.9
mVP-P
mVP-P
2.5
4.1
6.2
9.3
22.0
29.0
36.0
mVP-P
44.8
62.0
mVP-P
36.0
53.7
63.6
mVP-P
86.0
115
mVP-P
VCC 1.3V
VCC 1.19
V
TTL/CMOS I/O
VCC 1.35
VREF Voltage
VREF
LOS Output High Voltage
VOH
RLOS = 4.7kΩ to 10kΩ to VCC_HOST (3V)
LOS Output Low Voltage
VOL
RLOS = 4.7kΩ to 10kΩ to VCC_HOST (3.6V)
DISABLE Input High
VIH
DISABLE Input Low
VIL
DISABLE Input Current
2.4
V
0.4
2.0
RLOS = 4.7kΩ to 10kΩ to VCC_HOST
V
V
0.8
V
10
µA
The data-input transition time is controlled by a 4th-order Bessel filter with f-3dB = 0.75 x 2.667GHz for all data rates of
2.667Gbps and below. The f-3db = 0.75 x 3.2GHz for a data rate of 3.2Gbps.
Note 2: Supply current is measured with unterminated outputs or with AC-coupled output termination (see Figure 1).
Note 3: Between sensitivity and overload, all AC specifications are met and the output is 0.95 x limited output amplitude.
Note 4: Guaranteed by design and characterization.
Note 5: The deterministic jitter (DJ) caused by the input filter is not included in the DJ generation specification.
Note 6: The PRBS 223 - 1 equivalent pattern consists of a K28.5 pattern plus 240 ones plus K28.5 pattern plus 240 zeros.
Note 7: Random jitter was measured without using a filter at the input.
Note 8: The signal at the input is switched between two amplitudes, Signal_ON and Signal_OFF, as shown in Figure 2A.
Note 9: The signal at the input is switched between 1.2VP-P and Signal_OFF as shown in Figure 2B.
Note 10: VTH is the voltage at pin 5 referenced to VCC (see Figure 5).
Note 1:
Maxim Integrated
3
MAX3747A/MAX3747B
155Mbps to 3.2Gbps, Low-Power SFP
Limiting Amplifiers
VCC
ICC
(SUPPLY
CURRENT)
IOUT
(CML OUTPUT
CURRENT)
50I
50I
MAX3747A
MAX3747B
Figure 1. Power-Supply Current Measurement
VIN
VIN
SIGNAL_ON = 1.2VP-P (OVERLOAD)
SIGNAL_ON
1dB
MAXIMUM DEASSERT LEVEL FOR A GIVEN VTH
6dB
MAXIMUM POWER-DETECT WINDOW
MAXIMUM DEASSERT LEVEL FOR A GIVEN RTH1/RTH2 RATIO
6dB
MINIMUM ASSERT LEVEL FOR A GIVEN VTH
0V
SIGNAL_OFF
MINIMUM ASSERT LEVEL FOR A GIVEN RTH1/RTH2 RATIO
TIME
Figure 2A. LOS Deassert Threshold—Set 1dB Below Receiver
Sensitivity
4
MAXIMUM POWER-DETECT WINDOW
0V
SIGNAL_OFF
TIME
Figure 2B. LOS Deassert Threshold—Operating at Input
Overload
Maxim Integrated
MAX3747A/MAX3747B
155Mbps to 3.2Gbps, Low-Power SFP
Limiting Amplifiers
Typical Operating Characteristics
(VCC = +3.3V, TA = +25°C, unless otherwise noted.)
OUTPUT EYE DIAGRAM
(MINIMUM INPUT)
OUTPUT EYE DIAGRAM
(MINIMUM INPUT)
OUTPUT EYE DIAGRAM
(MAXIMUM INPUT)
MAX3747A/MAX3747B toc01
MAX3747A/MAX3747B toc03
MAX3747A/MAX3747B toc02
3.2Gbps, 223 - 1 PRBS, 4mVP-P
2.7Gbps, 223 - 1 PRBS, 4mVP-P
3.2Gbps, 223 - 1 PRBS, 1200mVP-P
60mV/div
60mV/div
60mV/div
50ps/div
70ps/div
50ps/div
OUTPUT EYE DIAGRAM
(MAXIMUM INPUT)
SUPPLY CURRENT vs. TEMPERATURE
(EXCLUDES OUTPUT CURRENT)
OUTPUT EYE DIAGRAM AT +100°C
MAX3747A/MAX3747B toc05
2.7Gbps, 223 - 1 PRBS, 1200mVP-P
50
2.125Gbps, CJTPAT, 50mVP-P
MAX3747A/MAX3747B toc06
MAX3747A/MAX3747B toc04
SUPPLY CURRENT (mA)
45
60mV/div
60mV/div
40
35
30
25
20
15
10
80ps/div
TRANSFER FUNCTION
(OUTPUT VOLTAGE vs. INPUT VOLTAGE)
600
500
400
300
VIN = 50mVP-P, FREQ = 2.7Gbps
2.4
2.1
1.8
1.5
1.2
0.9
200
0.6
100
0.3
0
1
2
3
4
DIFFERENTIAL INPUT (mVP-P)
Maxim Integrated
5
3.2Gbps
4
3
2
1
0
0
5
RANDOM JITTER (psRMS)
MAX3747A/MAX3747B
2.7
RANDOM JITTER vs. INPUT AMPLITUDE
MAX3747A/MAX3747B toc08
800
3.0
RANDOM JITTER (psRMS)
DIFFERENTIAL OUTPUT (mVP-P)
900
700
RANDOM JITTER vs. TEMPERATURE
MAX3747A/MAX3747B toc07
1000
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80
TEMPERATURE (°C)
MAX3747A/MAX3747B toc09
70ps/div
0
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80
TEMPERATURE (°C)
1
10
100
1000
10,000
DIFFERENTIAL INPUT AMPLITUDE (mVP-P)
5
MAX3747A/MAX3747B
155Mbps to 3.2Gbps, Low-Power SFP
Limiting Amplifiers
Typical Operating Characteristics (continued)
(VCC = +3.3V, TA = +25°C, unless otherwise noted.)
5
6
7
8
9
10
100
1000
MAX3747A/MAX3747B toc12
20
15
VIN = 5mVP-P
10
LOS ASSERT/DEASSERT TIMES vs. INPUT
AMPLITUDE (LOW RTH1/RTH2 SETTINGS)
LOS ASSERT/DEASSERT TIMES vs. INPUT
AMPLITUDE (HIGH RTH1/RTH2 SETTINGS)
LOS ASSERT
20
15
LOS DEASSERT
10
MAX3747A/MAX3747B toc14
25
MAX3747B
LOS ASSERT/DEASSERT TIME (µs)
30
40
35
30
25
20
LOS DEASSERT
15
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80
TEMPERATURE (°C)
10,000
DIFFERENTIAL INPUT AMPLITUDE (mVP-P)
MAX3747A/MAX3747B toc13
LOS ASSERT
10
ASSERT/DEASSERT vs. VTH
120
5
0
0
200
400
600
800
0
1000 1200 1400
200
400
600
800
110
100
90
80
70
60
50
40
VTH (V) = VOLTAGE AT PIN 5 (V)
WITH RESPECT TO VCC
DEASSERT
ASSERT
30
20
10
0
1000 1200 1400
-1.4
-1.2
-1.0
-0.8
-0.6
-0.4
-0.2
0
INPUT AMPLITUDE (mVP-P)
INPUT AMPLITUDE (mVP-P)
VTH (V)
ASSERT/DEASSERT vs. TEMPERATURE
OUTPUT RETURN vs. FREQUENCY (SDD22)
(INPUT SIGNAL LEVEL = -60dBm)
INPUT RETURN vs. FREQUENCY (SDD11)
(INPUT SIGNAL LEVEL = -60dBm)
DEASSERT
15
ASSERT
5
0
20
10
0
-10
-10
-20
-20
-30
-30
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80
TEMPERATURE (°C)
MAX3747A/MAX3747B toc18
10
30
SDD11 (dB)
25
20
SDD22 (dB)
30
30
MAX3747A/MAX3747B toc16
VTH = -1.1V, FREQ = 2.7Gbps
PATTERN = PRBS 223 - 1
MAX3747A/MAX3747B toc17
LOS ASSERT/DEASSERT TIME (µs)
10
1
0
ASSERT/DEASSERT (mV)
25
0
DIFFERENTIAL INPUT AMPLITUDE (mVP-P)
5
6
30
MAX3747A/MAX3747B toc15
4
ASSERT/DEASSERT (mVP-P)
3
MAX3747B
10
5
FREQ = 3.2Gbps
PATTERN = K28.5
VIN = 500mVP-P
2
35
20
10
0
1
40
35
15
35
5
0
40
20
40
DETERMINISTIC JITTER (ps)
MICREL
SY88993V
3.2Gbps, K28.5 PATTERN
MAX3747A/MAX3747B toc11
MAXIM
MAX3747A/MAX3747B
25
DETERMINISTIC JITTER (psP-P)
MAX3747A/MAX3747B toc10
BIT-ERROR RATIO (10-12)
13,000
12,000
11,000
10,000
9000
8000
7000
6000
5000
4000
3000
2000
1000
1
DETERMINISTIC JITTER
vs. TEMPERATURE
DETERMINISTIC JITTER
vs. INPUT AMPLITUDE
BIT-ERROR RATIO vs. INPUT VOLTAGE
100
1000
FREQUENCY (MHz)
10,000
100
1000
10,000
FREQUENCY (MHz)
Maxim Integrated
MAX3747A/MAX3747B
155Mbps to 3.2Gbps, Low-Power SFP
Limiting Amplifiers
Pin Description
NAME
PIN
MAX3747A/
MAX3747B
FUNCTION
MICREL
SY8893V
Disable Function Pin. The data outputs are held static when this pin is asserted high,
transistor-to-transistor logic (TTL). The data outputs are enabled when this pin is held
low. LOS functions remain active when outputs are disabled. For normal operation
connect to GND.
1
DISABLE
EN
2
IN+
IN-
DIN
Noninverted Input Signal
3
DIN
Inverted Input Signal
4
VREF
VREF
Reference Voltage for LOS Threshold Setting
Loss-of-Signal Level Set. A voltage on this pin created by a two-resistor divider sets
the threshold level. Connect one resistor from this pin to VCC and another from this pin
to VREF (see Figure 5).
5
TH
LOSLVL
6
GND
GND
Ground
Loss of Signal. Open collector for the MAX3747A; internal 100kΩ pullup to VCC for the
MAX3747B. LOS is high when the level of the input signal drops below the preset
threshold set by the TH input. LOS is deasserted low when the signal level is above
the threshold.
7
LOS
LOS
8
OUT-
DOUT
9
OUT+
DOUT
10
VCC
VCC
Inverted Data Output, CML
Noninverted Data Output, CML
Positive Power Supply
Detailed Description
The limiting amplifiers consist of a multistage amplifier,
offset-correction circuitry, an output buffer, and loss-ofsignal detect circuitry (see the Functional Diagram).
VCC
MAX3747A
MAX3747B
Input Stage
The input stage is shown in Figure 3. It provides 50Ω termination to VREF for each input signal, IN+ and IN-. The
MAX3747A/MAX3747B should be AC-coupled.
Multistage Amplifier
ESD
STRUCTURES
The high-bandwidth multistage amplifier provides approximately 61dB of gain for the MAX3747A/MAX3747B.
Offset Correction Loop
The MAX3747A/MAX3747B are susceptible to DC offsets
in the signal path because they have high gain. In communication systems using NRZ data with a 50% duty
cycle, pulse-width distortion present in the signal or generated in the transimpedance amplifier appears as an input
offset and is reduced by the offset correction loop.
The offset correction loop sets a low-frequency cutoff of
3.2kHz.
Maxim Integrated
50Ω
50Ω
VREF
Figure 3. Differential Input Stage
7
MAX3747A/MAX3747B
155Mbps to 3.2Gbps, Low-Power SFP
Limiting Amplifiers
Functional Diagram
VCC
MAX3747A
MAX3747B
50Ω
50Ω
DIGITAL
OFFSET
CORRECTION
OUT+
OUT-
IN+
IN-
50Ω
DISABLE
50Ω
VREF
VREF
SIGNAL DETECT
VREF
TH
LOS
RTH1
RTH2
RTH1 + RTH2 ≥ 5kΩ
VCC
CML Output Buffer
The CML outputs of the MAX3747A/MAX3747B limiting
amplifiers provide high tolerance to impedance mismatches and inductive connectors. The output current
is approximately 16mA for the MAX3747A/MAX3747B.
Connecting the DISABLE pin to VCC disables the output. If the LOS pin is connected to the DISABLE pin,
the outputs OUT+ and OUT- are at a static voltage
(squelch) whenever the input signal level drops below
the LOS threshold. The output buffer can be AC- or DCcoupled to the load (Figure 4).
The MAX3747A/MAX3747B output is 800mVP-P.
VCC
50Ω
50Ω
OUT+
OUTDISABLE
Q3
Q4
Q1
Q2
ESD
STRUCTURES
DATA
DISABLE
DISABLE
Figure 4. CML Output Buffer
8
Maxim Integrated
MAX3747A/MAX3747B
155Mbps to 3.2Gbps, Low-Power SFP
Limiting Amplifiers
Loss-of-Signal Indicator
The MAX3747A/MAX3747B are equipped with LOS circuitry that indicates when the input signal is below a programmable threshold, set by a voltage on the TH pin
(see the Typical Operating Characteristics). The voltage
on the TH pin is set by two resistors, one connecting
from the TH pin to VCC and the other connecting from TH
to VREF (Figure 5). An RMS power detector compares
the input signal amplitude with this threshold and feeds
the signal-detect information to the LOS output, which is
open collector. To prevent LOS chatter in the region of
the programmed threshold, approximately 2dB of hysteresis is built into the LOS assert/deassert function.
Once asserted, LOS is not deasserted until the input
amplitude rises to the required level. Figure 6 shows the
LOS output circuit.
VCC
Applications Information
Program the LOS Assert Threshold
Program the LOS assert threshold according to Figure
5. The combination of R TH1 and R TH2 should be
greater than or equal to 5kΩ, see the Assert/Deassert
vs. VTH graph in the Typical Operating Characteristics.
Select the Coupling Capacitor
When AC-coupling is desired, coupling capacitors CIN
and COUT should be selected to minimize the receiver’s deterministic jitter. Jitter is decreased as the input
low-frequency cutoff (fIN) is decreased:
fIN = 1/[2π(50)(CIN)]
For all applications, the recommended value for CIN
and COUT is 0.1µF, which provides fIN equal to 32kHz.
Refer to Application Note HFAN-1.1: Choosing ACCoupling Capacitors on the Maxim website
(www.maximintegrated.com).
RTH2
TH
RTH1
VREF
VTH = (RTH2 x (VREF - VCC)) / (RTH1 + RTH2)
VTH IS VCC REFERENCED
RTH1 + RTH2 ≥ 5kΩ
Figure 5. MAX3747A/MAX3747B LOS Threshold Circuit
VCC
*
LOS
ESD
STRUCTURE
*100kΩ PULLUP (MAX3747B ONLY)
Figure 6. MAX3747A/MAX3747B LOS Output Circuit
Maxim Integrated
9
MAX3747A/MAX3747B
155Mbps to 3.2Gbps, Low-Power SFP
Limiting Amplifiers
Pin Configuration
Chip Information
PROCESS: SiGe Bipolar
TOP VIEW
+
DISABLE 1
IN+
10 VCC
2
MAX3747A
MAX3747B
OUT+
8
OUT-
IN-
3
VREF
4
7
LOS
TH
5
6
GND
µMAX
10
9
Package Information
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but the
drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE NO.
LAND
PATTERN NO.
10 µMAX
U10CN+1
21-0061
90-0330
Maxim Integrated
MAX3747A/MAX3747B
155Mbps to 3.2Gbps, Low-Power SFP
Limiting Amplifiers
Revision History
REVISION
NUMBER
REVISION
DATE
0
5/05
Initial release
1
10/07
2
8/12
Release of the MAX3747B.
Removed MAX3747 from data sheet, updated Electrical Characteristics.
DESCRIPTION
PAGES
CHANGED
—
1–10
1–10
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent
licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and
max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 ________________________________ 11
© 2012 Maxim Integrated Products, Inc.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
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