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MAX38904A/B/C/D
1.7V to 5.5VIN, 2A Low-Noise LDO Linear
Regulators in TDFN and WLP
General Description
Benefits and Features
The MAX38904 is a 1.7V–5.5V VIN, low-noise linear regulator that delivers up to 2A of output current with only
5.1μVRMS of output noise from 10Hz to 100kHz. The regulator maintains ±1% output accuracy over a wide input voltage range, requiring only 100mV of input-to-output
headroom at full load. The 1.3mA no-load supply current is
independent of dropout voltage. The MAX38904A/B/C/D
have a 70Ω active discharge feature to quickly discharge
output capacitors.
● Delivers Flexible Operating Range
• 1.7V to 5.5V Input Voltage Range
• 0.6V to 5.0V Programmable Output Voltage
• 2A Maximum Output Current
• 100mV Maximum Dropout at 2A Load
• < 1.5μA Shutdown Supply Current
The output voltage on MAX38904B can be adjusted to a
value in the range of 0.6V to 5.0V by using two external
resistors. The MAX38904B also includes an active-high
POK signal for trouble-free load startup.
The MAX38904A has nine pin-selectable output voltages
1.2V, 1.5V, 1.8V, 2.5V, 3.0V, 3.1V, 3.3V, 4.0V, and 5V.
The wafer-level package (WLP) versions of the
MAX38904 are available as C and D variants. The
MAX38904C uses external feedback resistors for adjusting the output voltage, while the MAX38904D has factory
preset output voltages over the range of 0.7V to 5.0V in
50mV steps.
All versions include a programmable output soft-start rate,
output overcurrent, and thermal overload protection.
● Reduces Noise and Improves Accuracy
• ±1% DC Accuracy Over Load, Line, and
Temperature
• 5.1μVRMS Output Noise, 10Hz to 100kHz
• 1.3mA Quiescent Supply Current
• > 70dB PSRR at 10kHz
● Enables Ease-of-Use and Robust Protection
• Active Discharge of 70Ω at OUT
• Stable with 8μF (Min) Output Capacitance
• Programmable Soft-Start Rate
• Overcurrent and Overtemperature Protection
• Output-to-Input Reverse Current Protection
• Power-OK Status Pin
● Reduces Size, Improves Reliability
• 3mm x 3mm 14-pin TDFN Package and 2.2mm x
1.37mm, 5 x 3 Bump, 0.4mm Pitch WLP
• -40ºC to 125ºC Operating Temperature
The MAX38904A/B are offered in a 3mm x 3mm, 14-pin
TDFN package, while the MAX38904C/D are available in
5 x 3 bump, 2.2mm x 1.37mm WLP, 0.4mm pitch.
Applications
● Communication Systems, Test Equipment, Medical
Equipment
● High-End Audio Systems
● High-Resolution Data Acquisition Systems
Ordering Information appears at end of data sheet.
19-100443; Rev 8; 6/22
© 2022 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.
One Analog Way, Wilmington, MA 01887 U.S.A. | Tel: 781.329.4700 | © 2022 Analog Devices, Inc. All rights reserved.
MAX38904A/B/C/D
1.7V to 5.5VIN, 2A Low-Noise LDO Linear
Regulators in TDFN and WLP
Simplified Block Diagram
VIN
(1.7V TO 5.5V)
IN
VOUT
(1.5V/2A)
OUT
CBYP
47nF
CIN
22µF
GND
COUT
22µF
R3
100k
BYP
MAX38904B
ENABLE
EN
POK
RESETB
R1
90k
GS
EP
FB
R2
60k
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Analog Devices | 2
MAX38904A/B/C/D
1.7V to 5.5VIN, 2A Low-Noise LDO Linear
Regulators in TDFN and WLP
Absolute Maximum Ratings
IN, OUT, SELA, SELB, EN, POK, OUTS, FB, GS to GND ..-0.3V
to +6V
BYP .......................................................................... -0.3V to +2V
Output Short-Circuit Duration ..................................... Continuous
Continuous Power Dissipation TDFN (TA = +70°C, derate ..........
24.4mW/°C above +70°C.) ............................................. 1951mW
Continuous Power Dissipation WLP (TA = +70°C, derate ............
16.4mW/°C above +70°C.) .............................................1312mW
Operating Temperature Range ...........................-40°C to +125°C
Maximum Junction Temperature ...................................... +150°C
Storage Temperature Range .............................. -65ºC to +150ºC
Soldering Temperature (reflow) ........................................ +260ºC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the
device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Package Information
14 TDFN
Package Code
T1433+2C
Outline Number
21-0137
Land Pattern Number
90-0063
THERMAL RESISTANCE, SINGLE-LAYER BOARD
Junction to Ambient (θJA)
54°C/W
Junction to Case (θJC)
8°C/W
THERMAL RESISTANCE, FOUR-LAYER BOARD
Junction to Ambient (θJA)
41°C/W
Junction to Case (θJC)
8°C/W
WLP
Package Code
N151B2+1
Outline Number
21-100315
Land Pattern Number
Refer to Application Note 1891
THERMAL RESISTANCE, FOUR-LAYER BOARD
Junction to Ambient (θJA)
61.55°C/W
Junction to Case (θJC)
N/A
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages.
Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different
suffix character, but the drawing pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a
four-layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/
thermal-tutorial.
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Analog Devices | 3
MAX38904A/B/C/D
1.7V to 5.5VIN, 2A Low-Noise LDO Linear
Regulators in TDFN and WLP
Electrical Characteristics
(VIN = 3.6V, TJ = -40°C to +125°C, CBYP = 47nF, CIN = 22μF, COUT = 22μF, Typical Operating Circuit, unless otherwise specified.
(Note 1))
PARAMETER
Input Voltage Range
SYMBOL
MIN
Guaranteed by Output Accuracy
1.7
VUVLO
VIN rising, 100mV hysteresis
1.5
Output Voltage Range
VOUT
VIN > VOUT + 0.1V
0.6
Output Capacitance
COUT
For stability and proper operation
Input Undervoltage
Lockout
VIN
CONDITIONS
8
VEN = VIN = 3.6V, IOUT = 0mA
Supply Current
FB Regulation Accuracy
(MAX38904B/C Only)
OUT Regulation
Accuracy (MAX38904A/
D Only)
IIN
VEN = 0V
1.5
0.594
ACC
IOUT from 0.1mA to 2A, VIN from VOUT +
0.3V to 5.5V, VIN > 1.7V
-1
Load Transient
Output Voltage deviation with a load
change of IOUT = 50mA to 2.0A to 50mA,
with tRISE = tFALL = 1μs
Line Regulation
VIN from 2.8V to 5.5V, VOUT = 2.5V,
IOUT = 800mA
Line Transient
VIN = 4V to 5V to 4V, IOUT = 2A, tRISE =
tFALL = 5µs
Active Discharge
Resistance
RDIS
1.7
V
0.6
1.5
μA
0.606
V
+1
%
0.032
%
50
mVP-P
0.054
%/V
3
mVP-P
100
VIN = 3.6V WLP
34
100
VIN = 2.5V TDFN
(Note 3)
65
200
VIN = 2.5V WLP
(Note 3)
44
200
VIN = 1.7V TDFN
100
300
VIN = 1.7V WLP
73
300
mV
VEN = 0V
70
Output Noise
IOUT = 100mA,
CBYP = 100nF
Power Supply Rejection
Ratio
PSRR
VIN = VOUT +
400mV, IOUT =
1.6A
BYP Capacitor Range
CBYP
Regulator Remain Stable
2.2
2.8
f = 10Hz to 100kHz
5.1
f = 1kHz
70
f = 10kHz
70
f = 100kHz
60
f = 1MHz
From BYP to GND during startup
V
μF
47
VOUT = 95% of Regulation, VIN = 3.6V,
(For TDFN, VIN - VOUT = 0.5V. For WLP,
VIN - VOUT = 0.4V.)
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V
VIN = 3.6V TDFN
Current Limit
BYP Soft-Start Current
5.5
5.0
TA = 125°C
VIN = 2.8V, VOUT = 2.5V, IOUT from
0.1mA to 2A
UNITS
22
0.04
Load Regulation
MAX
1300
ACC
IOUT = 2A
1.6
TA = +25°C
IOUT from 0.1mA to 2A, VIN from VOUT +
0.3V to 5.5V, VIN > 1.7V
Dropout Voltage
(Note 2)
TYP
Ω
3.4
A
μVRMS
dB
40
0.001
0.1
50
μF
μA
Analog Devices | 4
MAX38904A/B/C/D
1.7V to 5.5VIN, 2A Low-Noise LDO Linear
Regulators in TDFN and WLP
Electrical Characteristics (continued)
(VIN = 3.6V, TJ = -40°C to +125°C, CBYP = 47nF, CIN = 22μF, COUT = 22μF, Typical Operating Circuit, unless otherwise specified.
(Note 1))
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
0.8
1.2
EN Input Threshold
VIN from 1.7V to
5.5V
EN rising
EN falling
0.4
0.7
EN Input Leakage
Current
VEN from 1.7V to
5.5V
TA = +25ºC
-1
+0.001
POK Threshold
(MAX38904B Only)
VOUT when POK
switches
VOUT rising
POK Voltage, Low
(MAX38904B Only)
VOL
POK Leakage Current
(MAX38904B Only)
RINSELA/B
SELA/B Input
Capacitance
(MAX38904A Only)
CINSELA/B
IN Reverse-Current
Threshold
IIN_REV
Thermal Shutdown
Threshold
88
VOUT falling
TA = +25°C
91
-0.1
10
100
+0.001
+0.1
0.01
When shorted to GND or IN
500
1
10
VOUT = 3.6V, when VIN falls to 0V
V
μA
%
mV
μA
Ω
MΩ
When Hi-Z
TJ when output
turns on/off
94
88
TA = +125°C
When Hi-Z
+1
0.01
IPOK = 1mA
VPOK = 5.5V
SELA/B Input
Resistance
(MAX38904A Only)
TA = +125°C
UNITS
800
TJ rising
165
TJ falling
150
pF
mA
ºC
Note 1: Limits over the specified operating temperature and supply voltage range are guaranteed by design and characterization, and
production tested at room temperature only.
Note 2: Dropout voltage is defined as (VIN - VOUT) when VOUT is 95% of its nominal value.
Note 3: Guaranteed by design and characterization.
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Analog Devices | 5
MAX38904A/B/C/D
1.7V to 5.5VIN, 2A Low-Noise LDO Linear
Regulators in TDFN and WLP
Typical Operating Characteristics
(MAX38904BATD+, VIN = 3.6V, VOUT = 2.5V, CBYP = 47nF, CIN = 22μF, COUT = 22μF, TA = 25ºC, unless otherwise noted)
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Analog Devices | 6
MAX38904A/B/C/D
1.7V to 5.5VIN, 2A Low-Noise LDO Linear
Regulators in TDFN and WLP
Pin Configurations
MAX38904A
IN
1
14
OUT
IN
2
13
OUT
IN
3
12
OUT
IN
4
11
OUT
GND
5
10
BYP
EN
6
9
OUTS
SELA
7
8
SELB
EXPOSED PAD
3mm x 3mm 14LD TDFN
TOP VIEW
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Analog Devices | 7
MAX38904A/B/C/D
1.7V to 5.5VIN, 2A Low-Noise LDO Linear
Regulators in TDFN and WLP
MAX38904B
IN
1
14
OUT
IN
2
13
OUT
IN
3
12
OUT
IN
4
11
OUT
GND
5
10
BYP
EN
6
9
FB
GS
7
8
POK
EXPOSED PAD
3mm x 3mm 14LD TDFN
TOP VIEW
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Analog Devices | 8
MAX38904A/B/C/D
1.7V to 5.5VIN, 2A Low-Noise LDO Linear
Regulators in TDFN and WLP
MAX38904C
1
2
3
4
5
A
IN
IN
IN
IN
EN
B
GND
GND
GND
GND
FB
C
OUT
OUT
OUT
OUT
BYP
3 x 5 BUMP 0.4mm PITCH WLP
TOP VIEW
MAX38904D
1
2
3
4
5
A
IN
IN
IN
IN
EN
B
GND
GND
GND
GND
OUTS
C
OUT
OUT
OUT
OUT
BYP
3 x 5 BUMP 0.4mm PITCH WLP
TOP VIEW
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Analog Devices | 9
MAX38904A/B/C/D
1.7V to 5.5VIN, 2A Low-Noise LDO Linear
Regulators in TDFN and WLP
Pin Description
PIN
NAME
MAX38904A
MAX38904B
MAX38904C
MAX38904D
1, 2, 3, 4
1, 2, 3, 4
A1, A2, A3,
A4
A1, A2, A3,
A4
IN
5
5
B1, B2, B3,
B4
B1, B2, B3,
B4
GND
6
6
A5
A5
Output Select Input. Connect to GND, IN, or Hi-Z
to select one of three states. The state of the
SELA and SELB pins are read when the device is
enabled and used to select one of nine output
voltages.
-
-
SELA
-
7
-
-
GS
-
-
Regulator Ground. Bring IN and OUT bypass
capacitor GND connections to this pin for best
performance.
EN
-
-
Regulator Supply Input. Connect to a voltage
between 1.7V and 5.5V and bypass with a 22μF
capacitor from IN to GND.
Enable Input. Connect this pin to a logic signal to
enable (VEN high) or disable (VEN low) the
regulator output. Connect to IN to keep the output
enable whenever a valid supply voltage is
present. When EN is pulled low or disabled,
output is shorted to GND through a 70Ω active
discharge circuit.
7
8
FUNCTION
Ground Sense. Connect GS to GND.
SELB
Output Select Input. Connect to GND, IN, or Hi-Z
to select one of three states. The state of the
SELA and SELB pins are read when the device is
enabled and used to select one of nine output
voltages.
-
8
-
-
POK
Active-High Power-OK Output. Connect a pullup
resistor from this pin to a supply to create a reset
signal that goes high after the regulator output
has reached its regulation voltage.
9
-
-
B5
OUTS
Output Voltage Sense Input. Connect to the load
at a point where accurate regulation is required to
eliminate resistive metal drops.
-
9
B5
-
FB
Feedback Divider Input. Connect a resistor
divider string from OUT to GND with the midpoint
tied to this pin to set the output voltage. In the
Typical Application Circuits, VOUT = 0.6V x (1 +
R2/R1).
10
10
C5
C5
BYP
Bypass Capacitor Input. Connect a 0.001μF to
0.1μF capacitor between OUT and BYP to reduce
output noise and set the regulator soft-start rate.
11, 12, 13, 14
11, 12, 13, 14
C1, C2, C3,
C4
C1, C2, C3,
C4
OUT
Regulator Output. Sources up to 2A at the output
regulation voltage. Bypass with a 22μF (8μF
minimum, including voltage derating) low ESR (<
0.03Ω) capacitor to GND.
EP
EP
—
—
EP
Exposed Pad (TDFN Only). Connect the exposed
pad to a ground plane with low thermal resistance
to ambient to provide best heat sinking.
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Analog Devices | 10
MAX38904A/B/C/D
1.7V to 5.5VIN, 2A Low-Noise LDO Linear
Regulators in TDFN and WLP
Simplified Functional Diagram
EN
IN
CURRENT
LIMIT
THERMAL
PROTECTION
REVERSE
CURRENT
PROTECTION
CONTROL
OUT
ACTIVE
DISCHARGE
BYP
BYP
REF
0.6V
MAX38904B ONLY
EA
MAX38904A
MAX38904B
MAX38904C
MAX38904D
POK
0.54V
MAX38904B/C ONLY
FB
OUTS
MAX38904A ONLY
MAX38904A/D
ONLY
SELA
VOLTAGE
SELB
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SELECT
GND
Analog Devices | 11
MAX38904A/B/C/D
1.7V to 5.5VIN, 2A Low-Noise LDO Linear
Regulators in TDFN and WLP
Detailed Description
The MAX38904 is a high-performance PMOS linear regulator that is optimized for low noise, high input supply rejection,
low dropout voltage, and small solution size. It can deliver up to a maximum load current of 2A while maintaining a low
dropout voltage of 47mV. An enable input allows the regulator to be powered up and down, while an internal soft-start
circuit controls the in-rush current at the input. SELA and SELB inputs are provided on A version for selecting one of nine
output voltages and a power-OK output is provided on the B version for system power-up sequencing.
Enable (EN)
The MAX38904 includes an enable pin (EN). Pull EN low to shut down the output, or drive EN high to enable the output.
If a separate shutdown signal is not available, connect EN to IN. When EN is pulled low or disabled, output is shorted to
GND through a 70Ω active discharge circuit.
Bypass (BYP)
The capacitor connected from BYP to OUT filters noise at the reference, feedback resistors and regulator input stage. It
provides a high speed feedback path for improved transient response. A 10nF capacitor rolls off noise at around 32Hz.
The slew rate of the output voltage during startup is also determined by the BYP capacitor. A 10nF capacitor sets the slew
rate to 5V/ms. This startup rate results in a 110mA slew current drawn from the input at startup to charge 22μF output
capacitance. The BYP capacitor value can be adjusted from 1nF to 100nF to change the startup slew rate according to
the following formula:
5V
10nF
StartupSlewRate = ms × C
BYP
where CBYP is in nF.
Note that this slew rate applies only at startup. Recovery from a short-circuit will occur at a slew rate approximately 500
times slower. Also, note that being a low-frequency filter node, BYP is sensitive to leakage. BYP leakage currents above
10nA cause measurable inaccuracy at the output and should be avoided.
Protection Features
The MAX38904 is fully protected from an output short-circuit by a current limiting and thermal overload circuit. If the
output is shorted to GND, the output current is limited to 2.8A (typ). Under these conditions, the device quickly heats up.
When the junction temperature reaches 165°C, a thermal limit circuit shuts the output device off. Once the device cools
to 150°C, the output turns back on in an attempt to reestablish regulation. If the fault persists, the output current cycles on
and off as the junction temperature slews between 150°C and 165°C. The MAX38904 is also protected against reverse
current when the output voltage is higher than the input. In the event that extra output capacitance is used at the output,
a power down transient at the input would normally cause a large reverse-current through a conventional regulator. The
MAX38904 includes a reverse-voltage detector that trips when IN drops 10mV below OUT shutting off the regulator and
opening the PMOS body diode connection preventing any reverse current.
Active Discharge
When EN is pulled low, the MAX38904A/B/C/D connect a 70Ω resistor from OUT to GND in order to discharge the
output capacitors. This feature reduces time required to discharge the output capacitor, which simplifies system power
sequencing.
Output Voltage Configuration (MAX38904A)
The MAX38904A has two configuration pins, SELA and SELB, that are read during power-up to determine the output
regulation voltage.
Table 1. MAX38904A Output Configuration Table
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VOUT (V)
SELA
SELB
1.2
Hi-Z
IN
1.5
IN
Hi-Z
Analog Devices | 12
MAX38904A/B/C/D
1.7V to 5.5VIN, 2A Low-Noise LDO Linear
Regulators in TDFN and WLP
Table 1. MAX38904A Output Configuration Table (continued)
VOUT (V)
SELA
SELB
1.8
Hi-Z
GND
2.5
Hi-Z
Hi-Z
3.0
GND
GND
3.1
GND
IN
3.3
GND
Hi-Z
4.0
IN
GND
5.0
IN
IN
Output Voltage Configuration (MAX38904B/C)
The MAX38904B and MAX38904C use external feedback resistors to set the output regulation voltage as shown in the
Typical Operating Circuit. The output voltage can be set form 0.6V to 5.0V. Set the lower feedback resistor R1 to 300kΩ
or less to minimize FB input bias current error. Then, calculate the value of the upper feedback resistor R2 as follows:
VOUT
R2 = R1 × ( V
− 1)
FB
where VFB is the feedback regulation voltage of 0.6V. To set the output to 2.4V, for example, R2 should be:
24V
R2 = 300kΩ × ( 0.6V − 1) = 900kΩ
Output Voltage Configuration (MAX38904D)
The MAX38904D output voltage comes preprogrammed from the factory. Any output voltage between 0.7V and 5.0V
in 50mV steps can be factory programmed and special ordered. See the Ordering Information table for available output
voltages. Contact an Analog Devices representative to order preprogrammed parts.
Power-OK (MAX38904B)
The MAX38904B includes an additional open-drain output, POK, that goes high to indicate the output voltage is in
regulation. Connect a pullup resistor from this pin to an external supply. During startup, POK stays low until the output
voltage rises to 91% (typ) of its regulation level. If an overload event occurs at the output, or the output is shutdown, POK
goes low.
Input Capacitor
A 22μF ceramic capacitor is recommended for the input. Select a capacitor that does not degrade significantly over
temperature and DC bias. Capacitors with X5R or X7R temperature characteristics generally perform well.
Output Capacitor
A minimum of 8μF capacitance is required at OUT to ensure stable operation. Select a ceramic capacitor that maintains
its capacitance (8μF minimum) over temperature and DC bias. Capacitors with X5R or X7R temperature characteristics
generally perform well.
Thermal Considerations
The MAX38904 is packaged in a 14-pin 3mm x 3mm TDFN package with an exposed paddle. The exposed paddle is the
main thermal path for heat to escape the IC, and therefore, must be connected to a ground plane with thermal vias to
allow heat to dissipate from the device. Thermal properties of the package are given in the Package Information section.
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Analog Devices | 13
MAX38904A/B/C/D
1.7V to 5.5VIN, 2A Low-Noise LDO Linear
Regulators in TDFN and WLP
Typical Application Circuits
VIN
(1.7V TO 5.5V)
IN
VOUT
1.2V-5.0V
OUT
CBYP
47nF
CIN
22µF
GND
COUT
22µF
BYP
MAX38904A
TDFN
ENABLE
EN
OUTS
SELB
VOUT SELECT:
TO GND,
IN OR FLOAT
SELA
VIN
(1.7V TO 5.5V)
EP
IN
OUT
CIN
22µF
CBYP
47nF
GND
COUT
22µF
BYP
MAX38904B
ENABLE
EN
VOUT
ADJUSTABLE
(0.6V – 5.0V)
R3
100k
TDFN
RESETB
POK
R1
GS
FB
EP
R2
VIN
(1.7V TO 5.5V)
IN
CIN
22µF
CBYP
47nF
MAX38904C
GND
VOUT
ADJUSTABLE
(0.6V – 5.0V)
OUT
WLP
COUT
22µF
BYP
R1
ENABLE
EN
FB
R2
VIN
(1.7V TO 5.5V)
IN
CIN
22µF
MAX38904D
GND
ENABLE
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OUT
EN
WLP
CBYP
47nF
VOUT
FACTORY
COUT PROGRAMMED
22µF
BYP
OUTS
Analog Devices | 14
MAX38904A/B/C/D
1.7V to 5.5VIN, 2A Low-Noise LDO Linear
Regulators in TDFN and WLP
Ordering Information
TEMP
RANGE
PIN-PACKAGE
FEATURES
MAX38904AATD+
-40°C to
+125°C
14-pin, 3mm x 3mm, TDFN
Pin-Selectable Output Voltage, Enable
MAX38904BATD+
-40°C to
+125°C
14-pin, 3mm x 3mm, TDFN
External Resistor Feedback, POK Output with Delay,
Enable
MAX38904CANL+
-40°C to
+125°C
15-bump, 5 x 3, 0.4mm pitch,
WLP
External Resistor Feedback, Enable
MAX38904DANL__*
-40°C to
+125°C
15-bump, 5 x 3, 0.4mm pitch,
WLP
Factory Programmed from 0.7V to 5V in 50mV Steps
MAX38904DANL15+
-40°C to
+125°C
15-bump, 5 x 3, 0.4mm pitch,
WLP
Factory Programmed to 1.5V, Enable
MAX38904DANL50+T
-40°C to
+125°C
15-bump, 5 x 3, 0.4mm pitch,
WLP
Factory Programmed to 5.0V, Enable
MAX38904DANL37+T
-40°C to
+125°C
15-bump, 5 x 3, 0.4mm pitch,
WLP
Factory Programmed to 3.7V, Enable
PART NUMBER
+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
*Contact Analog Devices representative for factory preprogrammed output voltages.
www.analog.com
Analog Devices | 15
MAX38904A/B/C/D
1.7V to 5.5VIN, 2A Low-Noise LDO Linear
Regulators in TDFN and WLP
Revision History
REVISION
NUMBER
REVISION
DATE
PAGES
CHANGED
0
11/18
Initial release
1
12/18
Updated title of data sheet and Ordering Information
1–16
2
3/19
Updated Table 2 and Ordering Information
14, 16
3
5/19
Updated Electrical Characteristics and Typical Operating Characteristics
4
1/20
Updated Electrical Characteristics
5
4/20
Corrected Functional Diagram
6
5/21
Updated Detailed Description and Ordering Information
7
2/22
Updated General Description section, Benefits and Features section, Electrical
Characteristics table, Pin Description Table, Simplified Functional Block Diagram, Enable
(EN) section, and added Active Discharge section in Detailed Description
8
6/22
Updated Ordering Information table
DESCRIPTION
—
4, 6
4
10
13, 15
1, 4, 10–12
15
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is
assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may
result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of
their respective owners.
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