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MAX41463/MAX41464
General Description
The MAX41463/MAX41464 is a UHF sub-GHz ISM/SRD
transmitter designed to transmit Frequency-Shift Keying
(FSK), or Gaussian (G)FSK (or 2GFSK) data in the 286MHz
to 960MHz frequency range. It integrates a fractional phaselocked-loop (PLL) so that a single, low-cost crystal can be
used to generate commonly used world-wide sub-GHz
frequencies. The fast response time of the PLL allows for
frequency-hopping spread spectrum protocols for increased
range and security. The chip also features preset modes
with pin-selectable frequencies so that only one wire is
required for an external microcontroller interface. The only
frequency-dependent components required are for the
external antenna-matching network. A buffered clock-out
signal at 800kHz is also provided. Optionally, the device
can be put into programmable mode and programmed
using an I2C interface. The crystal-based architecture
of the MAX41463/MAX41464 eliminates many of the
common problems with SAW-based transmitters by
providing greater modulation depth, faster frequency
settling, higher tolerance of the transmit frequency, and
reduced temperature dependence.
The MAX41463/MAX41464 provides output power up
to +13dBm into a 50Ω load while drawing < 12mA at
315MHz. The output load can be adjusted to increase
power up to +16dBm, and a PA boost mode can be
enabled at frequencies above 850MHz to compensate for
losses. The PA output power can also be controlled using
programmable register settings in I2C mode.
The MAX41463/MAX41464 also features single-supply
operation from +1.8V to +3.6V. The device has an autoshutdown feature to extend battery life and a fast oscillator
wake-up with data activity detection.
300MHz–960MHz (G)FSK
Transmitter with I2C Interface
Benefits and Features
●● Low Implementation Cost
• Bits-to-RF Single Wire Operation
• Low Bill-of-Materials (BOM)
• Uses Single, Low-Cost, 16MHz Crystal
• Small 3mm x 3mm TSSOP10 Package
●● Increased Range, Data Rates, and Security
• Up to +16dBm PA Output Power
• Fast Frequency Switching for FHSS/DSSS
• Fast-On Oscillator: (tXO + tPLL)
DATA
> tTX
WAKEUP PULSE
TRANSMITTING
tXO
3.2 MHz
CLOCK
OSCILLATING
80 ms
OSCILLATING
CLKOUT
Figure 2. Wake-up timing diagram for preset mode
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Maxim Integrated │ 13
MAX41463/MAX41464
300MHz–960MHz (G)FSK
Transmitter with I2C Interface
Programmable Output Capacitance
Boost Mode
The PA can deliver up to 16dBm of output power.
High output power can be achieved in two ways:
●● Lower the load impedance for the PA by adjusting the
output matching network,
●● For frequencies over 850MHz, change the duty cycle
of the square wave driving the FET from 25% to 50%
by setting PA_BOOST = 1 in register SHDN (0x05)
and adjusting the output matching network.
Note that, when using PA_BOOST = 1, the maximum supply
voltage should not exceed 3V. For frequencies under
850MHz, the PA_BOOST bit should remain at 0, the output
match can be adjusted to provide higher output power.
The MAX41463/MAX41464 has an internal set of capacitors
that can be switched in and out to present different capacitor
values at the PA output. The capacitors are connected
from the PA output to ground. This allows changing the
tuning network along with the synthesizer divide ratio
each time the transmitted frequency changes, making it
possible to maintain maximum transmitter power while
moving rapidly from one frequency to another.
The variable capacitor is programmed through register
PA2 (0x07) bits 4:0 (PACAP). The tuning capacitor has a
nominal resolution of 0.18pF, from 0pF to 5.4pF. In preset
mode, the variable capacitor is set to 0pF.
PA
LODRV[7]
5 PACAP[4:0]
PA_BOOST
PAPWR[2:0]
3
LODRV[2]
FREQUENCY + DUTY CYCLE
GENERATOR
SYNTHESIZER
LODRV[1]
LODRV[0]
PAPWR[2:0] IS ON REGISTER PA1 (ADDRESS 0x06).
PACAP[4:0] IS ON REGISTER PA2 (ADDRESS 0x07).
Figure 3. Power Amplifier
Table 3. PA Load Impedance for Desired Output Power
FREQUENCY
OUTPUT POWER
PA LOAD IMPEDANCE
315MHz
13dBm
165Ω
315MHz
16dBm
(PA_BOOST = 0)
45Ω
434MHz
13dBm
180Ω
434MHz
16dBm
(PA_BOOST = 0)
57Ω
863MHz–928MHz
11dBm
190Ω
863MHz–928MHz
16dBm
(PA_BOOST = 1)
34Ω
Refer to the MAX4146x EV Kit User's Guide for details.
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Maxim Integrated │ 14
MAX41463/MAX41464
300MHz–960MHz (G)FSK
Transmitter with I2C Interface
Transmitter Power Control
Additional pulling can be calculated if the electrical
parameters of the crystal are known. The frequency pulling is given by:
The transmitter power of the MAX41463/MAX41464
can be set in approximately 2.5dB steps by setting
PAPWR[2:0] register bits using the I2C interface. The
transmitted power (and the transmitter current) can be
lowered by increasing the load impedance on the PA.
Conversely, the transmitted power can be increased by
lowering the load impedance.
fP
CM
(
1
1
)
= 2 C
−
× 106
CASE + CLOAD CCASE + CSPEC
where:
fP is the amount the crystal frequency pulled in ppm
Preset Mode Output Power
CM is the motional capacitance of the crystal
The output power of the PA in Preset mode (where both
SEL0 and SEL1 pins are not connected to GND) is always
set for maximum power level (PAPWR[2:0] = 0x7) for a
given load impedance. In order to adjust output power
levels in preset mode, the load impedance must be
adjusted accordingly.
CCASE is the case capacitance
CSPEC is the specified load capacitance
CLOAD is the load capacitance
When the crystal is loaded as specified (i.e., CLOAD =
CSPEC), the frequency pulling equals zero. For additional
details on crystal pulling and load capacitance affects,
refer to Maxim Tutorial 5422 - Crystal Calculations for ISM
RF Products.
Crystal (XTAL) Oscillator
The XTAL oscillator in the MAX41463/MAX41464 is
designed to present a capacitance of approximately 12pF
from the XTAL1 and XTAL2 pins to ground. In most cases,
this corresponds to a 6pF load capacitance applied to
the external crystal when typical PCB parasitics are
included. It is very important to use a crystal with a load
capacitance equal to the capacitance of the MAX41463/
MAX41464 crystal oscillator plus PCB parasitics. If a
crystal designed to oscillate with a different load
capacitance is used, the crystal is pulled away from its
stated operating frequency introducing an error in the
reference frequency. The crystal’s natural frequency is
typically below its specified frequency. However, when
loaded with the specified load capacitance, the crystal
is pulled and oscillates at its specified frequency. This
pulling is already accounted for in the specification of the
load capacitance. Accounting for typical board parasitics, a 16MHz, 12pF crystal is recommended. Note that
adding discrete capacitance on the crystal also increases
the startup time and adding too much capacitance could
prevent oscillation altogether.
Turn-On Time of Crystal Oscillator
The turn-on time of crystal oscillator (XO), tXO, is defined
as elapsed time from the instant of turning on XO circuit
to the first rising edge of XO divider clock output. The
external microcontroller turns on the XO by,
1) Sending a wakeup pulse for MAX41461–MAX41464
in the preset mode, or
2) Writing to device I2C address for MAX41461–
MAX41464 in the I2C mode, or
3) Pulling CSB pin low on the MAX41460.
Crystal Divider
The recommended crystal frequencies are 13.0
MHz, 16.0 MHz, and 19.2 MHz. An internal clock of
3.2MHz±0.1MHz frequency is required. To maintain the
internal 3.2MHz time base, XOCLKDIV[1:0] (register
CFG1, 0x00, bit 4) must be programmed, based on the
crystal frequency, as shown in the table below.
Table 4. Required Crystal Divider Programming
CRYSTAL FREQUENCY
CRYSTAL DIVIDER RATIO
XOCLKDIV[1:0]
13.0MHz
4
00
16.0MHz
5
01
19.2MHz
6
10
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Maxim Integrated │ 15
MAX41463/MAX41464
300MHz–960MHz (G)FSK
Transmitter with I2C Interface
Crystal Frequency in Preset Mode
For MAX41463/MAX41464 in preset mode (where both
SEL0 and SEL1 pins are not connected to GND), crystal
frequency must be 16MHz to ensure accurate output
frequency.
Phase-Locked Loop (PLL)
The MAX41463/MAX41464 utilizes a fully integrated
fractional-N PLL for its frequency synthesizer. All PLL
components, including loop filter, are included on-chip.
The synthesizer has a 16-bit fractional-N topology with
a divide ratio that can be set from 11 to 72, allowing
the transmit frequency to be adjusted in increments of
fXTAL/65536. The fractional-N architecture also allows
exact FSK frequency deviations to be programmed. FSK
deviations as low as ±1kHz and as high as ±100kHz can
be set by programming the appropriate registers.
The internal VCO can be tuned continuously from 286MHz
to 960MHz in normal mode, and from 286MHz–320MHz,
425MHz–480MHz, and 860MHz–960MHz in low phase
noise mode.
Frequency Programming
The desired frequency can be programmed by setting bits
FREQ in registers PLL3, PLL4, and PLL5 (0x0B, 0x0C,
0x0D). To calculate the FREQ bits, use:
FREQ[23 : 0] = ROUND
(
65536 x fC
fXTAL
)
Follow Table 4 to program the LODIV bits in register PLL1
(0x08) when choosing a LO frequency. It is recommended to leave bits CPVAL and CPLIN at factory defaults. If
integer-N synthesis is desired, set bit FRACMODE = 0 in
register PLL1.
Fractional-N Spurious
The 16-bit fractional-N, delta-sigma modulator can
produce spurious that can show up on the power amplifier
output spectrum. If slight frequency offsets can be tolerated,
set the LSB of FREQ (register PLL5, bit 0) to logic-high.
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Table 5. LODIV Setting
FREQUENCY RANGE
LODIV SETTING
286MHz–960MHz, Low Noise Mode
0x0
286MHz–320MHz, Low Phase Noise
0x3
425MHz–480MHz, Low Phase Noise
0x2
860MHz–960MHz, Low Phase Noise
0x1
Using an odd value (logic 1 at bit 0) of the 24-bit FREQ
register will produce lower PLL spurious compared to
even values (logic 0 at bit 0).
Turn-on Time of PLL
The turn-on time of PLL, tPLL, is defined as elapsed time
from the instant when the XO output is available to the
instant when PLL frequency acquisition is complete.
Two-Wire I2C Serial Interface
When pins SEL0 and SEL1 are grounded, the MAX41463/
MAX41464 features a 2-wire I2C-compatible serial
interface consisting of a serial-data line (SDA) and a
serial-clock line (SCL). SDA and SCL facilitate bidirectional
communication between the MAX41463/MAX41464 and
the master at clock frequencies up to 1MHz. The master
device initiates a data transfer on the bus and generates
the SCL signal to permit data transfer. The MAX41463/
MAX41464 functions as an I2C slave device that transfers
and receives data to and from the master. Pull SDA and
SCL high with external pull-up resistors of 1kΩ or greater,
referenced to VDD for proper I2C operation.
One bit transfers during each SCL clock cycle. A minimum
of nine clock cycles is required to transfer a byte into or
out of the MAX41463/MAX41464 (8 bits and an ACK/
NACK). The data on SDA must remain stable during the
high period of the SCL clock pulse. Changes in SDA while
SCL is high and stable are considered control signals (see
the START and STOP Conditions section). Both SDA and
SCL remain high when the bus is not busy.
Figure 4 and Figure 5 show I2C Write transaction and I2C
Read transaction protocols, respectively.
Maxim Integrated │ 16
MAX41463/MAX41464
300MHz–960MHz (G)FSK
Transmitter with I2C Interface
SCLK
S6 S5 S4 S3 S2 S1 S0
0
A
SDI
START
A7 A6 A5
DEVICE ADD
A4 A3 A2 A1 A0
A
D7 D6 D5 D4 D3 D2 D1 D0
REG ADD
R/W = 0
0
A
A
WR DATA
STOP
ACK FROM SLAVE
Figure 4. I2C Write
SCLK
S6 S5 S4 S3 S2 S1 S0 0 A
SDI
START
DEVICE ADD
R/W = 0
S6 S5 S4 S3 S2 S1 S0 1 A
A7 A6 A5 A4 A3 A2 A1 A0 A
REG ADD
0 A ACK FROM SLAVE
START
DEVICE ADD
R/W = 1
D7 D6 D5 D4 D3 D2 D1 D0 A
RD DATA
1
STOP
A ACK FROM MASTER
Figure 5. I2C Read
START and STOP Conditions
The master initiates a transmission with a START
condition (S), which is a high-to-low transition on SDA
while SCL is high. The master terminates a transmission
with a STOP condition (P), which is a low-to-high
transition on SDA while SCL is high.
Acknowledge and Not-Acknowledge Conditions
Data transfers are framed with an acknowledge bit (ACK)
or a not-acknowledge bit (NACK). Both the master and
the MAX41463/MAX41464 (slave) generate acknowledge
bits. To generate an acknowledge, the receiving device
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must pull SDA low before the rising edge of the acknowledgerelated clock pulse (ninth pulse) and keep it low during the
high period of the clock pulse.
To generate a not-acknowledge condition, the receiver
allows SDA to be pulled high before the rising edge of
the acknowledge-related clock pulse, and leaves SDA
high during the high period of the clock pulse. Monitoring
the acknowledge bits allows for detection of unsuccessful
data transfers. An unsuccessful data transfer happens if a
receiving device is busy or if a system fault has occurred.
In the event of an unsuccessful data transfer, the bus
master must reattempt communication at a later time.
Maxim Integrated │ 17
MAX41463/MAX41464
300MHz–960MHz (G)FSK
Transmitter with I2C Interface
Figure 6 illustrates I2C Burst Write transaction protocol.
Slave Address
The MAX41463/MAX41464 has a 7-bit I2C slave address
that must be sent to the device following a START
condition to initiate communication. The slave address is
internally programmed to 0xD2 for WRITE and 0xD3 for
READ. The MAX41463/MAX41464 continuously awaits
a START condition followed by its slave address. When
the device recognizes its slave address, it acknowledges
by pulling the SDA line low for one clock period, then it is
ready to accept or send data, depending on the R/W bit.
Write Cycle
When addressed with a write command, the MAX41463/
MAX41464 allows the master to write to either a single
register or to multiple successive registers.
A write cycle begins with the bus master issuing a START
condition, followed by the 7 slave address bits and a
write bit (R/W = 0). The MAX41463/MAX41464 issues an
ACK if the slave address byte is successfully received.
The bus master must then send the address of the first
register it wishes to write to (see Register Map). The slave
acknowledges the address and the master can then write
one byte to the register at the specified address. Data is
written beginning with the most significant bit (MSB). The
MAX41463/MAX41464 again issues an ACK if the data is
successfully written to the register.
The master can continue to write data to the successive internal registers with the MAX41463/MAX41464
acknowledging each successful transfer, or the master
can terminate transmission by issuing a STOP condition.
The write cycle does not terminate until the master issues
a STOP condition.
Read Cycle
When addressed with a read command, the MAX41463/
MAX41464 allows the master to read back a single
register or multiple successive registers.
A read cycle begins with the bus master issuing a START
condition, followed by the 7 slave address bits and a
write bit (R/W = 0). The device issues an ACK if the slave
address byte is successfully received. The bus master
must then send the address of the first register it wishes
to read. The slave acknowledges the address. A START
condition is then issued by the master, followed by the 7
slave address bits and a read bit (R/W = 1). The device
issues an ACK if the slave address byte is successfully
received. The device starts sending data MSB first with
each SCL clock cycle. At the 9th clock cycle, the master
can issue an ACK and continue to read successive
registers, or the master can terminate the transmission by
issuing a NACK. The read cycle does not terminate until
the master issues a STOP condition.
Buffered Clock Output
MAX41463/MAX41464 provides a buffered clock output
(CLKOUT) on pin 6 of the chip in the preset mode,
and the frequency of CLKOUT is 800kHz. In I2C mode,
MAX41463/MAX41464 uses pin 6 as the SCL line of the
I2C interface.
CLKOUT_DELAY[1:0] (register CFG2, address 0x01,
bits 7:6) is only used in the preset modes, with a preset
value of 0x02. These two register bits are not used in
programming mode.
SCLK
…..
S6 S5 S4 S3 S2 S1 S0 0 A
SDI
START
DEVICE ADDR
R/W = 0
A7 A6 A5 A4 A3 A2 A1 A0 A
REG ADDR
0 A
ACK FROM SLAVE
D7 D6 D5 D4 D3 D2 D1 D0 A
WR DATA TO ADDR
D7 D6 D5 D4 D3 D2 D1 D0 A
D7 D6 D5 D4 D3 D2 D1 D0 A
WR DATA TO ADDR+1
WR DATA TO ADDR+2
…..
….
D7 D6 D5 D4 D3 D2 D1 D0 A
WR DATA TO ADDR+N
STOP
NOTE: ADDRESS AUTO-INCREMENT
Figure 6. I2C Burst Write
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Maxim Integrated │ 18
MAX41463/MAX41464
300MHz–960MHz (G)FSK
Transmitter with I2C Interface
State Diagrams
In the preset mode, the MAX41463/MAX41464 device has
two major states: shutdown and transmitter-enabled.
In the shutdown state, the crystal oscillator (XO), the PLL
synthesizer, and the power amplifier (PA) are all turned
off.
In transmitter-enabled state, XO and PLL are turned on;
PA is turned on with a ramp-up process.
After power is applied, the device enters the shutdown
state. See Initial Programming. A rising edge on DATA
(pin 7) initiates the warm-up of the XO and PLL. After PLL
is locked, a falling edge on DATA enables the transmitter.
The device returns to shutdown state when there is no
DATA activity, i.e. DATA stays at 0 for 4096 cycles of the
internal 3.2MHz clock.
In the I2C programming mode, the device has four major
states: shutdown, programming, transmitter-enabled, and
standby.
●● Shutdown state: The crystal oscillator (XO), the PLL
synthesizer, and the power amplifier (PA) are all
turned off.
●● Programming state: XO and PLL are turned on; PA is
turned off.
●● Standby state: XO is turned on; PLL and PA are
turned off.
●● Transmitter-enabled state: XO and PLL are turned
on; PA is turned on with a ramp-up process.
A wakeup byte with 7-bit device address from the I2C bus
initiates the warm-up of the XO and PLL.
The device can support two types of I2C transactions:
register access only, and register access followed by
XO+PLL
WARM-UP
RISING DATA
POWER-ON-RESET
SHUTDOWN
XO CLOCK
AVAILABLE
data transmission. The event trigger of data transmission
is a rising edge on I2C_TXEN, which is a special signal
with two register-bit aliases I2C_TXEN1 (register CFG6,
0x0A, bit 2) and I2C_TXEN2 (register CFG7, 0x10, bit
2). A rising edge on I2C_TXEN can be generated by
clearing I2C_TXEN1 and setting I2C_TXEN2 in a single
I2C transaction.
I2C_TXEN is automatically cleared in two cases: 1) wakeup from shutdown, 2) return to programming state from
the transmitter-enabled state. In those two cases, a rising
edge on I2C_TXEN can be generated by setting I2C_
TXEN2 in CFG7, without explicit clearing of I2C_TXEN1.
Data to be transmitted are written into a special register,
byte I2C_TX_DATA[7:0] (register I2C3, 0x13, bits 7:0).
Automatic incrementing of addresses in I2C burst-write
are disabled for this special register. Each data byte
written into I2C_TX_DATA will be transferred into a FIFO
buffer. The device has an internal 1-bit signal FIFO_STOP.
At the end of data transmission, FIFO_STOP is set, and
the device references the PWDN_MODE[1:0] (register
CFG4, 0x03, bits 1:0) to enter shutdown, standby, or
programming state.
In both standby and shutdown states, programming
through the I2C interface is not allowed. The device will
exit the standby or shutdown state once its 7-bit I2C
address is received.
Initial Programming
After turning on power supply (or a soft reset), two I2C
transactions are required to initialize the PLL frequency
synthesizer. The first transaction ensures register ADDL2
at address 0x1A is written to its default of 0x80. The
second transaction burst-writes 20 consecutive registers
from address 0x00 to 0x13.
WAIT FOR PLL
SETTLING
FALLING
DATA
TX
ENABLED
SHUT-DOWN TIMER
TIMEOUT
PA RAMP
DOWN
Figure 7. State Diagram in Preset Mode
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Maxim Integrated │ 19
MAX41463/MAX41464
300MHz–960MHz (G)FSK
Transmitter with I2C Interface
Case 1: Using Two I2C Transactions for Startup from
Shutdown
The device needs to transmit an 8-bit dummy packet
for initial programming. The initial programming must
clear MODMODE (register CFG1, address 0x00, bit
0), clear I2C_TXEN1 (register CFG6, address 0x0A,
bit 2), configure FREQ[23:0] (register PLL3, PLL4 and
PLL5) to desired frequency, set I2C_TXEN2 (register
CFG7, address 0x10, bit 2), and configure I2C_TX_
DATA[7:0] (register I2C3, address 0x13) to 0x00. In
addition, BCLK_POSTDIV[2:0], BCLK_PREDIV[7:0], and
PKTLEN_MODE should be configured to default values
in the register map.
The startup of MAX41463/MAX41464 in programming
mode, from the shutdown state, uses two I2C transactions:
one for configuration update and the other for data
transmission. FSK modulation can only be enabled
through configuration update because the initial programming
must clear MODMODE (register CFG1, address 0x00, bit
0).
In the first I2C transaction, the master device burst-writes
consecutive registers that are a portion or all of the 16
registers from address 0x00 to 0x0F. Those consecutive
registers may or may not include CFG6. If CFG6 is
included, the I2C_TXEN1 bit should be cleared; otherwise,
I2C_TXEN1 is automatically cleared in the wake-up from
shutdown.
Initial programming cannot be completed by a single
burst-write transaction because the I2C_TX_DATA
register at address 0x13 is a special register that
disables automatic address increment. However, two I2C
transactions may be merged to a combined transaction,
where each write begins with a START mark and the
slave address.
In the second I2C transaction, the master device can
set I2C_TXEN2 (register CFG7, address 0x10, bit 2),
configure PKTLEN_MODE (register I2C1, address 0x11,
bit 7) and PKTLEN[14:0], and write the data to be
transmitted into I2C_TX_DATA (register I2C3, address
0x13). Automatic increment of register address during
burst write is disabled at address 0x13.
After initial programming, the device will enter the shutdown, standby, or programming state according to the
setting of PWDN_MODE[1:0] (register CFG4, address
0x03, bit[1:0] ). Configuration register values are retained
unless changed by programming.
Startup
The event-trigger for wake-up is the recognition of I2C
address of the device. The event trigger for data transmission is the rising edge I2C_TXEN that has two aliases
of I2C_TXEN1 and I2C_TXEN2. The time lag between
those two triggers must be longer than tXO+tPLL. To meet
this requirement, the master device can adjust the wait
time between the two I2C transactions.
Programming Mode
This section assumes that initial programming is done
after power on (or soft reset). Until the next time of power
off/on (or soft reset), configuration registers are retained
unless changed by programming.
PROGRAMMING
(PLL ON)
XO+PLL
WARM-UP
7-BIT ADDRESS
RECOGNIZED
POWER-ON-RESET
SHUTDOWN
FIFO STOP,
PWDN_MODE
== 2
RISING
I2C_TXEN
PA RAMP
DOWN
FIFO STOP,
PWDN_MODE
== 0
PLL ENABLED
TX
ENABLED
FIFO STOP,
PWDN_MODE
== 1
7-BIT ADDRESS
RECOGNIZED
PA RAMP
DOWN
STANDBY
(PLL OFF)
Figure 8. Simplified State Diagram in Programming Mode
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Maxim Integrated │ 20
MAX41463/MAX41464
300MHz–960MHz (G)FSK
Transmitter with I2C Interface
Case 2: Using a Single I2C Transaction for Startup
from Shutdown (Recommended for Use with I2C Fast
Mode)
bined I2C transaction with repeated START marks. In a
combined transaction, the master device can do multiple
read/write operations without losing control to other master
devices on the I2C bus. For example, the combined
transaction can have a burst-read operation followed by a
burst-write operation.
From shutdown state, the start up of device in programming mode may use a single I2C transaction to burstwrite consecutive registers starting from address 0x00.
Data to be transmitted are written into I2C_TX_DATA
(register I2C3, address 0x13). Automatic incrementing of
register addresses during burst-write is disabled at
address 0x13. The programming should clear I2C_
TXEN1 and set I2C_TXEN2.
In the burst-write operation, the master device should write
consecutive registers starting from CFG7 (address 0x10)
or any register preceding CFG7. Data to be transmitted
are written into I2C_TX_DATA (register I2C3, address
0x13). Automatic incrementing of register addressed
during burst-write is disabled at address 0x13. The
programming should set I2C_TXEN2 (and clear I2C_
TXEN1 if CFG6 is included in the registers to write).
The event-trigger for wake-up is the recognition of I2C
address of the device. The event-trigger for data transmission is the rising edge of I2C_TXEN that two aliases
of I2C_TXEN1 and I2C_TXEN2. The time lag between
those two triggers, here 162 cycles of SCL, must be
longer than tXO+tPLL. To meet this requirement, the fast
mode I2C speed with 400kHz SCL is recommended.
The event-trigger for wake-up is the recognition of device
address in the burst-read operation. The event-trigger for
data transmission is the rising edge of I2C_TXEN that has
two aliases of I2C_TXEN1 and I2C_TXEN2. The time lag
between those two triggers must be longer than tXO+tPLL.
To meet this requirement, the master device can adjust
the number of registers to read in the burst-read operation.
Case 3: Using a Combined I2C Transactions for
Startup from Shutdown (Recommended for Most I2C
Clock Rates)
From shutdown state, the start up of MAX41463/
MAX41464 in programming mode can use a com-
SHUTDOWN
DEVICE
ADDR
DEVICE
ADDR
SDA
BYTE
+ACK
PROGRAMMING
1ST
DATA
BYTE
SET
TXEN
BYTE BYTE BYTE
+ACK +ACK +ACK
BYTE
+ACK
BYTE
+ACK
BYTE
+ACK
CFG7
I2C1
I2C2
I2C3
> (tXO + tPLL)
...
Figure 9. Using two I2C transactions to start data transmission from the shutdown state.
SHUTDOWN
DEVICE
ADDR
SDA
BYTE
+ACK
CLEAR
TXEN
BYTE
+ACK
BYTE
+ACK
CFG1
...
1ST
DATA
BYTE
SET
TXEN
BYTE
+ACK
...
BYTE
+ACK
BYTE
+ACK
BYTE
+ACK
BYTE
+ACK
CFG6
PLL3~7
CFG7
I2C1
I2C2
I2C3
...
> (tXO + tPLL)
Figure 10. Using a single I2C transaction to start data transmission from the shutdown state.
www.maximintegrated.com
Maxim Integrated │ 21
MAX41463/MAX41464
300MHz–960MHz (G)FSK
Transmitter with I2C Interface
Case 4: Using a Single I2C Transaction for Startup
from Standby (recommended for use with I2C Fastmode and I2C Fast-mode Plus)
Case 5: Using a Single I2C Transaction for Startup
from Programming Mode
The MAX41463/MAX41464 device can transmit a
data packet each time in the transmitter-enabled state.
After data transmission, the device refers to the setting
of PWDN_MODE[1:0] to enter the shutdown, standby, or
programming state. If the next data packet requires fast
start-up, PWDN_MODE[1:0] can be configured to 2 so
that the device returns to the programming state.
From standby state, the start-up of MAX41463/MAX41464
in programming mode can use a single I2C transaction
to burst-write consecutive registers starting from CFG6
(address 0x0A) or any register preceding CFG6. Data
to be transmitted are written into I2C_TX_DATA (register
I2C3, address 0x13). Automatic incrementing of register addresses during burst-write is disabled at address
0x13. The programming should clear I2C_TXEN1 and
set I2C_TXEN2.
Then, the master device can use a single I2C transaction
to burst-write consecutive registers starting from CFG7
(address 0x10) or any register preceding CFG7. Data to
be transmitted are written into I2C_TX_DATA (register
I2C3, address 0x13). Automatic incrementing of register addresses during burst-write is disabled at address
0x13. The programming should set I2C_TXEN2 (and
clear I2C_TXEN1 if CFG6 is included in the registers to
write). There is no restrictions arising from tXO and tPLL.
The event-trigger for wake-up is the recognition of I2C
address of the device. The event-trigger for data transmission is the rising edge of I2C_TXEN that two aliases
of I2C_TXEN1 and I2C_TXEN2. The time lag between
those two triggers, here ≥ 72 cycles of SCL, must be longer than tPLL for startup from standby. This requirement is
met for the fast-mode I2C with 400kHz SCL. In the case of
Fast-mode Plus, I2C with 1MHz SCL, the master device
can burst-write registers starting from PLL1.
SHUTDOWN
DEVICE
ADDR
SDA
BYTE
+ACK
REG
READ
1ST
DATA
BYTE
SET
TXEN
DEVICE
ADDR
BYTE BYTE
BYTE
OPTIONAL
+ACK +ACK
+ACK
CFG7
BYTE
+ACK
I2C1
BYTE
+ACK
I2C2
BYTE
+ACK
I2C3
...
> (tXO + tPLL)
Figure 11. Using a Combined I2C Transaction to Start Data Transmission from the Shutdown State.
STANDBY
CLEAR
TXEN
DEVICE
ADDR
SDA
BYTE
+ACK
BYTE
OPTIONAL
+ACK
1ST
DATA
BYTE
SET
TXEN
BYTE
+ACK
...
BYTE
+ACK
BYTE
+ACK
BYTE
+ACK
BYTE
+ACK
CFG6
PLL3~7
CFG7
I2C1
I2C2
I2C3
...
> tPLL
Figure 12. Using a Single I2C Transaction to Start Data Transmission from the Standby State.
PROGRAMMING STATE
SDA
DEVICE
ADDR
BYTE
+ACK
1ST
DATA
BYTE
SET
TXEN
BYTE
+ACK
OPTIONAL
BYTE
+ACK
BYTE
+ACK
BYTE
+ACK
BYTE
+ACK
CFG7
I2C1
I2C2
I2C3
...
Figure 13. Using a Single I2C Transaction to Start Data Transmission from the Programming State.
www.maximintegrated.com
Maxim Integrated │ 22
MAX41463/MAX41464
FIFO Buffer
The I2C interface is a bus connected to multiple master or
slave devices. The microcontroller is a master device and
the MAX41463/MAX41464 is a slave device. The microcontroller can initiate communication with the slave device
by I2C addressing (e.g., sending a START mark followed
by 7-bit device address). The slave device is required to
acknowledge every byte transferred through I2C.
For data transmission, the microcontroller can burstwrite consecutive registers, including CFG7 and I2C3.
The purpose of writing CFG7 is to set I2C_TXEN2 and,
therefore, generate a trigger to enable the transmitter.
Automatic increment of register address in I2C burst-write
is disabled for the I2C3 register, which is also named
I2C_TX_DATA. Once the transmitter is enabled, all bytes
written to I2C_TX_DATA are moved into a FIFO buffer.
The buffer size is 4 bytes. The FIFO buffer is enabled only
in the transmitter-enabled state.
A programmable baud-rate clock is used for retrieving
and transmitting bits from the FIFO buffer. The baud rate
is programmable by BCLK_PREDIV[7:0] (register CFG3,
0x02, bits 7:0) and BCLK_POSTDIV[2:0] (register CFG2,
0x01, bits 2:0) as the following expression:
BaudRate =
fCLK
2 × (1 + BCLK_PREDIV) × 2BCLK_POSTDIV
where fCLK is the crystal-divider output clock rate (nominally, 3.2 MHz). Valid values of BCLK_PREDIV are from
3 to 255. Valid values of BCLK_POSTDIV are from 1 to 5.
To avoid underflow of the FIFO buffer, the baud-rate
must be lower than 8/9 of the SCL clock rate. The
device can support three modes of SCL clock frequencies:
100kHz, 400kHz, and 1MHz. In the 100kHz mode, it is
recommended to limit baud-rate to no more than 50kbps.
A FIFO overflow is avoided by utilizing the I2C clock
stretching mechanism. Clock stretching is done before the
ACK bit. There is no clock-stretching timeout.
Each time before data transmission, the I2C1 and I2C2
registers are configured to specify PKTLEN_MODE and
PKTLEN[14:0]. Data transmission stops when PKTLEN_
MODE is set and the number of bauds transmitted is
equal to PKTLEN[14:0]. Data transmission also stops at
www.maximintegrated.com
300MHz–960MHz (G)FSK
Transmitter with I2C Interface
FIFO underflow or overflow. An internal 1-bit flag FIFO_
STOP is set at the end of data transmission. The rising
edge of FIFO_STOP serves as the event trigger to disable
the transmitter. See the State Diagrams section.
When the number of bauds to be transmitted is known
before data transmission and less than 32768, it is
recommended to set PKTLEN_MODE and configure
PKTLEN[14:0] as the number of bauds to be transmitted.
Otherwise, clear PKTLEN_MODE and utilize FIFO underflow to stop data transmission. Once the microcontroller
stops writing I2C_TX_DATA, FIFO underflow will occur
after the data stored in FIFO buffer are transmitted.
Read-only register I2C4, I2C5, and I2C6 are provided to
report diagnostic information for the FIFO buffer.
Frequency Hopping
In programming mode, the frequency synthesizer is
initialized to a frequency in a selected ISM band by Initial
Programming. After that, for the purpose of frequency
dithering or frequency hopping, the FREQ[23:0] registers
can be updated to a new frequency in the same selected
band for each data packet to be transmitted.
Because programming is not allowed in the transmittedenabled state (see the State Diagrams section),
frequency configuration cannot be changed when PA is
enabled. See the Startup section for details on how to
program the device for data transmission.
After transmitting a data packet, the device enters the
shutdown, standby, or programming states according
to the setting of PWDN_MODE[1:0] register. The three
options have different startup times for transmitting the
next data packet.
The startup time from shutdown is at least (tXO + tPLL +
tTX), where tXO is the turn-on time of crystal oscillator,
tPLL is the turn-on time of PLL, tTX is the turn-on time of
transmitter.
The startup time from standby is at least (tPLL + tTX).
The tTX time is 27 cycles of the SCL clock plus 2 cycles
of the baud-rate clock. For example, the SCL clock rate
is 1MHz, the baud rate is 100kbps, the value of tTX is
47μs. Refer to the Electrical Characteristics for typical
values of tXO and tPLL.
Maxim Integrated │ 23
MAX41463/MAX41464
300MHz–960MHz (G)FSK
Transmitter with I2C Interface
Register Map
ADDRESS
NAME
MSB
LSB
TX
0x00
CFG1[7:0]
XOCLKDELAY[1:0]
0x01
CFG2[7:0]
CLKOUT_
DELAY[1:0]
0x02
CFG3[7:0]
0x03
CFG4[7:0]
–
–
0x04
CFG5[7:0]
–
–
0x05
SHDN[7:0]
–
–
0x06
PA1[7:0]
0x07
PA2[7:0]
XOCLKDIV[1:0]
–
FSKSHAPE
–
–
–
BCLK_PREDIV[7:0]
–
–
–
–
–
–
–
–
–
RERESERVED SERVED
–
PACAP[4:0]
CPLIN[1:0]
0x09
PLL2[7:0]
RERESERVED SERVED
–
–
–
–
0x0A
CFG6[7:0]
–
–
–
I2C_
TXEN1
0x0B
PLL3[7:0]
FREQ[23:16]
0x0C
PLL4[7:0]
FREQ[15:8]
0x0D
PLL5[7:0]
FREQ[7:0]
0x0E
PLL6[7:0]
–
0x0F
PLL7[7:0]
–
–
–
–
0x10
CFG7[7:0]
–
–
–
–
0x11
I2C1[7:0]
PKTLEN_
MODE
0x12
I2C2[7:0]
0x13
I2C3[7:0]
–
RESERVED[1:0]
–
RESERVED
I2C_
TXEN2
RESERVED
RESERVED
I2C_TX_DATA[7:0]
PKTCOMPLETE
0x16
I2C6[7:0]
UFLOW
OFLOW
FIFO_
EMPTY
FIFO_
FULL
–
0x17
CFG8[7:0]
–
–
–
–
–
www.maximintegrated.com
RESERVED
PKTLEN[7:0]
I2C5[7:0]
ADDL2[7:0]
CPVAL[1:0]
PKTLEN[14:8]
0x15
0x1A
LOMODE
DELTAF_SHAPE[3:0]
I2C4[7:0]
ADDL1[7:0]
LODIV[1:0]
DELTAF[6:0]
0x14
0x19
PA_BOOST
PAPWR[2:0]
PLL1[7:0]
–
PWDN_MODE[1:0]
TSTEP[5:0]
RESERVED[2:0]
–
–
0x08
CFG9[7:0]
MODMODE
BCLK_POSTDIV[2:0]
FRACMODE
0x18
SYNC
TX_PKTLEN[14:8]
TX_PKTLEN[7:0]
RESERVED[4:0]
RESERVED[1:0]
RESERVED
RESERVED[1:0]
FIFO_WORDS[2:0]
–
–
SOFTRESET
RERESERVED SERVED
RESERVED[1:0]
RESERVED
RESERVED[1:0]
RESERVED[6:0]
Maxim Integrated │ 24
MAX41463/MAX41464
300MHz–960MHz (G)FSK
Transmitter with I2C Interface
Register Details
CFG1 (0x00)
BIT
7
6
5
4
3
2
1
0
Field
XOCLKDELAY[1:0]
XOCLKDIV[1:0]
–
FSKSHAPE
SYNC
MODMODE
Reset
0x2
0x1
–
0b0
0b0
0b0
Write, Read
Write, Read
–
Write, Read
Write, Read
Write, Read
Access Type
BITFIELD
XOCLK
DELAY
BITS
7:6
DESCRIPTION
DECODE
Start delay before enabling XO clock to digital
block
0x0: No delay. XO clock is immediately enabled to
rest of digital block
0x1: XO clock is enabled after 16 cycles to rest of
digital block
0x2: XO clock is enabled after 32 cycles to rest of
digital block
0x3: XO clock is enabled after 64 cycles to rest of
digital block
XO clock division ratio for digital block
0x0: Divide XO clock by 4 for digital clock
0x1: Divide XO clock by 5 for digital clock. High
time is 2 cycles, low time is 3 cycles
0x2: Divide XO clock by 6 for digital clock.
0x3: Divide XO clock by 7 for digital clock. High
time is 3 cycles, and low time is 4 cycles.
XOCLKDIV
5:4
FSKSHAPE
2
Sets the state of FSK Gaussain Shaping
0x0: FSK Shaping disabled
0x1: FSK Shaping enabled
SYNC
1
Controls if clock output acts as an input.
When an input, it will sample the DATA pin.
0x0
0x1
MODMODE
0
Configures modulator mode
0x0: ASK Mode
0x1: FSK Mode
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Maxim Integrated │ 25
MAX41463/MAX41464
300MHz–960MHz (G)FSK
Transmitter with I2C Interface
CFG2 (0x01)
BIT
Field
5
4
3
CLKOUT_DELAY[1:0]
7
6
–
–
–
0x2
–
–
–
0x1
Write, Read
–
–
–
Write, Read
Reset
Access Type
BITFIELD
CLKOUT_
DELAY
BCLK_
POSTDIV
BITS
7:6
2:0
2
1
0
BCLK_POSTDIV[2:0]
DESCRIPTION
DECODE
Selects the delay when CLKOUT starts
toggling upon exiting SHUTDOWN mode, in
divided XO clock cycles
0x0: CLKOUT will start toggling after 64 cycles
whenever moving into normal mode from shutdown
mode
0x1: CLKOUT will start toggling after 128 cycles
whenever moving into normal mode from shutdown
mode
0x2: CLKOUT will start toggling after 256 cycles
whenever moving into normal mode from shutdown
mode
0x3: CLKOUT will start toggling after 512 cycles
whenever moving into normal mode from shutdown
mode
Baud clock post-divider setting.
0x0: RESERVED
0x1: Divide by 1
0x2: Divide by 2
0x3: Divide by 3
0x4: Divide by 4
0x5: Divide by 5
0x6: RESERVED
0x7: RESERVED
CFG3 (0x02)
BIT
7
6
5
Field
Reset
BCLK_
REDIV
3
2
1
0
0x3
Access Type
BITFIELD
4
BCLK_PREDIV[7:0]
Write, Read
BITS
7:0
www.maximintegrated.com
DESCRIPTION
Baud clock predivision ratio. Valid values are
from 3 to 255.
DECODE
0x00: RESERVED
0x01: RESERVED
0x02: RESERVED
0x03: Divide by 3
...
0xFF: Divide by 255
Maxim Integrated │ 26
MAX41463/MAX41464
300MHz–960MHz (G)FSK
Transmitter with I2C Interface
CFG4 (0x03)
7
6
5
4
3
2
Field
BIT
–
–
–
–
–
–
Reset
–
–
–
–
–
–
0x0
Access Type
–
–
–
–
–
–
Write, Read
BITFIELD
BITS
PWDN_
MODE
1:0
DESCRIPTION
1
0
PWDN_MODE[1:0]
DECODE
0x0: SHUTDOWN low power state is enabled.
While entering low power state, XO, PLL, and PA
are shutdown.
0x1: STANDBY low power state is enabled. While
entering low power state, XO is enabled. PLL and
PA are shutdown
0x2: FAST WAKEUP low power state is enabled.
While entering low power state, XO and PLL are
enabled. PA is shutdown.
0x3: Will revert to 0x2
Power Down Mode Select
CFG5 (0x04)
BIT
7
6
Field
–
–
TSTEP[5:0]
Reset
–
–
0x00
Access Type
–
–
Write, Read
BITFIELD
5
4
3
BITS
TSTEP
2
1
0
DESCRIPTION
5:0
Controls GFSK shaping. See Digital FSK Modulation section.
SHDN (0x05)
BIT
7
6
5
4
3
2
1
0
Field
–
–
–
–
–
RESERVED
RESERVED
PA_BOOST
Reset
–
–
–
–
–
0x1
0x0
0x0
Access Type
–
–
–
–
–
Write, Read
Write, Read
Write, Read
BITFIELD
BITS
DESCRIPTION
DECODE
RESERVED
2
Write to 1 binary.
1
RESERVED
1
Write to 0 binary.
0
0
Enables a boost in PA output power for
frequencies above 850MHz. This requires
a different PA match compared to normal
operation.
0x0: PA Output power in normal operation.
0x1: PA Output power in boost mode for more
output power.
PA_BOOST
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Maxim Integrated │ 27
MAX41463/MAX41464
300MHz–960MHz (G)FSK
Transmitter with I2C Interface
PA1 (0x06)
BIT
7
Field
Reset
Access Type
BITFIELD
RESERVED
PAPWR
BITS
7:5
2:0
www.maximintegrated.com
4
3
RESERVED[2:0]
6
5
–
–
0x4
–
–
0x0
Write, Read
–
–
Write, Read
DESCRIPTION
2
1
0
PAPWR[2:0]
DECODE
Write to 100 binary.
100
Controls the PA output power by enabling
parallel drivers.
0x0: Minimum, 1 driver
0x1: 2 Drivers
0x2: 3 Drivers
0x3: 4 Drivers
0x4: 5 Drivers
0x5: 6 Drivers
0x6: 7 Drivers
0x7: 8 Drivers
Maxim Integrated │ 28
MAX41463/MAX41464
300MHz–960MHz (G)FSK
Transmitter with I2C Interface
PA2 (0x07)
7
6
5
Field
BIT
–
–
–
Reset
–
–
–
0x0
Access Type
–
–
–
Write, Read
BITFIELD
BITS
PACAP
4:0
www.maximintegrated.com
4
3
2
1
0
PACAP[4:0]
DESCRIPTION
DECODE
0x00: 0
0x01: 175
0x02: 350
0x03: 525
0x04: 700
0x05: 875
0x06: 1050
0x07: 1225
0x08: 1400
0x09: 1575
0x0A: 1750
0x0B: 1925
0x0C: 2100
0x0D: 2275
0x0E: 2450
0x0F: 2625
Controls shunt capacitance on PA output in fF.
0x10: 2800
0x11: 2975
0x12: 3150
0x13: 3325
0x14: 3500
0x15: 3675
0x16: 3850
0x17: 4025
0x18: 4200
0x19: 4375
0x1A: 4550
0x1B: 4725
0x1C: 4900
0x1D: 5075
0x1E: 5250
0x1F: 5425
Maxim Integrated │ 29
MAX41463/MAX41464
300MHz–960MHz (G)FSK
Transmitter with I2C Interface
PLL1 (0x08)
BIT
7
6
Field
CPLIN[1:0]
Reset
Access Type
BITFIELD
5
FRACMODE
4
3
2
RESERVED[1:0]
1
0
LODIV[1:0]
LOMODE
0x1
0x1
0x00
0x0
0b0
Write, Read
Write, Read
Write, Read
Write, Read
Write, Read
BITS
DESCRIPTION
DECODE
7:6
Sets the level of charge pump offset current
for fractional N mode to improve close in
phase noise. Set to 'DISABLED' for integer
N mode.
0x0: No extra current
0x1: 5% of charge pump current
0x2: 10% of charge pump current
0x3: 15% of charge pump current
FRACMODE
5
Sets PLL between fractional-N and integer-N
mode.
0x0: Integer N Mode
0x1: Fractional N Mode
RESERVED
4:3
Write to 00 binary.
00
CPLIN
LODIV
LOMODE
0x0: Disabled
0x1: LC VCO divided by 4
0x2: LC VCO divided by 8
0x3: LC VCO divided by 12
2:1
0
Sets LO generation. For lower power, choose
LOWCURRENT. For higher performance,
choose LOWNOISE.
0x0: Ring Oscillator Mode
0x1: LC VCO Mode
PLL2 (0x09)
BIT
7
6
5
4
3
2
Field
RESERVED
RESERVED
–
–
–
–
CPVAL[1:0]
Reset
0x0
0b0
–
–
–
–
0x0
Access Type
Write, Read
Write, Read
–
–
–
–
Write, Read
BITFIELD
BITS
DESCRIPTION
7
Write to 0 binary.
0
RESERVED
6
Write to 0 binary.
0
Sets Charge Pump Current
0x0: 5µA
0x1: 10µA
0x2: 15µA
0x3: 20µA
1:0
www.maximintegrated.com
0
DECODE
RESERVED
CPVAL
1
Maxim Integrated │ 30
MAX41463/MAX41464
300MHz–960MHz (G)FSK
Transmitter with I2C Interface
CFG6 (0x0A)
7
6
5
4
3
2
1
0
Field
BIT
–
–
–
–
–
I2C_TXEN1
RESERVED
RESERVED
Reset
–
–
–
–
–
0x0
0x0
0x0
Access Type
–
–
–
–
–
Write, Read
Write, Read
Write, Read
BITFIELD
BITS
DESCRIPTION
DECODE
I 2C
I2C_TXEN1
2
Enables DATA transmission in
mode.
Aliased address for I2C_TXEN1.
RESERVED
1
Write to 0 binary.
RESERVED
0
Write to 0 binary.
0x0: Data transmission not enabled in I2C mode.
0x1: Data transmission enabled in I2C mode.
PLL3 (0x0B)
BIT
7
6
5
4
3
Field
FREQ[23:16]
Reset
0x13
Access Type
2
1
0
Write, Read
BITFIELD
BITS
FREQ
DESCRIPTION
7:0
FREQ value to PLL. LO frequency= FREQ/2^16*fXTAL
PLL4 (0x0C)
BIT
7
6
5
4
3
Field
FREQ[15:8]
Reset
0xB0
Access Type
2
1
0
1
0
Write, Read
BITFIELD
BITS
FREQ
DESCRIPTION
7:0
FREQ value to PLL
PLL5 (0x0D)
BIT
7
6
5
4
3
Field
FREQ[7:0]
Reset
0x00
Access Type
BITFIELD
FREQ
www.maximintegrated.com
2
Write, Read
BITS
7:0
DESCRIPTION
FREQ value to PLL
Maxim Integrated │ 31
MAX41463/MAX41464
300MHz–960MHz (G)FSK
Transmitter with I2C Interface
PLL6 (0x0E)
BIT
7
6
5
4
3
2
Field
–
Reset
–
0x28
Access Type
–
Write, Read
BITFIELD
BITS
DELTAF
1
0
DELTAF[6:0]
DESCRIPTION
For FSK mode, MODMODE = 1 and FSKSHAPE = 0, sets the frequency
deviation from the space frequency for the mark frequency. fDELTA = DELTAF[6:0] * fXTAL/8192
6:0
PLL7 (0x0F)
BIT
7
6
5
4
3
2
1
0
Field
–
–
–
–
DELTAF_SHAPE[3:0]
Reset
–
–
–
–
0x4
Access Type
–
–
–
–
Write, Read
BITFIELD
BITS
DELTAF_SHAPE
DESCRIPTION
For FSK mode, MODMODE = 1 and FSKSHAPE = 1, sets the frequency
deviation from the space frequency for the mark frequency. fDELTA = DELTAF_SHAPE[3:0] * fXTAL/81920
3:0
CFG7 (0x10)
BIT
7
6
5
4
3
2
1
0
Field
–
–
–
–
–
I2C_TXEN2
RESERVED
RESERVED
Reset
–
–
–
–
–
0x0
0x0
0x0
Access Type
–
–
–
–
–
Write, Read
Write, Read
Write, Read
BITFIELD
BITS
DESCRIPTION
I2C_TXEN2
2
Enables DATA transmission in I2C
mode. Aliased address for I2C_
TXEN1.
RESERVED
1
RESERVED
DECODE
0x0: Data transmission not enabled in
I2C mode.
0x1: Data transmission enabled in I2C
mode.
0
Write to 0 binary.
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Maxim Integrated │ 32
MAX41463/MAX41464
300MHz–960MHz (G)FSK
Transmitter with I2C Interface
I2C1 (0x11)
BIT
7
6
5
4
3
PKTLEN_
MODE
Field
Reset
2
0x0
0x0
Write, Read
Write, Read
BITFIELD
BITS
7
PKTLEN
6:0
0
PKTLEN[14:8]
Access Type
PKTLEN_
MODE
1
DESCRIPTION
DECODE
0x0: PKTLEN[14:0] need not be programmed. FIFO
underflow event will be treated as end of packet
event. For cases where actual packet length is
greater than 32767 bits, it is expected that the µC will
pad such a packet to make it an integral multiple of
8-bits
0x1: PKTLEN[14:0] will provide the length of packet.
Once FIFO is read for PKTLEN[14:0] bits, or if FIFO
underflow, MAX41463/MAX41464 will consider that
as an end of packet event.
Packet Length Mode
Packet Length
I2C2 (0x12)
BIT
7
6
5
4
Field
3
2
1
0
1
0
PKTLEN[7:0]
Reset
0xFF
Access Type
Write, Read
BITFIELD
BITS
PKTLEN
DESCRIPTION
7:0
Packet Length
I2C3 (0x13)
BIT
7
6
5
4
3
Field
I2C_TX_DATA[7:0]
Reset
0x0
Access Type
BITFIELD
I2C_TX_DATA
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2
Write, Read
BITS
DESCRIPTION
7:0
Transmit data to be written into FIFO for I2C mode of operation. At this
address, I2C register address will not auto increment within an I2C transaction
burst, and subsequent writes will keep going to FIFO
Maxim Integrated │ 33
MAX41463/MAX41464
300MHz–960MHz (G)FSK
Transmitter with I2C Interface
I2C4 (0x14)
BIT
7
6
5
4
3
PKTCOMPLETE
Field
Reset
2
0x0
0x0
Read Only
Read Only
BITFIELD
BITS
7
TX_PKTLEN
6:0
0
TX_PKTLEN[14:8]
Access Type
PKTCOMPLETE
1
DESCRIPTION
DECODE
Indicates if Packet tranmission is completed
0x0: Packet transmission is not completed
0x1: Packet transmission is completed
Provides status information of bits transmitted
for the current packet
I2C5 (0x15)
BIT
7
6
5
4
3
Field
TX_PKTLEN[7:0]
Reset
0x0
Access Type
2
1
0
Read Only
BITFIELD
BITS
TX_PKTLEN
DESCRIPTION
7:0
Provides status information of bits transmitted for the current packet
I2C6 (0x16)
BIT
7
6
5
4
3
Field
UFLOW
OFLOW
FIFO_EMPTY
FIFO_FULL
–
FIFO_WORDS[2:0]
Reset
0x0
0x0
0x1
0x0
–
0x0
Read Only
Read Only
Read Only
Read Only
–
Read Only
Access Type
BITFIELD
BITS
7
FIFO Underflow status
OFLOW
6
FIFO Overflow status
FIFO_EMPTY
5
FIFO Empty Status
FIFO_FULL
4
FIFO Full Status
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2:0
1
0
DESCRIPTION
UFLOW
FIFO_WORDS
2
This field captures the number of locations currently filled in FIFO. Each
location corresponds to 8-bit data word
Maxim Integrated │ 34
MAX41463/MAX41464
300MHz–960MHz (G)FSK
Transmitter with I2C Interface
CFG8 (0x17)
BIT
7
Field
6
5
4
3
2
1
0
SOFTRESET
–
–
–
–
–
–
–
Reset
–
–
–
–
–
–
–
0b0
Access Type
–
–
–
–
–
–
–
Write, Read
BITFIELD
BITS
SOFTRESET
0
DESCRIPTION
DECODE
0x0: Deassert the reset
0x1: Resets the entire digital, until this bit is set to 0
Places DUT into software reset.
CFG9 (0x18)
BIT
7
6
Field
5
4
3
RESERVED[4:0]
Reset
Access Type
BITFIELD
BITS
2
1
0
RESERVED
RESERVED
RESERVED
0x0
0x0
0x0
0x0
Write, Read
Write, Read
Write, Read
Write, Read
DESCRIPTION
DECODE
RESERVED
7:3
Write to 0_0000 binary.
00000
RESERVED
2
Write to 0 binary.
0
RESERVED
1
Write to 0 binary.
0
RESERVED
0
Write to 0 binary.
0
ADDL1 (0x19)
BIT
7
Field
6
5
RESERVED[1:0]
Reset
Access Type
BITFIELD
4
RESERVED[1:0]
3
2
RESERVED[1:0]
1
0
RESERVED[1:0]
0x0
0x0
0x0
0x0
Write, Read
Write, Read
Write, Read
Write, Read
BITS
DESCRIPTION
DECODE
RESERVED
7:6
Write to 00 binary.
00
RESERVED
5:4
Write to 00 binary.
00
RESERVED
3:2
Write to 00 binary.
00
RESERVED
1:0
Write to 00 binary.
00
ADDL2 (0x1A)
BIT
7
6
5
4
3
Field
RESERVED
RESERVED[6:0]
Reset
0x1
0x0
Access Type
Write, Read
Write, Read
BITFIELD
BITS
RESERVED
7
RESERVED
6:0
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DESCRIPTION
2
1
0
DECODE
Write to 1 binary.
1
Write to 000_0000 binary.
0000000
Maxim Integrated │ 35
MAX41463/MAX41464
Applications Information
Power-On Programming
Preset Mode
To ensure the MAX41463/MAX41464 device enters shutdown state after power-on, the DATA pin must be held
low at power-on. If the DATA pin cannot be guaranteed
low at power-on, then a high value pulldown resistor is
recommended. After VDD has settled, a logic low-highlow transition on DATA must occur in the preset mode.
If the pulse duration of low-high-low transition is longer
than tXO + tPLL, it is a valid wake-up pulse before data
transmission. It is also allowed to have a short pulse
duration between 5μs and 20μs. The short pulse will not
wake up the device.
300MHz–960MHz (G)FSK
Transmitter with I2C Interface
filtered frequency shaping to help reduce spectral
emissions.
The space frequency is defined by the FREQ[23:0] bits
(registers PLL3, PLL4, PLL5). To set the space frequency,
use the following equation:
FREQ[23 : 0]
The mark frequency is defined by the space frequency
plus a frequency deviation. If frequency shaping is
disabled by setting FSKSHAPE = 0 (register CFG1, bit
2), the frequency deviation is defined by DELTAF[6:0]
(register PLL6, bits 6:0).
DELTAF[6 : 0]
Programming Mode
After turning on power supply in I2C mode, a logic-high-lowhigh transition on SDA must occur to minimize leakage current in shutdown state. It is highly recommended that the I2C
resistors are connected to the MAX41463/MAX41464 VDD.
Two I2C transactions are required to initialize the PLL
frequency synthesizer. The first transaction ensures
register ADDL2 at address 0x1A is written to its default
of 0x80. The second transaction burst-writes 20 consecutive
registers from address 0x00 to 0x13. The device is
programmed to transmit a dummy packet with 8 zero bits
in ASK mode. There is no RF emission at PA output. See
Initial Programming section.
For example, the crystal frequency is 16MHz, the RF
frequency is 315MHz, the 20 consecutive registers from
address 0x00 to 0x13 can be configured as:
[0x90, 0x81, 0x03, 0x00, 0x00, 0x04, 0x80, 0x80, 0x60,
0x00, 0x00, 0xC4, 0xDE, 0x98, 0x28, 0x04, 0x04, 0x00,
0xFF, 0x00]
After initial programming, the device will enter the shutdown, standby, or programming state according to the setting
of PWDN_MODE[1:0] (register CFG4, address 0x03,
bit[1:0] ). Configuration register values are retained unless
changed by programming or if the device is powered off
or undergoes a SOFTRESET. See the Startup section for
how to program the device for data transmission.
65536 * fSPACE
fXTAL
=
=
fΔ * 8192
fXTAL
If frequency shaping is enabled by setting FSKSHAPE = 1
(register CFG1, bit 2), the frequency deviation is defined
by DETLAF_SHAPE[3:0] (register PLL7, bits 3:0).
DELTAF_SHAPE[3 : 0]
=
fΔ * 8192
fXTAL * 10
When FSK shaping is enabled by setting FSKSHAPE = 1,
the frequency is transitioned in 16 steps between the
two frequencies using a Gaussian filter shape. The time
between each step is controlled by TSTEP[5:0] (register
CFG5, bits 5:0). The time step can be adjusted based on
the data rate.
TSTEP[5 : 0]
=
(
minimum 64,
(
200000
floor f
DATA_RATE
))
−1
where fDATARATE has a unit of bits per second. For
example, if fDATARATE is 47kbps, then TSTEP is
floor(200000/47000) -1 = 3.
In the preset mode, the frequency deviation is fixed at
78kHz.and TSTEP = 1.
FSK shaping supports a data rate up to 110kbps. Higher
data rates is not recommended.
Digital FSK Modulation
The FSK moduIation in MAX41463/MAX41464 is defined
by the space frequency and the mark frequency. The
space frequency is the lower frequency that represents a
logic 0. The mark frequency is the higher frequency that
represents a logic 1. The device defaults to Gaussian
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Maxim Integrated │ 36
MAX41463/MAX41464
Tuning Capacitor Settings
The internal variable shunt capacitor, which can be used
to match the PA to the antenna with changing transmitter
frequency, is controlled by setting the 5-bit cap variable in
the registers. This allows for 32 levels of shunt capacitance
control. Since the control of these 5 bits is independent of
the other settings, any capacitance value can be chosen
at any frequency, making it possible to maintain maximum
transmitter efficiency while moving rapidly from one
frequency to another. The internal tuning capacitor adds 0
to 5.425pF to the PA output in 0.175pF steps.
Crystal Frequency Selection
In order to avoid integer boundary spurs in fractional-N
PLL synthesizers, the crystal should be selected so that
the RF carrier frequency is more than 0.4MHz apart from
the nearest integer multiple of crystal frequency.
For example, the 16±0.002MHz crystals can be selected
for the 433.92MHz RF carrier, which is more than 0.4MHz
apart from the nearest integer multiple of crystal frequency
at 432±0.054MHz. However, the 16±0.002MHz crystals
are not suitable for a RF carrier at 912MHz or 928MHz.
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300MHz–960MHz (G)FSK
Transmitter with I2C Interface
In the programming mode, the crystal divider ratio is
programmable. The crystal divider ratio should be configured so that the divided clock frequency is 3.2±0.1MHz.
In addition, the PLL synthesizer requires a reference
frequency (same as crystal frequency) between 12.8MHz
and 19.2MHz. Therefore, when crystal divider ratio is 4, 5, or
6, allowed range of crystal frequency is 12.8MHz~13.2MHz,
15.5MHz~16.5MHz, or 18.6MHz~19.2MHz.
In another example, desired RF frequencies are
319.5MHz,
345.0MHz,
and
433.92MHz,
and
recommended crystal selection is 13±0.002MHz so
that integer boundary spurs are completely suppressed
for three desired RF frequencies. Nevertheless, the
16±0.002MHz and 19.2±0.002MHz crystals are also
acceptable.
In the preset mode, the crystal divider ratio is preset at 5.
When the RF carrier frequency is very close to an integer
multiple of 16MHz, the crystal selection can change to
16.384MHz or 16.128MHz, and the RF carrier frequency
should be preset through OTP memory in production.
Maxim Integrated │ 37
MAX41463/MAX41464
300MHz–960MHz (G)FSK
Transmitter with I2C Interface
Typical Application Circuit
CLKOUT /
SCL
GND
DATA / SDA
SEL1
MAX41461-64
VDD
SEL0
L1A
XTAL1
PA
Y1
L2
C7
XTAL2
C6
C8
GND_PA
Ordering Information
PART NUMBER
TEMP RANGE
PIN-PACKAGE
MAX41463GUB+
-40°C to +105°C
TSSOP-10
MAX41463GUB+T
-40°C to +105°C
TSSOP-10
MAX41464GUB+
-40°C to +105°C
TSSOP-10
MAX41464GUB+T
-40°C to +105°C
TSSOP-10
+ Denotes a lead(Pb)-free/RoHS-compliant package.
T Denotes tape-and-reel.
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Maxim Integrated │ 38
MAX41463/MAX41464
300MHz–960MHz (G)FSK
Transmitter with I2C Interface
Revision History
REVISION
NUMBER
REVISION
DATE
DESCRIPTION
PAGES
CHANGED
0
6/18
Initial release
—
1
11/18
Updated Ordering Information
38
For pricing, delivery, and ordering information, please visit Maxim Integrated’s online storefront at https://www.maximintegrated.com/en/storefront/storefront.html.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
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