MAX4959/MAX4960
High-Voltage OVP with Battery Switchover
General Description
Features
The MAX4959/MAX4960 overvoltage protection controllers protect low-voltage systems against high-voltage faults of up to +28V. When the input voltage
exceeds the overvoltage lockout (OVLO) threshold,
these devices turn off an external pFET to prevent damage to the protected components. The undervoltage
lockout (UVLO) threshold holds the external pFET off
until the input voltage rises to the correct level. An additional safety feature latches off the pFET when an incorrect low-power adapter is plugged in.
The MAX4959/MAX4960 control an external battery
switchover pFET (P2) (see Figures 4 and 6) that switches
in the battery when the AC adapter is unplugged. The
undervoltage and overvoltage trip levels can be adjusted
with external resistors.
o Overvoltage Protection Up to +28V
o ± 2.5% Accurate Externally Adjustable
OVLO/UVLO Thresholds
o Battery Switchover pFET Control
o Protection Against Incorrect Power Adapter
o Low (100µA Typ) Supply Current
o 25ms Input Debounce Timer
o 25ms Blanking Time
o 10-Pin (2mm x 2mm) µDFN Packages
Ordering Information
The input is protected against ±15kV HBM ESD when
bypassed with a 1µF ceramic capacitor to ground. All
devices are available in a small 10-pin (2mm x 2mm)
µDFN and are specified for operation over the extended -40°C to +85°C temperature range.
Applications
PART
TEMP RANGE
PINPACKAGE
TOP
MARK
MAX4959ELB+
-40°C to +85°C
10 µDFN
AAO
MAX4960ELB+
-40°C to +85°C
10 µDFN
AAP
+Denotes a lead-free package.
Notebooks
Laptops
Camcorders
Ultra-Mobile PCs
N.C.
GND
CB
VDD
TOP VIEW
GATE2
Pin Configuration
10
9
8
7
6
MAX4959
MAX4960
4
5
OVS
N.C.
(SOURCE1)
3
UVS
2
IN
1
GATE1
+
µDFN
( ) MAX4960 ONLY.
Typical Operating Circuits appear at end of data sheet.
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.
19-0874; Rev 1; 7/14
MAX4959/MAX4960
High-Voltage OVP with Battery Switchover
ABSOLUTE MAXIMUM RATINGS
IN, SOURCE1, GATE1, GATE2, to GND ................-0.3V to +30V
VDD to GND ..............................................................-0.3V to +6V
UVS, OVS, CB to GND .............................................-0.3V to +6V
Continuous Power Dissipation (TA = +70°C)
10-pin µDFN (derate 5.0mW/°C above +70°C) ...........403mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VIN = +19V, TA = -40°C to +85°C, unless otherwise noted, CVDD = 100nF. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
4
28
V
6
28
V
IN
Input Voltage Range
Overvoltage Adjustable Trip
Range
VIN
OVLO
(Note 2)
Overvoltage Comp Reference
OVREF
VIN rising edge
OVS Input Leakage Current
OVILKG
Overvoltage Trip Hysteresis
OVHYS
Undervoltage Adjustable Trip
Range
UVLO
(Note 2)
Undervoltage Comp Reference
UVREF
VIN falling edge
UVS Input Leakage Current
UVILKG
Undervoltage Trip Hysteresis
UVHYS
Internal Undervoltage Trip Level
INTUVREF
Internal Undervoltage Trip
Hysteresis
INTUVHYS
Power-On Trip Level
Power-On Trip Hysteresis
IN Supply Current
POTL
1.18
1.276
V
+100
nA
1
5
1.18
1.228
-100
%
28
V
1.276
V
+100
nA
1
VIN falling edge
4.1
4.4
%
4.7
1
VDD > +3V, IN rising edge
0.5
POTLHYS
IIN
1.228
-100
0.75
%
1
10
VIN = +19V, VOVS < OVREF and
VUVS > UVREF
100
V
V
%
300
µA
2.7
5.5
V
1.55
2.40
V
VDD
VDD Voltage Range
VDD
VDD Undervoltage Lockout
VDDUVLO
VDD Undervoltage Lockout
Hysteresis
VDDUVLOHYS
VDD Supply Current
VDD falling edge
50
mV
IVDD
VDD = +5V, VIN = 0V
10
µA
GATE1 Open-Drain MOS RON
Resistance
RON
VCB = 0V, VIN = 19V, VOVS < OVREF and
VUVS > UVREF, IGATE_ = 0.5mA (MAX4959)
1
kΩ
GATE2 Open-Drain MOS RON
Resistance
RON
VCB = 3V, IGATE_ = 0.5mA
1
kΩ
GATE_
2
Maxim Integrated
MAX4959/MAX4960
High-Voltage OVP with Battery Switchover
ELECTRICAL CHARACTERISTICS (continued)
(VIN = +19V, TA = -40°C to +85°C, unless otherwise noted, CVDD = 100nF. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
GATE1 Leakage Current
G1ILKG
VOVS > OVREF, VUVS < UVREF, or VCB = +5V
-1
+1
µA
GATE2 Leakage Current
G2ILKG
VCB = 0V
-1
+1
µA
CB
Logic-Level High
VIH
Logic-Level Low
VIL
CB Pulldown Resistor
1.5
RCBPD
V
0.4
V
1
2
3
MΩ
10
25
40
ms
TIMING
Debounce Time
VOVP > VIN > VUVP for greater than tDEB for
GATE1 to go low
tDEB
GATE1 Assertion Delay from
CB Pin
t1GATE
CB = +3V to 0
rise time = fall time = 5ns (Note 3)
50
ns
GATE2 Assertion Delay from
CB Pin
t2GATE
CB = 0 to +3V
rise time = fall time = 5ns (Note 3)
50
ns
Blanking Time
tBLANK
10
25
40
ms
MAX4960
SOURCE1/GATE1 Resistance
RSG
(MAX4960)
140
200
260
kΩ
GATE1/Ground Resistance
RGG
GATE1 Asserted (MAX4960)
140
200
260
kΩ
Note 1: All devices are production tested at TA = +25°C. Specifications over temperature are guaranteed by design.
Note 2: Do not exceed absolute maximum rating; the ratio between the externally set OVLO and UVLO threshold must not exceed 4,
[OVLO/UVLO]MAX ≤ 4.
Note 3: Assertion delay starts from switching of CB pin to reaching of 80% of GATE1/GATE2 transition. This delay is measured without
external capacitive load.
Typical Operating Characteristics
(VOVLO = 22.2V and VUVLO = 10.1V, R1 = 887kΩ, R2 = 66.5kΩ, R3 = 54.9kΩ, all resistors 1%, OVREF = UVREF = 1.228V.)
25
VOLTAGE (V)
VOLTAGE (V)
8
6
VDD
4
20
VGATE1
15
VDD
10
2
16
DRAIN OF P1
14
12
VIN
10
8
6
VGATE1
4
0
5
-2
0
-150
-100
-50
0
TIME (μs)
Maxim Integrated
50
100
150
MAX4959/60 toc03
VGATE1
VIN
VOLTAGE (V)
VIN
MAX4959/60 toc02
30
MAX4959/60 toc01
12
10
UNDERVOLTAGE RESPONSE
(WITHIN BLANKING TIME)
(RPULLUP = 1kΩ)
OVERVOLTAGE RESPONSE
(RPULLUP = 5kΩ)
POWER-UP RESPONSE
(RPULLUP = 1kΩ)
2
0
-150
-100
-50
0
50
TIME (μs)
100
150
0
10
20
30
40
50
60
70
TIME (μs)
3
MAX4959/MAX4960
High-Voltage OVP with Battery Switchover
Typical Operating Characteristics (continued)
(VOVLO = 22.2V and VUVLO = 10.1V, R1 = 887kΩ, R2 = 66.5kΩ, R3 = 54.9kΩ, all resistors 1%, OVREF = UVREF = 1.228V.)
BATTERY SWITCHOVER WITH ADAPTERPLUGGED RESPONSE
(VIN = 19V, VGATE2-PULLUP = 4.2V, RPULLUP = 5kΩ)
20
VGATE1
VIN
VOLTAGE (V)
VOLTAGE (V)
9
7
5
4
3
VGATE1
15
2
VOLTAGE (V)
11
5
MAX4959/60 toc05
25
MAX4959/60 toc04
13
OVERVOLTAGE AND UNDERVOLTAGE TRIP
DIFFERENCE vs. TEMPERATURE
(RPULLUP = 1kΩ)
VGATE2
10
CB
5
3
1
UV TRIP DIFF
1
0
-1
-2
DRAIN OF P1
LOAD BECOMES
PRESENT
MAX4959/60 toc06
LOW-POWER ADAPTER RESPONSE
(VOVLO = 22.3V, VUVLO = 10.1V, pFET = IRF7726)
OV TRIP DIFF
-3
0
-4
-5
0.1
0.15
0.2
0.25
0.3
TIME (s)
SUPPLY CURRENT vs. INPUT VOLTAGE
120
80
40
-50
0
50
TIME (μs)
100
-50
150
2
1.8
1.6
LOGIC THRESHOLD (V)
ISUPP (μA)
160
-100
VTH-HI
1.4
1.2
1
0.8
VTH-LO
0.6
-30
-10
10
30
50
70
90
TEMPERATURE (°C)
VDD SUPPLY CURRENT vs. TEMPERATURE
LOGIC-INPUT THRESHOLD vs. TEMPERATURE
MAX4959/60 toc07
200
-5
-150
5
VDD SUPPLY CURRENT (μA)
.05
MAX4959/60 toc08
0
MAX4959/60 toc09
-1
4.5
4
0.4
0
0.2
3.5
0
-40
0
5
10
15
20
-50
25
-30
-10
VIN (V)
10
30
50
70
-50
90
-30
-10
10
30
50
70
90
110
TEMPERATURE (°C)
TEMPERATURE (°C)
VOLTAGE RANGE vs. INPUT VOLTAGE RANGE
MAX4959/60 toc10
6
5
VDD (V)
4
3
2
1
0
0
5
10
15
20
25
VIN (V)
4
Maxim Integrated
MAX4959/MAX4960
High-Voltage OVP with Battery Switchover
Pin Description
PIN
MAX4959
MAX4960
1
1
NAME
GATE1
FUNCTION
pFET Gate Drive Output Open Drain. GATE1 is actively driven low, except during fault
(OVP or UVP) condition (the external pFET is turned off). When VUVLO < VIN < VOVLO,
GATE1 is driven low (the external pFET P1 is turned on).
2, 9
9
N.C.
—
2
SOURCE1
pFET Source Output. An internal resistor is connected between SOURCE1 and GATE1.
3
3
IN
Voltage Input. IN is both the power-supply input and the overvoltage/undervoltage
sense input. Bypass IN to GND with a 1µF ceramic capacitor to get a ±15kV protected
input. A minimum 0.1µF ceramic capacitor is required for proper operation.
4
4
UVS
Undervoltage Threshold Set Input. Connect UVS to an external resistive divider from IN to
GND to set the undervoltage lockout threshold. (See Typical Operating Circuits.)
5
5
OVS
Overvoltage Threshold Set Input. Connect OVS to an external resistive divider from
IN to GND to set the overvoltage lockout threshold. (See Typical Operating Circuits.)
6
6
VDD
Internal Power-Supply Output. Bypass VDD to GND with a 0.1µF minimum capacitor.
VDD powers the internal power-on reset circuits. (See the VDD Capacitor Selection section.)
7
7
CB
Battery Switchover Control Input. When CB is high, GATE1 is high (P1 is off), and GATE2
is low (P2 is on). When CB is low, GATE1 is controlled by internal logic and GATE2 is
high (P2 is off). GATE1 is controlled by CB only if VUVLO < VIN < VOVLO.
8
8
GND
10
10
GATE2
No Connection. Not internally connected. (Connect to ground or leave unconnected.)
Ground
pFET Gate Drive Output, Open Drain. When CB is high, GATE2 is low (P2 is on).
When CB is low, GATE2 is high impedance (P2 is off).
Detailed Description
The MAX4959/MAX4960 provide up to +28V overvoltage
protection for low-voltage systems. When the input voltage exceeds the overvoltage trip level, the MAX4959/
MAX4960 turn off an external pFET to prevent damage
to the protected components.
The MAX4959/MAX4960 feature a control bit (CB) pin
that controls an external battery-switchover function that
switches in the battery when the adapter is unconnected. The host system detects when the battery switchover
must take place and pulls CB high to turn on P2. The
load current is not interrupted during battery switchover
as the body diode of P2 conducts until the CB line is driven high (see the MAX4959 Typical Operating Circuit 1,
Figure 4).
An additional safety feature latches off pFET P1 when a
low-power adapter is plugged in. This protects the system from seeing repeated adapter insertions and
removals when an incorrect low-power adapter is
plugged in that cannot provide sufficient current.
Maxim Integrated
Undervoltage Lockout (UVLO)
The MAX4959/MAX4960 have an adjustable undervoltage lockout threshold ranging from +5V to +28V. When
VIN is less than the VUVLO, the device waits for a blanking time, tBLANK, to see if the fault still exists. If the fault
does not exist at the end of tBLANK, P1 remains on. If
VIN is less than VUVLO for longer than the blanking
time, the device turns P1 off and P1 does not turn on
again until VIN < 0.75V. See Figure 1.
Overvoltage Lockout (OVLO)
The MAX4959/MAX4960 have an adjustable overvoltage lockout threshold ranging from +6V to +28V. When
VIN is greater than the VOVLO, the device turns P1 off
immediately. When VIN drops below VOVLO, P1 turns on
again after the debounce time has elapsed.
Device Operation
High-Voltage Adapter (VIN > VOVLO)
If an adapter with a voltage higher than V OVLO is
plugged in, the MAX4959/MAX4960 is in an OVP condition, so P1 is kept off or immediately turned off. There is
5
MAX4959/MAX4960
High-Voltage OVP with Battery Switchover
Functional Diagrams
Functional Diagram for the MAX4959
GATE1
IN
GATE2
N1
VSG
+
N2
BANDGAP
N
-
VDD
ANALOG
SUPPLY
CB
DIGITAL
SUPPLY
POWER
ON
+
VREF2 = 0.7V
+
VDD
UVLO
POWER-ON
RESET AND
OFF STORAGE
LOGIC
VREF1 = 2V
GND
+
OVS
+
OVLO
-
UVS
+
MAX4959
no blanking time for OVP, but the debounce time
applies once the IN voltage falls below V OVLO but
above VUVLO. When the voltage at IN is higher than
VOVLO, the CB pin does not control P1.
Correct Adapter (VUVLO < VIN < VOVLO)
In this case, when the adapter is plugged in, the device
goes through a 20ms (typ) debounce time and ensures
that the voltage at IN is between VUVLO and VOVLO
before P1 is turned on. In this state, the CB pin controls
both P1 and P2.
6
UVLOINT
-
UVLO
-
Low-Power Adapter or Glitch Condition
If the adapter has the correct voltage but not enough
power (incorrect low-power adapter), the MAX4959/
MAX4960 protect pFET P1 from oscillation. When the
adapter is first plugged in, P1 is off so the voltage is correct. When P1 is turned on after the debounce time, the
low-power adapter is dragged down to below VUVLO.
The device waits for a 10ms blanking time to make sure
it is not a temporary glitch, and, if a fault still exists, it
latches off P1. P1 does not turn on again until the
adapter is unplugged (VIN < ~0.75V) and plugged in
again. This feature can work without the battery present
Maxim Integrated
MAX4959/MAX4960
High-Voltage OVP with Battery Switchover
Functional Diagrams (continued)
Functional Diagram for the MAX4960
IN
SOURCE1
GATE1
GATE2
N2
VSG
+
BANDGAP
N
-
VDD
N1
ANALOG
SUPPLY
CB
DIGITAL
SUPPLY
POWER
ON
+
VREF2 = 0.7V
+
VDD
UVLO
POWER-ON
RESET AND
OFF STORAGE
LOGIC
VREF1 = 2V
GND
+
OVS
+
OVLO
-
UVS
+
MAX4960
only if the backup capacitor on VDD is large enough to
maintain power for greater than the 10ms blanking time.
The detection that the adapter is unplugged and
plugged in again is implemented by monitoring the VIN
signal. The adapter is unplugged when VIN drops below
VIN = ~0.75V, and it is plugged in when VIN becomes
greater than VIN = ~0.75V. To ensure the monitoring of
this lower threshold, an external storage capacitor at the
VDD pin is necessary. When the input voltage VIN drops
below 4V, power for some internal VIN monitoring circuitry is supplied by the external capacitor at the VDD pin.
Maxim Integrated
UVLOINT
-
UVLO
-
This capacitor is supplied by VIN through a diode and is
internally limited to 5.5V.
Adapter Not Present (VIN < VUVLO)
When the input voltage VIN drops below 4.4V, P1 is
turned off automatically and P1 does not turn on again
until the adapter is unplugged (V IN < ~0.75V) and
plugged in again. When the adapter is not present, P1 is
kept off with the gate-source resistor (which is internal for
the MAX4960 and external for the MAX4959), and the
CB pin controls the battery switchover pFET P2.
7
MAX4959/MAX4960
High-Voltage OVP with Battery Switchover
VIN
VOVLO
VOVLO
VUVLO
tDEB
tDEB
INTUVREF
tBLANK
VUVLO
tDEB
tBLANK
VGATE1
VDD
VDD REGULATED
VCB
VGATE2
Figure 1. Timing Diagram
The following table lists the different modes of operations:
IN RANGE
P1 STATE
VIN > VOVLO
P1 OFF (not affected by CB)
VUVLO < VIN < VOVLO
(debounce timeout ongoing)
P1 OFF (not affected by CB)
VUVLO < VIN < VOVLO
(debounce timeout elapsed)
CB = 1 -> P1 is OFF
CB = 0 -> P1 is ON
VINTUVREF < VIN < VOVLO
(blanking timeout ongoing)
CB = 1 -> P1 is OFF
CB = 0 -> P1 is ON
VINTUVREF < VIN < VOVLO
(blanking timeout elapsed)
P1 OFF (not affected by CB). P1 does not turn on again until
adapter is unplugged (VIN < ~0.75V) and plugged in again.
VIN < VINTUVREF
P1 OFF (not affected by CB). P1 does not turn on again until
adapter is unplugged (VIN < ~0.75V) and plugged in again.
8
P2 STATE
CB = 1 -> P2 is ON
CB = 0 -> P2 is OFF
Maxim Integrated
MAX4959/MAX4960
High-Voltage OVP with Battery Switchover
4 [VOVLO / VUVLO]MAX ≤ 4
Applications Information
MOSFET Configuration and Selection
The MAX4959/MAX4960 are used with a single MOSFET configuration as shown in the Typical Operating
Circuits to regulate voltage as a low-cost solution.
The MAX4959/MAX4960 are designed with pFETs. For
lower on-resistance, the external MOSFET can be multiple pFETs in parallel. In most situations, MOSFETs with
RDS(ON) specified for a VGS of 4.5V work well. Also,
MOSFETs (with VDS ≥ 30V) withstand the full +28V IN
range of the MAX4959/MAX4960.
Resistor Selection for
Overvoltage/Undervoltage Window
The MAX4959/MAX4960 include undervoltage and
overvoltage comparators for window detection (see
Figure 4). GATE1 is enhanced and after the debounce
time, the pFET is turned on when the monitored voltage
is within the selected window.
The resistor values R1, R2, and R3 can be calculated
as follows:
⎛R
⎞
VUVLO = (UVREF )⎜ TOTAL ⎟
⎝ R2 + R 3 ⎠
⎛R
⎞
VOVLO = (OVREF )⎜ TOTAL ⎟
⎝ R3 ⎠
where RTOTAL = R1 + R2 + R3.
Use the following steps to determine the values for R1,
R2, and R3:
1) Choose a value for RTOTAL, the sum of R1, R2, and
R3. Because the MAX4959/MAX4960 have very
high input impedance, RTOTAL can be up to 5MΩ.
2) Calculate R3 based on R TOTAL and the desired
VOVLO trip point:
R3 =
OVREF × R TOTAL
VOVLO
3) Calculate R2 based on RTOTAL, R3, and the desired
VUVLO trip point:
⎡ UV
× R TOTAL ⎤
R2 = ⎢ REF
⎥ − R3
VUVLO
⎣
⎦
VDD Capacitor Selection
VDD is regulated to +5V by a linear regulator. Since the
minimum external adjustable UVLO trip threshold is
+5V, the VDD range is +5V to +28V and the value at
VDD is:
VDD = VIN – 0.8V
where VIN = 5V to 5.8V
VDD = +5V
where VIN > 5.8V
The capacitor at VDD must be large enough to provide
power to the device for an external settable time,
tHOLD, when VIN drops to 0V. The capacitor value to
have a minimum time of tHOLD is:
C = (IVDD x tHOLD) / (VDD - VDDUVLO)
The worst case scenario is where VIN = +5V, VDD = VIN
- 0.8V = +4.2V, IVDD = 10µA (max). For a tHOLD time of
20ms, C = (10µA x 20ms) / (4.2V - 2.2V) = 100nF.
Note: The capacitor must be greater than 100nF for the
internal regulator to be stable, and needs to have low
ESR and low leakage current, for example, a ceramic
capacitor.
IN Bypass Considerations
For most applications, bypass IN to GND with a 1µF
ceramic capacitor. If the power source has significant
inductance due to long lead length, take care to prevent overshoots due to the LC tank circuit, and provide
protection if necessary to prevent exceeding the +30V
absolute maximum rating on VIN.
The MAX4959/MAX4960 provide protection against voltage faults up to+28V, but this does not include negative
voltages. If negative voltages are a concern, connect a
Schottky diode from IN to GND to clamp negative input
voltages.
ESD Test Conditions
The MAX4959/MAX4960 are protected from ±15kV
Human Body Model ESD on IN when IN is bypassed to
ground with a 1µF ceramic capacitor.
Human Body Model
Figure 2 shows the Human Body Model and Figure 3
shows the current waveform it generates when discharged into a low impedance. This model consists of a
100pF capacitor charged to the ESD voltage of interest
that is then discharged into the device through a 1.5kΩ
resistor.
4) Calculate R1 based on RTOTAL, R2, and R3:
R1 = RTOTAL – R2 – R3
Note that the ratio between the externally set OVLO and
UVLO threshold must not exceed:
Maxim Integrated
9
MAX4959/MAX4960
High-Voltage OVP with Battery Switchover
RC
1MΩ
CHARGE-CURRENTLIMIT RESISTOR
RD
1.5kΩ
IP 100%
90%
DISCHARGE
RESISTANCE
Ir
PEAK-TO-PEAK RINGING
(NOT DRAWN TO SCALE)
AMPERES
HIGHVOLTAGE
DC
SOURCE
Cs
100pF
STORAGE
CAPACITOR
DEVICE
UNDER
TEST
36.8%
10%
0
0
Figure 2. Human Body ESD Test Model
tRL
TIME
tDL
CURRENT WAVEFORM
Figure 3. Human Body Current Waveform
Chip Information
PROCESS: BiCMOS
10
Maxim Integrated
MAX4959/MAX4960
High-Voltage OVP with Battery Switchover
Typical Operating Circuits
D1
DC-DC
CONVERTER
AC ADAPTER
P1
C1
RU1
C2
RD1
IN
RU2
GATE1
RD2
BATTERY
CHARGER
VSUPPLY
GATE2
N2
VDD
HOLD-UP
POWER SUPPLY
N1
P2
CB
VREF
R1
UVS
UVLO
GND
R2
LOGIC
OVS
OVLO
R3
1-CELL (4.2V) TO
4-CELL (16.8V)
Figure 4. MAX4959 Typical Operating Circuit 1
Maxim Integrated
11
MAX4959/MAX4960
High-Voltage OVP with Battery Switchover
Typical Operating Circuits (continued)
28V
PROTECTED
CHARGER
AC ADAPTER
DC-DC
CONVERTER
EN
3.3V
RD1
IN
GATE1
VSUPPLY
SYSTEM LOAD
GATE2
N2
VDD
HOLD-UP
POWER SUPPLY
CB
N1
VREF
R1
UVS
UVLO
GND
R2
LOGIC
OVS
OVLO
R3
1-CELL (4.2V) TO
4-CELL (16.8V)
Figure 5. MAX4959 Typical Operating Circuit 2
12
Maxim Integrated
MAX4959/MAX4960
High-Voltage OVP with Battery Switchover
Typical Operating Circuits (continued)
DC-DC
CONVERTER
AC ADAPTER
P1
C1
C2
IN
SOURCE1
RU2
GATE1
RD2
BATTERY
CHARGER
VSUPPLY
GATE2
N2
VDD
HOLD-UP
POWER SUPPLY
P2
CB
N1
VREF
R1
UVS
UVLO
GND
R2
LOGIC
OVS
OVLO
R3
1-CELL (4.2V) TO
4-CELL (16.8V)
Figure 6. MAX4960 Typical Operating Circuit 1
Maxim Integrated
13
MAX4959/MAX4960
High-Voltage OVP with Battery Switchover
Typical Operating Circuits (continued)
BATTERY
CHARGER
AC ADAPTER
P1
C1
DC-DC
CONVERTER
IN
GATE1
SOURCE1
VSUPPLY
SYSTEM LOAD
GATE2
N2
VDD
HOLD-UP
POWER SUPPLY
CB
N1
VREF
R1
UVS
UVLO
GND
R2
LOGIC
OVS
OVLO
1-CELL (4.2V) TO
4-CELL (16.8V)
R3
Figure 7. MAX4960 Typical Operating Circuit 2
Package Information
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or
“-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the
package regardless of RoHS status.
14
PACKAGE TYPE
PACKAGE CODE
OUTLINE NO.
LAND
PATTERN NO.
10 µDFN
L1022+1
21-0164
90-0006
Maxim Integrated
MAX4959/MAX4960
High-Voltage OVP with Battery Switchover
Revision History
REVISION
NUMBER
REVISION
DATE
0
7/07
Initial release
1
7/14
Removed µMAX products for MAX4959 and MAX4960
DESCRIPTION
PAGES
CHANGED
—
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent
licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and
max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 ________________________________ 15
© 2014 Maxim Integrated Products, Inc.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
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