19-0280; Rev 2; 11/96
5V, Low-Power, Voltage-Output,
Serial 10-Bit DACs
The MAX504/MAX515 are low-power, voltage-output,
10-bit digital-to-analog converters (DACs) specified for
single +5V power-supply operation. The MAX504 can
also be operated with ±5V supplies. The MAX515
draws only 140µA, and the MAX504 (with internal reference) draws only 260µA. The MAX515 comes in 8-pin
DIP and SO packages, while the MAX504 comes in 14pin DIP and SO packages. Both parts have been
trimmed for offset voltage, gain, and linearity, so no further adjustment is necessary.
The MAX515’s buffer is fixed at a gain of 2. The MAX504’s
internal op amp may be configured for a gain of 1 or 2, as
well as for unipolar or bipolar output voltages. The
MAX504 can also be used as a four-quadrant multiplier
without external resistors or op amps.
For parallel data inputs, see the MAX503 data sheet.
For a hardware and software compatible 12-bit
upgrade, refer to the MAX531/MAX538/MAX539 data
sheet.
_______________________Applications
Battery-Powered Test Instruments
Digital Offset and Gain Adjustment
Battery-Operated/Remote Industrial Controls
Machine and Motion Control Devices
Cellular Telephones
________________Functional Diagram
REFOUT*
REFIN BIPOFF*
___________________________Features
♦ Operate from Single +5V Supply
♦ Buffered Voltage Output
♦ Internal 2.048V Reference (MAX504)
♦ 140µA Supply Current (MAX515)
♦ INL = ±1/2LSB (max)
♦ Guaranteed Monotonic Over Temperature
♦ Flexible Output Ranges:
0V to VDD (MAX504/MAX515)
VSS to VDD (MAX504)
♦ 8-Pin SO/DIP (MAX515)
♦ Power-On Reset
♦ Serial Data Output for Daisy-Chaining
______________Ordering Information
PART
MAX504CPD
MAX504CSD
MAX504EPD
MAX504ESD
MAX515CPA
MAX515CSA
MAX515EPA
MAX515ESA
TEMP. RANGE
PIN-PACKAGE
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
14 Plastic DIP
14 SO
14 Plastic DIP
14 SO
8 Plastic DIP
8 SO
8 Plastic DIP
8 SO
Refer to the MAX531/MAX538/MAX539 data sheet for military temperature or die equivalents.
MAX504
MAX515
2.048V
REFERENCE*
_________________Pin Configurations
RFB*
TOP VIEW
VOUT
DAC
AGND
VDD
POWER-UP
RESET
10-BIT DAC REGISTER
DGND*
CLR*
CS
CONTROL
LOGIC
VSS*
4
(MSB)
2 (LSB)
DUMMY
0s
10 DATA BITS
BITS
SCLK
DIN
16-BIT SHIFT REGISTER
* MAX504 ONLY
DIN
1
SCLK
2
CS 3
MAX515
DOUT 4
8
VDD
7
VOUT
6
REFIN
5
AGND
DOUT
DIP/SO
MAX504 appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 408-737-7600 ext. 3468.
MAX504/MAX515
_______________General Description
MAX504/MAX515
5V, Low-Power, Voltage-Output
Serial 10-Bit DACs
ABSOLUTE MAXIMUM RATINGS
Continuous Power Dissipation (TA = +70°C)
8-Pin Plastic DIP (derate 9.09mW/°C above +70°C) .....727mW
8-Pin SO (derate 5.88mW/°C above +70°C)..................471mW
14-Pin Plastic DIP (derate 10.00mW/°C above +70°C) ..... 800mW
14-Pin SO (derate 8.33mW/°C above +70°C)................667mW
Operating Temperature Ranges
MAX5_ _C_ _.........................................................0°C to +70°C
MAX5_ _E_ _ ......................................................-40°C to +85°C
Storage Temperature Range .............................-65°C to +165°C
Lead Temperature (soldering, 10sec) .............................+300°C
VDD to DGND and VDD to AGND ................................-0.3V, +6V
VSS to DGND and VSS to AGND .................................-6V, +0.3V
VDD to VSS .................................................................-0.3V, +12V
AGND to DGND........................................................-0.3V, +0.3V
Digital Input Voltage to DGND ......................-0.3V, (VDD + 0.3V)
REFIN ..................................................(VSS - 0.3V), (VDD + 0.3V)
REFOUT to AGND .........................................-0.3V, (VDD + 0.3V)
RFB .....................................................(VSS - 0.3V), (VDD + 0.3V)
BIPOFF ................................................(VSS - 0.3V), (VDD + 0.3V)
VOUT (Note 1) ................................................................VSS, VDD
Continuous Current, Any Pin................................-20mA, +20mA
Note 1: The output may be shorted to VDD, VSS, or AGND if the package power dissipation limit is not exceeded.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS—Single +5V Supply
(VDD = 5V, VSS = 0V, AGND = DGND = 0V, REFIN = 2.048V (external), RFB = BIPOFF = VOUT (MAX504), C REFOUT = 33µF (MAX504),
RL = 10kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
STATIC PERFORMANCE
Resolution
Relative Accuracy (Note 2)
N
DNL
Unipolar Offset Error
VOS
Unipolar Offset Tempco
TCVOS
Unipolar Offset-Error
Power-Supply Rejection Ratio
PSRR
Guaranteed monotonic
0
4.5V ≤ VDD ≤ 5.5V
PSRR
±0.5
LSB
±1
LSB
3
LSB
3
ppm/°C
0.1
LSB/V
GE
±1
Gain-Error Tempco
Gain-Error Power-Supply
Rejection Ratio
Bits
INL
Differential Nonlinearity
Gain Error (Note 2)
10
4.5V ≤ VDD ≤ 5.5V
LSB
1
ppm/°C
0.1
LSB/V
VOLTAGE OUTPUT (VOUT)
Output Voltage Range
Output Load Regulation
Short-Circuit Current
MAX504 (G = 1)
0
VDD - 2
MAX504 (G = 2), MAX515
0
VDD - 0.4
VOUT = 2V, RL = 2kΩ
0.5
ISC
12
V
LSB
mA
REFERENCE INPUT (REFIN)
Voltage Range
0
Input Resistance
Code dependent, minimum at code 0101...
40
Input Capacitance
Code dependent (Note 3)
10
AC Feedthrough
REFIN = 1kHz, 2Vp-p
2
VDD - 2
V
kΩ
50
-80
_______________________________________________________________________________________
pF
dB
5V, Low-Power, Voltage-Output,
Serial 10-Bit DACs
MAX504/MAX515
ELECTRICAL CHARACTERISTICS—Single +5V Supply (continued)
(VDD = 5V, VSS = 0V, AGND = DGND = 0V, REFIN = 2.048V (external), RFB = BIPOFF = VOUT (MAX504), C REFOUT = 33µF (MAX504),
RL = 10kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
TA = +25°C
2.024
2.048
2.072
MAX504C
2.015
2.081
MAX504E
2.011
2.085
UNITS
REFERENCE OUTPUT (REFOUT—MAX504 Only)
Reference Output Voltage
Temperature Coefficient
Resistance
TCREFOUT
RREFOUT
Power-Supply Rejection Ratio
Noise Voltage
PSRR
en
Required External Capacitor
30
V
ppm/°C
0.5
4.5V ≤ VDD ≤ 5.5V
200
µV/V
0.1Hz to 10kHz
400
µVp-p
CREFOUT
2
Ω
(Note 4)
3.3
µF
DIGITAL INPUTS (DIN, SCLK, CS, CLR)
Input High
VIH
Input Low
VIL
Input Current
IIN
Input Capacitance
CIN
2.4
V
VIN = 0V or VDD
0.8
V
±1
µA
8
pF
DIGITAL OUTPUT (DOUT)
Output High
Output Low
VOH
VOL
ISOURCE = 2mA
ISINK = 2mA
VDD - 1
0.4
V
V
DYNAMIC PERFORMANCE
Voltage-Output Slew Rate
Voltage-Output Settling Time
Digital Feedthrough
Signal-to-Noise Plus Distortion
SR
SINAD
TA = +25°C
To ±1/2LSB, VOUT = 2V
CS = VDD, DIN = 100kHz
0.15
REFIN = 1kHz, 2Vp-p (G = 1 or 2),
code = 1111...
0.25
25
5
V/µs
µs
nV-s
68
dB
POWER SUPPLY
Positive Supply Voltage
Power-Supply Current
VDD
IDD
4.5
All inputs = 0V or VDD, MAX504
output = no load
MAX515
260
140
5.5
400
300
V
µA
SWITCHING CHARACTERISTICS (Note 5)
CS Setup Time
tCSS
20
ns
SCLK Fall to CS Fall Hold Time
tCSH0
15
ns
SCLK Fall to CS Rise Hold Time
tCSH1
0
ns
SCLK High Width
tCH
35
ns
SCLK Low Width
tCL
35
ns
DIN Setup Time
tDS
45
ns
DIN Hold Time
tDH
0
DOUT Valid Propagation Delay
tDO
CL = 50pF
ns
80
ns
CS High Pulse Width
tCSW
20
ns
CLR Pulse Width
tCLR
25
ns
CS Rise to SCLK Rise Setup Time
tCS1
50
ns
_______________________________________________________________________________________
3
MAX504/MAX515
5V, Low-Power, Voltage-Output,
Serial 10-Bit DACs
ELECTRICAL CHARACTERISTICS—Dual ±5V Supplies (MAX504 Only)
(VDD = 5V, VSS = -5V, AGND = DGND = 0V, REFIN = 2.048V (external), RFB = BIPOFF = VOUT, CREFOUT = 33µF, RL = 10kΩ,
CL = 100pF, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER
SYMBOL
Resolution
CONDITIONS
N
MIN
TYP
MAX
UNITS
±0.5
LSB
LSB
10
Bits
Relative Accuracy
INL
Differential Nonlinearity
DNL
Guaranteed monotonic
±1
Bipolar Offset Error
VOS
BIPOFF = REFIN
±3
Bipolar Offset Tempco
TCVOS
BIPOFF = REFIN
Offset-Error Power-Supply
Rejection Ratio
PSRR
4.5V ≤ VDD ≤ 5.5V, -5.5V ≤ VSS ≤ -4.5V
Gain Error (Unipolar or Bipolar)
ppm/°C
0.1
LSB/V
GE
±1
Gain-Error Tempco
Gain-Error Power-Supply
Rejection Ratio
PSRR
4.5V ≤ VDD ≤ 5.5V, -5.5V ≤ VSS ≤ -4.5V
LSB
3
LSB
1
ppm/°C
0.1
LSB/V
REFERENCE INPUT (REFIN)
Voltage Range
VSS + 2
Input Resistance
Code dependent, minimum at code 0101...
40
Input Capacitance
Code dependent (Note 3)
10
AC Feedthrough
REFIN = 1kHz, 2.0Vp-p
VDD - 2
V
kΩ
50
-80
pF
dB
REFERENCE OUTPUT (REFOUT—MAX504 Only)
Reference Output Voltage
Temperature Coefficient
2.024
MAX504C
2.015
2.081
MAX504E
2.011
2.085
TCREFOUT
Resistance
RREFOUT
Power-Supply Rejection Ratio
PSRR
Noise Voltage
Required External Capacitor
TA = +25°C
en
2.048
2.072
30
V
ppm/°C
0.5
4.5V ≤ VDD ≤ 5.5V
200
µV/V
0.1Hz to 10kHz
400
µVp-p
CREFOUT
2
Ω
(Note 4)
3.3
µF
DIGITAL INPUTS (DIN, SCLK, CS)
Input High
VIH
Input Low
VIL
Input Current
IIN
Input Capacitance
CIN
2.4
V
VIN = 0V or VDD
0.8
V
±1
µA
8
pF
DIGITAL OUTPUT (DOUT)
Output High
VOH
ISOURCE = 2mA
Output Low
VOL
ISINK = 2mA
4
VDD - 1
_______________________________________________________________________________________
V
0.4
V
5V, Low-Power, Voltage-Output,
Serial 10-Bit DACs
(VDD = 5V, VSS = -5V, AGND = DGND = 0V, REFIN = 2.048V (external), RFB = BIPOFF = VOUT, CREFOUT = 33µF, RL = 10kΩ,
CL = 100pF, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
VOLTAGE OUTPUT (VOUT)
Output Voltage Range
Output Load Regulation
Short-Circuit Current
(G = 1)
VSS + 2
VDD - 2
(G = 2)
VSS + 0.4
VDD - 0.4
VOUT = 2V, RL = 2kΩ
0.5
ISC
V
LSB
12
mA
0.25
V/µs
16
µs
nV-s
DYNAMIC PERFORMANCE
Voltage-Output Slew Rate
SR
0.15
Voltage-Output Settling Time
To ±1/2LSB, VOUT = 2V
Digital Feedthrough
Step all 0s to all 1s
5
REFIN = 1kHz, 2Vp-p (G = 1)
68
REFIN = 1kHz, 2Vp-p (G = 2)
68
Signal-to-Noise Plus Distortion
SINAD
dB
POWER SUPPLY
Positive Supply Voltage
VDD
4.5
5.5
V
Negative Supply Voltage
VSS
-5.5
0
V
Positive Supply Current
IDD
All inputs = 0V or VDD, no load
260
400
µA
Negative Supply Current
ISS
All inputs = 0V or VDD, no load
-120
-200
µA
SWITCHING CHARACTERISTICS
CS Setup Time
tCSS
20
ns
SCLK Fall to CS Fall Hold Time
tCSH0
15
ns
SCLK Fall to CS Rise Hold Time
tCSH1
0
ns
tCH
35
ns
SCLK Low Width
tCL
35
ns
DIN Setup Time
tDS
45
ns
DIN Hold Time
tDH
0
ns
SCLK High Width
DOUT Valid Propagation Delay
tDO
CL = 50pF
80
ns
CS High Pulse Width
tCSW
20
ns
CLR Pulse Width
tCLR
25
ns
CS Rise to SCLK Rise Setup Time
tCS1
50
ns
Note 2:
Note 3:
Note 4:
Note 5:
In single-supply operation, INL and GE calculated from Code 3 to Code 1023.
Guaranteed by design.
Tested at IOUT = 100µA. The reference can typically source up to 5mA (see Typical Operating Characteristics).
The timing characteristics limits for the MAX515 are guaranteed by design.
_______________________________________________________________________________________
5
MAX504/MAX515
ELECTRICAL CHARACTERISTICS—Dual ±5V Supplies (MAX504 Only) (continued)
__________________________________________Typical Operating Characteristics
(VDD = +5V, VREFIN = 2.048V, TA = +25°C, unless otherwise noted.)
OUTPUT SOURCE CAPABILITY vs.
OUTPUT PULL-UP VOLTAGE
8
6
4
2
2
3
4
5
6
7
OUTPUT PULL-DOWN VOLTAGE (V)
VDD-4
VDD-3
VDD-2
VDD-1
1
MAX504-4
2.045
260
MAX515
-12
-14
MAX504-8
RFB CONNECTED TO AGND (G=2)
RFB CONNECTED TO VOUT (G=1)
GAIN
0
0
PHASE
-10
-20
-180
-30
100k
1
10
100
FREQUENCY (kHz)
10k
800
2.0520
180
10
0
1k
100k
MAX504 REFERENCE OUTPUT VOLTAGE
vs. REFERENCE LOAD CURRENT
REFERENCE OUTPUT VOLTAGE (V)
GAIN (dB)
20
100
FREQUENCY (Hz)
PHASE (degrees)
MAX504-7
30
FREQUENCY (Hz)
1
MAX504
GAIN AND PHASE vs.FREQUENCY
40
10k
-6
-10
160
10
1k
-4
TEMPERATURE (°C)
50
1M
-8
-60 -40 -20 0 20 40 60 80 100 120 140
60
100k
0
200
20
10k
-2
180
20 40 60 80 100 120
1k
REFIN = 4Vp-p
2
MAX504
220
MAX504
AMPLIFIER SIGNAL-TO-NOISE RATIO
100
100
4
240
TEMPERATURE (°C)
10
10
MAX504
GAIN vs. FREQUENCY
120
70
-20
FREQUENCY (Hz)
280
140
REFIN = 4Vp-p
-30
VDD-0
300
SUPPLY CURRENT (µA)
REFERENCE VOLTAGE (V)
2.050
80
-50
-40
SUPPLY CURRENT vs.
TEMPERATURE
2.055
0
-60
OUTPUT PULL-UP VOLTAGE (V)
MAX504
REFERENCE VOLTAGE vs.
TEMPERATURE
-60 -40 -20
-70
0
VDD-5
1.0
CODE = all 0s
-80
MAX504-9
0.8
0.6
0.4
GAIN (dB)
0.2
MAX504-5
0
-90
-10
8
0
6
-100
MAX504-6
10
1
ANALOG FEEDTHROUGH (dB)
12
-110
MAX504-2
0
MAX504-1
14
OUTPUT SOURCE CAPABILITY (mA)
OUTPUT SINK CAPABILITY (mA)
16
ANALOG FEEDTHROUGH vs.
FREQUENCY
MAX504-3
OUTPUT SINK CAPABILITY vs.
OUTPUT PULL-DOWN VOLTAGE
SIGNAL-TO-NOISE RATIO (dB)
MAX504/MAX515
5V, Low-Power, Voltage-Output,
Serial 10-Bit DACs
2.0515
2.0510
2.0505
2.0500
2.0495
2.0490
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
REFERENCE LOAD CURRENT (mA)
_______________________________________________________________________________________
5V, Low-Power, Voltage-Output,
Serial 10-Bit DACs
(VDD = +5V, VREFIN = 2.048V, TA = +25°C, unless otherwise noted.)
DIGITAL FEEDTHROUGH
A
B
2µs/div
CS = HIGH
A: DIN = 4Vp-p, 100kHz
B: VOUT, 10mV/div
NEGATIVE SETTLING TIME (MAX504)
POSITIVE SETTLING TIME (MAX504)
A
A
B
B
5µs/div
A: CS RISING EDGE, 5V/div
B: VOUT, NO LOAD, 1V/div
DUAL SUPPLY ±5V
BIPOLAR CONFIGURATION
VREFIN = 2V
5µs/div
A: CS RISING EDGE, 5V/div
B: VOUT, NO LOAD, 1V/div
DUAL SUPPLY ±5V
BIPOLAR CONFIGURATION
VREFIN = 2V
_______________________________________________________________________________________
7
MAX504/MAX515
____________________________Typical Operating Characteristics (continued)
MAX504/MAX515
5V, Low-Power, Voltage-Output
Serial 10-Bit DACs
____________________Pin Description
_______________Detailed Description
General DAC Discussion
PIN
NAME
FUNCTION
Bipolar offset/gain
resistor
MAX504
MAX515
1
—
BIPOFF
2
1
DIN
Serial data input
3
—
CLR
Clear. Asynchronously sets
DAC register to all 0s.
4
2
SCLK
5
3
CS
6
4
DOUT
Serial data output for
daisy-chaining
7
—
DGND
Digital ground
8
5
AGND
Analog ground
9
6
REFIN
Reference input
10
—
REFOUT
Reference output,
2.048V. Connect to VDD
if not used.
11
—
VSS
Negative power supply
12
7
VOUT
13
8
VDD
Positive power supply
14
—
RFB
Feedback resistor
The MAX504/MAX515 use an “inverted” R-2R ladder network with a single-supply CMOS op amp to convert 10-bit
digital data to analog voltage levels (see Functional
Diagram). The term “inverted” describes the ladder network because the REFIN pin in current-output DACs is the
summing junction, or virtual ground, of an op amp.
However, such use would result in the output voltage
being the inverse of the reference voltage. The
MAX504/MAX515’s topology makes the output the same
polarity as the reference input.
An internal reset circuit forces the DAC register to reset
to all 0s on power-up. Additionally, a clear (CLR) pin,
when held low, sets the DAC register to all 0s. CLR
operates asynchronously and independently from the
chip select (CS) pin.
Serial clock input
Chip select, active low
Buffer Amplifier
The output buffer is a unity-gain stable, rail-to-rail output,
BiCMOS op amp. Input offset voltage and CMRR are
trimmed to achieve better than 10-bit performance.
Settling time is 25µs to 0.01% of final value. The output is
short-circuit protected and can drive a 2kΩ load with more
than 100pF load capacitance.
DAC output
CS
tCSH0
tCSW
tCH
tCSS
tCL
tCSH1
SCLK
tDH
tCS1
tDS
DIN
tDO
DOUT
Figure 1. Timing Diagram
8
_______________________________________________________________________________________
5V, Low-Power, Voltage-Output,
Serial 10-Bit DACs
TOTAL
REFERENCE
NOISE
CS
CREFOUT
REFERENCE NOISE (µVRMS)
1.6
250
1.4
CREFOUT = 3.3µF
200
1.2
1.0
150
0.8
100
0.6
50
CREFOUT = 47µF
0.4
Logic Interface
REFERENCE NOISE (mVp-p)
1.8
SINGLE POLE ROLLOFF
MAX504-FIG02
TEK 7A22
300
0.2
0
0.1
1
10
100
FREQUENCY (kHz)
0.0
1000
Figure 2. Reference Noise vs. Frequency
Internal Reference (MAX504 only)
The on-chip reference is laser trimmed to generate 2.048V
at REFOUT. The output stage can source and sink current
so REFOUT can settle to the correct voltage quickly in
response to code-dependent loading changes. Typically,
source current is 5mA and sink current is 100µA.
REFOUT connects the internal reference to the R-2R DAC
ladder at REFIN. The R-2R ladder draws 50µA maximum
load current. If any other connection is made to REFOUT,
ensure that the total load current is less than 100µA to
avoid gain errors.
For applications requiring very low-noise performance, connect a 33µF capacitor from REFOUT to AGND. If noise is
not a concern, a lower value (3.3µF min) capacitor may be
used. To reduce noise further, insert a buffered RC filter
between REFOUT and REFIN (Figure 2). The reference
bypass capacitor CREFOUT is still required for reference stability. In applications not requiring the reference, connect
REFOUT to VDD (to save power and to eliminate the need
for CREFOUT) or use the MAX515 (no internal reference).
External Reference
An external reference in the range (VSS + 2V) to (VDD - 2V)
may be used with the MAX504 in dual-supply operation.
With the MAX515 or the MAX504 in single-supply use, the
reference must be positive and may not exceed VDD - 2V.
The reference voltage determines the DAC’s full-scale output. The DAC input resistance is code dependent and is
minimum (40kΩ) at code 0101... and virtually infinite at
The MAX504/MAX515 logic inputs are designed to be
compatible with TTL or CMOS logic levels. However, to
achieve the lowest power dissipation, drive the digital
inputs with rail-to-rail CMOS logic. With TTL logic levels,
the power requirement increases by a factor of approximately 2.
Serial Clock and Update Rate
Figure 1 shows the MAX504/MAX515 timing. The maximum serial clock rate is given by 1/(tCH+tCL), approximately 14MHz. The digital update rate is limited by the
chip-select period, which is 16 x (tCH + tCL) + tCSW.
This equals a 1.14µs, or 877kHz, update rate. However,
the DAC settling time to 10 bits is 25µs, which may limit
the update rate to 40kHz for full-scale step transitions.
____________Applications Information
Refer to Figures 3a and 3b for typical operating connections.
Serial Interface
The MAX504/MAX515 use a three-wire serial interface that
is compatible with SPI™, QSPI™ (CPOL = CPHA = 0), and
Microwire™ standards as shown in Figures 4 and 5. The
DAC is programmed by writing two 8-bit words (see Figure
1 and the Functional Diagram). 16 bits of serial data are
clocked into the DAC in the following order: 4 fill (dummy)
bits, 10 data bits, and 2 sub-LSB 0s. The 4 dummy bits are
not normally needed, and are required only when DACs
are daisy chained. The 2 sub-LSB 0s, however, are always
needed, and allow hardware and software compatibility
with the 12-bit MAX531/MAX538/MAX539. Transitions at
CS should occur while SCLK is low. Data is clocked in on
SCLK’s rising edge while CS is low. The serial input data is
held in a 16-bit serial shift register. On CS’s rising edge, the
10 data-bits are transferred to the DAC register and update
the DAC. With CS high, data cannot be clocked into the
MAX504/MAX514.
The MAX504/MAX515 inputs data in 16-bit blocks. The SPI
and Microwire interfaces output data in 8-bit blocks, thereby requiring two write cycles to input data to the DAC. The
QSPI interface allows variable data input from 8 to 16 bits,
and can be loaded into the DAC in one write cycle.
SPI and QSPI are trademarks of Motorola, Inc. Microwire is a trademark of National Semiconductor Corp.
_______________________________________________________________________________________
9
MAX504/MAX515
code 0000.... REFIN’s input capacitance is also code
dependent and has a 50pF maximum value at several
codes.
If an upgrade to the internal reference is required, the 2.5V
MAX873A is suitable: ±15mV initial accuracy, TCVOUT =
7ppm/°C (max).
RS
REFOUT
MAX504/MAX515
5V, Low-Power, Voltage-Output,
Serial 10-Bit DACs
DIN
DIN
DOUT SCLK
CS
REFIN
VOUT
AGND DGND
DOUT
VOUT
INVERTED
R-2R DAC
REFOUT
33µF
CS
REFIN
INVERTED
R-2R DAC
2.048V
SCLK
CLR
2R
2R
2R
MAX504
VDD VSS
0.1µF
0.1µF
RFB
BIPOFF CONNECT BIPOFF
TO VOUT FOR G=1,
TO AGND FOR G=2,
OR TO REFIN FOR
+5V
BIPOLAR GAIN
0V to -5V
Figure 3a. MAX504 Typical Operating Circuit
2R
MAX515
AGND
VDD
0.1µF
MAX515
ONLY
+5V
Figure 3b. MAX515 Typical Operating Circuit
Daisy-Chaining Devices
Bipolar Configuration
The serial output, DOUT, allows cascading of two or more
DACs. The data at DIN appears at DOUT, delayed by 16
clock cycles plus one clock width. For low power, DOUT is
a CMOS output that does not require an external pull-up
resistor. DOUT does not go into a high-impedance state
when CS is high. DOUT changes on SCLK’s falling edge
when CS is low. When CS is high, DOUT remains in the
state of the last data bit.
Any number of MAX504/MAX515 DACs can be daisychained by connecting the DOUT of one device to the DIN
of the next device in the chain. For proper timing, ensure
that tCL (SCLK low) is greater than tDO + tDS.
A bipolar range is set up by connecting BIPOFF to
REFIN and RFB to VOUT, and operating from dual
(±5V) supplies (Figure 8). Table 3 shows the DAC-latch
contents (input) vs. VOUT (output). In this range,
1LSB = VREFIN (2 -9).
Unipolar Configuration
The MAX504 is configured for a gain of 1 (0V to VREFIN
unipolar output) by connecting BIPOFF and RFB to VOUT
(Figure 6). The converter operates from either single or
dual supplies in this configuration. See Table 1 for the
DAC-latch contents (input) vs. the analog VOUT (output).
In this range, 1LSB = VREFIN (2 -10), where VREF is the
voltage on REFIN.
A gain of 2 (0V to 2VREFIN unipolar output) is set up by
connecting BIPOFF to AGND and RFB to VOUT (Figure
7). Table 2 shows the DAC-latch contents vs. VOUT. The
MAX504 operates from either single or dual supplies in
this mode. In this range,
Four-Quadrant Multiplication
The MAX504 can be used as a four-quadrant multiplier
by connecting BIPOFF to REFIN and RFB to VOUT, and
using (1) an offset binary digital code, (2) bipolar power
supplies, and (3) a bipolar analog input at REFIN within
the range VSS + 2V to VDD - 2V, as shown in Figure 9.
In general, a 10-bit DAC’s output is (D)(VREFIN)(G),
where “G” is the gain (1 or 2) and “D” is the binary representation of the digital input divided by 210 or 1,024.
This formula is precise for unipolar operation. However,
for bipolar, offset binary operation, the MSB is really a
polarity bit. No resolution is lost because the number of
steps is the same. The output voltage, however, has
been shifted from a range of, for example, 0V to 4.096V
(G = 2) to a range of -2.048V to +2.048V.
Keep in mind that when using the DAC as a four-quadrant multiplier, the scale is skewed. Negative full scale
is -VREFIN, while positive full scale is +VREFIN - 1LSB.
1LSB = (2)(VREFIN)(2 -10) = (VREFIN)(2 -9).
The MAX515 is internally configured for unipolar gain of
2 operation.
10
______________________________________________________________________________________
5V, Low-Power, Voltage-Output,
Serial 10-Bit DACs
SK
DIN
SO
CS
I/O
DOUT
SCLK
MICROWIRE
PORT
MAX504
MAX515
SCK
DIN
MOSI
CS
I/O
DOUT
SI
MAX504/MAX515
MAX504
MAX515
SCLK
SPI
PORT
MISO
CPOL = 0, CPHA = 0
THE DOUT-SI CONNECTION IS NOT REQUIRED FOR WRITING TO THE
MAX504/MAX515, BUT MAY BE USED FOR VERIFYING DATA TRANSFER .
Figure 4. Microwire Connection
THE DOUT-MISO CONNECTION IS NOT REQUIRED FOR WRITING TO THE
MAX504/MAX515, BUT MAY BE USED FOR VERIFYING DATA TRANSFER .
Figure 5. SPI/QSPI Connection
+5V
+5V
VDD
REFIN
BIPOFF
REFOUT
VDD
REFIN
REFOUT
33µF
33µF
AGND
MAX504
MAX504
BIPOFF
RFB
RFB
AGND
DGND
VOUT
VOUT
VSS
VOUT
DGND
VSS
G=1
VOUT
G=2
0V TO -5V
0V TO -5V
Figure 6. Unipolar Configuration (0V to +2.048V Output)
Figure 7. Unipolar Configuration (0V to +4.096V Output)
Table 1. Unipolar Binary Code Table
(0V to VREFIN Output), Gain = 1
Table 2. Unipolar Binary Code Table
(0V to 2VREFIN Output), Gain = 2
OUTPUT
INPUT*
OUTPUT
INPUT*
1111
1111
11(00)
(VREFIN)
1023
1024
1111
1111
11(00)
+2 (VREFIN)
1023
1024
1000
0000
01(00)
(VREFIN)
513
1024
1000
0000
01(00)
+2 (VREFIN)
513
1024
1000
0000
00(00)
1000
0000
00(00)
+2 (VREFIN)
512
= +VREFIN
1024
0111
1111
11(00)
(VREFIN)
511
1024
0111
1111
11(00)
+2 (VREFIN)
511
1024
0000
0000
01(00)
(VREFIN)
1
1024
0000
0000
01(00)
+2 (VREFIN)
1
1024
0000
0000
00(00)
0000
0000
00(00)
(VREFIN)
512
= +VREFIN/2
1024
OV
* Write 10-bit data words with two sub-LSB 0s because the
DAC input latch is 12 bits wide.
OV
* Write 10-bit data words with two sub-LSB 0s because the
DAC input latch is 12 bits wide.
______________________________________________________________________________________
11
MAX504/MAX515
5V, Low-Power, Voltage-Output,
Serial 10-Bit DACs
Table 3. Bipolar (Offset Binary) Code
Table (-VREFIN to +VREFIN Output)
+5V
BIPOFF
REFOUT
33µF
OUTPUT
INPUT*
REFIN
1111
1111
11(00)
(+VREFIN)
511
512
1000
0000
01(00)
(+VREFIN)
1
512
1000
0000
00(00)
0111
1111
11(00)
(-VREFIN)
1
512
0000
0000
01(00)
(-VREFIN)
511
512
0000
0000
00(00)
(-VREFIN)
512
= -VREFIN
512
MAX504
RFB
AGND
DGND
VOUT
VOUT
0V
-5V
Figure 8. Bipolar Configuration (-2.048V to +2.048V Output)
* Write 10-bit data words with two sub-LSB 0s because the
DAC input latch is 12 bits wide.
Single-Supply Linearity
As with any amplifier, the MAX504/MAX515’s output
buffer offset can be positive or negative. When the offset is positive, it is easily accounted for (Figure 10).
However, when the offset is negative, the buffer output
cannot follow linearly when there is no negative supply.
In that case, the amplifier output (VOUT) remains at
ground until the DAC voltage is sufficient to overcome
the offset and the output becomes positive.
Normally, linearity is measured after accounting for
zero error and gain error. Since, in single-supply operation, the actual value of a negative offset is unknown, it
cannot be accounted for during test. Additionally, the
output buffer amplifier exhibits a nonlinearity near-zero
output when operating with a single supply. To account
for this nonlinearity in the MAX504/MAX515, linearity
and gain error are measured from code 3 to code
1023. The output buffer’s offset and nonlinearity do not
affect monotonicity, and these DACs are guaranteed
monotonic starting with code zero. In dual-supply operation, linearity and gain error are measured from code
0 to 1023.
Power-Supply Bypassing and
Ground Management
Best system performance is obtained with printed circuit boards that use separate analog and digital
ground planes. Wire-wrap boards are not recommended. The two ground planes should be connected
together at the low-impedance power-supply source.
12
DGND and AGND should be connected together at the
chip. For the MAX504 in single-supply applications,
connect VSS to AGND at the chip. The best ground
connection may be achieved by connecting the DAC's
DGND and AGND pins together and connecting that
point to the system analog ground plane. If the DAC's
DGND is connected to the system digital ground, digital noise may get through to the DAC’s analog portion.
Bypass V DD (and V SS in dual-supply mode) with a
0.1µF ceramic capacitor connected between VDD and
AGND (and between VSS and AGND). Mount it with
short leads close to the device. Ferrite beads may also
be used to further isolate the analog and digital power
supplies.
Figures 11a and 11b illustrate the grounding and
bypassing scheme described.
Saving Power
When the DAC is not being used by the system, minimize power consumption by setting the appropriate
code to minimize load current. For example, in bipolar
mode, with a resistive load to ground, set the DAC
code to mid-scale (see Table 3). If there is no output
load, minimize internal loading on the reference by setting the DAC to all 0s (on the MAX504, use CLR).
Under this condition, REFIN is high impedance and the
op amp operates at its minimum quiescent current.
Due to these low currents, the output settling time for a
zero input code typically increases to 60µs (100µs
max).
______________________________________________________________________________________
5V, Low-Power, Voltage-Output,
Serial 10-Bit DACs
REFOUT VDD
MAX504/MAX515
CS CLR DIN DOUT
VSS
2.048V
5
POSITIVE OFFSET
REFIN
MAX504
4
VOUT
INVERTED
R-2R DAC
2R
RFB
2R
BIPOFF
OUTPUT (LSBs)
SIGNAL
IN
3
2
NEGATIVE OFFSET
1
0
1
Figure 9. MAX504 Connected as Four-Quadrant Multiplier. The
unused REFOUT is connected to VDD.
2
3
4
5
DAC CODE (LSBs)
Figure 10. Single-Supply Offset
AC Considerations
Digital Feedthrough
High-speed serial data at any of the digital input or output
pins may couple through the DAC package and cause
internal stray capacitance to appear at the DAC output as
noise, even though CS is held high (see Typical Operating
Characteristics). This digital feedthrough is tested by holding CS high transmitting 0101... from DIN to DOUT.
Analog Feedthrough
Because of internal stray capacitance, higher frequency
analog input signals may couple to the output as shown in
the Analog Feedthrough vs. Frequency graph in the
Typical Operating Characteristics. It is tested by holding
CS high, setting the DAC code to all 0s, and sweeping
REFIN.
ANALOG GROUND PLANE
0.1µF
1
14
2
13
3
12
4
11
5
10
6
9
7
8
0.1µF
(a) MAX504 BYPASSING
1
8
2
7
3
6
4
5
0.1µF
(b) MAX515 BYPASSING
Figure 11. Power-Supply Bypassing
______________________________________________________________________________________
13
MAX504/MAX515
5V, Low-Power, Voltage-Output,
Serial 10-Bit DACs
____Pin Configurations (continued)
___________________Chip Information
TRANSISTOR COUNT: 922
TOP VIEW
BIPOFF
1
DIN
2
CLR 3
14 RFB
13 VDD
MAX504
SCLK 4
12 VOUT
11
VSS
CS
5
10 REFOUT
DOUT
6
9
REFIN
DGND 7
8
AGND
DIP/SO
14
______________________________________________________________________________________
5V, Low-Power, Voltage-Output,
Serial 10-Bit DACs
SOICN.EPS
______________________________________________________________________________________
15
MAX504/MAX515
________________________________________________________Package Information
___________________________________________Package Information (continued)
PDIPN.EPS
MAX504/MAX515
5V, Low-Power, Voltage-Output,
Serial 10-Bit DACs
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 1997 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
工商网监
湘ICP备2023018690号
