19-3661; Rev 1; 8/05
KIT
ATION
EVALU
LE
B
A
IL
A
AV
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
The MAX5066 is a two-phase, configurable single- or
dual-output buck controller with an input voltage range of
4.75V to 5.5V or from 5V to 28V. Each phase of the
MAX5066 is designed for 180° operation. A mode pin
allows for a dual-output supply or connecting two phases
together for a single-output, high-current supply. Each
output channel of the MAX5066 drives n-channel
MOSFETs and is capable of providing more than 25A of
load current. The MAX5066 uses average current-mode
control with a switching frequency up to 1MHz per phase
where each phase is 180° out of phase with respect to
the other. Out-of-phase operation results in significantly
reduced input capacitor ripple current and output voltage ripple in dual-phase, single-output voltage applications. Each buck regulator output has its own highperformance current and voltage-error amplifier that can
be compensated for optimum output filter L-C values and
transient response.
The MAX5066 offers two enable inputs with accurate
turn-on thresholds to allow for output voltage sequencing
of the two outputs. The device’s switching frequency can
be programmed from 100kHz to 1MHz with an external
resistor. The MAX5066 can be synchronized to an external clock. Each output voltage is adjustable from 0.61V to
5.5V. Additional features include thermal shutdown, “hiccup mode” short-circuit protection. Use the MAX5066
with adaptive voltage positioning for applications that
require a fast transient response, or accurate output voltage regulation.
The MAX5066 is available in a thermally enhanced 28-pin
TSSOP package capable of dissipating 1.9W. The device
is rated for operation over the -40°C to +85°C extended,
or -40°C to +125°C automotive temperature range.
Features
♦ 4.75V to 5.5V or 5V to 28V Input
♦ Dual-Output Synchronous Buck Controller
♦ Configurable for Two Separate Outputs or One
Single Output
♦ Each Output is Capable of Up to 25A Output
Current
♦ Average Current-Mode Control Provides Accurate
Current Limit
♦ 180° Interleaved Operation Reduces Size of Input
Filter Capacitors
♦ Limits Reverse Current Sinking When Operated in
Parallel Mode
♦ Each Output is Adjustable from 0.61V to 5.5V
♦ Independently Programmable Adaptive Voltage
Positioning
♦ Independent Shutdown for Each Output
♦ 100kHz to 1MHz per Phase Programmable
Switching Frequency
♦ Oscillator Frequency Synchronization from
200kHz to 2MHz
♦ Hiccup Mode Overcurrent Protection
♦ Overtemperature Shutdown
♦ Thermally Enhanced 28-Pin TSSOP Package
Capable of Dissipating 1.9W
♦ Operates Over -40°C to +85°C or -40°C to +125°C
Temperature Range
Ordering Information
Applications
High-End Desktop Computers
Graphics Cards
Networking Systems
PART
TEMP RANGE
PIN-PACKAGE
MAX5066EUI
-40°C to +85°C
28 TSSOP-EP*
MAX5066AUI
-40°C to +125°C
28 TSSOP-EP*
*Exposed Pad
Point-of-Load High-Current/High-Density
Telecom DC-DC Regulators
RAID Systems
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX5066
General Description
MAX5066
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
ABSOLUTE MAXIMUM RATINGS
IN to AGND.............................................................-0.3V to +30V
BST_ to AGND........................................................-0.3V to +35V
DH_ to LX_ ....................................-0.3V to (VBST_ - VLX_) + 0.3V
DL_ to PGND ..............................................-0.3V to (VDD + 0.3V)
BST_ to LX_ ..............................................................-0.3V to +6V
VDD to PGND............................................................-0.3V to +6V
AGND to PGND .....................................................-0.3V to +0.3V
REG, RT/CLKIN, CSP_, CSN_ to AGND ..................-0.3V to +6V
All Other Pins to AGND ............................-0.3V to (VREG + 0.3V)
REG Continuous Output Current
(Limited by Power Dissipation, No Thermal or Short-Circuit
Protection).........................................................................67mA
REF Continuous Output Current ........................................200µA
Continuous Power Dissipation (TA = +70°C)
28-Pin TSSOP (derate 23.8mW/°C above +70°C) .....1904mW
Package Thermal Resistance (θJC) ...................................2°C/W
Operating Temperature Ranges
MAX5066EUI ...................................................-40°C to +85°C
MAX5066AUI .................................................-40°C to +125°C
Maximum Junction Temperature .....................................+150°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VIN = VREG = VDD = VEN_ = +5V, TA = TJ = TMIN to TMAX, unless otherwise noted, circuit of Figure 6. Typical values are at TA = +25°C.)
(Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SYSTEM SPECIFICATIONS
Input Voltage Range
VIN
IN and REG shorted together for +5V
operation
Quiescent Supply Current
IIN
fOSC = 500kHz, DH_, DL_ = open
5
28
4.75
5.5
V
4
20
mA
4.5
V
STARTUP/INTERNAL REGULATOR OUTPUT (REG)
REG Undervoltage Lockout
UVLO
VREG rising
4.0
4.15
Hysteresis
REG Output Accuracy
VHYST
VIN = 5.8V to 28V, ISOURCE = 0 to 65mA
4.75
5.10
REG Dropout
VIN < 5.8V, ISOURCE = 60mA
200
mV
5.30
V
0.5
V
INTERNAL REFERENCE
Internal Reference Voltage
VEAN_
EAN_ connected to EAOUT_ (Note 2)
Internal Reference Voltage
Accuracy
VEAN_
VIN = VREG = 4.75V to 5.5V or VIN = 5V to
28V, EAN_ connected to EAOUT_ (Note 2)
0.6135
-0.9
V
+0.9
%
3.37
V
3.4
V
EXTERNAL REFERENCE VOLTAGE OUTPUT (REF)
Accuracy
VREF
Load Regulation
IREF = 100µA
3.23
IREF = 0 to 200µA
3.2
3.3
MOSFET DRIVERS
p-Channel Output Driver
Impedance
RON_P
1.35
4
Ω
n-Channel Output Driver
Impedance
RON_N
0.45
1.35
Ω
Output Driver Source Current
IDH_, IDL_
2.5
A
Output Driver Sink Current
IDH_, IDL_
8
A
30
ns
Nonoverlap Time (Dead Time)
2
tNO
CDH_ or CDL_ = 5nF
_______________________________________________________________________________________
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
(VIN = VREG = VDD = VEN_ = +5V, TA = TJ = TMIN to TMAX, unless otherwise noted, circuit of Figure 6. Typical values are at TA = +25°C.)
(Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
OSCILLATOR
Switching Frequency
fSW
Switching Frequency Accuracy
1MHz (max)
switching
frequency per
phase
RRT = 12.4kΩ
1000
RRT = 127kΩ
100
kHz
fSW = 250kHz nominal, RRT = 50kΩ
-7.5
+7.5
fSW = 1MHz nominal, RRT = 12.4kΩ
-10
+10
%
RT/CLKIN Output Voltage
VRT/CLKIN
1.225
V
RT/CLKIN Current Sourcing
Capability
IRT/CLKIN
0.5
mA
RT/CLKIN Logic-High Threshold
VRT/CLKIN_H
RT/CLKIN Logic-Low Threshold
VRT/CLKIN_L
RT/CLKIN High Pulse Width
tRT/CLKIN
RT/CLKIN Synchronization
Frequency Range
fRT/CLKIN
2.4
V
0.8
30
200
V
ns
2000
kHz
CURRENT LIMIT
Average Current-Limit Threshold
VCL_
VCSP_ - VCSN_
20.4
22.5
24.75
mV
Reverse Current-Limit Threshold
VRCL_
VCSP_ - VCSN_
-3.13
-1.63
-0.1
mV
Cycle-by-Cycle Current-Limit
Threshold
VCLpk_
VCSP_ - VCSN_
Cycle-by-Cycle Current-Limit
Response Time
52.5
mV
tR
260
ns
Number of Switching Cycles to
Shutdown in Current-Limit
NSDF_
32,768
Clock
cycles
Number of Switching Cycles to
Recover from Shutdown
NRDF_
524,288
Clock
cycles
RCS_
1.9835
kΩ
DIGITAL FAULT INTEGRATION (DF_)
CURRENT-SENSE AMPLIFIER
CSP_ to CSN_ Input Resistance
Common-Mode Range
Input Offset Voltage
Amplifier Gain
-3dB Bandwidth
CSP_ Input Bias Current
VCMR(CS)
VIN = VREG = 4.75V to 5.5V or
VIN = 5V to 10V
-0.3
+3.6
V
VIN = 7V to 28V
-0.3
+5.5
V
VOS(CS)
100
µV
AV(CS)
36
V/V
f-3dB
4
MHz
ICSA(IN)
VCSP_ = 5.5V, sinking
120
VCSP_ = 0V, sourcing
30
µA
_______________________________________________________________________________________
3
MAX5066
ELECTRICAL CHARACTERISTICS (continued)
MAX5066
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
ELECTRICAL CHARACTERISTICS (continued)
(VIN = VREG = VDD = VEN_ = +5V, TA = TJ = TMIN to TMAX, unless otherwise noted, circuit of Figure 6. Typical values are at TA = +25°C.)
(Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CURRENT-ERROR AMPLIFIER (CEA_)
Transconductance
Open-Loop Gain
gM
AVOL(CEA)
No load
550
µS
50
dB
VOLTAGE ERROR AMPLIFIER (EAOUT_)
Open-Loop Gain
Unity-Gain Bandwidth
AVOL(EA)
70
dB
fUGEA
3
MHz
VEAN_ = 2.0V
100
nA
With respect to VCM
1.14
V
With respect to VCM
-0.234
V
EAN_ Input Bias Current
IBIAS(EA)
Error Amplifier Output Clamping
High Voltage
VCLMP_HI
Error Amplifier Output Clamping
Low Voltage
VCLMP_LO
(EA)
(EA)
EN_ INPUTS
EN_ Input High Voltage
VENH
EN rising
1.204
EN_ Hysteresis
EN_ Input Leakage Current
1.222
1.240
0.05
IEN
-1
+1
MODE Logic-High Threshold
VMODE_H
2.4
MODE Logic-Low Threshold
VMODE_L
MODE Input Pulldown
IPULLDWN
5
Thermal Shutdown
TSHDN
160
Thermal Shutdown Hysteresis
THYST
10
V
µA
MODE INPUT
V
0.8
V
µA
THERMAL SHUTDOWN
°C
Note 1: The device is 100% production tested at TA = +85°C (MAX5066EUI) and TA = TJ = +125°C (MAX5066AUI). Limits at -40°C
and +25°C are guaranteed by design.
Note 2: The internal reference voltage accuracy is measured at the negative input of the error amplifiers (EAN_). Output voltage
accuracy must include external resistor-divider tolerances.
4
_______________________________________________________________________________________
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
16
SUPPLY CURRENT (mA)
1000
100
10
fSW = 500kHz
12
10
8
fSW = 250kHz
6
16
fSW = 125kHz
12
fSW = 1MHz
fSW = 500kHz
10
8
fSW = 250kHz
6
4
2
2
0
fSW = 125kHz
0
-40 -25 -10 5 20 35 50 65 80 95 110 125
RT (kΩ)
TEMPERATURE (°C)
TEMPERATURE (°C)
SUPPLY CURRENT
vs. TEMPERATURE AND FREQUENCY
(VIN = 24V)
SUPPLY CURRENT
vs. OSCILLATOR FREQUENCY
SUPPLY CURRENT
vs. DRIVER LOAD CAPACITANCE
12
10
8
fSW = 250kHz
6
fSW = 125kHz
4
13
SUPPLY CURRENT (mA)
fSW = 500kHz
CDH_ = CDL_ = 0
12
11
VIN = 12V
VIN = 24V
10
9
8
2
7
0
6
70
60
50
40
30
10
0
TEMPERATURE (°C)
FREQUENCY (kHz)
REG LOAD REGULATION
5.05
80
20
200 400 600 800 1000 1200 1400 1600 1800 2000
0
REG LINE REGULATION
10
15
20
25
30
REF LOAD REGULATION
3.305
MAX5066 toc06
5.08
5
CLOAD (nF)
5.10
MAX5066 toc05
VIN = 24V
CLOAD = CDH = CDL
90
VIN = 5V
-40 -25 -10 5 20 35 50 65 80 95 110 125
5.10
100
IREG = 0
MAX5066 toc07
14
14
SUPPLY CURRENT (mA)
fSW = 1MHz
MAX5066 toc03
CDH = CDL = 0
MAX5066 toc04
-40 -25 -10 5 20 35 50 65 80 95 110 125
MAX5066 toc02c
16
CDH = CDL = 0
14
4
0 100 200 300 400 500 600 700 800 900 1000
SUPPLY CURRENT (mA)
fSW = 1MHz
CDH = CDL = 0
14
SUPPLY CURRENT (mA)
MAX5066 toc01
OSCILLATOR FREQUENCY (kHz)
CDH = CDL = 0
MAX5066 toc02a
OSCILLATOR FREQUENCY vs. RT
10,000
SUPPLY CURRENT
vs. TEMPERATURE AND FREQUENCY
(VIN = 12V)
MAX5066 toc02b
SUPPLY CURRENT
vs. TEMPERATURE AND FREQUENCY
(VIN = 5V)
3.300
5.06
VREF (V)
VIN = 12V
5.00
VREG (V)
VREG (V)
VIN = 24V
5.04
5.02
VIN = 12V
3.295
VIN = 5.5V
VIN = 5V
5.00
4.95
3.290
IREG = 60mA
4.98
4.90
4.96
0
10 20 30 40 50 60 70 80 90 100
IREG (mA)
3.285
5
7
9
11
13
15
VIN (V)
17
19
21
23
0
100 200 300 400 500 600 700 800
IREF (µA)
_______________________________________________________________________________________
5
MAX5066
Typical Operating Characteristics
(Circuit of Figure 6, TA = +25°C, unless otherwise noted. VIN = 12V, VOUT1 = 0.8V, VOUT2 = 1.3V, fSW = 500kHz per phase.)
Typical Operating Characteristics (continued)
(Circuit of Figure 6, TA = +25°C, unless otherwise noted. VIN = 12V, VOUT1 = 0.8V, VOUT2 = 1.3V, fSW = 500kHz per phase.)
90
80
70
3.300
60
tRISE (ns)
3.301
3.299
30
DL
50
5
10
3.296
0
5
7
9
11
13
15 17
19
21
DL
20
10
20
IREF = 200µA
25
15
30
3.297
DH
DH
40
3.298
35
tFALL (ns)
IREF = 0
40
MAX5066 toc09
3.302
100
MAX5066 toc08
3.303
DRIVER FALL TIME
vs. LOAD CAPACITANCE
0
23
0
2
VIN (V)
4
6
8 10 12 14 16 18 20 22
0
2
4
6
8 10 12 14 16 18 20 22
CLOAD (nF)
CLOAD (nF)
HIGH-SIDE DRIVER RISE TIME
(VIN = 12V, CLOAD = 10nF)
HIGH-SIDE DRIVER FALL TIME
(VIN = 12V, CLOAD = 10nF)
MAX5066 toc11
MAX5066 toc12
DH_
2V/div
DH_
2V/div
20ns/div
20ns/div
LOW-SIDE DRIVER RISE TIME
(VIN = 12V, CLOAD = 10nF)
MAX5066 toc13
DL_
2V/div
20ns/div
6
MAX5066 toc10
DRIVER RISE TIME
vs. LOAD CAPACITANCE
REF LINE REGULATION
VREF (V)
MAX5066
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
_______________________________________________________________________________________
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
LOW-SIDE DRIVER FALL TIME
(VIN = 12V, CLOAD = 10nF)
OUT1/OUT2 OUT-OF-PHASE WAVEFORMS
(VOUT1 = 0.8V, VOUT2 = 1.3V)
MAX5066 toc14
MAX5066 toc15
LX1
10V/div
OUT1
100mV/div
DL_
2V/div
LX2
10V/div
OUT2
100mV/div
20ns/div
10µs/div
TURN-ON/-OFF WAVEFORMS
(IOUT1 = IOUT2 = 10A)
SHORT-CIRCUIT CURRENT WAVEFORMS
(VIN = 5V)
MAX5066 toc17
MAX5066 toc16
VOUT1
1V/div
IOUT1
10A/div
EN1
5V/div
VOUT2
1V/div
IOUT2
10A/div
EN2
5V/div
2ms/div
200ms/div
_______________________________________________________________________________________
7
MAX5066
Typical Operating Characteristics (continued)
(Circuit of Figure 6, TA = +25°C, unless otherwise noted. VIN = 12V, VOUT1 = 0.8V, VOUT2 = 1.3V, fSW = 500kHz per phase.)
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
MAX5066
Pin Description
PIN
NAME
1
CSN2
Current-Sense Differential Amplifier Negative Input for Output2. Connect CSN2 to the negative
terminal of the sense resistor. The differential voltage between CSP2 and CSN2 is internally amplified
by the current-sense amplifier (AV(CS) = 36V/V).
2
CSP2
Current-Sense Differential Amplifier Positive Input for Output2. Connect CSP2 to the positive terminal
of the sense resistor. The differential voltage between CSP2 and CSN2 is internally amplified by the
current-sense amplifier (AV(CS) = 36V/V).
3
Voltage Error-Amplifier Output2. Connect to an external gain-setting feedback resistor. The erroramplifier gain determines the output voltage load regulation for adaptive voltage positioning. This
output also serves as the compensation network connection from EAOUT2 to EAN2. A resistive
network results in a drooped output voltage regulation characteristic. An integrator configuration
results in very tight output voltage regulation (see the Adaptive Voltage Positioning section).
4
EAN2
Voltage Error-Amplifier Inverting Input for Output2. Connect a resistive divider from VOUT2 to EAN2 to
AGND to set the output voltage. A compensation network connects from EAOUT2 to EAN2. A
resistive network results in a drooped output-voltage-regulation characteristic. An integrator
configuration results in very tight output-voltage regulation (see the Adaptive Voltage Positioning
section).
5
CLP2
Current-Error Amplifier Output2. Compensate the current loop by connecting an R-C network from
CLP2 to AGND.
6
REF
3.3V Reference Output. Bypass REF to AGND with a minimum 0.1µF ceramic capacitor. REF can
source up to 200µA for external loads.
7
RT/CLKIN
8
AGND
Analog Ground
9
MODE
Mode Function Input. MODE selects between a single-output dual phase or a dual-output buck
regulator. When MODE is grounded, VEA1 and VEA2 connect to CEA1 and CEA2, respectively (see
Figure 1) and the device operates as a two-output, out-of-phase buck regulator. When MODE is
connected to REG (logic high), VEA2 is disconnected and VEA1 is routed to both CEA1 and CEA2.
10
CLP1
Current-Error Amplifier Output1. Compensate the current loop by connecting an R-C network from
CLP1 to AGND.
EAN1
Voltage Error Amplifier Inverting Input for Output1. Connect a resistive divider from VOUT1 to EAN1 to
regulate the output voltage. A compensation network connects from EAOUT1 to EAN1. A resistive
network results in a drooped output-voltage-regulation characteristic. An integrator configuration
results in very tight output voltage regulation (see the Adaptive Voltage Positioning section).
11
8
EAOUT2
FUNCTION
12
EAOUT1
13
CSP1
External Clock Input or Internal Frequency-Setting Connection. Connect a resistor from RT/CLKIN to
AGND to set the switching frequency. Connect an external clock at RT/CLKIN for external frequency
synchronization.
Voltage Error Amplifier Output1. Connect to an external gain-setting feedback resistor. The error
amplifier gain determines the output-voltage-load regulation for adaptive voltage positioning. This
output also serves as the compensation network connection from EAOUT1 to EAN1. A resistive
network results in a drooped output-voltage-regulation characteristic. An integrator configuration
results in very tight output-voltage regulation (see the Adaptive Voltage Positioning section).
Current-Sense Differential Amplifier Positive Input for Output1. Connect CSP1 to the positive terminal
of the sense resistor. The differential voltage between CSP1 and CSN1 is internally amplified by the
current-sense amplifier (AV(CS) = 36V/V).
_______________________________________________________________________________________
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
PIN
NAME
FUNCTION
14
CSN1
15
EN1
Output 1 Enable. A logic-low shuts down channel 1’s MOSFET drivers. EN1 can be used for output
sequencing.
16
BST1
Boost Flying Capacitor Connection. Reservoir capacitor connection for the high-side MOSFET driver
supply. Connect a 0.47µF ceramic capacitor between BST1 and LX1.
17
DH1
High-Side Gate Driver Output1. DH1 drives the gate of the high-side MOSFET.
18
LX1
External inductor connection and source connection for the high-side MOSFET for Output1. LX1 also
serves as the return terminal for the high-side MOSFET driver.
19
DL1
Low-Side Gate Driver Output1. Gate driver output for the synchronous MOSFET.
20
VDD
Supply Voltage for Low-Side Drivers. REG powers VDD. Connect a parallel combination of 0.1µF and
1µF ceramic capacitors from VDD to PGND and a 1Ω resistor from VDD to REG to filter out the highpeak currents of the driver from the internal circuitry.
21
REG
Internal 5V Regulator Output. REG is derived internally from IN and is used to power the internal bias
circuitry. Bypass REG to AGND with a 4.7µF ceramic capacitor.
22
IN
23
PGND
24
DL2
Low-Side Gate Driver Output2. Gate driver for the synchronous MOSFET.
25
LX2
External inductor connection and source connection for the high-side MOSFET for Output2. Also
serves as the return terminal for the high-side MOSFET driver.
26
DH2
High-Side Gate Driver Output2. DH2 drives the gate of the high-side MOSFET.
27
BST2
Boost Flying Capacitor Connection. Reservoir capacitor connection for the high-side MOSFET driver
supply. Connect a 0.47µF ceramic capacitor between BST2 and LX2.
28
EN2
Output 2 Enable. A logic-low shuts down channel 2’s MOSFET drivers. EN2 can be used for output
sequencing.
EP
EP
Current-Sense Differential Amplifier Negative Input for Output1. Connect CSN1 to the negative
terminal of the sense resistor. The differential voltage between CSP1 and CSN1 is internally amplified
by the current-sense amplifier (AV(CS) = 36V/V).
Supply Voltage Connection. Connect IN to a 5V to 28V input supply.
Power Ground. Source connection for the low-side MOSFET. Connect VDD’s bypass capacitor returns
to PGND.
Exposed Pad. Connect exposed pad to ground plane.
Detailed Description
The MAX5066 switching power-supply controller can
be configured in two ways. With the MODE input high, it
operates as a single-output, dual-phase, step-down
switching regulator where each output is 180° out of
phase. With the MODE pin connected low, the
MAX5066 operates as a dual-output, step-down switching regulator. The average current-mode control topology of the MAX5066 offers high-noise immunity while
having benefits similar to those of peak current-mode
control. Average current-mode control has the intrinsic
ability to accurately limit the average current sourced
by the converter during a fault condition. When a fault
condition occurs, the error amplifier output voltage
(EAOUT1 or EAOUT2) that connects to the positive
input of the transconductance amplifier (CA1 or CA2) is
clamped thus limiting the output current.
The MAX5066 contains all blocks necessary for two
independently regulated average current-mode PWM
regulators. It has two voltage error amplifiers (VEA1
and VEA2), two current-error amplifiers (CEA1 and
CEA2), two current-sensing amplifiers (CA1 and CA2),
two PWM comparators (CPWM1 and CPWM2), and drivers for both low- and high-side power MOSFETs (see
Figure 1). Each PWM section is also equipped with a
pulse-by-pulse, current-limit protection and a fault integration block for hiccup protection.
_______________________________________________________________________________________
9
MAX5066
Pin Description (continued)
MAX5066
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
13 CSP1
CLP1 10
EAOUT1
12
EAN1
11
CA1
14 CSN1
DF1 AND
HICCUP
LOGIC
CEA1
VEA1
16 BST1
CPWM1
17 DH1
IN
22
REG
21
EN1
15
REF
6
UVLO
VREG = 5V
2VP-P
RAMP
CONTROL
AND DRIVER
LOGIC 1
FOR INTERNAL
BIASING
18 LX1
20 VDD
19 DL1
CEN1
0°
1.225V
VREF = 3.3V
VINTREF = 0.61V
THERMAL
SHUTDOWN
UV33
OSCILLATOR
AND PHASE
SPLITTER
1.225V
EXTERNAL FREQUENCY SYNC
27 BST2
180°
CEN2
26 DH2
EN2 28
CONTROL
AND DRIVER
LOGIC 2
2VP-P
RAMP
AGND
7 RT/CLKIN
8
25 LX2
VDD
24 DL2
VEA2
EAN2
4
EAOUT2
3
MODE
9
MUX
CPWM2
23 PGND
CEA2
DF2 AND
HICCUP
LOGIC
2 CSP2
CA2
CLP2
5
1 CSN2
Figure 1. Block Diagram
Two enable comparators (CEN1 and CEN2) are available to control and sequence the two PWM sections
through the enable (EN1 or EN2) inputs. An oscillator,
with an externally programmable frequency generates
two clock pulse trains and two ramps for both PWM
sections. The two clocks and the two ramps are 180°
out of phase with each other.
A linear regulator (REG) generates the 5V to supply the
device. This regulator has the output-current capability
10
necessary to provide for the MAX5066’s internal circuitry and the power for the external MOSFET’s gate drivers. A low-current linear regulator (REF) provides a
precise 3.3V reference output and is capable of driving
loads of up to 200µA. Internal UVLO circuitry ensures
that the MAX5066 starts up only when VREG and VREF
are at the correct voltage levels to guarantee safe operation of the IC and of the power MOSFETs.
______________________________________________________________________________________
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
Dual-Output/Dual-Phase Select (MODE)
The MAX5066 can operate as a dual-output independently regulated buck converter, or as a dual-phase,
single-output buck converter. The MODE input selects
between the two operating modes. When MODE is
grounded (logic low), VEA1 and VEA2 connect to CEA1
and CEA2, respectively (see Figure 1) and the device
operates as a two-output DC-DC converter. When
MODE is connected to REG (logic high), VEA2 is disconnected and VEA1 is routed to both CEA1 and CEA2
and the device works as a dual-phase, single-output
buck regulator with each output 180° out of phase with
respect to each other.
Supply Voltage Connections (VIN/VREG)
The MAX5066 accepts a wide input voltage range at IN
of 5V to 28V. An internal linear regulator steps down VIN
to 5.1V (typ) and provides power to the MAX5066. The
output of this regulator is available at REG. For VIN =
4.75V to 5.5V, connect IN and REG together externally.
REG can supply up to 65mA for external loads. Bypass
REG to AGND with a 4.7µF ceramic capacitor for highfrequency noise rejection and stable operation.
REG supplies the current for both the MAX5066’s internal circuitry and for the MOSFET gate drivers (when
connected externally to VDD), and can source up to
65mA. Calculate the maximum bias current (IBIAS) for
the MAX5066:
IBIAS = IIN + fSW × (QGQ1 + QGQ2 + QGQ3 + QGQ4 )
where IIN is the quiescent supply current into IN (4mA,
typ), Q GQ1 , Q GQ2 , Q GQ3 , Q GQ4 are the total gate
charges of MOSFETs Q1 through Q4 at VGS = 5V (see
Figure 6), and fSW is the switching frequency of each
individual phase.
Low-Side MOSFET Driver Supply (VDD)
VDD is the power input for the low-side MOSFET drivers. Connect the regulator output REG externally to
VDD through an R-C lowpass filter. Use a 1Ω resistor
and a parallel combination of 1µF and 0.1µF ceramic
capacitors to filter out the high peak currents of the
MOSFET drivers from the sensitive internal circuitry.
High-Side MOSFET Drive Supply (BST_)
BST1 and BST2 supply the power for the high-side
MOSFET drivers for output 1 and output 2, respectively.
Connect BST1 and BST2 to V DD through rectifier
diodes D1 and D2 (see Figure 6). Connect a 0.1µF
ceramic capacitor between BST_ and LX_.
Minimize the trace inductance from BST_ and VDD to
rectifier diodes, D1 and D2, and from BST_ and LX_ to
the boost capacitors, C8 and C9 (see Figure 6). This is
accomplished by using short, wide trace lengths.
Undervoltage Lockout (UVLO)/
Power-On Reset (POR)/Soft-Start
The MAX5066 includes an undervoltage lockout
(UVLO) with hysteresis, and a power-on reset circuit for
converter turn-on and monotonic rise of the output voltage. The UVLO threshold monitors VREG and is internally set between 4.0V and 4.5V with 200mV of
hysteresis. Hysteresis eliminates “chattering” during
startup. Most of the internal circuitry, including the
oscillator, turns on when V REG reaches 4.5V. The
MAX5066 draws up to 4mA (typ) of current before
VREG reaches the UVLO threshold.
The compensation network at the current-error amplifiers (CLP1 and CLP2) provides an inherent soft-start of
the output voltage. It includes (R14 and C10) in parallel
with C11 at CLP1 and (R15 and C12) in parallel with
C13 at CLP2 (see Figure 6). The voltage at the currenterror amplifier output limits the maximum current available to charge the output capacitors. The capacitor at
CLP_ in conjunction with the finite output-drive current
of the current-error amplifier yields a finite rise time for
the output current and thus the output voltage.
Setting the Switching Frequency (fSW)
An internal oscillator generates the 180o out-of-phase
clock signals required for both PWM modulators. The
oscillator also generates the 2VP-P voltage ramps necessary for the PWM comparators. The oscillator frequency can be set from 200kHz to 2MHz by an external
resistor (RT) connected from RT/CLKIN to AGND (see
Figure 6). The equation below shows the relationship
between RT and the switching frequency:
fOSC =
2.5 × 1010
Hz
RRT
where RRT is in ohms and fSW(PER PHASE) = fOSC/2.
Use RT/CLKIN as a clock input to synchronize the
MAX5066 to an external frequency (fRT/CLKIN). Applying
an external clock to RT/CLKIN allows each PWM section
to work at a frequency equal to fRT/CLKIN/2. An internal
comparator with a 1.6V threshold detects fRT/CLKIN. If
fRT/CLKIN is present, internal logic switches from the
internal oscillator clock, to the clock present at
RT/CLKIN.
______________________________________________________________________________________
11
MAX5066
Finally, a thermal-shutdown feature protects the device
during thermal faults and shuts down the MAX5066
when the die temperature exceeds +160°C.
MAX5066
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
Hiccup Fault Protection
The MAX5066 includes overload fault protection circuitry that prevents damage to the power MOSFETs. The
fault protection consists of two digital fault integration
blocks that enable “hiccuping” under overcurrent conditions. This circuit works as follows: for every clock
cycle the current-limit threshold is exceeded, the fault
integration counter increments by one count. Thus, if
the current-limit condition persists, then the counter
reaches its shutdown threshold in 32,768 counts and
shuts down the external MOSFETs. When the MAX5066
shuts down due to a fault, the counter begins to count
down, (since the current-limit condition has ended),
once every 16 clock cycles. Thus, the device counts
down for 524,288 clock cycles. At this point, switching
resumes. This produces an effective duty cycle of
6.25% power-up and 93.75% power-down under fault
conditions. With a switching frequency set to 250kHz,
power-up and power-down times are approximately
131ms and 2.09s, respectively.
Control Loop
The MAX5066 uses an average current-mode control
topology to regulate the output voltage. The control
CSN1
CSP1
RCF
loop consists of an inner current loop and an outer voltage loop. The inner current loop controls the output
current, while the outer voltage loop controls the output
voltage. The inner current loop absorbs the inductor
pole, reducing the order of the outer voltage loop to
that of a single-pole system. Figure 2 is the block diagram of OUT1’s control loop.
The current loop consists of a current-sense resistor,
RSENSE, a current-sense amplifier (CA1), a currenterror amplifier (CEA1), an oscillator providing the carrier ramp, and a PWM comparator (CPWM1). The
precision current-sense amplifier (CA1) amplifies the
sense voltage across RSENSE by a factor of 36. The
inverting input to CEA1 senses the output of CA1. The
output of CEA1 is the difference between the voltageerror amplifier output (EAOUT1) and the gained-up voltage from CA1. The RC compensation network
connected to CLP1 provides external frequency compensation for the respective CEA1 (see the
Compensation section). The start of every clock cycle
enables the high-side driver and initiates a PWM oncycle. Comparator CPWM1 compares the output voltage from CEA1 against a 0 to 2V ramp from the
CCF
CA 1
CLP1
RF
CCFF
VIN
IL
CEA1
CPWM1
VEA1
RSENSE
VOUT1
DRIVE
2VP-P
R1
COUT
LOAD
VREF = 0.61V
R2
Figure 2. Current and Voltage Loops
12
______________________________________________________________________________________
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
Peak-Current Comparator
The peak-current comparator (see Figure 3) monitors
the voltage across the current-sense resistor (RSENSE)
and provides a fast cycle-by-cycle current limit with a
threshold of 52.5mV. Note that the average current-limit
threshold of 22.5mV still limits the output current during
short-circuit conditions. To prevent inductor saturation,
select an output inductor with a saturation current
specification greater than the average current limit of
22.5mV/RSENSE. Proper inductor selection ensures that
only extreme conditions trip the peak-current comparator, such as a damaged output inductor. The typical
propagation delay of the peak current-limit comparator
is 260ns.
Current-Error Amplifier
The MAX5066 has two dedicated transconductance
current-error amplifiers CEA1 and CEA2 with a typical
gM of 550µS and 320µA output sink and source capability. The current-error amplifier outputs (CLP1 and CLP2)
serve as the inverting input to the PWM comparators.
CLP1 and CLP2 are externally accessible to provide frequency compensation for the inner current loops (see
CCFF, CCF, and RCF in Figure 2). Compensate the current-error amplifier such that the inductor current down
slope, which becomes the up slope at the inverting
input of the PWM comparator, is less than the slope of
the internally generated voltage ramp (see the
Compensation section).
PWM Comparator and R-S Flip-Flop
The PWM comparator (CPWM1 or CPWM2) sets the
duty cycle for each cycle by comparing the currenterror amplifier output to a 2VP-P ramp. At the start of
each clock cycle an R-S flip-flop resets and the highside drivers (DH1 and DH2) turn on. The comparator
sets the flip-flop as soon as the ramp voltage exceeds
the current-error amplifier output voltage, thus terminating the on cycle.
Voltage Error Amplifier
The voltage-error amplifier (VEA_) sets the gain of the
voltage control loop. Its output clamps to 1.14V and
-0.234V relative to VCM = 0.61V. Set the MAX5066 output voltage by connecting a voltage-divider from the
output to EAN_ to GND (see Figure 4). At no load the
output of the voltage error amplifier is zero.
Use the equation below to calculate the no load voltage:
⎛
R ⎞
VOUT(NL) = 0.6135 × ⎜1 + 1 ⎟
⎝ R2 ⎠
The voltage at full load is given by:
⎛
R ⎞
VOUT(FL) = 0.6135 × ⎜1 + 1 ⎟ − ∆VOUT
⎝ R2 ⎠
where ∆V OUT is the voltage-positioning window
described in the Adaptive Voltage Positioning section.
Adaptive Voltage Positioning
Powering new-generation ICs requires new techniques
to reduce cost, size, and power dissipation. Voltage
positioning (Figure 5) reduces the total number of output capacitors to meet a given transient response
requirement. Setting the no-load output voltage slightly
higher than the output voltage during nominally loaded
conditions allows a larger downward voltage excursion
when the output current suddenly increases.
Regulating at a lower output voltage under a heavy
load allows a larger upward-voltage excursion when
the output current suddenly decreases. A larger
allowed voltage-step excursion reduces the required
number of output capacitors and/or allows the use of
higher ESR capacitors.
The internal 0.61V reference in the MAX5066 has a tolerance of ±0.9%. If we use 0.1% resistors for R1 and R2,
we still have another 4% available for the variation in the
output voltage from nominal. This available voltage
range allows us to reduce the total number of output
capacitors to meet a given transient response requirement. This results in a voltage-positioning window as
shown in Figure 5.
From the allowable voltage-positioning window we can
calculate the value of RF from the equation below.
I
× RSENSE × 36 × R1
RF = OUT
∆VOUT
where ∆VOUT is the allowable voltage-positioning window, RSENSE is the sense resistor, 36 is the currentsense amplifier gain, and R1 is as shown in Figure 4.
______________________________________________________________________________________
13
MAX5066
oscillator. The PWM on-cycle terminates when the ramp
voltage exceeds the error voltage from the current-error
amplifier (CEA1).
The outer voltage control loop consists of the voltageerror amplifier (VEA1). The noninverting input (EAN1) is
externally connected to the midpoint of a resistive voltage-divider from OUT1 to EAN1 to AGND. The voltage
loop gain is set by using an external resistor from the
output of this amplifier (EAOUT1) to its inverting input
(EAN1). The noninverting input of (VEA1) is connected
to the 0.61V internal reference.
MAX5066
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
VDD
PEAK-CURRENT
COMPARATOR
52.5mV
CLP_
AV = 36
CSP_
gM = 500µS
CSN_
BST_
PWM
COMPARATOR
GMIN
Q
S
DH_
RAMP
LX_
2 x fSW (V/S)
CLK
R
Q
DL_
1.225V
PGND
EN_
Figure 3. Current Comparator and MOSFET Driver Logic
VOUT
VOLTAGE-POSITIONING WINDOW
VCNTR + ∆VOUT/2
RF
VCNTR
R1
COUT
EAN_
LOAD
VCNTR - ∆VOUT/2
EAOUT_
R2
VREF = 0.61V
NO LOAD
1/2 LOAD
FULL LOAD
LOAD (A)
Figure 4. Voltage Error Amplifier
MOSFET Gate Drivers (DH_, DL_)
The high-side drivers (DH1 and DH2) and low-side drivers (DL1 and DL2) drive the gates of external n-channel
MOSFETs. The high-peak sink and source current capability of these drivers provides ample drive for the fast
rise and fall times of the switching MOSFETs. Faster rise
and fall times result in reduced switching losses. For low14
Figure 5. Defining the Voltage-Positioning Window
output, voltage-regulating applications where the duty
cycle is less than 50%, choose high-side MOSFETs (Q2
and Q4, Figure 6) with a moderate RDS(ON) and a very
low gate charge. Choose low-side MOSFETs (Q1 and
Q3, Figure 6) with very low RDS(ON) and moderate gate
charge. The driver block also includes a logic circuit that
provides an adaptive nonoverlap time (30ns typical) to
______________________________________________________________________________________
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
MAX5066
VIN
IN
VDD
D1
(100mA, 30V)
REG
BST1
0.8V/10A
C8
0.1µF
BST2
C4
4.7µF
C9
0.1µF
DH2
LX1
Q1
IRF7832
LX2
DL1
D3
(1A, 30V)
C3
0.1µF
Q4
IRF7821
DH1
MAX5066
C6
680µF
D2
(100mA, 30V)
22Ω
Q2
IRF7821
L1
0.5µH
R3
1Ω
22Ω
C2
1µF
R1
2mΩ
C5
10µF
L2
0.8µH
Q3
IRF7832
D4
(1A, 30V)
DL2
R2
2mΩ
1.3V/10A
C7
680µF
PGND
R4
1.74kΩ
CSP1
CSN1
CSP2
EAN1
CSN2
EAN2
EAOUT1
R5
4.64kΩ
EAOUT2
R8
29.4kΩ
MODE
VREG OR VREF
R16
100kΩ
R7
4.75kΩ
R9
60.4kΩ
R14
1kΩ
EN1
C10
15nF
CLP1
C14
0.1µF
R17
100kΩ
R6
5.11kΩ
C11
120pF
EN2
R15
1kΩ
C15
0.1µF
C12
15nF
CLP2
RT/CLKIN
RT
24.9kΩ
REF
AGND
C13
120pF
C1
0.22µF
EXTERNAL FREQUENCY SYNC
Figure 6. Dual-Output Buck Regulator
______________________________________________________________________________________
15
MAX5066
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
VIN
IN
VDD
D1
(100mA, 30V)
1.3V/20A
REG
BST1
L1
0.8µH
C8
0.1µF
C3
0.1µF
BST2
Q4
IRF7821
DH1
C9
0.1µF
DH2
LX1
Q1
IRF7832
L2
0.8µH
LX2
Q3
IRF7832
DL1
D3
(1A, 30V)
D2
(100mA, 30V)
22Ω
Q2
IRF7821
MAX5066
C6
680µF
R3
1Ω
22Ω
C2
1µF
R1
2mΩ
C5
10µF
D4
(1A, 30V)
DL2
PGND
R4
5.11kΩ
CSP1
CSN1
CSP2
EAN1
CSN2
EAN2
EAOUT1
R5
4.75kΩ
EAOUT2
R8
60.4kΩ
MODE
VREG OR VREF
R16
100kΩ
R14
1kΩ
EN1
C10
15nF
CLP1
C14
0.1µF
R17
100kΩ
TO REG
C11
120pF
EN2
R15
1kΩ
C15
0.1µF
C12
15nF
CLP2
RT/CLKIN
RT
24.9kΩ
REF
AGND
C13
120pF
C1
0.22µF
EXTERNAL FREQUENCY SYNC
Figure 7. Dual-Phase, Single-Output Buck Regulator
16
______________________________________________________________________________________
R2
2mΩ
C4
4.7µF
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
inductor with a saturating current greater than the
worst-case peak inductor current:
Design Procedures
Inductor Selection
The switching frequency per phase, peak-to-peak ripple
current in each phase, and allowable voltage ripple at
the output, determine the inductance value. Selecting
higher switching frequencies reduces the inductance
requirement, but at the cost of lower efficiency due to
the charge/discharge cycle of the gate and drain
capacitances in the switching MOSFETs. The situation
worsens at higher input voltages, since capacitive
switching losses are proportional to the square of the
input voltage. Lower switching frequencies on the other
hand will increase the peak-to-peak inductor ripple current (∆IL) and therefore increase the MOSFET conduction losses (see the Power MOSFET Selection section for
a detailed description of MOSFET power loss).
When using higher inductor ripple current, the ripple
cancellation in the multiphase topology, reduces the
input and output capacitor RMS ripple current. Use the
following equation to determine the minimum inductance value:
L=
VOUT (VIN(MAX) − VOUT )
VIN × fSW × ∆IL
Choose ∆IL to be equal to about 30% of the output current per channel. Since ∆IL affects the output-ripple voltage, the inductance value may need minor adjustment
after choosing the output capacitors for full-rated efficiency. Choose inductors from the standard high-current, surface-mount inductor series available from various
manufacturers. Particular applications may require custom-made inductors. Use high-frequency core material
for custom inductors. High ∆IL causes large peak-to-peak
flux excursion increasing the core losses at higher
frequencies. The high-frequency operation coupled with
high ∆IL, reduces the required minimum inductance and
even makes the use of planar inductors possible. The
advantages of using planar magnetics include low-profile
design, excellent current sharing between phases due to
the tight control of parasitics, and low cost. For example,
the minimum inductance at VIN = 12V, VOUT = 0.8V, ∆IL
= 3A, and fSW = 500kHz is 0.5µH.
The average current-mode control feature of the
MAX5066 limits the maximum inductor current, which
prevents the inductor from saturating. Choose an
IL _ PEAK =
24.75 × 10 −3 ∆IL
+
RSENSE
2
where 24.75mV is the maximum average current-limit
threshold for the current-sense amplifier and RSENSE is
the sense resistor.
Power MOSFET Selection
When choosing the MOSFETs, consider the total gate
charge, R DS(ON) , power dissipation, the maximum
drain-to-source voltage, and package thermal impedance. The product of the MOSFET gate charge and onresistance is a figure of merit, with a lower number
signifying better performance. Choose MOSFETs optimized for high-frequency switching applications. The
average gate-drive current from the MAX5066’s output
is proportional to the total capacitance it drives at DH1,
DH2, DL1, and DL2. The power dissipated in the
MAX5066 is proportional to the input voltage and the
average drive current. See the Supply Voltage
Connection (V IN /V REG ) and the Low-Side MOSFET
Drives Supply (VDD) sections to determine the maximum total gate charge allowed from all driver outputs
together.
The losses may be broken into four categories: conduction loss, gate drive loss, switching loss and output loss.
The following simplified power loss equation is true for
both MOSFETs in the synchronous buck-converter:
PLOSS = PCONDUCTION + PGATEDRIVE + PSWITCH + POUTPUT
For the low-side MOSFET, the PSWITCH term becomes
virtually zero because the body diode of the MOSFET is
conducting before the MOSFET is turned on.
Tables 1 and 2 describe the different losses and shows
an approximation of the losses during that period.
Input Capacitance
The discontinuous input-current waveform of the buck
converter causes large ripple currents in the input
capacitor. The switching frequency, peak inductor current, and the allowable peak-to-peak voltage ripple
reflected back to the source, dictate the capacitance
requirement. Increasing the number of phases increases the effective switching frequency and lowers the
peak-to-average current ratio, yielding lower input
capacitance requirement. It can be shown that the
______________________________________________________________________________________
17
MAX5066
prevent shoot-through currents during transition. Figure 7
shows the dual-phase, single-output buck regulator.
MAX5066
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
Table 1. High-Side MOSFET Losses
LOSS
DESCRIPTION
Conduction Loss
Losses associated with MOSFET on-time and
on-resistance. IRMS is a function of load current
and duty cycle.
Gate Drive Loss
Losses associated with charging and
discharging the gate capacitance of the
MOSFET every cycle. Use the MOSFET’s (QG)
specification.
Switching Loss
Losses during the drain voltage and drain
current transitions for every switching cycle.
Losses occur only during the QGS2 and QGD
time period and not during the initial QGS1
period. The initial QGS1 period is the rise in the
gate voltage from zero to VTH.
RDH is the high-side MOSFET driver’s onresistance and RGATE is the internal gate
resistance of the high-side MOSFET (QGD and
QGS2 are found in the MOSFET data sheet).
Output Loss
Losses associated with QOSS of the MOSFET
occur every cycle when the high-side MOSFET
turns on. The losses are caused by both
MOSFETs but are dissipated in the high-side
MOSFET.
worst-case RMS current occurs when only one controller section is operating. The controller section with
the highest output power needs to be used in determining the maximum input RMS ripple current requirement.
Increasing the output current drawn from the other outof-phase controller section results in reducing the input
ripple current. A low-ESR input capacitor that can handle the maximum input RMS ripple current of one channel must be used. The maximum RMS capacitor ripple
current is given by:
ICIN(RMS) ≈ IMAX
VOUT (VIN − VOUT )
VIN
where I MAX is the full load current of the regulator.
VOUT is the output voltage of the same regulator and
CIN is C5 in Figure 6. The ESR of the input capacitors
wastes power from the input and heats up the capacitor. Reducing the ESR is important to maintain a high
overall efficiency and in reducing the heating of the
capacitors.
18
SEGMENT LOSS
PCONDUCTION = IRMS 2 × RDS(ON)
where IRMS ≈
VOUT
× ILOAD
VIN
PGATEDRIVE = VDD × QG × fSW
PSWITCH = VIN × ILOAD × fSW ×
where IGATE =
POUTPUT =
(QGS2 + QGD )
IGATE
VDD
2 × (RDH + RGATE )
QOSS(HS) + QOSS(LS)
× VIN × fSW
2
Output Capacitors
The worst-case peak-to-peak inductor ripple current,
the allowable peak-to-peak output ripple voltage, and
the maximum deviation of the output voltage during
step loads determine the capacitance and the ESR
requirements for the output capacitors. The output ripple can be approximated as the inductor current ripple
multiplied by the output capacitor’s ESR (RESR_OUT).
The peak-to-peak inductor current ripple is given by:
V
(1 − D)
∆IL = OUT
L × fSW
During a load step, the allowable deviation of the output voltage during the fast transient load dictates the
output capacitance and ESR. The output capacitors
supply the load step until the controller responds with a
greater duty cycle. The response time (tRESPONSE )
depends on the closed-loop bandwidth of the regulator. The resistive drop across the capacitor’s ESR and
capacitor discharge causes a voltage drop during a
______________________________________________________________________________________
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
MAX5066
Table 2. Low-Side MOSFET Losses
LOSS
DESCRIPTION
SEGMENT LOSSES
PCONDUCTION = IRMS 2 × RDS(ON)
Conduction Loss
Losses associated with MOSFET on-time, IRMS
is a function of load current and duty cycle.
Gate Drive Loss
Losses associated with charging and
discharging the gate of the MOSFET every
cycle. There is no QGD charging involved in this
MOSFET due to the zero-voltage turn-on. The
charge involved is (QG - QGD).
where IRMS ≈
VIN − VOUT
× ILOAD
VIN
PGATEDRIVE = VDD × (QG − QGD ) × fSW
Note: The gate drive losses are distributed between the drivers and the MOSFETs in the ratio of the gate driver’s resistance and the
MOSFET’s internal gate resistance.
load step. Use a combination of SP polymer and
ceramic capacitors for better transient load and ripple/noise performance.
Keep the maximum output-voltage deviation less than
or equal to the adaptive voltage-positioning window
(∆VOUT). During a load step, assume a 50% contribution each from the output capacitance discharge and
the voltage drop across the ESR (∆VOUT = ∆VESR_OUT
+ ∆VQ_OUT). Use the following equations to calculate
the required ESR and capacitance value:
RESR _ OUT =
COUT =
∆VESR _ OUT
ILOAD _ STEP
ILOAD _ STEP × tRESPONSE
∆VQ _ OUT
where I LOAD_STEP is the step in load current and
t RESPONSE is the response time of the controller.
Controller response time depends on the control-loop
bandwidth. COUT is C6 and C7 in Figure 6.
Current Limit
The average current-mode control technique of the
MAX5066 accurately limits the maximum average output current per phase. The MAX5066 senses the voltage across the sense resistor and limits the maximum
inductor current accordingly. Use the equations below
to calculate the current-sense resistor values:
ILOAD(MAX) =
24.75 × 10 −3
RSENSE
Due to tolerances involved, the minimum average voltage at which the voltage across the current-sense
resistor is clamped is 20.4mV. Therefore, the minimum
average current limit is set at:
ILIMIT(MIN) =
20.4 × 10 −3
RSENSE
For example, the current-sense resistor:
20.4mV
RSENSE =
= 2.04mΩ
10A
for a maximum output current of 10A. The standard
value is 2mΩ. Also, adjust the value of the currentsense resistor to compensate for parasitics associated
with the PC board. Select a noninductive resistor with
appropriate wattage rating.
The second type of current limit is the peak current limit
as explained in the Peak-Current Comparator section.
The third current-protection circuit is the hiccup fault
protection as explained in the Hiccup Fault Protection
section. The average current during a short at the output is given by:
IAVG(SHORT) =
1.41 × 10 −3
RSENSE
Reverse Current Limit
The MAX5066 limits the reverse current when the output
capacitor voltage is higher than the preset output voltage. Calculate the maximum reverse current limit based
on VCLAMP_LO and the current-sense resistor RSENSE.
______________________________________________________________________________________
19
MAX5066
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
1.63 × 10 −3
IREVERSE =
RSENSE
Output-Voltage Setting
The output voltage is set by the combination of resistors
R1, R2, and RF as described in the Voltage Error Amplifier
section. First select a value for resistor R2. Then calculate
the value of R1 from the following equation:
R1 =
(VOUT(NL) − 0.6135)
0.6135
× R2
where VOUT(NL) is the voltage at no load. Then find the
value of RF from the following equation:
I
× RSENSE × 36 × R1
RF = OUT
∆VOUT
where ∆VOUT is the allowable drop in voltage from no
load to full load. RF is R8 and R9, R1 is R4 and R6, R2
is R5 and R7 in Figure 6.
For stability of the current loop, the amplified inductorcurrent downslope at the negative input of the PWM
comparator (CPWM1 and CPWM2) must not exceed
the ramp slope at the comparator’s positive input. This
puts an upper limit on the current-error amplifier gain at
the switching frequency. The inductor current downslope is given by VOUT/L where L is the value of the
inductor (L1 and L2 in Figure 6) and VOUT is the output
voltage. The amplified inductor current downslope at
the negative input of the PWM comparator is given by:
∆VL VOUT
=
× RSENSE × 36 × gM × RCF
∆t
L
where RSENSE is the current-sense resistor (R1 and R2
in Figure 6) and gM x RCF is the gain of the current-error
amplifier (CEA_) at the switching frequency. The slope
of the ramp at the positive input of the PWM comparator
is 2V x fSW. Use the following equation to calculate the
maximum value of RCF (R14 or R15 in Figure 6).
RCF ≤
2 × fSW × L
VOUT × RSENSE × 36 × gM
(1)
Compensation
The MAX5066 uses an average current-mode control
scheme to regulate the output voltage (see Figure 2).
The main control loop consists of an inner current loop
and an outer voltage loop. The voltage error amplifier
(VEA1 and VEA2) provides the controlling voltage for
the current loop in each phase. The output inductor is
“hidden” inside the inner current loop. This simplifies
the design of the outer voltage control loop and also
improves the power-supply dynamics. The objective of
the inner current loop is to control the average inductor
current. The gain-bandwidth characteristic of the current loop can be tailored for optimum performance by
the compensation network at the output of the currenterror amplifier (CEA1 or CEA2). Compared with peak
current-mode control, the current-loop gain crossover
frequency, fC, can be made approximately the same,
but the gain at low frequencies is much higher. This
results in the following advantages over peak currentmode control.
1) The average current tracks the programmed current with a high degree of accuracy.
2) Slope compensation is not required, but there is a
limit to the loop gain at the switching frequency in
order to achieve stability.
3) Noise immunity is excellent.
4) The average current-mode method can be used to
sense and control the current in any circuit branch.
20
The highest crossover frequency fCMAX is given by:
f
× VIN
fCMAX = SW
2π × VOUT
or alternatively:
f
× 2π × VOUT
fSW = CMAX
VIN
Equation (1) can now be rewritten as:
RCF =
π × fC × L
VIN × RS × 9 × gM
(2)
In practical applications, pick the crossover frequency
(fC) in the range of:
fSW
f
< fC < SW .
10
2
First calculate RCF in equation 2 above. Calculate CCF
such that:
10
CCF =
2 × π × fC × RCF
where CCF is C10 and C12 in Figure 6.
______________________________________________________________________________________
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
CCFF =
1
2 × π × fC × 10 × RCF
where CCFF is C11 and C13 in Figure 6.
Applications Information
8) Distribute the power components evenly across the
top side for proper heat dissipation.
9) Keep AGND and PGND isolated and connect them
at one single point close to the IC. Do not connect
them together anywhere else.
10) Place all input bypass capacitors for each input as
close to each other as is practical.
Independant Turn-On and Off
The MAX5066 can be used to regulate two outputs
from one controller. Each of the two outputs can be
turned on and off independently of one another by controlling the enable input of each phase (EN1 and EN2).
A logic-low on each enable pin shuts down the
MOSFET drivers for that phase. When the voltage on
the enable pin exceeds 1.2V, the drivers are turned on
and the output can come up to regulation. This method
of turning on the outputs allows the MAX5066 to be
used for power sequencing.
Pin Configuration
TOP VIEW
CSN2 1
28 EN2
CSP2 2
27 BST2
EAOUT2 3
26 DH2
EAN2 4
25 LX2
CLP2 5
PC Board Layout Guidelines
REF 6
Careful PC board layout is critical to achieve low losses, low output noise, and clean and stable operation.
This is especially true for dual-phase converters where
one channel can affect the other. Use the following
guidelines for PC board layout:
1) Place the V DD , REG, and the BST1 and BST2
bypass capacitors close to the MAX5066.
2) Minimize all high-current switching loops.
RT/CLKIN 7
3) Keep the power traces and load connections short.
This practice is essential for high efficiency. Use
thick copper PC boards (2oz or higher) to enhance
efficiency and minimize trace inductance and
resistance.
4) Run the current-sense lines CSP_ and CSN_ very
close to each other to minimize loop areas. Do not
cross these critical signal lines through power circuitry. Sense the current right at the pads of the
current-sense resistors.
5) Place the bank of output capacitors close to the
load.
24 DL2
MAX5066
23 PGND
22 IN
AGND 8
21 REG
MODE 9
20 VDD
CLP1 10
19 DL1
EAN1 11
18 LX1
EAOUT1 12
17 DH1
CSP1 13
CSN1 14
16 BST1
*EXPOSED PADDLE
15 EN1
TSSOP
*CONNECT EXPOSED PAD TO GROUND PLANE.
Chip Information
TRANSISTOR COUNT: 6252
PROCESS: BiCMOS
6) Isolate the power components on the top side from
the analog components on the bottom side with a
ground plane in between.
7) Provide enough copper area around the switching
MOSFETs, inductors, and sense resistors to aid in
thermal dissipation and reducing resistance.
______________________________________________________________________________________
21
MAX5066
Calculate CCFF such that:
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
TSSOP 4.4mm BODY.EPS
MAX5066
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
XX XX
PACKAGE OUTLINE, TSSOP, 4.40 MM BODY,
EXPOSED PAD
21-0108
E
1
1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
22 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2005 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products, Inc.
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