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MAX5079
General Description
The MAX5079 ORing MOSFET controller replaces ORing
diodes in high-reliability redundant, parallel-connected
power supplies. Despite their low forward-voltage drop,
ORing Schottky diodes cause excessive power dissipation at high currents. The MAX5079 allows for the use of
low-on-resistance n-channel power MOSFETs to replace
the Schottky diodes. This results in low power dissipation,
smaller size, and elimination of heatsinks in high-power
applications.
The MAX5079 operates from 2.75V to 13.2V and includes
a charge pump to drive the high-side n-channel MOSFET.
Operation down to 1V is possible if an auxiliary voltage
of at least 2.75V is available. When the controller detects
a positive voltage difference between IN and BUS, the
n-channel MOSFET is turned on. The MOSFET is turned
off as soon as the MAX5079 sees a negative potential at
IN with respect to the BUS voltage, and is automatically
turned back on when the positive potential is restored.
Under fault conditions, the ORing MOSFET’s gate is
pulled down with a 1A current, providing an ultra-fast
200ns turn-off. The reverse voltage turn-off threshold is
externally adjustable to avoid unintentional turn-off of the
ORing MOSFET due to glitches at IN or BUS caused by
hot plugging the power supply.
ORing MOSFET Controller with
Ultra-Fast 200ns Turn-Off
Benefits and Features
●● Drives External MOSFETs Reducing Power
Dissipation and Board Space
• 2.75V to 13.2V Input ORing Voltage
• 1V to 13.2V Input ORing Voltage with 2.75V
AuxiliaryVoltage
• 14-Pin TSSOP Package
●● Protection Features Increase System Reliability
• 2A MOSFET Gate Pulldown Current During Fault
Condition
• Ultra-Fast 200ns, MOSFET Turn-Off During Fault
Condition
• Supply Undervoltage and Bus Overvoltage
Detection
• Power-Good (PGOOD) and Overvoltage (OVP)
Outputs for Fault Detection
Typical Operating Circuit
SUB 75N 03-04
VOUT1
POWER SUPPLY 1
(PS1)
●●
●●
●●
●●
●●
●●
Paralleled DC-DC Converter Modules
N+1 Redundant Power Systems
Servers
Base-Station Line Cards
RAID
Networking Line Cards
Ordering Information appears at end of data sheet.
19-3584; Rev 3; 5/18
VBUS
N1
BUS
COMMON
VIN
>2.75V
Additional features include an OVP flag to facilitate shutdown of a failed power supply due to an overvoltage
condition, and a PGOOD signal that indicates if VIN is
either below the undervoltage lockout or VBUS is in an
overvoltage condition. The MAX5079 operates over the
-40°C to +85°C temperature range and is available in a
space-saving 14-pin TSSOP package.
Applications
1V TO 13.2V
IN
GATE
AUXIN
U1
UVLO
MAX5079
BUS
PGOOD
OVI
OVP
STH
RSTH
CSTH
C+
C-
FTH
GND
RFTH
CEXT
SUB 75N 03-04
VOUT2
1V TO 13.2V
POWER SUPPLY 2
(PS2)
VBUS
N2
VIN
>2.75V
IN
GATE
AUXIN
U2
UVLO
MAX5079
CSTH
C+
CEXT
OVI
OVP
STH
RSTH
BUS
PGOOD
C-
FTH
GND
RFTH
CBUS
MAX5079
ORing MOSFET Controller with
Ultra-Fast 200ns Turn-Off
Absolute Maximum Ratings
GATE to GND..............................................-0.3V to (VIN + 8.5V)
All Other Pins to GND............................................-0.3V to +15V
Continuous Current Into Any Pin.......................................±50mA
Continuous Power Dissipation (TA = +70°C)
14-Pin TSSOP (derate 9.1mW/°C above +70°C)......727.3mW
Operating Temperature Range............................ -40°C to +85°C
Junction Temperature.......................................................+150°C
Storage Temperature Range............................. -65°C to +150°C
Lead Temperature (soldering, 10s).................................. +300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Information
PACKAGE TYPE: 14-PIN TSSOP
Package Code
U14+2
Outline Number
21-0066
Land Pattern
90-0113
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
Electrical Characteristics
((VIN = 2.75V to 13.2V and VAUXIN = 0V) or (VIN = 1V and VAUXIN = 2.75V to 13.2V), RSTH = open, RFTH = 0, VUVLO = 1V, VOVI = 0V,
TA = -40°C to +85°C, unless otherwise noted. Typical values are at VIN = 12V and TA = +25°C. See the Typical Operating Circuit.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER SUPPLIES
IN Input Voltage Range
AUXIN Input Voltage Range
(VAUXIN - VIN) High Threshold
(When GATE Connects Directly
to AUXIN) (Note 2)
(VAUXIN - VIN) Hysteresis
(When GATE Connects Directly
To AUXIN)
IN Supply Current
AUXIN Leakage Current
VIN
VAUXIN
VAUXIN_
THRESHOLD
IIN
ILEAK_AUX
IAUXIN
BUS Leakage Current
ILEAK_BUS
www.maximintegrated.com
VAUXIN rising, IGATE = 10µA
VAUXIN_
HYSTERESIS
AUXIN Supply Current
BUS Supply Current
VAUXIN ≥ 2.75V
IBUS
2.75
13.20
1.0
13.2
0
13.2
V
5.7
V
4.2
4.9
40
V
mV
VUVLO = 1V, VIN > VBUS
4
mA
VAUXIN = 0
20
µA
VUVLO = 1V, VAUXIN = VIN, = 3V;
VIN > VBUS
4
mA
VIN = 13.2V, VBUS = 0
1
mA
VBUS = 13.2V, VBUS > VIN,
VBUS > VAUXIN
3
mA
Maxim Integrated │ 2
MAX5079
ORing MOSFET Controller with
Ultra-Fast 200ns Turn-Off
Electrical Characteristics (continued)
((VIN = 2.75V to 13.2V and VAUXIN = 0V) or (VIN = 1V and VAUXIN = 2.75V to 13.2V), RSTH = open, RFTH = 0, VUVLO = 1V, VOVI = 0V,
TA = -40°C to +85°C, unless otherwise noted. Typical values are at VIN = 12V and TA = +25°C. See the Typical Operating Circuit.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
IN TO AUXIN SWITCHOVER
Switchover High Threshold
VAUXIN_HIGH
(VIN - VAUXIN), VAUXIN falling
-60
+25
+200
mV
Switchover Low Threshold
VAUXIN_LOW
(VIN - VAUXIN), VAUXIN rising
-200
-25
+50
mV
2.0
2.25
2.5
V
IN UNDERVOLTAGE LOCKOUT
Internal UVLO High Threshold
VINTUVLO_HIGH
VIN rising, VAUXIN = 0 or VAUXIN rising,
VIN = 1V, VBUS = 2.75V
Internal UVLO Hysteresis
VINTUVLO_HYST
VIN falling, VAUXIN = 0 or VAUXIN
falling, VIN = 1V
External UVLO Threshold
VUVLO
External UVLO Hysteresis
VUVLO_HYST
External UVLO Input Bias
IUVLO
VUVLO falling
30
0.568
0.6
mV
0.632
60
V
mV
500
nA
10
25
µs
12.5
20
mV
ORing MOSFET CONTROL
ORing MOSFET Turn-On Time
tON
ORing MOSFET Forward Voltage
Threshold (Fast Comparator)
VDTH
ORing MOSFET Reverse
Voltage Turn-Off Threshold (Fast
Comparator (VIN - VBUS))
VFTH
ORing MOSFET Reverse Voltage
Blanking Time (Fast Comparator)
tFBL
Slow-Comparator Output Voltage
Threshold on STH
VO_STH
ORing MOSFET Reverse
Voltage Turn-Off Threshold (Slow
Comparator (VIN - VBUS))
VSTH
(VIN - VBUS) to ISTH
Transconductance (Slow
Comparator)
ORing MOSFET Reverse Voltage
Blanking Time (Slow Comparator)
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GM_STH
CGATE = 10nF, CEXT = 100nF,
MOSFET gate threshold = 2V
(VIN - VBUS) rising, VAUXIN ≥ 2.75V
RFTH = 0
RFTH = 12kΩ
RFTH = 27kΩ, VIN ≥ 3.5V
-12
-24
-31
-63
-104
-150
-126
-204
-300
VBUS = 2.8V, RFTH = 0,
VBUS - VIN = 0.3V
50
0.95
1
1.05
RSTH open
-0.1
-12
-24.0
RSTH = 500kΩ
-25
RSTH = 64kΩ
-100
VSTH = 0V
0.17
CSTH = 0.047µF
CSTH = 0.22µF
0.5
0.9
5
mV
ns
VIN ≥ 2.75V
STH floating
tSBL
VAUXIN ≥
2.75V
5
V
mV
mS
1.5
ms
14
Maxim Integrated │ 3
MAX5079
ORing MOSFET Controller with
Ultra-Fast 200ns Turn-Off
Electrical Characteristics (continued)
((VIN = 2.75V to 13.2V and VAUXIN = 0V) or (VIN = 1V and VAUXIN = 2.75V to 13.2V), RSTH = open, RFTH = 0, VUVLO = 1V, VOVI = 0V,
TA = -40°C to +85°C, unless otherwise noted. Typical values are at VIN = 12V and TA = +25°C. See the Typical Operating Circuit.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
CEXT = 100nF, VIN ≥ 2.75V
0.7
2
VGATE = VIN, VIN = 5.1V, VBUS = 5V;
VOUT = 1V
0.9
2
MAX
UNITS
ORing MOSFET DRIVER
Gate-Charge Current
Gate Discharge Current (Note 3)
IGATE
IGATE.DIS_MIN
VGATE ≥ VIN, VIN = 2.75V, VBUS = 3.5V
1.3
VBUS = 3.5V, CGATE = 0.1µF
600
VBUS = 3.5V, CGATE = 0.01µF
200
tDIS_GATE
VBUS = 3.5V
70
RGATE_IN
(VGATE - VIN) = 100mV; VIN ≥ 2.75V
VGATE ≥ VIN, VIN = 12V, VBUS = 13.2V
Gate Fall Time
Gate Discharge Current Delay
Time (Time from VIN Falling from
3.7V to 3V to VGATE = VIN)
Gate to IN Resistance
Gate to IN Clamp Voltage
tFGATE
VGATE_IN_CLAMP IGATE = 10mA, VIN ≥ VBUS
Gate-Drive Voltage (Measured
with Respect to VIN)
(VGATE - VIN)
VIN Switchover Threshold to
Higher GATE Voltage (Note 4)
VIN_SOTH+
VIN Switchover Hysteresis
(Note 4)
VIN_SOHYS
Charge-Pump Frequency
fCP
PROTECTION
OVI Input Bias Current
OVI Threshold
OVP Output Low Voltage
OVP Leakage Current
PGOOD Leakage Current
PGOOD Output Low Voltage
IOVI
VOVI_TH
VOVP_LOW
IOVP_LEAK
IPG_LEAK
VPG_LOW
mA
6.8
A
3.2
8.5
ns
200
ns
900
Ω
11
V
V
2.7V < VIN < 13.2V
3.8
6.5
7
7.7
VIN = 2.75V
4.5
5
5.5
7.4
8
8.5
VIN = 13.2V
40
External
OVI rising
VOVI = 1V, ISINK = 10mA
ISINK = 2mA
kHz
1100
0.568
500
nA
0.6
0.632
V
0.2
0.4
V
1
µA
1
µA
0.4
V
VIN = 2.75V, VOVP = 13.2V
VPGOOD = 13.2V
mV
70
Internal, VIN < 5V, VAUXIN < 5V
V
0.2
Note 1: All devices are production tested at +25°C. Limits over temperature are guaranteed by design.
Note 2: Threshold is reached when charge pump turns off.
Note 3: Gate discharge current is guaranteed through the testing of gate fall time.
Note 4: VIN switchover threshold is VIN at which the gate-drive voltage (VGATE - VIN) goes from 5V to 7V, VIN rising and (VIN ≥ VBUS).
www.maximintegrated.com
Maxim Integrated │ 4
MAX5079
ORing MOSFET Controller with
Ultra-Fast 200ns Turn-Off
Typical Operating Characteristics
(TA = +25°C, unless otherwise noted. See the Typical Operating Circuit.)
2.0
1.5
1.0
0.5
0
-40 -25 -10 5 20 35 50 65 80 95 110 125
TA = +125°C
0.02
60
VFTH (V)
tSTH (ms)
70
50
40
30
20
10
78
76
fCP (kHz)
74
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
TA = +125°C
TA = +25°C
66
TA = -40°C
64
62
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
VIN (V)
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80
72
64
FAST-COMPARATOR RESPONSE TIME
VIN = 1V, VAUXIN = 5V
VIN = 5V, VAUXIN = 0V
48
40
VIN = 12V,
VAUXIN = 0V
32
16
VIN = 2.75V,
VAUXIN = 12V
8
0
6.0
5.5
20
40
60
80
100
120
0
140
-40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
FAULT CURRENT WAVEFORM
(IN SHORTED TO PGND)
VIN = 12V
5.0
MAX5079 toc09
MOSFET REVERSE
CURRENT
5A/div
4.5
4.0
BUS
5V/div
3.5
3.0
2.5
GATE
10V/div
2.0
1.5
1.0
0.5
0
1000
56
24
TA = -40°C
GATE-CHARGE CURRENT vs. CEXT
70
60
TA = +85°C
CHARGE-PUMP FREQUENCY
vs. INPUT VOLTAGE
72
68
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
FAST-COMPARATOR REVERSE VOLTAGE
THRESHOLD (VFTH vs. RFTH)
RFTH (kΩ)
TA = +125°C
TA = +85°C
100
10
RSTH (kΩ)
CSTH (µF)
GATE-CHARGE CURRENT (mA)
80
0
MAX5079 toc07
0
0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
MAX5079 toc05
80
0.08
0.06
tRESPONSE (ns)
SLOW-COMPARATOR BLANKING TIME
tSTH vs. CSTH (RSTH = 180kΩ)
75mV OVERDRIVE
0.10
VIN (V)
MAX5079 toc04
90
0.12
0.04
TEMPERATURE (°C)
100
VSTH (V)
TA = +85°C
MAX5079 toc06
VAUXIN = 2.7V
0.16
0.14
TA = -40°C
3.5
3.0
2.5
TA = -40°C, TA = +25°C,
TA = +85°C, TA = +125°C
0.18
TA = +25°C
4.0
1
0
MAX5079 toc02
4.5
2
0.20
MAX5079 toc08
VAUXIN = 5V
IGATE (mA)
IAUXIN (mA)
VAUXIN = 10V
6.0
5.5
5.0
MAX5079 toc01
3
SLOW-COMPARATOR REVERSE VOLTAGE
THRESHOLD (VSTH vs. RSTH)
GATE-CHARGE CURRENT vs. VIN
MAX5079 toc03
AUXIN SUPPLY CURRENT
vs. TEMPERATURE (VIN = VBUS = 1V)
IN
5V/div
1
10
CEXT (nF)
100
400ns/div
VIN = 5V, VBUS = 5V,
VAUXIN = 0V, CSTH = 0,
RSTH = OPEN, RFTH = 0,
UVLO = IN
Maxim Integrated │ 5
MAX5079
ORing MOSFET Controller with
Ultra-Fast 200ns Turn-Off
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted. See the Typical Operating Circuit.)
FAULT CURRENT WAVEFORM
(IN SHORTED TO PGND)
FAULT CURRENT WAVEFORM
(IN SHORTED TO PGND)
MAX5079 toc10
MAX5079 toc11
MOSFET REVERSE
CURRENT
10A/div
MOSFET REVERSE
CURRENT
10A/div
BUS
2V/div
BUS
10V/div
GATE
5V/div
GATE
20V/div
IN
2V/div
IN
10V/div
1µs/div
VIN = 2.75V, VBUS = 2.75V,
VAUXIN = 0V, CSTH = 0µF,
RSTH = OPEN, RFTH = 0,
UVLO = IN
400ns/div
VIN = 12V, VBUS = 12V,
VAUXIN = 0V, CSTH = 0µF,
RSTH = OPEN, RFTH = 0,
UVLO = IN
FAULT CURRENT WAVEFORM
(IN SHORTED TO PGND)
FAULT CURRENT WAVEFORM
(IN SHORTED TO PGND)
MAX5079 toc12
MAX5079 toc13
MOSFET REVERSE
CURRENT
10A/div
MOSFET REVERSE
CURRENT
10A/div
BUS
1V/div
BUS
5V/div
GATE
5V/div
GATE
10V/div
IN
1V/div
1µs/div
VIN = 1V, VBUS = 1V,
VAUXIN = 5V, CSTH = 0µF,
RSTH = OPEN, RFTH = 0,
UVLO = IN
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IN
5V/div
1µs/div
VIN = 5V, VBUS = 5V,
VAUXIN = 5V, CSTH = 0µF,
RSTH = OPEN, RFTH = 0,
UVLO = IN
Maxim Integrated │ 6
MAX5079
ORing MOSFET Controller with
Ultra-Fast 200ns Turn-Off
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted. See the Typical Operating Circuit.)
FAULT CURRENT WAVEFORM
(IN SHORTED TO PGND)
POWER-UP WAVEFORM
MAX5079 toc15
MAX5079 toc14
MOSFET REVERSE
CURRENT
10A/div
IN
2V/div
BUS
10V/div
BUS
2V/div
GATE
20V/div
GATE
10V/div
IN
10V/div
CXN
10V/div
40µs/div
VIN = 5.2V, VBUS = 4.9V,
IBUS = 5A
1µs/div
VIN = 12V, VBUS = 12V,
VAUXIN = 5V, CSTH = 0,
RSTH = OPEN, RFTH = 0,
UVLO = IN
POWER-UP WAVEFORM
POWER-UP WAVEFORM
MAX5079 toc16
MAX5079 toc17
IN
5V/div
IN
1V/div
BUS
5V/div
BUS
500mV/div
GATE
10V/div
GATE
5V/div
CXN
10V/div
CXN
10V/div
20µs/div
VIN = 12.2V, VBUS = 11.9V,
IBUS = 5A
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20µs/div
VIN = 1.2V, VBUS = 1V,
VAUXIN = 5V, IBUS = 5A
Maxim Integrated │ 7
MAX5079
ORing MOSFET Controller with
Ultra-Fast 200ns Turn-Off
Pin Configuration
TOP VIEW
CXN 1
14 AUXIN
CXP
2
13 IN
OVP
3
PGOOD 4
MAX5079
12 GND
11 BUS
STH 5
10 GATE
FTH 6
9
PGND
OVI 7
8
UVLO
TSSOP
Pin Description
PIN
NAME
1
CXN
Negative Terminal of External Flying Charge-Pump Capacitor
FUNCTION
2
CXP
Positive Terminal of External Flying Charge-Pump Capacitor
3
OVP
Open-Drain Active-Low Output. OVP sinks up to 10mA when VOVI ≥ 0.6V and VIN ≥ VBUS. OVP can be
used to drive an optodiode. Cycle power or pull UVLO low and then high to reset OVP.
4
PGOOD
5
STH
ORing MOSFET Slow-Comparator Reverse Voltage Threshold and Blanking Time Setting Input. Connect
a resistor from STH to GND to set the threshold. Connect a capacitor from STH to GND to set the blanking
time. Leave STH floating to set the internal threshold (-12mV) and internal blanking time (0.9ms).
6
FTH
Fast-Comparator Reverse Threshold Setting. Connect a resistor from FTH to GND to set the fastcomparator reverse voltage threshold from -24mV to -400mV.
7
OVI
Overvoltage Comparator Input. Connect OVI to BUS through a resistive divider.
8
UVLO
Undervoltage Lockout Comparator Input. Connect UVLO to IN through a resistive divider. The MAX5079
remains off until VUVLO rises above 0.66V. When VUVLO rises above 0.664V, VGATE is raised to VIN.
Open-Drain Active-Low Output. PGOOD pulls low when VUVLO ≤ 0.6V or VOVI ≥ 0.6V.
9
PGND
Power Ground. Ground discharge path of the 2A GATE pulldown. Connect to external power ground plane.
10
GATE
Gate-Driver Output for n-Channel ORing MOSFET
11
BUS
Bus Voltage-Sense Input. Connect BUS to the drain of the ORing MOSFET to sense the polarity of the Bus
Current. The MAX5079 receives its power from BUS when VIN and VAUXIN are not present.
12
GND
Signal Ground. Connect to the low-level signal or analog ground.
13
IN
14
AUXIN
Source Connection for ORing MOSFET and Supply Input for the MAX5079. Connect IN directly to the
power-supply voltage of 2.75V to 13.2V or 1V to 13.2V with VAUXIN ≥ 2.75V.
Auxiliary Power-Supply Input. AUXIN supplies power to the IC when 1V ≤ VIN ≤ 2.75V. Connect AUXIN to
2.75V or higher if VIN is less than 2.75V.
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Maxim Integrated │ 8
MAX5079
ORing MOSFET Controller with
Ultra-Fast 200ns Turn-Off
Block Diagram
CXP
CXN
GATE
IN
BUS
VSUPPLY
AUXIN TO GATE
DIRECT CONNECTION
VSUPPLY
GM
BUS
IN/AUXIN/BUS
SWITCHOVER
AUXIN
IN
STH
VSUPPLY
VSUPPLY
CPOFF
0.6V
REFERENCE
INTERNAL
UVLO
GND
VSUPPLY
UVLO PGOOD
OVI
PULLDOWN
REG
DRIVER
2A
PULLDOWN
N
MAX5079
PGOOD
LOGIC
OV
LOGIC
OVP
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FTH
TOP LOGIC
GATE TARGET SELECTOR
COMPARATOR
OVI
0.9ms
DELAY
VSUPPLY
IN/AUXIN SUPPLY
SWITCHOVER
UVLO
20µA
CHARGE
PUMP
IN/AUXIN CHARGE-PUMP
SWITCHOVER
HYSTERESIS
CONTROL
PGOOD
PGND
Maxim Integrated │ 9
MAX5079
Detailed Description
The MAX5079 ORing MOSFET controller drives an
external n-channel MOSFET and replaces ORing diodes
in high-reliability redundant power-management systems
or multiple paralleled power supplies. The device has an
internal charge pump to drive the high-side n-channel
ORing MOSFET. Additional features include an adjustable undervoltage lockout threshold (UVLO), output
overvoltage detector (OVI/OVP), input power-good detector (PGOOD), and two programmable reverse voltage
detectors to detect both fast and slow rises in the reverse
voltage across the ORing MOSFET. The input powersupply range is from 2.75V to 13.2V or down to 1V when
an auxiliary supply of at least 2.75V is available.
Operational Description
This section describes a detailed startup sequence and
behavior of the MAX5079 under different conditions of
VBUS and VIN. The MAX5079 powers up whenever VIN
is equal to or greater than 2.75V and VUVLO exceeds the
UVLO threshold of 0.66V. Operation with VIN down to 1V
is possible as long as VUVLO ≥ 0.6V and VAUXIN ≥ 2.75V.
When VUVLO crosses the UVLO threshold, VGATE rises
to VIN and the charge pump turns on. The charge pump
delivers 2mA to charge the gate capacitance of the external
MOSFET connected to GATE. The constant gate-charge
current prevents large inrush currents from the input supply. During turn-on, the MAX5079 will ignore the reverse
voltage at IN with respect to BUS. This is necessary to
avoid the unintentional turn-off of the ORing MOSFET as
the momentary inrush current causes VIN to dip.
The Figure 1 shows the MAX5079 in an ORing configuration with three parallel power supplies (PS1, PS2, and
PS3) and three MAX5079s (U1, U2, and U3) provided by
outputs VOUT1, VOUT2, and VOUT3. The following events
must be carefully considered to ensure proper functionality of the MAX5079 ICs.
1) VBUS is zero with a discharged capacitor (CBUS).
All three power supplies are turned ON simultaneously. VOUT1 comes up before VOUT2 and VOUT3.
a. When VOUT1 turns on, the bus capacitors (CBUS)
begin charging from VOUT1 through N1’s body
diode. When VUVLO (U1) rises above the UVLO
threshold, the MAX5079 (U1) charge pump turns
on, and U1 monitors the positive potential from
VOUT1 to VBUS. When VOUT1 ≥ VBUS the charge
pump brings GATE (U1) to 5.5V above VIN (U1)
(or 7.5V above VIN depending on the magnitude of
VIN), by sourcing 2mA into N1’s gate capacitance.
This results in a less than 10μs turn-on time for
www.maximintegrated.com
ORing MOSFET Controller with
Ultra-Fast 200ns Turn-Off
the FDB7045L used in the MAX5079 evaluation
kit. The fast turn-on is needed to assure that N1
is ON before the rising VOUT1 reaches its steadystate value. If the MOSFET is not turned on before
VOUT1 reaches its steady state, VBUS may overshoot due to the shorting of the 0.7V (forward drop)
of N1’s body diode. A higher VIN (U1) can more
quickly charge the charge-pump capacitor to 5V
(or 7V), while a lower VIN (U1) will take longer. Typically the MOSFET turns on at VGS = 2.5V. Ensure
that the soft-start time of the power supply is large
enough (> 5ms) to avoid VOUT1 racing ahead and
causing VBUS to overshoot. Care must be taken to
avoid the overloading of VOUT1 by either limiting
the source current (using the current-sharing circuit) or delay the loading of the BUS until all three
power supplies are up and running.
b. VOUT2 turns on and begins increasing the voltage
at IN (U2). VUVLO (U2) crosses the UVLO threshold, the MAX5079 (U2) charge pump turns on and
U2 monitors the VOUT2 to VBUS voltage. When
this voltage difference becomes positive, GATE
(U2) begins sourcing 2mA into N2’s gate capacitance. During turn-on, the reverse voltage turn-off
circuit is momentarily disabled. If VOUT2 is lower
than VOUT1, the external load-sharing controller
circuit of PS2 will try to increase VOUT2 to source
current from VOUT2. Assume VOUT2’s rise time is
slow enough not to cause any overshoot before N2
turns on and starts sharing the current.
c. VOUT3 turns on and U3 follows the same sequence
as U2. Eventually VOUT1, VOUT2, and VOUT3
reach to equilibrium and sharing equal currents.
2) PS1 and PS2 are on and sharing the load when
PS3 is hot-inserted. PS3 will take the same
course as discussed in 1b above.
a. If VOUT3 is higher than VBUS, the BUS voltage will
increase to the new level determined by VOUT3.
The external load-sharing controller circuit of PS1
and PS2 will increase VOUT1 and VOUT2 to force
current sharing.
b. If VOUT3 is lower than VBUS, the load-sharing circuit of PS3 will increase VOUT3 to force the sharing
of current. This causes VOUT3 to increases above
VBUS. When this voltage difference becomes positive, GATE (U3) begins sourcing 2mA into N3’s
gate capacitance. Again, the reverse voltage turnoff circuit is disabled momentarily, as discussed
before. The load-sharing circuit of PS3’s controller
will adjust VOUT3 so as to share the load current.
Maxim Integrated │ 10
MAX5079
c. During the hot insertion, a voltage spike can occur at N1 and N2 and cause the (VOUT1 to VBUS)
or (VOUT2 to VBUS) voltage to go negative. If
the reverse voltage is below the fast-comparator
reverse voltage threshold (VFTH) but above the
programmed slow-comparator reverse voltage
threshold (VSTH), the spike is ignored for the programmed blanking time (tSTH). If the spike is longer than 50ns (the fast-comparator internal blanking time, tFBL) and larger than VFTH, then U1 and
U2 will turn off N1 and N2 quickly. If the magnitude
of the voltage spike is above VSTH but less than
VFTH, and longer than the slow-comparator blanking time (tSTH), U1 and U2 will turn off their respective ORing MOSFETs (N1 and N2) by discharging
their GATE pins to PGND. The external load-sharing circuit of PS1 and PS2 will force VOUT1, VOUT2
above VBUS and N1, N2 will turn back on through
the 2mA current sourcing from the GATE pins of
U1 and U2. To avoid this situation the user can set
the slow-comparator threshold and blanking time
depending on the magnitude and duration of the
voltage spikes.
d. PS3 fails to start. VUVLO (U3) threshold is not
crossed and U3 keeps N3 off.
e. PS3 goes into an overvoltage condition (no feedback). This causes VBUS to go into an overvoltage
condition increasing the loading on PS3 (provided
PS3 is able to supply all the required BUS current).
The current-sharing circuit will force the outputs of
PS1 and PS2 to increase and eventually saturate
at their current-sharing voltage range. Eventually
only PS3 will have a positive voltage at IN (U3) with
respect to BUS. PS1 and PS2 will have a negative
voltage at VOUT1 and VOUT2 with respect to BUS.
All overvoltage inputs OVI (U1), OVI (U2), and OVI
(U3) sense the overvoltage, but only OVP (U3) is
asserted and latched low. GATE (U3) is pulled to
PGND and remains low as long as VOVI ≥ 0.6V.
When VOVI drops below 0.6V, OVP remains low.
However, U3 tries to turn on N3 unless VOUT3 is
actively kept below the undervoltage lockout. Use
OVP (U3) to either drive the cathode of the optocoupler to shutdown PS3 from the primary side or
use OVP (U3) to fire an SCR connected between
VOUT3 and PGND.
3) PS1, PS2, PS3 are turned on with a shorted BUS.
Body diodes of N1, N2, and N3 conduct and short the outputs of PS1, PS2, and PS3 to PGND. The power supplies
go into current limit (either in foldback or in hiccup mode).
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ORing MOSFET Controller with
Ultra-Fast 200ns Turn-Off
The MAX5079s remain in undervoltage lockout and keep
all ORing MOSFETs off. The average current sourced by
PS1, PS2, or PS3 must be low enough so as not to exceed
the MOSFETs power dissipation (PD = VF x ISHORT).
a. Use additional n-channel MOSFETs in series with
N1, N2, and N3 in the reverse direction to isolate
the power supplies from a shorted bus (Figure 2).
When power is turned on with a shorted bus, VIN_
(U1, U2, U3) increases and VUVLO rises above the
UVLO threshold. The MAX5079’s GATE outputs
start charging the back-to-back ORing MOSFET
gates. The short-circuit condition at BUS collapses VIN (U1), VIN (U2), and VIN (U3) sending the
MAX5079s into undervoltage lockout. This turns
off the MAX5079s entirely, including discharging of
the charge-pump storage capacitors. The IN voltages come back up again crossing UVLO (UVLO
has 60mV hysteresis). A new cycle starts and the
time required to charge the chargepump capacitor and the turn-on time of the device serves as
a dead time. However, the dead time may not be
enough to reduce the dissipation in the MOSFETs
to an acceptable level. We advise in keeping the
short-circuit current low and providing hiccup current-limit protection to the power supplies (PS1,
PS2, and PS3).
b. Any other overload condition that would sustain the
IN voltage above UVLO, will keep the MOSFETs
ON continuously. Ensure the MOSFETs’ current
rating is higher than the maximum short-circuit
source current of the power supplies (PS1, PS2,
and PS3) to avoid damage to the ORing MOSFETs.
4) PS1, PS2, and PS3 are present and PS1 is
shorted to GND.
VOUT1 drops below VBUS. The negative potential from
VIN (U1) to VBUS increases above the fast-comparator
threshold and lasts longer than the 50ns blanking time.
The MAX5079 (U1) takes its power from the voltage at
BUS (U1). Connect BUS close to CBUS, away from N1
so that U1 can receive power from BUS for a few microseconds until N1 isolates BUS from IN. N1 is discharged
with 2A pulldown current, turning off N1 and isolating PS1
from the BUS. The load-sharing circuit of PS2 and PS3
will increase PS2 and PS3’s load current until the total
bus current requirement is satisfied.
For VIN (U1) < 2.75V, VAUXIN (U1) must come from an
independent source or remain on for some time (a few
microseconds) after VIN (U1) has failed. This minimum
on-time is needed to discharge the gate of the ORing
MOSFET and isolate PS1 from the BUS.
Maxim Integrated │ 11
MAX5079
5) PS1, PS2, PS3 are present and PS1 goes open.
PS1’s output capacitors discharge and VOUT1 drops
below VBUS. The MAX5079 (U1) senses a negative
potential from VOUT1 to VBUS. Depending upon how fast
PS1’s output capacitor discharges, N1 is turned off due
to the crossing of the fast- or slow-comparator reverse
voltage threshold. N1’s gate is discharged with a 2A sink
current into GATE (U1), turning off N1 and isolating PS1
from the BUS. The load-sharing circuit of PS2 and PS3
will increase PS2 and PS3’s load current until the total
BUS current requirement is satisfied.
6) PS1, PS2, PS3 are present and providing BUS
current. PS1 loses its feedback signal and goes
into an overvoltage condition.
VBUS increases and PS1 is loaded heavily. The current
share circuit forces VOUT2 and VOUT3 higher and they
will eventually saturate at their current-sharing voltage
range. Now only PS1 has a positive voltage at IN (U1)
with respect to BUS. All OVI inputs will sense the overvoltage, but only OVP (U1) will be asserted and latched low.
GATE (U1) is pulled to PGND and remains low as long as
VOVI ≥ 0.6V. When VOVI drops below 0.6V, OVP remains
low, however, U1 tries to turn on N1 unless VOUT1 is
actively kept below the undervoltage lockout. Use OVP
(U1) to either drive the cathode of an optocoupler to shutdown PS1 from the primary, or fire an SCR connected
between IN (U1) and PGND.
Internal and External
Undervoltage Lockout
The internal undervoltage lockout monitors VIN and
VAUXIN and keeps the MAX5079 off until either voltage
reaches 2.75V. Once powered and VIN and/or VAUXIN
increase above 2.75V, the external UVLO is monitored.
The external undervoltage lockout feature monitors the
UVLO input and keeps the MAX5079 off (GATE shorted
to PGND) until VUVLO is greater than 0.66V. Connect a
resistive divider from IN to UVLO to GND or from AUXIN
to UVLO to GND to set the external undervoltage lockout
threshold. We advise setting the external UVLO ≥ 2.75V
when AUXIN is not present.
Charge Pump
The MAX5079 has an internal charge pump that pumps
the gate-drive voltage (VGATE) high enough to fully
enhance the n-channel ORing MOSFET. The charge
pump is divided into two stages, a voltage doubler running at 70kHz using an external charge-pump capacitor
www.maximintegrated.com
ORing MOSFET Controller with
Ultra-Fast 200ns Turn-Off
(CEXT), and a voltage tripler running at 1MHz using an
internal capacitor.
Connect an external capacitor (CEXT) between C+ and
C-. CEXT is charged from the higher of VIN or VAUXIN.
When the rising VIN becomes greater then VBUS (VUVLO
> 0.66V), CEXT is discharged through GATE into the
external MOSFET’s gate capacitance. The charge-pump
output is controlled by an internal regulator. The chargepump output at GATE sources typically 2mA. This provides enough current drive to turn on a typical ORing
MOSFET in less than 10μs. When (VGATE - VIN) reaches
the target value (depending on VIN) the charge pump
is switched off (see the Electrical Characteristics table).
Choose CEXT equal to 10 times the ORing MOSFET gate
capacitance. Too low of a capacitance will delay the turnon of the ORing MOSFET, while too high of a capacitance
can cause excessive ripple at VIN. Bypass IN to GND with
a 1μF ceramic capacitor to avoid ripple at IN caused by
the charge-pump switching. A clamp is placed internally
between GATE and IN to prevent (VGATE - VIN) from
exceeding 11V. When VIN is less than 5V, the charge
pump (tripler) will increase VGATE to 3x’s VIN to further
reduce the RDSON of the ORing MOSFET. The internal
charge-pump booster (voltage tripler) section is operational only when VIN and VAUXIN are low and is turned off
when VIN exceeds 5V.
When an additional supply is connected to AUXIN and
(VAUXIN - VIN) > 5V, both charge pumps are completely
disabled. In this case, the charging of the ORing gate
comes entirely from VAUXIN. In this case, the chargepump flying capacitor can be eliminated and C+, Ccan be
left floating.
GATE Drive and Gate Pulldown
The MAX5079’s charge pump provides bias to charge the
ORing MOSFET gate above IN (the MOSFET’s source).
GATE source current and the turn-on speed depends
upon the value of CEXT (connected between C+ and C-).
Typically GATE can source up to 2mA with CEXT = 0.1μF.
This enables VGATE to rise to over 2V above VIN in less
than 10μs for an ORing MOSFET gate capacitance of up
to 10nF. With VIN < 5V, 12V MOSFETs can be used for
better RDSON characteristics. The MAX5079 automatically selects the gate-drive voltage for VIN = 5V or VIN =
12V. For VIN ≤ 8V, the gate drive is 5V above VIN and for
VIN > 8V, the gate drive is 7V above VIN. Lower gate drive
means faster turn-off during faults, while higher gatedrive
means lower RDSON.
Maxim Integrated │ 12
MAX5079
ORing MOSFET Controller with
Ultra-Fast 200ns Turn-Off
A fast and slow comparator monitor the voltage from IN
to BUS. When this voltage crosses the negative fast- or
slow-comparator threshold voltage for the blanking time
duration, GATE is pulled low by an internal 2A current
sink. Both comparators have an adjustable threshold voltage. GATE is pulled low if any of the following conditions
are met.
1) VUVLO < 0.6V.
2) VAUXIN < 2.25V and VIN < 2.25V.
3) VOVI ≥ 0.6V.
4) VIN ≤ (VBUS - VFTH) or VIN ≤ (VBUS - VSTH) and
(VGATE - VIN) ≥ 1.8V.
When the above conditions are not true and VIN ≤
VBUS, GATE is shorted to IN. To insure that the external
MOSFET is quickly turned off, given the above conditions, the GATE pulldown circuitry is powered by either
VIN, VAUXIN, or VBUS as long as any one is greater then
2.75V.
Fast Comparator (FTH)
The fast comparator has a 50ns blanking time to avoid
unintentional turn-off of the ORing MOSFET during fast
transients. Additionally, the fast-comparator reverse voltage threshold (VFTH) is programmable to suit the need of
an individual application. Higher VFTH threshold allows
for a larger glitch at BUS during a fault, but improves the
noise immunity. Lower VFTH reduces glitches at BUS
during a fault, however, with lower VFTH spikes at BUS or
glitches at IN can be read as faults, unintentionally turning off the ORing MOSFET. Program VFTH by connecting
a resistor from FTH to GND. Adjust VFTH to optimize the
system performance using the following equation:
R FTH =
VFTH − 24mV
6.67µA
VFTH can be chosen from 24mV to 400mV. Connect FTH
to GND to choose the default 24mV threshold.
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Slow Comparator (STH)
The MAX5079 includes a slow comparator to provide
glitch immunity during the hot insertion or removal of
paralleled power supplies. During the hot insertion, BUS
can see voltage spikes. These spikes can be interpreted
as a reverse voltage across the ORing MOSFET. The
amplitude of the spikes is proportional to the load step
seen by the parallel power supply while the duration of the
spikes depends on the loop response of the load share
and PWM controller.
The slow comparator has a programmable reverse voltage threshold (VSTH) as well as a programmable blanking time (tSTH). An internal transconductance amplifier
converts the IN to BUS differential voltage to a current
and applies it to a parallel combination of resistor and
capacitor (RSTH and CSTH) from STH to GND. The
reverse threshold voltage (VSTH) for the slow comparator
is adjusted through RSTH. Use the following equation to
calculate the RSTH for a required VSTH.
R STH =
1V
V
12mV
−
( STH
) x G M_STH
where GM_STH = 0.17mS.
The internal 500kΩ resistance from the output of the
transconductance to GND can change the actual VSTH
if RSTH is above 50kΩ. In this case, see the Typical
Operating Circuit to select RSTH. Once RSTH is chosen,
the blanking time can be adjusted by CSTH. The delay
time is:
VSTH
= R STH × C STH × −ln 1 −
t STH
+ t SBL
VSTH + VOD
where tSBL = 0.9ms and is the default blanking time generated by an internal digital delay. Leaving STH floating
results in a 12mV threshold voltage and a 0.9ms blanking
time. VOD (overdrive) is the difference between actual
reverse voltage (VBUS - VIN) and VSTH threshold.
Maxim Integrated │ 13
MAX5079
Overvoltage Protection Latch (OVI/OVP)
OVI is the negative input to the overvoltage comparator. The positive input of this comparator is connected to
the internal 0.6V reference and an open-drain output is
provided at OVP. The overvoltage sensing for overvoltage protection is done at either IN or BUS. OVP latches
low and the internal GATE pulldown circuitry is activated
and pulls GATE low only when both of the conditions are
satisfied:
1) VOVI ≥ 0.6V.
2) VIN ≥ VBUS.
OVP can sink 10mA maximum. Cycle power or pull UVLO
low and then high again to reset the OVP latch. GATE is
pulled to PGND and remains low as long as VOVI ≥ 0.6V.
When VOVI drops below 0.6V, OVP remains low. However,
the MAX5079 tries to turn on the ORing MOSFET unless
VIN is actively kept below the undervoltage lockout. Use
OVP to drive the cathode of an optocoupler to shut down
the respective power supply from the primary side (see
Figure 1) or fire an SCR connected from IN to PGND.
ORing MOSFET Controller with
Ultra-Fast 200ns Turn-Off
1) Place a 1μF ceramic input bypass capacitor physically close to IN and PGND. Connect IN as close as
possible to the source of the ORing MOSFET.
2) Sense the VBUS close to the bulk capacitor, away
from the drain of the ORing MOSFET. When IN is
shorted to ground during a fault, BUS is also pulled
low through the ORing MOSFET. In the absence of
VAUXIN, the MAX5079 loses both power inputs VIN
and VBUS. This can cause a delayed pulldown of the
gate. Sensing the BUS away from the ORing MOSFET drain, close to the BUS bulk capacitor provides
power to the MAX5079 for a few microseconds, long
enough to pull down the ORing MOSFET gate and
isolate BUS from a shorted IN.
3) Place the charge-pump capacitor (CEXT) and the
slow-comparator blanking time adjustment capacitor
(CSTH) as close as possible to the MAX5079.
4) Run a thick trace from the gate of the ORing MOSFET to GATE.
Power-Good Comparator (PGOOD)
PGOOD output pulls low when VUVLO falls below 0.6V
or VOVI goes above 0.6V. PGOOD can sink a maximum
of 2mA.
Layout Guidelines
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Maxim Integrated │ 14
MAX5079
ORing MOSFET Controller with
Ultra-Fast 200ns Turn-Off
Typical Application Circuit
VOUT1
POWER SUPPLY 1
(PS1)
N1
1V TO 13.2V
VIN
>2.75V
RSTH
IN
GATE
AUXIN
U1
UVLO
OVP
STH
MAX5079
C+
OVI
PGOOD
CSTH
GND
RFTH
N2
1V TO 13.2V
VBUS
VBUS
VIN
TO PRIMARY-SIDE
SHUTDOWN
>2.75V
RSTH
IN
GATE
AUXIN
U2
UVLO
OVP
STH
MAX5079
C+
BUS
CBUS
OVI
PGOOD
C- FTH
CSTH
GND
RFTH
CEXT
VOUT3
POWER SUPPLY 3
(PS3)
BUS
C- FTH
CEXT
POWER SUPPLY 2
(PS2)
BUS
COMMON
VBUS
TO PRIMARY-SIDE
SHUTDOWN
VOUT2
VBUS
N3
1V TO 13.2V
VBUS
VBUS
VIN
TO PRIMARY-SIDE
SHUTDOWN
>2.75V
RSTH
IN
GATE
AUXIN
U3
UVLO
OVP
STH
MAX5079
C+
C- FTH
BUS
OVI
PGOOD
GND
CSTH
CEXT
RFTH
Figure 1. Typical Application Circuit
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Maxim Integrated │ 15
MAX5079
ORing MOSFET Controller with
Ultra-Fast 200ns Turn-Off
Typical Application Circuit (continued)
VOUT1
POWER SUPPLY 1
(PS1)
1V TO 13.2V
VBUS
VBUS
VIN
TO PRIMARY-SIDE
SHUTDOWN
>2.75V
RSTH
IN
GATE
AUXIN
U1
UVLO
OVP
STH
MAX5079
C+
C- FTH
CSTH
POWER SUPPLY 2
(PS2)
BUS
OVI
PGOOD
GND
RFTH
CEXT
VOUT2
BUS
COMMON
1V TO 13.2V
VBUS
VBUS
TO PRIMARY-SIDE
SHUTDOWN
VIN
>2.75V
RSTH
IN
GATE
AUXIN
U2
UVLO
OVP
STH
MAX5079
C+
C- FTH
CSTH
CEXT
BUS
CBUS
OVI
PGOOD
GND
RFTH
Figure 2. Parallel Supplies with Back-to-Back MOSFET
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Maxim Integrated │ 16
MAX5079
ORing MOSFET Controller with
Ultra-Fast 200ns Turn-Off
Chip Information
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
MAX5079EUD
-40°C to +85°C
14 TSSOP
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TRANSISTOR COUNT: 2,911
PROCESS: BiCMOS
Maxim Integrated │ 17
MAX5079
ORing MOSFET Controller with
Ultra-Fast 200ns Turn-Off
Revision History
REVISION
NUMBER
REVISION
DATE
0
2/05
Initial release
1
3/09
Updated Electrical Characteristics table
2, 3
2
4/15
Revised Benefits and Features section
1
Corrected blanking time equation in the Slow Comparator (STH) section;
updated tDELAY to tSTH and VDD to VOD
13
Updated Package Information table
2
2.5
3
5/18
PAGES
CHANGED
DESCRIPTION
—
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
© 2018 Maxim Integrated Products, Inc. │ 18