EVALUATION KIT AVAILABLE
MAX5134–MAX5137
Pin-/Software-Compatible,
16-/12-Bit, Voltage-Output DACs
General Description
The MAX5134–MAX5137 is a family of pin-compatible
and software-compatible 16-bit and 12-bit DACs. The
MAX5134/MAX5135 are low-power, quad 16-/12-bit,
buffered voltage-output, high-linearity DACs. The
MAX5136/MAX5137 are low-power, dual 16-/12-bit,
buffered voltage-output, high-linearity DACs. They use
a precision internal reference or a precision external reference for rail-to-rail operation. The MAX5134–MAX5137
accept a wide +2.7V to +5.25V supply-voltage range to
accommodate most low-power and low-voltage applications. These devices accept a 3-wire SPI-/QSPI TM-/
MICROWIRE®-/DSP-compatible serial interface to save
board space and reduce the complexity of optically isolated and transformer-isolated applications. The digital
interface’s double-buffered hardware and software
LDAC provide simultaneous output updates. The serial
interface features a READY output for easy daisy-chaining of several MAX5134–MAX5137 devices and/or other
compatible devices. The MAX5134–MAX5137 include a
hardware input to reset the DAC outputs to zero or midscale upon power-up or reset, providing additional safety
for applications that drive valves or other transducers
that need to be off during power-up. The high linearity of
the DACs makes these devices ideal for precision control and instrumentation applications. The MAX5134–
MAX5137 are available in an ultra-small (4mm x 4mm),
24-pin TQFN package or a 16-pin TSSOP package. Both
packages are specified over the -40°C to +105°C
extended industrial temperature range.
Features
o 16-/12-Bit Resolution Available in a 4mm x 4mm,
24-Pin TQFN Package or 16-Pin TSSOP
o Hardware-Selectable to Zero/Midscale DAC
Output on Power-Up or Reset
o Double-Buffered Input Registers
o LDAC Asynchronously Updates DAC Outputs
Simultaneously
o READY Facilitates Daisy Chaining
o High-Performance 10ppm/°C Internal Reference
o Guaranteed Monotonic Over All Operating
Conditions
o Wide +2.7V to +5.25V Supply Range
o Rail-to-Rail Buffered Output Operation
o Low Gain Error (Less Than ±0.5%FS) and Offset
(Less Than ±10mV)
o 30MHz 3-Wire SPI-/QSPI-/MICROWIRE-/
DSP-Compatible Serial Interface
o CMOS-Compatible Inputs with Hysteresis
o Low-Power Consumption (ISHDN = 2µA max)
Ordering Information
PART
PINPACKAGE
RESOLUTION
(BITS)
INL
(LSB)
MAX5134AGTG+
24 TQFN-EP*
16 Quad
±8
MAX5134AGUE+
16 TSSOP
16 Quad
±8
MAX5135GTG+
24 TQFN-EP*
12 Quad
±1
MAX5135GUE+
16 TSSOP
12 Quad
±1
Automatic Test Equipment
MAX5136AGTG+
24 TQFN-EP*
16 Dual
±8
Automatic Tuning
MAX5136AGUE+
16 TSSOP
16 Dual
±8
MAX5137GTG+
24 TQFN-EP*
12 Dual
±1
Applications
Communication Systems
Data Acquisition
Gain and Offset Adjustment
Portable Instrumentation
MAX5137GUE+
16 TSSOP
12 Dual
±1
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
Note: All devices are specified over the -40°C to +105°C operating temperature range.
Power-Amplifier Control
Process Control and Servo Loops
Programmable Voltage and Current Sources
Functional Diagrams, Pin Configurations, and Typical
Operating Circuit appear at end of data sheet.
QSPI is a trademark of Motorola Inc.
MICROWIRE is a registered trademark of National
Semiconductor Corp.
For pricing, delivery, and ordering information, please contact Maxim Direct at
1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
19-4209; Rev 4; 11/13
MAX5134–MAX5137
Pin-/Software-Compatible,
16-/12-Bit, Voltage-Output DACs
ABSOLUTE MAXIMUM RATINGS
AVDD to GND...........................................................-0.3V to +6V
DVDD to GND...........................................................-0.3V to +6V
OUT0–OUT3 to GND ....................................-0.3V to the lower of
(AVDD + 0.3V) and +6V
REFI, REFO, M/Z to GND .............................-0.3V to the lower of
(AVDD + 0.3V) and +6V
SCLK, DIN, CS to GND ................................-0.3V to the lower of
(DVDD + 0.3V) and +6V
LDAC, READY to GND .................................-0.3V to the lower of
(DVDD + 0.3V) and +6V
Continuous Power Dissipation (TA = +70°C)
24-Pin TQFN (derate at 27.8mW/°C above +70°C)....2222.2mW
16-Pin TSSOP (derate at 11.1mW/°C above +70°C)....888.9mW
Maximum Current into Any Input or Output
with the Exception of M/Z Pin .......................................±50mA
Maximum Current into M/Z Pin ...........................................±5mA
Operating Temperature Range .........................-40°C to +105°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
PACKAGE THERMAL CHARACTERISTICS (Note 1)
TSSOP
Junction-to-Ambient Thermal Resistance (θJA) ............90°C/W
Junction-to-Case Thermal Resistance (θJC) .................27°C/W
TQFN
Junction-to-Ambient Thermal Resistance (θJA) ............36°C/W
Junction-to-Case Thermal Resistance (θJC) ...................3°C/W
Note 1:
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
ELECTRICAL CHARACTERISTICS
(VAVDD = 2.7V to 5.25V, VDVDD = 2.7V to 5.25V, VAVDD ≥ VDVDD, VGND = 0V, VREFI = VAVDD - 0.25V, COUT = 200pF, ROUT = 10kΩ,
TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
STATIC ACCURACY (Notes 1, 2)
Resolution
N
MAX5134/MAX5136
16
MAX5135/MAX5137
12
(Note 3)
-8
Integral Nonlinearity
(MAX5134/MAX5136)
INL
VREFI = 5V,
VAVDD = 5.25V
Integral Nonlinearity
(MAX5135/MAX5137)
INL
VREFI = 5V, VAVDD = 5.25V
Differential Nonlinearity
DNL
Guaranteed monotonic
-1.0
(Note 4)
-10
Offset Error
OE
±2
TA = +25°C
+10
±6
-1
Offset-Error Drift
Gain Error
Bits
+0.25
±1
+1
LSB
+1.0
LSB
+10
±4
GE
(Note 4)
-0.5
Gain Temperature Coefficient
±0.2
LSB
mV
μV/°C
+0.5
% of FS
ppm
FS/°C
±2
REFERENCE INPUT
Reference-Input Voltage Range
Reference-Input Impedance
2
VREFI
VAVDD = 3V to 5.25V
2
VAVDD
VAVDD = 2.7V to 3V
2
VAVDD
- 0.2
113
V
k
Maxim Integrated
MAX5134–MAX5137
Pin-/Software-Compatible,
16-/12-Bit, Voltage-Output DACs
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = 2.7V to 5.25V, VDVDD = 2.7V to 5.25V, VAVDD ≥ VDVDD, VGND = 0V, VREFI = VAVDD - 0.25V, COUT = 200pF, ROUT = 10kΩ,
TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
2.437
2.440
2.443
V
10
25
ppm/°C
INTERNAL REFERENCE
Reference Voltage
VREFO
Reference Temperature Coefficient
TA = +25°C
(Note 5)
Reference Output Impedance
Line Regulation
Maximum Capacitive Load
CR
1
100
ppm/V
0.1
nF
DAC OUTPUT VOLTAGE (Note 2)
Output Voltage Range
No load
CL
Resistive Load
RL
Short-Circuit Current
ISC
Power-Up Time
V
0.1
Series resistance = 0
0.2
nF
Series resistance = 500
15
DC Output Impedance
Maximum Capacitive Load
(Note 5)
VAVDD
- 0.02
0.02
μF
2
VAVDD = 5.25V
VAVDD = 2.7V
k
±35
-40
From power-down mode
±20
+40
25
mA
μs
DIGITAL INPUTS (SCLK, DIN, CS, LDAC) (Note 6)
Input High Voltage
VIH
Input Low Voltage
VIL
Input Leakage Current
IIN
Input Capacitance
CIN
0.7 x
VDVDD
VIN = 0 or VDVDD
-1
V
±0.1
0.3 x
VDVDD
V
+1
μA
10
pF
DIGITAL OUTPUTS (READY)
Output High Voltage
VOH
ISOURCE = 3mA
Output Low Voltage
VOL
ISINK = 2mA
Voltage-Output Slew Rate
SR
Positive and negative
Voltage-Output Settling Time
tS
VDVDD
- 0.5
V
0.4
V
DYNAMIC PERFORMANCE
Digital Feedthrough
1.25
V/μs
1/4 scale to 3/4 scale VREFI = VAVDD = 5V
settle to ±2 LSB (Note 5)
5
μs
Code 0, all digital inputs from 0 to VDVDD
0.5
nV•s
25
nV•s
nV/Hz
Major Code Transition Analog
Glitch Impulse
Output Noise
10kHz
120
Integrated Output Noise
1Hz to 10kHz
18
μV
25
nV•s
DAC-to-DAC Crosstalk
Maxim Integrated
3
MAX5134–MAX5137
Pin-/Software-Compatible,
16-/12-Bit, Voltage-Output DACs
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = 2.7V to 5.25V, VDVDD = 2.7V to 5.25V, VAVDD ≥ VDVDD, VGND = 0V, VREFI = VAVDD - 0.25V, COUT = 200pF, ROUT = 10kΩ,
TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
POWER REQUIREMENTS (Note 7)
Analog Supply Voltage Range
VAVDD
Digital Supply Voltage Range
VDVDD
IAVDD
Supply Current
No load, all digital inputs at 0 or DVDD
(MAX5134/MAX5135)
IDVDD
IAVDD
Supply Current
No load, all digital inputs at 0 or DVDD
(MAX5136/MAX5137)
IDVDD
IAVPD
Power-Down Supply Current
No load, all digital inputs at 0 or DVDD
IDVPD
TIMING CHARACTERISTICS (Note 8) (Figure 1)
Serial-Clock Frequency
fSCLK
SCLK Pulse-Width High
tCH
SCLK Pulse-Width Low
tCL
CS Fall-to-SCLK Fall Setup Time
tCSS
SCLK Fall-to CS-Rise Hold Time
tCSH
DIN-to-SCLK Fall Setup Time
tDS
DIN-to-SCLK Fall Hold Time
tDH
SCLK Fall to READY Transition
tSRL
(Note 9)
CS Pulse-Width High
tCSW
LDAC Pulse Width
tLDACPWL
MIN
TYP
MAX
UNITS
2.5
1
1.5
1
0.2
0.1
5.25
VAVDD
3.6
10
2.3
10
2
2
V
V
mA
μA
mA
μA
30
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
2.7
2.7
0
13
13
8
5
10
2
30
33
33
μA
Static accuracy tested without load.
Linearity is tested within 20mV of GND and AVDD, allowing for gain and offset error.
Codes above 2047 are guaranteed to be within ±8 LSB.
Gain and offset tested within 100mV of GND and AVDD.
Guaranteed by design.
Device draws current in excess of the specified supply current when a digital input is driven with a voltage of VI < VDVDD - 0.6V
or VI > 0.5V. At VI = 2.2V with VDVDD = 5.25V, this current can be as high as 2mA. The SPI inputs are CMOS-input level compatible. The 30MHz clock frequency cannot be guaranteed for a minimum signal swing.
Note 7: Excess current from AVDD is 10mA when powered without DVDD. Excess current from DVDD is 1mA when powered without
AVDD.
Note 8: All timing specifications are with respect to the digital input and output thresholds.
Note 9: Maximum daisy-chain clock frequency is limited to 25MHz.
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
tCSW
COMMAND EXECUTED ON
24TH FALLING EDGE OF SCLK
CS
tCL
tCSS
tCH
tCSH
SCLK
tDS
DIN
X
C7
C6
C5
D3
tDH
D2
D1
D0
X
tSRL
READY
X = DON'T CARE.
Figure 1. Serial-Interface Timing Diagram
4
Maxim Integrated
MAX5134–MAX5137
Pin-/Software-Compatible,
16-/12-Bit, Voltage-Output DACs
Typical Operating Characteristics
(TA = +25°C, unless otherwise noted.)
7
5
0
-3
-6
-9
16384
32768
49152
1
-1
3
1
-1
-3
-3
-5
-5
-7
-7
65536
-9
2.7
3.2
3.7
4.2
4.7
-40
5.2
-20
0
20
40
60
80
100
DIGITAL INPUT CODE (LSB)
AVDD ( V )
TEMPERATURE (°C)
MAX5134/MAX5136 DIFFERENTIAL
NONLINEARITY vs. DIGITAL INPUT CODE
MAX5134/MAX5136 DIFFERENTIAL
NONLINEARITY vs. ANALOG SUPPLY VOLTAGE
MAX5134/MAX5136 DIFFERENTIAL
NONLINEARITY vs. TEMPERATURE
0.6
0.4
DNL (LSB)
0.4
0.2
0
-0.2
1.0
0.2
0
-0.2
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.4
-0.4
-0.6
-0.6
-0.6
-0.8
-0.8
-0.8
-1.0
-1.0
16384
32768
49152
-1.0
2.7
65536
3.2
3.7
4.2
4.7
5.2
-40
0
20
40
60
80
100
AVDD ( V )
TEMPERATURE (°C)
MAX5134/MAX5136 OFFSET ERROR
vs. ANALOG SUPPLY VOLTAGE
MAX5135/MAX5137 DIFFERENTIAL
NONLINEARITY vs. DIGITAL INPUT CODE
MAX5135/MAX5137 INTEGRAL
NONLINEARITY vs. DIGITAL INPUT CODE
6
0.06
0.04
DNL (LSB)
4
0.08
2
0
-2
0.02
0
-0.02
-4
-0.04
-6
-0.06
-8
-0.08
-10
3.7
4.2
AVDD ( V )
Maxim Integrated
4.7
5.2
0.75
0.50
0.25
0
-0.25
-0.50
-0.75
-1.00
-0.10
3.2
1.00
INL (LSB)
8
MAX5134-MAX5137 toc09
0.10
MAX5134-MAX5137 toc07
10
2.7
-20
DIGITAL INPUT CODE (LSB)
MAX5134-MAX5137 toc08
0
MAX5134-MAX5137 toc06
0.6
0.8
DNL (LSB)
0.8
MAX5134-MAX5137 toc05
1.0
MAX5134-MAX5137 toc04
1.0
DNL (LSB)
5
-9
0
OFFSET ERROR (mV)
7
INL (LSB)
3
INL (LSB)
3
9
MAX5134-MAX5137 toc02
6
INL (LSB)
9
MAX5134-MAX5137 toc01
9
MAX5134/MAX5136 INTEGRAL
NONLINEARITY vs. TEMPERATURE
MAX5134/MAX5136 INTEGRAL
NONLINEARITY vs. ANALOG SUPPLY VOLTAGE
MAX5134-MAX5137 toc03
MAX5134/MAX5136 INTEGRAL
NONLINEARITY vs. DIGITAL INPUT CODE
0
1024
2048
3072
DIGITAL INPUT CODE (LSB)
4096
0
1024
2048
3072
4096
DIGITAL INPUT CODE (LSB)
5
MAX5134–MAX5137
Pin-/Software-Compatible,
16-/12-Bit, Voltage-Output DACs
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
GAIN ERROR vs.
ANALOG SUPPLY VOLTAGE
-0.3
-0.4
0.4
0.3
0.1
0
-0.1
0.084
VAVDD = 5.25V
VREFI = 5V
0
20
40
60
80
100
2.7
3.2
3.7
4.2
4.7
-40
5.2
-20
0
20
40
80
100
TEMPERATURE (°C)
ANALOG SUPPLY CURRENT
vs. ANALOG SUPPLY VOLTAGE
ANALOG SUPPLY CURRENT vs. TEMPERATURE
ANALOG SUPPLY CURRENT vs. SUPPLY VOLTAGE
(POWER-DOWN MODE)
VOUT_ = VREFO
(MAX5136/MAX5137)
1700
1500
VOUT_ = 0
(MAX5136/MAX5137)
IAVDD (MAX5136/MAX5137)
2000
1500
1000
0.45
0.40
IDVDD
3.7
4.2
4.7
5.2
0.30
0.25
TA = +105°C
0.20
TA = +25°C
0.15
0.05
0
3.2
TA = -40°C
0.35
0.10
500
900
MAX5134-MAX5137 toc15
MAX5134-MAX5137 toc14
2500
0.50
SUPPLY CURRENT (µA)
1900
IAVDD (MAX5134/MAX5135)
SUPPLY CURRENT (μA)
MAX5134-MAX5137 toc13
VOUT_ = 0 (MAX5134/MAX5135)
3000
1100
0
-40
-20
0
20
40
60
80
100
2.7
3.2
3.7
4.2
4.7
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
EXITING/ENTERING
POWER-DOWN MODE
MAJOR CODE TRANSITION
SETTLING TIME UP
MAX5134-MAX5137 toc16
5.2
MAX5134-MAX5137 toc18
MAX5134-MAX5137 toc17
500mV/div
CH1
10mV/div
500mV/div
500mV/div
CH0
4μs/div
6
60
AVDD ( V )
VOUT_ = VREFO (MAX5134/MAX5135)
2.7
VAVDD = 2.7V
0.070
TEMPERATURE (°C)
2300
1300
0.076
0.072
-0.4
2500
2100
0.078
0.074
-0.5
-20
0.080
-0.3
-0.6
-40
VAVDD = 5.25V
0.082
-0.2
-0.5
SUPPLY CURRENT (μA)
0.2
0.086
MAX5134-MAX5137 toc12
-0.2
MAX5134-MAX5137 toc11
VAVDD = 2.7V
VREFI = 2.5V
GAIN ERROR vs. TEMPERATURE
0.5
GAIN ERROR (%FS)
OFFSET ERROR (mV)
-0.1
MAX5134-MAX5137 toc10
0
GAIN ERROR (%FS)
OFFSET ERROR vs. TEMPERATURE
1μs/div
400ns/div
Maxim Integrated
MAX5134–MAX5137
Pin-/Software-Compatible,
16-/12-Bit, Voltage-Output DACs
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
CROSSTALK
SETTLING TIME DOWN
DIGITAL FEEDTHROUGH
MAX5134-MAX5137 toc20
MAX5134-MAX5137 toc19
MAX5134-MAX5137 toc21
10mV/div
SCLK
5V/div
2V/div
VOUT_
50mV/div
500mV/div
400ns/div
4μs/div
40ns/div
DIGITAL SUPPLY CURRENT vs.
DIGITAL SUPPLY VOLTAGE
REFERENCE VOLTAGE vs.
SUPPLY VOLTAGE
REFERENCE VOLTAGE
vs. TEMPERATURE
VREFO (V)
2.5
2.0
1.5
2.46
TA = +25°C
2.44
2.4400
2.4395
2.4390
2.4385
2.4380
1.0
TA = +105°C
TA = -40°C
2.42
2.4375
2.40
0
3.2
3.7
4.2
4.7
2.7
5.2
3.2
3.7
4.2
4.7
2.4370
-40
5.2
-20
0
20
40
60
80
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
DIGITAL SUPPLY CURRENT
vs. DIGITAL INPUT VOLTAGE
FULL-SCALE OUTPUT
vs. TEMPERATURE
OUTPUT VOLTAGE
vs. OUTPUT CURRENT
2500
UP
2000
1500
DOWN
1000
2.51
2.50
2.49
EXTERNAL
REFERENCE
2.500V
2.48
2.47
2.46
INTERNAL
REFERENCE
2.45
100
2.50
VAVDD = 5V
2.45
2.40
OUTPUT VOLTAGE (V)
VAVDD = VDVDD = 5.25V
MAX5134-MAX5137 toc26
MAX5134-MAX5137 toc25
3000
OUTPUT VOLTAGE (V)
2.7
2.35
MAX5134-MAX5137 toc27
0.5
DIGITAL SUPPLY CURRENT (µA)
MAX5134-MAX5137 toc24
2.48
2.4405
VREFO (V)
3.0
MAX5134-MAX5137 toc23
VAVDD = 5.25V, SCLK = 0Hz
3.5
SUPPLY CURRENT (nA)
2.50
MAX5134-MAX5137 toc22
4.0
2.30
2.25
VAVDD = 3.3V
2.20
2.15
2.10
500
2.44
0
2.05
2.43
0
1
2
3
4
DIGITAL INPUT VOLTAGE (V)
Maxim Integrated
5
2.00
-40
-20
0
20
40
60
TEMPERATURE (°C)
80
100
0
5
10
15
20
25
30
OUTPUT CURRENT (mA)
7
MAX5134–MAX5137
Pin-/Software-Compatible,
16-/12-Bit, Voltage-Output DACs
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
REFERENCE INPUT RESPONSE
vs. FREQUENCY
ZERO-SCALE REFERENCE FEEDTHROUGH
MAX5134-MAX5137 toc29
MAX5134-MAX5137 toc28
5
MAX5134-MAX5137 toc30
FULL-SCALE REFERENCE FEEDTHROUGH
0
500mV/div
REF
500mV/div
500mV/div
VREF
ATTENUATION (dB)
VOUT_
-5
-10
-15
-20
-25
-30
VOUT_
10mV/div
0V VOUT
-35
-40
0V VREF
-45
20μs/div
1
10
100
1000
10,000
INPUT FREQUENCY (kHz)
POWER-UP GLITCH, ZERO SCALE,
EXTERNAL REFERENCE
POWER-UP GLITCH, MIDSCALE,
EXTERNAL REFERENCE
POWER-UP GLITCH, ZERO SCALE,
INTERNAL REFERENCE
MAX5134-MAX5137 toc31
MAX5134-MAX5137 toc33
MAX5134-MAX5137 toc32
2V/div
VAVDD
2V/div
2V/div
VAVDD
VAVDD
1V/div
VOUT_
1V/div
VOUT_
1V/div
POWER-UP GLITCH, MIDSCALE,
INTERNAL REFERENCE
VOUT_
DC NOISE SPECTRUM, FFT PLOT
MAX5134-MAX5137 toc35
MAX5134-MAX5137 toc34
-40dBm
2V/div
VAVDD
10dB/div
1V/div
VOUT_
2.5kHz/div
8
25kHz
Maxim Integrated
MAX5134–MAX5137
Pin-/Software-Compatible,
16-/12-Bit, Voltage-Output DACs
Pin Description
PIN
MAX5134
MAX5135
TQFN-EP
TSSOP
1
MAX5136
MAX5137
TQFN-EP
TSSOP
NAME
FUNCTION
3
1
3
OUT0
2, 5, 8,
11, 14, 17,
20, 23
—
2, 5, 6, 8,
11, 13, 14,
17, 20, 23
6, 11
N.C.
3
4
3
4
DVDD
Digital Power Supply. Bypass DVDD with a 0.1μF capacitor to GND.
5
READY
Active-Low Ready. Indicated configuration ready. Use READY as CS for
consecutive part or as feedback to the μC.
4
5
4
Channel 0 Buffered DAC Output
No Connection. Not internally connected.
6
6
—
—
OUT3
Channel 3 Buffered DAC Output
7, 19
7, 15
7, 19
7, 15
GND
Ground
9
8
9
8
DIN
Data In
10
9
10
9
CS
Active-Low Chip-Select Input
12
10
12
10
SCLK
Serial-Clock Input
13
11
—
—
OUT2
Channel 2 Buffered DAC Output
15
12
15
12
LDAC
Load DAC Input. Active-low hardware load DAC input.
16
13
16
13
M/Z
Power-Up Reset Select. Connect M/Z to VAVDD to power up the DAC
outputs to midscale. Connect M/Z to GND to power up the DAC outputs to
zero.
18
14
18
14
OUT1
Channel 1 Buffered DAC Output
21
16
21
16
REFO
Reference Voltage Output
22
1
22
1
REFI
Reference Voltage Input. Bypass REFI with a 0.1μF capacitor to GND
when using external reference.
24
2
24
2
AVDD
Analog Power Supply. Bypass AVDD with a 0.1μF capacitor to GND.
EP
Exposed Pad. Not internally connected. Connect to a ground or leave
unconnected. Not intended as an electrical connection point.
—
—
—
—
Detailed Description
The MAX5134–MAX5137 is a family of pin-compatible
and software-compatible 16-bit and 12-bit DACs. The
MAX5134/MAX5135 are low-power, quad 16-/12-bit,
buffered voltage-output, high-linearity DACs. The
MAX5136/MAX5137 are low-power, dual 16-/12-bit,
buffered voltage-output, high-linearity DACs. The
MAX5134–MAX5137 minimize the digital noise
feedthrough from input to output by powering down the
SCLK and DIN input buffers after completion of each 24bit serial input. On power-up, the MAX5134–MAX5137
reset the DAC outputs to zero or midscale, depending on
the state of the M/Z input, providing additional safety for
applications that drive valves or other transducers that
need to be off on power-up. The MAX5134–MAX5137
contain a segmented resistor string-type DAC, a serial-in
parallel-out shift register, a DAC register, power-on reset
Maxim Integrated
(POR) circuit, and control logic. On the falling edge of
the clock (SCLK) pulse, the serial input (DIN) data is
shifted into the device, MSB first. During power-down, an
internal 80kΩ resistor pulls DAC outputs to GND.
Output Amplifiers (OUT0–OUT3)
The MAX5134–MAX5137 include internal buffers for all
DAC outputs. The internal buffers provide improved load
regulation and transition glitch suppression for the DAC
outputs. The output buffers slew at 1.25V/µs and drive up
to 2kΩ in parallel with 200pF. The analog supply voltage
(AVDD) determines the maximum output voltage range
of the device as AVDD powers the output buffers.
DAC Reference
Internal Reference
The MAX5134–MAX5137 feature an internal reference
with a nominal output of +2.44V. Connect REFO to REFI
9
MAX5134–MAX5137
Pin-/Software-Compatible,
16-/12-Bit, Voltage-Output DACs
Serial Interface
when using the internal reference. Bypass REFO to
GND with a 47pF (maximum 100pF) capacitor.
Alternatively, if heavier decoupling is required, use a
1kΩ resistor in series with a 1µF capacitor in parallel
with the existing 100pF capacitor. REFO can deliver up
to 100µA of current with no degradation in performance. Configure other reference voltages by applying
a resistive potential divider with a total resistance
greater than 33kΩ from REFO to GND.
The MAX5134–MAX5137 3-wire serial interface is compatible with MICROWIRE, SPI, QSPI, and DSPs (Figures
2, 3). The interface provides three inputs, SCLK, CS,
and DIN and one output, READY. Use READY to verify
communication or to daisy-chain multiple devices (see
the READY section). READY is capable of driving a
20pF load with a 30ns (max) delay from the falling edge
of SCLK. The chip-select input (CS) frames the serial
data loading at DIN. Following a chip-select input’s
high-to-low transition, the data is shifted synchronously
and latched into the input register on each falling edge
of the serial-clock input (SCLK). Each serial word is 24
bits. The first 8 bits are the control word followed by 16
data bits (MSB first), as shown in Table 1. The serial
input register transfers its contents to the input registers
after loading 24 bits of data. To initiate a new data
transfer, drive CS high, keep CS high for a minimum of
33ns before the next write sequence. The SCLK can be
either high or low between CS write pulses. Figure 1
shows the timing diagram for the complete 3-wire serialinterface transmission.
External Reference
The external reference input features a typical input
impedance of 113kΩ and accepts an input voltage
from +2V to AVDD. Connect an external voltage
supply between REFI and GND to apply an external reference. Leave REFO unconnected. Visit
www.maximintegrated.com/products/references for
a list of available external voltage-reference devices.
AVDD as Reference
Connect AVDD to REFI to use AVDD as the reference
voltage. Leave REFO unconnected.
Table 1. Operating Mode Truth Table*
24-BIT WORD
CONTROL BITS
DATA BITS
MSB
LSB
C7 C6 C5 C4 C3
0
0
0
0
0
C2
C1
0
0
C0 D15 D14 D13 D12 D11 D10 D9
0
X
X
X
X
X
X
X
D8
D7
D6–D0
X
X
X
DAC DAC DAC DAC
3
2
1
0
DESC
FUNCTION
NOP
No operation.
Move contents of input
to DAC registers
indicated by 1’s. No
effect on registers
indicated by 0’s.
0
0
0
0
0
0
0
1
X
X
X
X
0
0
0
0
0
0
1
0
X
X
X
X
X
Power down DACs
Power indicated by 1’s.
Control Set READY_EN = 1 to
enable READY.
Linearity Optimize DAC linearity.
X
X
X
X
X
X
LDAC
X
X
CLR
0
0
0
0
0
0
1
1
X
X
X
DAC DAC DAC DAC
READY_EN
X
3
2
1
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
1
0
0
LIN
DAC DAC DAC DAC
D15 D14 D13 D12 D11 D10 D9
3
2
1
0
0
0
1
DAC DAC DAC DAC
1
D15 D14 D13 D12 D11 D10 D9
3
2
1
0
0
0
1
0
0
0
0
0
X
X
X
X
X
X
X
0
0
0
D8
D7
D6
D8
D7
D6
X
X
X
Write
Software clear.
Write to selected input
registers (DAC output
not affected).
Write to selected input
Write- and DAC registers,
through DAC outputs updated
(writethrough).
NOP
No operation.
*For the MAX5136/MAX5137, DAC2 and DAC3 do not exist. For the MAX5135/MAX5137, D0–D3 are don’t-care bits.
10
Maxim Integrated
MAX5134–MAX5137
Pin-/Software-Compatible,
16-/12-Bit, Voltage-Output DACs
The MAX5134–MAX5137 digital inputs are double
buffered. Depending on the command issued through the
serial interface, the input register(s) can be loaded without
affecting the DAC register(s) using the write command. To
update the DAC registers, either pulse the LDAC input low
to synchronously update all DAC outputs, or use the software LDAC command. Use the writethrough commands
(see Table 1) to update the DAC outputs immediately after
the data is received. Only use the writethrough command
to update the DAC output immediately.
The MAX5134/MAX5136 DAC code is unipolar binary
with V OUT_ = (code/65,536) x V REF. The MAX5135/
MAX5137 DAC code is unipolar binary with VOUT_ =
(code/4096) x VREF. See Table 1 for the serial interface
commands.
Connect the MAX5134–MAX5137 DVDD supply to the
supply of the host DSP or microprocessor. The AVDD
supply may be set to any voltage within the operating
range of 2.7V to 5.25V, but must be greater than or
equal to the DVDD supply.
Writing to the Devices
Write to the MAX5134–MAX5137 using the following
sequence:
1) Drive CS low, enabling the shift register.
2) Clock 24 bits of data into DIN (C7 first and D0 last),
observing the specified setup and hold times. Bits
D15–D0 are the data bits that are written to the
internal register.
3) After clocking in the last data bit, drive CS high. CS
must remain high for 33ns before the next transmission is started.
Figure 1 shows a write operation for the transmission of
24 bits. If CS is driven high at any point prior to receiving
24 bits, the transmission is discarded.
+5V
SK
SCLK
SS
MISO*
READY*
MAX5134–
MAX5137
SO
DIN
MAX5134–
MAX5137 DIN
MICROWIRE
PORT
MOSI
SPI/QSPI
PORT
SI*
READY*
SCK
SCLK
I/O
CS
I/O
CS
*THE READY-TO-SI CONNECTION IS NOT REQUIRED FOR WRITING TO THE DEVICES
*BUT MAY BE USED FOR TRANSMISSION VERIFICATION.
*THE READY-TO-MISO CONNECTION IS NOT REQUIRED FOR WRITING TO THE
DEVICES BUT MAY BE USED FOR TRANSMISSION VERIFICATION.
Figure 3. Connections for SPI/QSPI
Figure 2. Connections for MICROWIRE
CS
DIN
SLAVE 1 DATA
SLAVE 2 DATA
SLAVE 3 DATA
SCLK
1
2
3
4
20
21
22
23
24
1
2
3
4
5
21
22
23
24
1
2
3
4
5
21
22
23
24
READY 1
READY 2
READY 3
Figure 4. READY Timing
Maxim Integrated
11
MAX5134–MAX5137
Pin-/Software-Compatible,
16-/12-Bit, Voltage-Output DACs
READY
Clear Command
Connect READY to a microcontroller (µC) input to monitor the serial interface for valid communications. The
READY pulse appears 24 clock cycles after the negative edge of CS (Figure 4). Since the MAX5134–
MAX5137 look at the first 24 bits of the transmission following the falling edge of CS, it is possible to daisy
chain devices with different command word lengths.
READY goes high 16ns after CS is driven high.
Daisy chain multiple MAX5134–MAX5137 devices by
connecting the first device conventionally, then connect
its READY output to the CS of the following device.
Repeat for any other devices in the chain, and drive the
SCLK and DIN lines in parallel (Figure 5). When sending
commands to daisy-chained devices, the devices are
accessed serially starting with the first device in the
chain. The first 24 data bits are read by the first device,
the second 24 data bits are read by the second device
and so on (Figure 4). Figure 6 shows the configuration
when CS is not driven by the µC. These devices can be
daisy chained with other compatible devices such as the
MAX15500 output conditioner.
To perform a daisy-chain write operation, drive CS low
and output the data serially to DIN. The propagation of
the READY signal then controls how the data is read by
each device. As the data propagates through the daisy
chain, each individual command in the chain is executed on the 24th falling clock edge following the falling
edge of the respective CS input. To update just one
device in a daisy chain, send the no-op command to
the other devices in the chain.
The MAX5134–MAX5137 feature a software clear command (0x02). The software clear command acts as a
software POR, erasing the contents of all registers. All
outputs return to the state determined by the M/Z input.
If READY is not required, write command 0x03 (power
control) and set READY_EN = 0 (see Table 1) to disable the READY output.
Power-Down Mode
The MAX5134–MAX5137 feature a software-controlled
individual power-down mode for each channel. The
internal reference and biasing circuits power down to
conserve power when all 4 channels are powered
down. In power-down, the outputs disconnect from the
buffers and are grounded with an internal 80kΩ resistor. The DAC register holds the retained code so that
the output is restored when the channel powers up. The
serial interface remains active in power-down mode.
Load DAC (LDAC) Input
The MAX5134–MAX5137 feature an active-low LDAC
logic input that allows the outputs to update asynchronously. Keep LDAC high during normal operation
(when the device is controlled only through the serial
interface). Drive LDAC low to simultaneously update all
DAC outputs with data from their respective input registers. Figure 7 shows the LDAC timing with respect to
OUT_. Holding LDAC low causes the input registers to
become transparent and data written to the DAC registers to immediately update the DAC outputs. A software
command can also activate the LDAC operation. To
activate LDAC by software, set control word 0x01 and
data bits A11–A8 to select which DAC to load, and all
other data bits to don’t care. See Table 1 for the data
format. This operation updates only the DAC outputs
that are flagged with a 1. DAC outputs flagged with a 0
remain unchanged.
μC
MOSI
SCK
SLAVE 2
SLAVE 1
MAX5134–
MAX5137
I/O
DIN
DIN
SCLK
SCLK
CS
READY
SLAVE 3
MAX5134–
MAX5137
CS
MAX5134–
MAX5137
DIN
SCLK
READY
CS
READY
Figure 5. Daisy-Chain Configuration
12
Maxim Integrated
MAX5134–MAX5137
Pin-/Software-Compatible,
16-/12-Bit, Voltage-Output DACs
TO OTHER CHIPS/CHAINS
CSm
μC
CS1
CS
SCLK
DWRITE
DREAD
INT
SLAVE 1
CS
SCLK
DIN
MAX5134–
MAX5137
READY
SLAVE 2
CS
SCLK
DIN
MAX5134–
MAX5137
READY
SLAVE N
CS
MAX15500
SCLK
DIN
DOUT
ERROR
READY
Figure 6. Daisy Chain (CS Not Used)
Maxim Integrated
13
MAX5134–MAX5137
Pin-/Software-Compatible,
16-/12-Bit, Voltage-Output DACs
tLDACPWL
LDAC
tS
±2 LSB
OUT_
Figure 7. Output Timing
Applications Information
Power-On Reset (POR)
On power-up, the input registers are set to zero, DAC
outputs power up to zero or midscale, depending on
the configuration of M/Z. Connect M/Z to GND to power
the outputs to GND. Connect M/Z to AVDD to power the
outputs to midscale.
To guarantee DAC linearity, wait until the supplies have
settled. Set the LIN bit in the DAC linearity register; wait
10ms, and clear the LIN bit.
Unipolar Output
The MAX5134–MAX5137 unipolar output voltage range
is 0 to VREFI. The output buffers each drive a load of
2kΩ in parallel with 200pF.
Layout Considerations
Digital and AC transient signals on GND inputs can create noise at the outputs. Connect both GND inputs to
form the star ground for the DAC system. Refer remote
DAC loads to this system ground for the best possible
performance. Use proper grounding techniques, such
as a multilayer board with a low-inductance ground
plane, or star connect all ground return paths back to
the MAX5134–MAX5137 GND. Carefully lay out the
traces between channels to reduce AC crosscoupling
and crosstalk. Do not use wire-wrapped boards and
sockets. Use shielding to improve noise immunity. Do
not run analog and digital signals parallel to one another (especially clock signals) and avoid routing digital
lines underneath the MAX5134–MAX5137 package.
Definitions
Bipolar Output
Use the MAX5134–MAX5137 in bipolar applications with
additional external components (see the Typical
Operating Circuit).
Power Supplies and
Bypassing Considerations
For best performance, use a separate supply for the
MAX5134–MAX5137. Bypass both DVDD and AVDD
with high-quality ceramic capacitors to a low-impedance ground as close as possible to the device.
Minimize lead lengths to reduce lead inductance.
Connect both MAX5134–MAX5137 GND inputs to the
analog ground plane.
Table 2. MAX5134/MAX5136 Input Code
vs. Output Voltage
DAC LATCH CONTENTS
MSB
1111 1111 1111 1111
14
ANALOG OUTPUT, VOUT_
LSB
Integral Nonlinearity (INL)
INL is the deviation of the measured transfer function
from a best fit straight line drawn between two codes.
For the MAX5134/MAX5136, this best fit line is a line
drawn between codes 3072 and 64,512 of the transfer
function, once offset and gain errors have been nullified.
For the MAX5135/MAX5137, this best fit line is a line
drawn between codes 192 and 4032 of the transfer function, once offset and gain errors have been nullified.
Differential Nonlinearity (DNL)
DNL is the difference between an actual step height
and the ideal value of 1 LSB. If the magnitude of the
DNL is greater than -1 LSB, the DAC guarantees no
missing codes and is monotonic.
Table 3. MAX5135/MAX5137 Input Code
vs. Output Voltage
DAC LATCH CONTENTS
MSB
ANALOG OUTPUT, VOUT_
LSB
VREF x (65,535/65,536)
1111
1111
1111
XXXX
VREF x (4095/4096)
1000 0000 0000 0000
VREF x (32,768/65,536) = 1/2 VREF
1000
0000
0000
XXXX
VREF x (2048/4096)
0000 0000 0000 0001
VREF x (1/65,536)
0000
0000
0001
XXXX
VREF x (1/4096)
0000 0000 0000 0000
0
0000
0000
0000
XXXX
0
Maxim Integrated
MAX5134–MAX5137
Pin-/Software-Compatible,
16-/12-Bit, Voltage-Output DACs
Offset Error
Digital-to-Analog Glitch Impulse
Offset error indicates how well the actual transfer function matches the ideal transfer function at a single point.
Typically, the point at which the offset error is specified is
at or near the zero-scale point of the transfer function.
A major carry transition occurs at the midscale point
where the MSB changes from low to high and all other
bits change from high to low, or where the MSB
changes from high to low and all other bits change from
low to high. The duration of the magnitude of the
switching glitch during a major carry transition is
referred to as the digital-to-analog glitch impulse.
Gain Error
Gain error is the difference between the ideal and the
actual full-scale output voltage on the transfer curve,
after nullifying the offset error. This error alters the slope
of the transfer function and corresponds to the same
percentage error in each step.
Settling Time
The settling time is the amount of time required from the
start of a transition, until the DAC output settles to the new
output value within the converter’s specified accuracy.
Digital Feedthrough
Digital feedthrough is the amount of noise that appears
on the DAC output when the DAC digital control lines
are toggled.
Digital-to-Analog Power-Up Glitch Impulse
The digital-to-analog power-up glitch is the duration of
the magnitude of the switching glitch that occurs as the
device exits power-down mode.
DC DAC-to-DAC Crosstalk
Crosstalk is the amount of noise that appears on a DAC
output set to 0 when the other DAC is updated from 0 to
AVDD
Chip Information
PROCESS: BiCMOS
N.C.
M/Z
LDAC
N.C.
OUT2**
TOP VIEW
OUT1
Pin Configurations
18
17
16
15
14
13
+
GND 19
12
SCLK
N.C. 20
11
N.C.
10
CS
MAX5134–
MAX5137
REF0 21
REFI 22
9
DIN
8
N.C.
7
GND
REFI 1
16 REFO
AVDD 2
15 GND
OUT0 3
DVDD 4
MAX5134–
MAX5137
READY 5
*EP
AVDD 24
11 OUT2**
GND 7
10 SCLK
DIN 8
9 CS
6
OUT3**
5
N.C.
4
READY
3
DVDD
2
N.C.
1
OUT0
+
13 M/Z
12 LDAC
OUT3 6
N.C. 23
14 OUT1
TSSOP
*EXPOSED PAD.
**N.C. FOR THE MAX5136/MAX5137.
Maxim Integrated
15
MAX5134–MAX5137
Pin-/Software-Compatible,
16-/12-Bit, Voltage-Output DACs
Functional Diagrams
AVDD
MAX5134
MAX5135
M/Z
DVDD
GND
REFI
REFO
REFERENCE
POR
CONTROL LOGIC
POWER-DOWN
CONTROL
INPUT
REGISTER
DAC
REGISTER
12-/16-BIT
DAC
BUFFER
INPUT
REGISTER
DAC
REGISTER
12-/16-BIT
DAC
BUFFER
INPUT
REGISTER
DAC
REGISTER
12-/16-BIT
DAC
BUFFER
INPUT
REGISTER
DAC
REGISTER
12-/16-BIT
DAC
BUFFER
OUT0
CS
SCLK
SERIAL-TOPARALLEL
CONVERTER
OUT1
DIN
READY
16
OUT2
OUT3
LDAC
Maxim Integrated
MAX5134–MAX5137
Pin-/Software-Compatible,
16-/12-Bit, Voltage-Output DACs
Functional Diagrams (continued)
AVDD
MAX5136
MAX5137
M/Z
SCLK
REFI
READY
REFO
REFERENCE
POWER-DOWN
CONTROL
INPUT
REGISTER
DAC
REGISTER
12-/16-BIT
DAC
BUFFER
INPUT
REGISTER
DAC
REGISTER
12-/16-BIT
DAC
BUFFER
SERIAL-TOPARALLEL
CONVERTER
DIN
Maxim Integrated
GND
POR
CONTROL LOGIC
CS
DVDD
OUT0
OUT1
LDAC
17
MAX5134–MAX5137
Pin-/Software-Compatible,
16-/12-Bit, Voltage-Output DACs
Typical Operating Circuit
DIGITAL POWER
SUPPLY
ANALOG POWER
SUPPLY
100nF
100nF
100nF
DVDD
AVDD
M/Z
LDAC
OUT
DAC
CS
SCLK
DIN
READY
MAX5134–
MAX5137
REFO
R1
R2
REFI
47pF
GND
NOTE: SHOWN IN BIPOLAR CONFIGURATION.
Package Information
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the
drawing pertains to the package regardless of RoHS status.
18
PACKAGE TYPE
PACKAGE CODE
OUTLINE NO.
LAND PATTERN NO.
24 TQFN-EP
T2444+4
21-0139
90-0022
16 TSSOP
U16+2
21-0066
90-0117
Maxim Integrated
MAX5134–MAX5137
Pin-/Software-Compatible,
16-/12-Bit, Voltage-Output DACs
Revision History
REVISION
NUMBER
REVISION
DATE
0
7/08
1
10/08
DESCRIPTION
Initial release of MAX5134.
Initial release of MAX5135/MAX5136/MAX5137.
Added the TSSOP package to the Ordering Information table, Absolute Maximum Ratings
section, and Pin Description table.
Changed the Major Code Transition Analog Glitch Impulse parameter in the Electrical
Characteristics table from 12nV•s (typ) to 25nV•s (typ).
2
1/10
In the Typical Operating Characteristics; added “SCLK = 0Hz” to TOC22, changed
TOC28 to “500mV/div” from “500mV”; and changed the title of TOC30 to “Reference Input
Response vs. Frequency.”
Added a statement to the Internal Reference section regarding using a resistor in series.
Changed the Functional Diagrams to show LDAC drawn to the DAC register.
Replaced the Typical Operating Circuit to show the correct op amp.
3
1/13
Revised the Absolute Maximum Ratings and added the Package Thermal Characteristics
section. Updated the Electrical Characteristics table.
4
11/13
Revised Ordering Information.
PAGES
CHANGED
—
1–19
1, 2, 9
3
7, 8
10
16, 17
18
2–4, 9
1
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent
licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and
max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000
© 2013 Maxim Integrated Products, Inc.
19
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
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