MAX5186BEEI+T

19-1581; Rev 4; 5/03 Dual, 8-Bit, 40MHz, Current/Voltage, Simultaneous-Output DACs The MAX5186/MAX5189 are designed to provide a high level of signal integrity for the least amount of power dissipation. Both DACs operate from a single supply voltage of 2.7V to 3.3V. Additionally, these DACs have three modes of operation: normal, low-power standby, and complete shutdown, which provides the lowest possible power dissipation with a 1µA (max) shutdown current. A fast wake-up time (0.5µs) from standby mode to full DAC operation allows power conservation by activating the DACs only when required. The MAX5186/MAX5189 are packaged in a 28-pin QSOP and are specified for the extended (-40°C to +85°C) temperature range. For higher resolution, dual 10-bit versions, refer to the MAX5180/MAX5183 data sheet. Features ♦ 2.7V to 3.3V Single-Supply Operation ♦ Wide Spurious-Free Dynamic Range: 70dB at fOUT = 2.2MHz ♦ Fully Differential Outputs for Each DAC ♦ ±0.5% FSR Gain Mismatch at fOUT = 2.2MHz ♦ ±0.15° Phase Mismatch at fOUT = 2.2MHz ♦ Low-Current Standby or Full Shutdown Modes ♦ Internal 1.2V, Low-Noise Bandgap Reference ♦ Small 28-Pin QSOP Package Ordering Information TEMP RANGE PART MAX5186BEEI MAX5189BEEI PIN-PACKAGE 28 QSOP 28 QSOP -40°C to +85°C -40°C to +85°C Pin Configuration TOP VIEW Applications Signal Reconstruction of I and Q Transmit Signals Digital Signal Processing Arbitrary Waveform Generation (AWG) Imaging Applications CREF1 1 28 CREF2 OUT1P 2 27 OUT2P OUT1N 3 26 OUT2N AGND 4 25 REFO AVDD 5 DACEN 6 24 REFR MAX5186 MAX5189 23 DGND PD 7 22 DVDD CS 8 21 D7 CLK 9 20 D6 N.C. 10 19 D5 REN 11 18 D4 DGND 12 17 D3 DGND 13 16 D2 D0 14 15 D1 QSOP ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX5186/MAX5189 General Description The MAX5186 contains two 8-bit, simultaneous-update, current-output digital-to-analog converters (DACs) designed for superior performance in communications systems requiring analog signal reconstruction with low distortion and low-power operation. The MAX5189 provides equal specifications, with on-chip precision resistors for voltage output operation. The MAX5186/ MAX5189 are designed for a 10pV-s glitch operation to minimize unwanted spurious signal components at the output. An on-board 1.2V bandgap circuit provides a well-regulated, low-noise reference that can be disabled for external reference operation. MAX5186/MAX5189 Dual, 8-Bit, 40MHz, Current/Voltage, Simultaneous-Output DACs ABSOLUTE MAXIMUM RATINGS AVDD, DVDD to AGND, DGND ................................ -0.3V to +6V Digital Input to DGND.............................................. -0.3V to +6V OUT1P, OUT1N, OUT2P, OUT2N, CREF1, CREF2 to AGND .................................................. -0.3V to +6V REF0, REFR to AGND.............................................. -0.3V to +6V AGND to DGND................................................... -0.3V to +0.3V AVDD to DVDD .................................................................... ±3.3V Maximum Current into Any Pin........................................... 50mA Continuous Power Dissipation (TA = +70°C) 28-Pin QSOP (derate 10.8mW/°C above +70°C) .... 860.2mW Operating Temperature Ranges MAX518_BEEI................................................. -40°C to +85°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (AVDD = DVDD = 3V, AGND = DGND = 0, fCLK = 40MHz, IFS = 1mA, 400Ω differential output, CL = 5pF, TA = TMIN to TMAX, unless otherwise noted. ≥ +25°C guaranteed by production test, < +25°C guaranteed by design and characterization. Typical values are at TA = +25°C.) PARAMETER Resolution SYMBOL CONDITIONS MIN TYP MAX UNITS +1 LSB +1 LSB N 8 Integral Nonlinearity INL -1 ±0.25 Differential Nonlinearity DNL Guaranteed monotonic -1 ±0.25 MAX5186 -1 +1 MAX5189 -4 +4 (Note 1) -20 Offset Error Gain Error Bits ±4 +20 LSB LSB DYNAMIC PERFORMANCE Output Settling Time To ±0.5LSB error band Glitch Impulse Spurious-Free Dynamic Range to Nyquist SFDR fCLK = 40MHz Total Harmonic Distortion to Nyquist THD fCLK = 40MHz Signal-to-Noise-Ratio to Nyquist SNR fCLK = 40MHz fOUT = 550kHz fOUT = 2.2MHz, TA = +25°C 25 ns 10 pV-s 72 57 fOUT = 550kHz -70 fOUT = 2.2MHz, TA = +25°C -68 fOUT = 550kHz fOUT = 2.2MHz, TA = +25°C dBc 70 -60 52 46 dBc dB 52 DAC-to-DAC Output Isolation fOUT = 2.2MHz -60 dB Clock and Data Feedthrough All 0s to all 1s 50 pV-s 10 pA/√Hz Output Noise Gain Mismatch Between DAC Outputs fOUT = 2.2MHz, TA = +25°C ±0.5 Phase Mismatch Between DAC Outputs fOUT = 2.2MHz ±0.15 2 _______________________________________________________________________________________ ±1 % FSR degrees Dual, 8-Bit, 40MHz, Current/Voltage, Simultaneous-Output DACs (AVDD = DVDD = 3V, AGND = DGND = 0, fCLK = 40MHz, IFS = 1mA, 400Ω differential output, CL = 5pF, TA = TMIN to TMAX, unless otherwise noted. ≥ +25°C guaranteed by production test, < +25°C guaranteed by design and characterization. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS ANALOG OUTPUT Differential Full-Scale Output Voltage VFS 400 Voltage Compliance Range Output Leakage Current mV -0.3 0.8 V DACEN = 0, MAX5186 only -1 1 µA 0.5 1.5 mA Full-Scale Output Current IFS MAX5186 only DAC External Output Resistor Load RL MAX5186 only 1 Ω 400 REFERENCE Output Voltage Range Output Voltage Temperature Drift Reference Output Drive Capability VREFO 1.12 1.2 1.28 V TCVREFO 50 ppm/°C IREFO 10 µA Reference Supply Rejection Current Gain (IFS /IREF) 0.5 mV/V 8 mA/mA POWER REQUIREMENTS Analog Power-Supply Voltage AVDD Analog Supply Current IAVDD Digital Power-Supply Voltage DVDD Digital Supply Current Standby Current Shutdown Current 2.7 PD = 0, DACEN = 1, digital inputs at 0 or DVDD 2.7 2.7 3.3 V 5.0 mA 3.3 V IDVDD PD = 0, DACEN = 1, digital inputs at 0 or DVDD 4.2 5.0 mA ISTANDBY PD = 0, DACEN = 0, digital inputs at 0 or DVDD 1.0 1.5 mA ISHDN PD = 1, DACEN = X, digital inputs at 0 or DVDD (X = don’t care) 0.5 1 µA LOGIC INPUTS AND OUTPUTS Digital Input Voltage High VIH 2 V Digital Input Voltage Low VIL Digital Input Current IIN Digital Input Capacitance CIN 10 pF DAC1 DATA to CLK Rise Setup Time tDS1 10 ns DAC2 DATA to CLK Fall Setup Time tDS2 10 ns DAC1 CLK Rise to DATA Hold Time tDH1 0 ns DAC2 CLK Fall to DATA Hold Time tDH2 0 ns VIN = 0 or DVDD 0.8 V ±1 µA TIMING CHARACTERISTICS _______________________________________________________________________________________ 3 MAX5186/MAX5189 ELECTRICAL CHARACTERISTICS (continued) ELECTRICAL CHARACTERISTICS (continued) (AVDD = DVDD = 3V, AGND = DGND = 0, fCLK = 40MHz, IFS = 1mA, 400Ω differential output, CL = 5pF, TA = TMIN to TMAX, unless otherwise noted. ≥ +25°C guaranteed by production test, < +25°C guaranteed by design and characterization. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS CS Fall to CLK Rise Time 5 ns CS Fall to CLK Fall Time 5 ns DACEN Rise Time to VOUT 0.5 µs PD Fall Time to VOUT 50 µs Clock Period tCLK 25 ns Clock High Time tCH 10 ns Clock Low Time tCL 10 ns Note 1: Excludes reference and reference resistor (MAX5189) tolerance. Typical Operating Characteristics (AVDD = DVDD = 3V, AGND = DGND = 0, 400Ω differential output, IFS = 1mA, CL = 5pF, TA = +25°C, unless otherwise noted.) 0.075 0.100 0.050 DNL (LSB) 0.050 0.025 0.025 0 -0.025 0 2.53 MAX5186 MAX5189 2.51 2.49 2.47 -0.050 -0.025 -0.050 2.45 -0.075 32 64 96 128 160 192 224 256 0 32 64 96 3.0 3.5 4.0 4.5 5.0 DIGITAL INPUT CODE DIGITAL INPUT CODE SUPPLY VOLTAGE (V) ANALOG SUPPLY CURRENT vs. TEMPERATURE DIGITAL SUPPLY CURRENT vs. SUPPLY VOLTAGE DIGITAL SUPPLY CURRENT vs. TEMPERATURE 3.0 MAX5189 2.5 MAX5186 2.0 1.5 8 MAX5186 6 MAX5189 4 2 10 35 TEMPERATURE (°C) 60 85 MAX5189 4 3 MAX5186 2 1 0 0 -15 5 5.5 MAX5186/9toc06 3.5 10 DIGITAL SUPPLY CURRENT (mA) MAX5186/9toc04 4.0 -40 2.5 128 160 192 224 256 MAX5186/9toc05 0 DIGITAL SUPPLY CURRENT (mA) INL (LSB) 0.075 2.55 SUPPLY CURRENT (mA) 0.125 MAX5186/9toc02 0.100 MAX5186/9toc01 0.150 4 ANALOG SUPPLY CURRENT vs. SUPPLY VOLTAGE DIFFERENTIAL NONLINEARITY vs. DIGITAL INPUT CODE MAX5186/9toc03 INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE ANALOG SUPPLY CURRENT (mA) MAX5186/MAX5189 Dual, 8-Bit, 40MHz, Current/Voltage, Simultaneous-Output DACs 2.5 3.0 3.5 4.0 4.5 SUPPLY VOLTAGE (V) 5.0 5.5 -40 -15 10 35 TEMPERATURE (°C) _______________________________________________________________________________________ 60 85 Dual, 8-Bit, 40MHz, Current/Voltage, Simultaneous-Output DACs 590 590 580 MAX5189 570 MAX5186 580 570 MAX5189 560 550 560 3.0 3.5 4.0 4.5 5.0 5.5 0.70 MAX5189 0.65 MAX5186 0.60 0.55 0.50 0.45 540 -40 -15 10 35 60 2.5 85 3.0 4.0 3.5 4.5 5.0 SUPPLY VOLTAGE (V) TEMPERATURE (°C) SUPPLY VOLTAGE (V) INTERNAL REFERENCE VOLTAGE vs. SUPPLY VOLTAGE INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE OUTPUT CURRENT vs. REFERENCE CURRENT 1.26 MAX5189 1.25 MAX5186 1.24 1.27 OUTPUT CURRENT (mA) REFERENCE VOLTAGE (V) 1.27 4 1.26 MAX5189 1.25 MAX5186 5.5 MAX5186/9toc12 1.28 MAX5186/9toc10 1.28 MAX5186/9toc11 2.5 3 2 1 1.24 1.23 0 1.23 3.0 3.5 4.0 4.5 5.0 5.5 -40 -15 10 35 60 0 85 100 200 300 400 SUPPLY VOLTAGE (V) TEMPERATURE (°C) REFERENCE CURRENT (µA) DYNAMIC RESPONSE RISE TIME DYNAMIC RESPONSE FALL TIME SETTLING TIME 50ns/div 500 MAX5186/9toc15 MAX5186/9toc14 2.5 MAX5186toc13 REFERENCE VOLTAGE (V) 0.75 SHUITDOWN CURRENT (µA) MAX5186 SHUTDOWN CURRENT vs. SUPPLY VOLTAGE 0.80 MAX5186/9toc08 MAX5186/9toc07 600 STANDBY CURRENT (µA) STANDBY CURRENT (µA) STANDBY CURRENT vs. TEMPERATURE 600 MAX5186/9toc09 STANDBY CURRENT vs. SUPPLY VOLTAGE 610 MAX5186/MAX5189 Typical Operating Characteristics (continued) (AVDD = DVDD = 3V, AGND = DGND = 0, 400Ω differential output, IFS = 1mA, CL = 5pF, TA = +25°C, unless otherwise noted.) OUT_P 150mV/ div OUT_P 150mV/ div OUT_N 100mV/ div OUT_N 150mV/ div OUT_N 150mV/ div OUT_P 100mV/ div 50ns/div 12.5ns/div _______________________________________________________________________________________ 5 Typical Operating Characteristics (continued) (AVDD = DVDD = 3V, AGND = DGND = 0, 400Ω differential output, IFS = 1mA, CL = 5pF, TA = +25°C, unless otherwise noted.) -40 -60 -80 -40 -60 -80 -100 -100 -120 -120 4 8 12 16 DAC1 60 50 8 12 16 10 15 20 25 30 35 40 45 50 55 60 20 CLOCK FREQUENCY (MHz) 78 fCLK = 60MHz fCLK = 20MHz 72 70 72 70 fCLK = 50MHz fCLK = 10MHz 68 fCLK = 20MHz fCLK = 40MHz 74 SFDR (dBc) 74 fCLK = 60MHz 76 MAX5186/9toc20 78 MAX5186/9toc19 SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT FREQUENCY AND CLOCK FREQUENCY, DAC2 76 SFDR (dBc) 70 SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT FREQUENCY AND CLOCK FREQUENCY, DAC1 fCLK = 40MHz fCLK = 10MHz fCLK = 50MHz 68 fCLK = 30MHz fCLK = 30MHz 66 66 500 700 900 1100 1300 1500 1700 1900 2100 2300 500 700 900 1100 1300 1500 1700 1900 2100 2300 OUTPUT FREQUENCY (kHz) OUTPUT FREQUENCY (kHz) SPURIOUS-FREE DYNAMIC RANGE vs. FULL-SCALE OUTPUT CURRENT MTPR PLOT (fCLK = 40MHz, 4096-POINT DATA RECORD) 0 MAX5186/89-21 74 70 68 66 64 fT1 = 1.81MHz fT2 = 2.01MHz fT3 = 2.41MHz fT4 = 2.59MHz AOUT = 0dBFS AVDD = DVDD = 2.7V -20 OUTPUT POWER (dBm) 72 SFDR (dBc) DAC2 fOUT (MHz) fOUT (MHz) -40 -60 -80 -100 62 60 -120 0.5 0.75 1.0 1.25 FULL-SCALE OUTPUT CURRENT (mA) 6 80 40 4 0 20 90 MAX5186/9toc23 0 MAX5186/9toc18 100 SPURIOUS-FREE DYNAMIC RANGE (dBc) fOUT = 2.2MHz AOUT = 0dBFS AVDD = DVDD = 2.7V -20 OUTPUT POWER (dBm) -20 0 MAX5186/9toc17 fOUT = 2.2MHz AOUT = 0dBFS AVDD = DVDD = 2.7V MAX5186/9toc16 0 SPURIOUS-FREE DYNAMIC RANGE vs. CLOCK FREQUENCY FFT PLOT, DAC2 (fCLK = 40MHz, 2048-POINT DATA RECORD) FFT PLOT, DAC1 (fCLK = 40MHz, 2048-POINT DATA RECORD) OUTPUT POWER (dBm) MAX5186/MAX5189 Dual, 8-Bit, 40MHz, Current/Voltage, Simultaneous-Output DACs 1.5 0 4 8 12 16 fOUT (MHz) _______________________________________________________________________________________ 20 Dual, 8-Bit, 40MHz, Current/Voltage, Simultaneous-Output DACs PIN NAME FUNCTION 1 CREF1 Reference Bias Bypass, DAC1 2 OUT1P Positive Analog Output, DAC1. Current output for MAX5186; voltage output for MAX5189. 3 OUT1N Negative Analog Output, DAC1. Current output for MAX5186; voltage output for MAX5189. 4 AGND Analog Ground 5 AVDD Analog Positive Supply, 2.7V to 3.3V 6 DACEN 7 PD Power-Down Select 0: Enter DAC standby mode (DACEN = DGND) or power-up DAC (DACEN = DVDD). 1: Enter shutdown mode. 8 CS Active-Low Chip Select 9 CLK Clock input 10 N.C. No Connect. Do not connect to this pin. 11 REN Active-Low Reference Enable. Connect to DGND to activate on-chip 1.2V reference. 12 DGND Digital Ground 13 DGND Digital Ground 14 D0 Data Bit D0 (LSB) 15–20 D1–D6 Data Bits D1–D6 21 D7 22 DVDD Digital Supply, 2.7V to 3.3V 23 DGND Digital Ground 24 REFR Reference Input 25 REFO Reference Output 26 OUT2N Negative Analog Output, DAC2. Current output for MAX5186; voltage output for MAX5189. 27 OUT2P Positive Analog Output, DAC2. Current output for MAX5186; voltage output for MAX5189. 28 CREF2 Reference Bias Bypass, DAC2 DAC Enable, Digital Input 0: Enter DAC standby mode with PD = DGND. 1: Power-up DAC with PD = DGND. X: Enter shutdown mode with PD = DVDD (X = don’t care). Data Bit D7 (MSB) _______________________________________________________________________________________ 7 MAX5186/MAX5189 Pin Description MAX5186/MAX5189 Dual, 8-Bit, 40MHz, Current/Voltage, Simultaneous-Output DACs Detailed Description The MAX5186/MAX5189 are dual, 8-bit digital-to-analog converters (DACs) capable of operating with clock speeds up to 40MHz. Each of these dual converters consists of separate input and DAC registers, followed by a current source array capable of generating up to 1.5mA full-scale output current (Figure 1). An integrated 1.2V voltage reference and control amplifier determine the data converters’ full-scale output currents/ voltages. Careful reference design ensures close gain matching and excellent drift characteristics. The MAX5189’s voltage output operation features matched 400Ω on-chip resistors that convert the current array current into a voltage. Internal Reference and Control Amplifier The MAX5186/MAX5189 provide an integrated 50ppm/°C, 1.2V, low-noise bandgap reference that can be disabled and overridden by an external reference voltage. REFO serves either as an external reference input or an integrated reference output. If REN is connected to DGND, the internal reference is selected and REFO provides a 1.2V output. Due to its limited 10µA output drive capability, REFO must be buffered with an external amplifier if heavier loading is required. The MAX5186/MAX5189 also employ a control amplifier designed to simultaneously regulate the full-scale output current (IFS) for both outputs of the devices. The output current is calculated as follows: IFS = 8 ✕ IREF where I REF is the reference output current (I REF = VREFO/RSET) and IFS is the full-scale output current. R SET is the reference resistor that determines the amplifier’s output current on the MAX5186 (Figure 2). This current is mirrored into the current source array where it is equally distributed between matched current segments and summed to valid output current readings for the DACs. The MAX5189 converts each output current (DAC1 and DAC2) into an output voltage (VOUT1, VOUT2) with two internal, ground-referenced 400Ω load resistors. Using the internal 1.2V reference voltage, the MAX5189’s integrated reference output-current resistor (RSET = 9.6kΩ) sets IREF to 125µA and IFS to 1mA. 8 External Reference To disable the MAX5186/MAX5189’s internal reference, connect REN to DVDD. A temperature-stable, external reference may now be applied to drive the REFO pin to set the full-scale output (Figure 3). Choose a reference capable of supplying at least 150µA to drive the bias circuit that generates the cascode current for the current array. For improved accuracy and drift performance, choose a fixed output voltage reference such as the 1.2V, 25ppm/°C MAX6520 bandgap reference. Standby Mode To enter the lower power standby mode, connect digital inputs PD and DACEN to DGND. In standby, both the reference and the control amplifier are active with the current array inactive. To exit this condition, DACEN must be pulled high with PD held at DGND. Both the MAX5186/MAX5189 typically require 50µs to wake up and let both outputs and reference settle. Shutdown Mode For lowest power consumption, the MAX5186/MAX5189 provide a power-down mode in which the reference, control amplifier, and current array are inactive and the DACs’ supply current is reduced to 1µA. To enter this mode, connect PD to DVDD. To return to active mode, connect PD to DGND and DACEN to DVDD. About 50µs are required for the parts to leave shutdown mode and settle to their outputs’ values prior to shutdown. Table 1 lists the power-down mode selection. Timing Information The MAX5186/MAX5189 dual DACs write to their outputs simultaneously (Figure 4). On the falling edge of the clock, the input data for DAC2 is preloaded into a latch. On the rising edge of the clock, input data for DAC1 is loaded to the DAC1 register, and the preloaded DAC2 data in the latch is loaded to the DAC2 register. Outputs The MAX5186 outputs are designed to supply full-scale output currents of 1mA into 400Ω loads in parallel with a capacitive load of 5pF. The MAX5189 features integrated 400Ω resistors that restore the array currents to proportional, differential voltages of 400mV. These differential output voltages can then be used to drive a balun transformer or a low-distortion, high-speed operational amplifier to convert the differential voltage into a single-ended voltage. _______________________________________________________________________________________ Dual, 8-Bit, 40MHz, Current/Voltage, Simultaneous-Output DACs AVDD AGND CS DACEN MAX5186/MAX5189 REN PD 1.2V REF REFO CREF1 CURRENTSOURCE ARRAY CREF2 REFR OUT1P OUT1N OUT2N OUT2N DAC1 SWITCHES 9.6kΩ* DAC2 SWITCHES OUTPUT LATCHES OUTPUT LATCHES MSB DECODE CLK 400Ω* MSB DECODE INPUT LATCHES INPUT LATCHES MAX5186 MAX5189 DVDD *INTERNAL 400Ω AND 9.6kΩ RESISTORS FOR MAX5189 ONLY. 400Ω* 400Ω* 400Ω* DGND D7–D0 Figure 1. Functional Diagram Applications Information Static and Dynamic Performance Definitions Integral Nonlinearity (INL) Integral nonlinearity is the deviation of the values on an actual transfer function from either a best straight-line fit (closest approximation to the actual transfer curve) or a line drawn between the endpoints of the transfer function, once offset and gain errors have been nullified. The MAX5186/MAX5189 use a straight-line endpoint fit for INL (and DNL) and the deviations are measured at every individual step. Differential Nonlinearity (DNL) Differential nonlinearity is the difference between an actual step height and the ideal value of 1LSB. A DNL error specification no more negative than -1LSB guarantees a monotonic transfer function. Offset Error The offset error is the difference between the ideal and the actual offset current/voltage. For the MAX5186/ MAX5189, the offset error is the midpoint value of the transfer function determined by the endpoints of a straight-line endpoint fit. This error affects all codes by the same amount. Gain Error Gain error is the difference between the ideal and the actual output value range. This range represents the output when all digital inputs are set to 1 minus the output when all digital inputs are set to 0. Glitch Impulse A glitch is generated when a DAC switches between two codes. The largest glitch is usually generated around the midscale transition, when the input pattern transitions from 011…111 to 100…000. This occurs due to timing variations between the bits. The glitch impulse is found by integrating the voltage of the glitch at the midscale transition over time. The glitch impulse is usually specified in pV-s. Settling Time The settling time is the amount of time required from the start of a transition until the DAC output settles its new output value to within the converter’s specified accuracy. _______________________________________________________________________________________ 9 MAX5186/MAX5189 Dual, 8-Bit, 40MHz, Current/Voltage, Simultaneous-Output DACs OPTIONAL EXTERNAL BUFFER FOR HEAVIER LOADS REN DGND 1.2V BANDGAP REFERENCE MAX4040 REFO CCOMP* REFR CURRENTSOURCE ARRAY IREF AGND RSET** 9.6kΩ RSET MAX5186 MAX5189 AGND IREF = VREF RSET *COMPENSATION CAPACITOR (CCOMP = 100nF) **9.6kΩ REFERENCE CURRENT-SET RESISTOR INTERNAL TO MAX5189 ONLY. USE EXTERNAL RSET FOR MAX5186. Figure 2. Setting IFS with the Internal 1.2V Reference and the Control Amplifier DVDD 10µF 0.1µF DGND REN 1.2V BANDGAP REFERENCE AVDD EXTERNAL 1.2V REFERENCE REFO CURRENTSOURCE ARRAY REFR IFS MAX6520 AGND RSET AGND 9.6kΩ* MAX5186 MAX5189 *9.6kΩ REFERENCE CURRENT-SET RESISTOR INTERNAL TO MAX5189 ONLY. USE EXTERNAL RSET FOR MAX5186. Figure 3. MAX5186/MAX5189 with External Reference 10 ______________________________________________________________________________________ IFS Dual, 8-Bit, 40MHz, Current/Voltage, Simultaneous-Output DACs MAX5186/MAX5189 Table 1. Power-Down Mode Selection PD (POWER-DOWN SELECT) DACEN (DAC ENABLE) POWER-DOWN MODE 0 0 Standby 0 1 Wake-Up 1 X Shutdown OUTPUT STATE MAX5186 High-Z MAX5189 AGND Last state prior to standby mode MAX5186 High-Z MAX5189 AGND X = Don’t care INPUT SAMPLE N FOR DAC 2 INPUT SAMPLE N FOR DAC 1 tCH INPUT SAMPLE N-1 FOR DAC 1 INPUT SAMPLE INPUT SAMPLE N+1 N+1 FOR DAC 1 FOR DAC 2 INPUT SAMPLE N+2 FOR DAC 2 INPUT SAMPLE N+2 FOR DAC 1 tCLK tCL CLK UPDATES DAC 1 AND PRELOADS SAMPLE N UPDATES DAC 1 DAC 2 TO N - 1 AND DAC 2 TO N FOR DAC 2 PRELOADS SAMPLE N + 1 FOR DAC 2 UPDATES DAC 1 AND DAC 2 TO N + 1 PRELOADS SAMPLE N + 2 FOR DAC 2 UPDATES DAC 1 AND DAC 2 TO N + 2 DAC 1 N-2 N-1 N N+1 N+2 DAC 2 N-2 N-1 N N+1 N+2 tDS1 D0–D7 DAC 1 (N - 1) tDS2 DAC 2 (N) tDH1 DAC 1 (N) tDH2 DAC 2 (N + 1) DAC 1 (N + 1) DAC 2 (N + 2) DAC 1 (N + 2) DAC 2 (N + 3) Figure 4. Timing Diagram Digital Feedthrough Digital feedthrough is the noise generated on a DAC’s output when any digital input transitions. Proper board layout and grounding will significantly reduce this noise, but there will always be some feedthrough caused by the DAC itself. Total Harmonic Distortion Total harmonic distortion (THD) is the ratio of the RMS sum of the input signal’s N harmonics to the fundamental itself. This is expressed as:  (V 2 + V 2 + V 2 ... + ...V 2 )  2 3 4 N THD = 20 × log   V 1   where V1 is the fundamental amplitude, and V2 through VN are the amplitudes of the 2nd- through Nth-order harmonics. Spurious-Free Dynamic Range (SFDR) SFDR is the ratio of RMS amplitude of the carrier frequency (maximum signal component) to the RMS value of the next largest noise or harmonic distortion component. SFDR is usually measured in dBc with respect to the carrier frequency amplitude or in dBFS with respect to the DAC’s full-scale range. Depending on its test condition, SFDR is observed within a predefined window or to Nyquist. In the case of the MAX5186/MAX5189, the SFDR performance is measured for a 0dBFS output amplitude and analyzed within the Nyquist window. ______________________________________________________________________________________ 11 MAX5186/MAX5189 Dual, 8-Bit, 40MHz, Current/Voltage, Simultaneous-Output DACs Differential to Single-Ended Conversion signal is both amplitude and phase modulated, created by summing two independently modulated carriers of identical frequency but different phase (90° phase difference). The MAX4108 low-distortion, high-input bandwidth amplifier may be used to generate a voltage from the array current output of the MAX5186. The differential voltage across OUT1P (or OUT2P) and OUT1N (or OUT2N) is converted into a single-ended voltage by designing an appropriate operational amplifier configuration (Figure 5). In a typical QAM application (Figure 6), the modulation occurs in the digital domain and the MAX5186/ MAX5189’s dual DACs may be used to reconstruct the analog I and Q components. The I/Q reconstruction system is completed by a quadrature modulator that combines the reconstructed I and Q components with in-phase and quadrature carrier frequencies and then sums both outputs to provide the QAM signal. I/Q Reconstruction in a QAM Application The MAX5186/MAX5189’s low distortion supports analog reconstruction of in-phase (I) and quadrature (Q) carrier components typically used in quadrature amplitude modulation (QAM) architectures where I and Q data are interleaved on a common data bus. A QAM 3V + AVDD AVDD 3V 0.1µF 10µF + 0.1µF 10µF 0.1µF 0.1µF AVDD DVDD CREF1 402Ω CREF2 5V 402Ω CLK OUT1P OUTPUT 1 400Ω* D0–D7 MAX5186 MAX5189 REFO 402Ω -5V MAX4108 OUT1N 0.1µF 402Ω 400Ω* REFR 402Ω RSET** 402Ω 5V OUT2P OUTPUT 2 400Ω* 402Ω DGND REN OUT2N AGND -5V MAX4108 402Ω 400Ω* **MAX5186 ONLY *400Ω RESISTORS INTERNAL TO MAX5189 ONLY. Figure 5. Differential to Single-Ended Conversion Using a Low-Distortion Amplifier 12 ______________________________________________________________________________________ Dual, 8-Bit, 40MHz, Current/Voltage, Simultaneous-Output DACs 3V 3V I COMPONENT DAC1 DIGITAL SIGNAL PROCESSOR MAX5186/MAX5189 3V BP FILTER CARRIER FREQUENCY MAX5186 MAX5189 Q COMPONENT DAC2 0° 90° Σ IF BP FILTER MAX2452 QUADRATURE MODULATOR Figure 6. Using the MAX5186/MAX5189 for I/Q Signal Reconstruction Grounding and Power-Supply Decoupling Grounding and power-supply decoupling strongly influence the MAX5186/MAX5189’s performance. Unwanted digital crosstalk may couple through the input, reference, power-supply, and ground connections, which may affect dynamic specifications like signal-to-noise ratio or SFDR. In addition, electromagnetic interference (EMI) can either couple into or be generated by the MAX5186/MAX5189. Therefore, grounding and powersupply decoupling guidelines for high-speed, high-frequency applications should be closely followed. First, a multilayer printed circuit (PC) board with separate ground and power-supply planes is recommended. High-speed signals should be run on controlled impedance lines directly above the ground plane. Since the MAX5186/MAX5189 have separate analog and digital ground buses (AGND and DGND, respectively), the PC board should also have separate analog and digital ground sections with only one point connecting the two. Digital signals should run above the digital ground plane, and analog signals should run above the analog ground plane. Digital signals should be kept far away from the sensitive analog reference and clock input. Both devices have two power-supply inputs: analog VDD (AVDD) and digital VDD (DVDD). Each AVDD input should be decoupled with parallel 10µF and 0.1µF ceramic-chip capacitors. These capacitors should be as close to the pin as possible, and their opposite ends should be as close to the ground plane as possible. The DVDD pins should also have separate 10µF and 0.1µF capacitors adjacent to their respective pins. Try to minimize analog load capacitance for proper operation. For best performance, it is recommended to bypass CREF1 and CREF2 with low-ESR 0.1µF capacitors to AVDD. The power-supply voltages should also be decoupled with large tantalum or electrolytic capacitors at the point they enter the PC board. Ferrite beads with additional decoupling capacitors forming a pi network can also improve performance. Chip Information TRANSISTOR COUNT: 9464 SUBSTRATE CONNECTED TO AGND ______________________________________________________________________________________ 13 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) QSOP.EPS MAX5186/MAX5189 Dual, 8-Bit, 40MHz, Current/Voltage, Simultaneous-Output DACs Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 14 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.