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MAX5532–MAX5535
Dual, Ultra-Low-Power,
12-Bit, Voltage-Output DACs
General Description
The MAX5532–MAX5535 are dual, 12-bit, ultra-lowpower, voltage-output, digital-to-analog converters (DACs)
offering rail-to-rail buffered voltage outputs. The DACs
operate from a 1.8V to 5.5V supply and consume less
than 5μA, making the devices suitable for low-power and
low-voltage applications. A shutdown mode reduces overall
current, including the reference input current, to just 0.18μA.
The MAX5532–MAX5535 use a 3-wire serial interface that
is compatible with SPI™, QSPI™, and MICROWIRE™.
Upon power-up, the MAX5532–MAX5535 outputs are
driven to zero scale, providing additional safety for
applications that drive valves or for other transducers that
need to be off during power-up. The zero-scale outputs
enable glitch-free power-up.
The MAX5532 accepts an external reference input and
provides unity-gain outputs. The MAX5533 contains
a precision internal reference and provides a buffered
external reference output with unity-gain DAC outputs.
The MAX5534 accepts an external reference input and
provides force-sense outputs. The MAX5535 contains
a precision internal reference and provides a buffered
external reference output with force-sense DAC outputs.
The MAX5534/MAX5535 are available in a 4mm x 4mm
x 0.8mm, 12-pin, thin QFN package. The MAX5532/
MAX5533 are available in an 8-pin μMAX® package.
All devices are guaranteed over the extended -40°C to
+85°C temperature range.
For 10-bit compatible devices, refer to the MAX5522–
MAX5525 data sheet. For 8-bit compatible devices, refer
to the MAX5512–MAX5515 data sheet.
Applications
● Portable Battery-Powered Devices
● Instrumentation
● Automatic Trimming and Calibration in Factory
or Field
● Programmable Voltage and Current Sources
● Industrial Process Control and Remote
Industrial Devices
● Remote Data Conversion and Monitoring
● Chemical Sensor Cell Bias for Gas Monitors
● Programmable LCD Bias
Features
● Ultra-Low 5μA Supply Current
● Shutdown Mode Reduces Supply Current to
0.18μA (max)
● Single +1.8V to +5.5V Supply
● Small 4mm x 4mm x 0.8mm Thin QFN Package
● Internal Reference Sources 8mA of Current
(MAX5533/MAX5535)
● Flexible Force-Sense-Configured Rail-to-Rail
Output Buffers
● Fast 16MHz, 3-Wire, SPI-/QSPI-/MICROWIRECompatible Serial Interface
● TTL- and CMOS-Compatible Digital Inputs with
Hysteresis
● Glitch-Free Outputs During Power-Up
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
PKG
CODE
MAX5532EUA
-40°C to +85°C
8 μMAX
U8C-3
MAX5533EUA
-40°C to +85°C
8 μMAX
U8C-3
MAX5534ETC
-40°C to +85°C
12 Thin QFN-EP*
T1244-4
MAX5535ETC
-40°C to +85°C
12 Thin QFN-EP*
T1244-4
*EP = Exposed paddle (internally connected to GND).
Selector Guide
PART
OUTPUTS
REFERENCE
TOP MARK
MAX5532EUA
Unity gain
External
—
MAX5533EUA
Unity gain
Internal
—
MAX5534ETC
Force sense
External
AACM
MAX5535ETC
Force sense
Internal
AACN
Pin Configurations
TOP VIEW
CS 1
SCLK 2
DIN 3
MAX5532
MAX5533
REFIN(MAX5532) 4
REFOUT(MAX5533)
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
μMAX is a registered trademark of Maxim Integrated Products, Inc.
8 OUTA
7 GND
6 VDD
5 OUTB
µMAX
Pin Configurations continued at end of data sheet.
19-3062; Rev 2; 3/20
© 2020 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.
One Analog Way, Wilmington, MA 01887 U.S.A.
|
Tel: 781.329.4700
|
© 2020 Analog Devices, Inc. All rights reserved.
MAX5532–MAX5535
Dual, Ultra-Low-Power,
12-Bit, Voltage-Output DACs
Absolute Maximum Ratings
VDD to GND.............................................................-0.3V to +6V
OUTA, OUTB to GND............................... -0.3V to (VDD + 0.3V)
FBA, FBB to GND..................................... -0.3V to (VDD + 0.3V)
SCLK, DIN, CS to GND............................ -0.3V to (VDD + 0.3V)
REFIN, REFOUT to GND.......................... -0.3V to (VDD + 0.3V)
Continuous Power Dissipation (TA = +70°C)
12-Pin Thin QFN (derate 16.9mW/°C above +70°C)......1349mW
8-Pin μMAX (derate 5.9mW/°C above +70°C).............471mW
Operating Temperature Range............................ -40°C to +85°C
Storage Temperature Range............................. -65°C to +150°C
Junction Temperature.......................................................+150°C
Lead Temperature (soldering, 10s).................................. +300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
Electrical Characteristics
(VDD = +1.8V to +5.5V, OUT_ unloaded, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
STATIC ACCURACY (MAX5532/MAX5534 EXTERNAL REFERENCE)
Resolution
Integral Nonlinearity (Note 1)
Differential Nonlinearity (Note 1)
Offset Error (Note 2)
N
INL
DNL
VOS
12
VDD = 5V, VREF = 4.096V
±4
±8
VDD = 1.8V, VREF = 1.024V
Guaranteed monotonic, VDD = 5V,
VREF = 4.096V
±4
±8
±0.2
±1
±0.2
±1
VDD = 5V, VREF = 4.096V
±1
±20
VDD = 1.8V, VREF = 1.024V
±1
±20
±2
GE
PSRR
VDD = 5V, VREF = 4.096V
±2
±4
±2
±4
1.8V ≤ VDD ≤ 5.5V
mV
µV/°C
VDD = 1.8V, VREF = 1.024V
Gain-Error Temperature
Power-Supply Rejection Ratio
LSB
LSB
Guaranteed monotonic, VDD = 1.8V,
VREF = 1.024V
Offset-Error Temperature Drift
Gain Error (Note 3)
Bits
LSB
±4
ppm/°C
85
dB
STATIC ACCURACY (MAX5533/MAX5535 INTERNAL REFERENCE)
Resolution
Integral Nonlinearity (Note 1)
Differential Nonlinearity (Note 1)
Offset Error (Note 2)
N
INL
DNL
12
VDD = 5V, VREF = 3.9V
VDD = 1.8V, VREF = 1.2V
±8
±4
±8
Guaranteed monotonic, VDD = 5V,
VREF = 3.9V
±0.2
±1
Guaranteed monotonic, VDD = 1.8V,
VREF = 1.2V
±0.2
±1
±1
±20
±1
±20
VOS
VDD = 5V, VREF = 3.9V
VDD = 1.8V, VREF = 1.2V
GE
VDD = 5V, VREF = 3.9V
VDD = 1.8V, VREF = 1.2V
Offset-Error Temperature Drift
Gain Error (Note 3)
www.analog.com
Bits
±4
LSB
LSB
±2
mV
µV/°C
±2
±4
±2
±4
LSB
Analog Devices │ 2
MAX5532–MAX5535
Dual, Ultra-Low-Power,
12-Bit, Voltage-Output DACs
Electrical Characteristics (continued)
(VDD = +1.8V to +5.5V, OUT_ unloaded, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
Gain-Error Temperature
Coefficient
Power-Supply Rejection Ratio
PSRR
1.8V ≤ VDD ≤ 5.5V
TYP
MAX
UNITS
±4
ppm/°C
85
dB
REFERENCE INPUT (MAX5532/MAX5534)
Reference-Input Voltage Range
VREFIN
Reference-Input Impedance
RREFIN
0
Normal operation
VDD
4.1
In shutdown
V
MΩ
2.5
GΩ
REFERENCE OUTPUT (MAX5533/MAX5535)
Initial Accuracy
Output-Voltage Temperature
Coefficient
Line Regulation
Load Regulation
Output Noise Voltage
Short-Circuit Current (Note 6)
VREFOUT
VTEMPCO
No external load, VDD = 1.8V
No external load, VDD = 2.5V
1.197
1.214
1.231
1.913
1.940
1.967
No external load, VDD = 3V
2.391
2.425
2.459
No external load, VDD = 5V
3.828
3.885
3.941
TA = -40°C to +85°C (Note 4)
12
30
ppm/°C
VREFOUT < VDD - 200mV (Note 5)
0 ≤ IREFOUT ≤ 1mA, sourcing, VDD = 1.8V,
VREF = 1.2V
2
200
µV/V
0.3
2
0.3
2
0 ≤ IREFOUT ≤ 8mA, sourcing, VDD = 5V,
VREF = 3.9V
-150µA ≤ IREFOUT ≤ 0, sinking
0.2
0.1Hz to 10Hz, VREF = 3.9V
10Hz to 10kHz, VREF = 3.9V
150
0.1Hz to 10Hz, VREF = 1.2V
50
10Hz to 10kHz, VREF = 1.2V
VDD = 5V
450
VDD = 1.8V
14
600
30
V
µV/µA
µVP-P
mA
Capacitive Load Stability Range
(Note 7)
0 to 10
nF
Thermal Hysteresis
(Note 8)
200
ppm
Reference Power-Up Time
(from Shutdown)
REFOUT unloaded, VDD = 5V
5.4
REFOUT unloaded, VDD = 1.8V
4.4
Long-Term Stability
www.analog.com
200
ms
ppm/
1khrs
Analog Devices │ 3
MAX5532–MAX5535
Dual, Ultra-Low-Power,
12-Bit, Voltage-Output DACs
Electrical Characteristics (continued)
(VDD = +1.8V to +5.5V, OUT_ unloaded, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DAC OUTPUTS (OUTA, OUTB)
Capacitive Driving Capability
CL
Short-Circuit Current (Note 6)
DAC Power-Up Time
Output Power-Up Glitch
1000
VDD = 5V, VOUT set to full scale,
OUT shorted to GND, source current
65
VDD = 5V VOUT set to 0V, OUT shorted to
VDD, sink current
65
VDD = 1.8V, VOUT set to full scale OUT
shorted to GND, source current
14
VDD = 1.8V, VOUT set to 0V, OUT shorted
to VDD, sink current
14
mA
Coming out of shutdown
(MAX5532/MAX5534)
VDD = 5V
VDD = 1.8V
3.8
3
Coming out of standby
(MAX5533/MAX5535)
VDD = 1.8V
to 5.5V
0.4
CL = 100pF
FB_ Input Current
DIGITAL INPUTS (SCLK, DIN, CS)
Input High Voltage
VIH
4.5V ≤ VDD ≤ 5.5V
2.7V < VDD ≤ 3.6V
VIL
2.7V < VDD ≤ 3.6V
Input Leakage Current
IIN
1.8V ≤ VDD ≤ 2.7V
(Note 9)
Input Capacitance
CIN
ms
10
mV
10
pA
2.4
V
2.0
1.8V ≤ VDD ≤ 2.7V
4.5V ≤ VDD ≤ 5.5V
Input Low Voltage
pF
0.7 x VDD
0.8
0.6
0.3 x VDD
±0.05
±0.5
V
µA
10
pF
Positive and negative (Note 10)
10
V/ms
0.1 to 0.9 of full scale to within 0.5 LSB
(Note 10)
660
µs
DYNAMIC PERFORMANCE
Voltage-Output Slew Rate
Voltage-Output Settling Time
SR
0.1Hz to 10Hz
Output Noise Voltage
10Hz to 10kHz
www.analog.com
VDD = 5V
80
VDD = 1.8V
55
VDD = 5V
620
VDD = 1.8V
476
µVP-P
Analog Devices │ 4
MAX5532–MAX5535
Dual, Ultra-Low-Power,
12-Bit, Voltage-Output DACs
Electrical Characteristics (continued)
(VDD = +1.8V to +5.5V, OUT_ unloaded, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
5.5
V
POWER REQUIREMENTS
Supply Voltage Range
VDD
1.8
MAX5533/MAX5535
Supply Current (Note 9)
IDD
MAX5532/MAX5534
Standby Supply Current
IDDSD
MAX5533/MAX5535
(Note 9)
Shutdown Supply Current
IDDPD
(Note 9)
VDD = 5V
7.0
8.0
VDD = 3V
6.4
8.0
VDD = 1.8V
7.0
8.0
VDD = 5V
3.8
5.0
VDD = 3V
3.8
5.0
VDD = 1.8V
4.7
6.0
VDD = 5V
3.3
4.5
VDD = 3V
2.8
4.0
VDD = 1.8V
µA
µA
2.4
3.5
0.05
0.25
µA
TYP
MAX
UNITS
16.7
MHz
Timing Characteristics
(VDD = +4.5V to +5.5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TIMING CHARACTERISTICS (VDD = 4.5V to 5.5V )
Serial Clock Frequency
fSCLK
0
DIN to SCLK Rise Setup Time
tDS
15
ns
DIN to SCLK Rise Hold Time
tDH
0
ns
SCLK Pulse-Width High
tCH
24
ns
SCLK Pulse-Width Low
tCL
24
ns
CS Pulse-Width High
tCSW
100
ns
SCLK Rise to CS Rise Hold Time
tCSH
0
ns
CS Fall to SCLK Rise Setup Time
tCSS
20
ns
SCLK Fall to CS Fall Setup
tCSO
0
ns
CS Rise to SCLK Rise Hold Time
tCS1
20
ns
www.analog.com
Analog Devices │ 5
MAX5532–MAX5535
Dual, Ultra-Low-Power,
12-Bit, Voltage-Output DACs
Timing Characteristics
(VDD = +1.8V to +5.5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
10
MHz
TIMING CHARACTERISTICS (VDD = 1.8V to 5.5V )
Serial Clock Frequency
fSCLK
0
DIN to SCLK Rise Setup Time
tDS
24
ns
DIN to SCLK Rise Hold Time
tDH
0
ns
SCLK Pulse-Width High
tCH
40
ns
SCLK Pulse-Width Low
tCL
40
ns
CS Pulse-Width High
tCSW
150
ns
SCLK Rise to CS Rise Hold Time
tCSH
0
ns
CS Fall to SCLK Rise Setup Time
tCSS
30
ns
SCLK Rise to CS Fall Setup
tCSO
0
ns
CS Rise to SCK Rise Hold Time
tCS1
30
ns
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
1: Linearity is tested within codes 96 to 4080.
2: Offset is tested at code 96.
3: Gain is tested at code 4095. For the MAX5534/MAX5535, FB_ is connected to its respective OUT_.
4: Guaranteed by design. Not production tested.
5: VDD must be a minimum of 1.8V.
6: Outputs can be shorted to VDD or GND indefinitely, provided that package power dissipation is not exceeded.
7: Optimal noise performance is at 2nF load capacitance.
8: Thermal hysteresis is defined as the change in the initial +25°C output voltage after cycling the device from TMAX to TMIN.
9: All digital inputs at VDD or GND.
10: Load = 10kΩ in parallel with 100pF, VDD = 5V, VREF = 4.096V (MAX5532/MAX5534) or VREF = 3.9V (MAX5533/MAX5535).
www.analog.com
Analog Devices │ 6
MAX5532–MAX5535
Dual, Ultra-Low-Power,
12-Bit, Voltage-Output DACs
Typical Operating Characteristics
(VDD = 5.0V, VREF = 4.096V (MAX5532/MAX5534), VREF = 3.9V (MAX5533/MAX5535), TA = +25°C, unless otherwise noted.)
SUPPLY CURRENT vs. TEMPERATURE
(MAX5532/MAX5534)
3.5
3.0
2.5
2.0
1.5
MAX5532 toc02
4.0
9
3.5
3.0
2.5
2.0
1.5
8
7
6
5
4
3
1.0
1.0
0.5
0.5
1
0
0
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
-40
-15
10
35
60
85
SUPPLY VOLTAGE (V)
SUPPLY CURRENT vs. TEMPERATURE
(MAX5533/MAX5535)
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE (MAX5532/MAX5534)
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE (MAX5533/MAX5535)
5
4
3
2
1
-40
-15
10
35
60
10
1
0.1
85
-40
-15
10
35
60
10
1
0.1
85
MAX5532 toc06
100
-40
-15
10
35
60
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
STANDBY SUPPLY CURRENT
vs. TEMPERATURE (MAX5533/MAX5535)
SUPPLY CURRENT
vs. CLOCK FREQUENCY
SUPPLY CURRENT
vs. LOGIC INPUT VOLTAGE
2.5
VREF = 1.9V
2.0
VREF = 1.2V
1.5
100
10
VDD = 1.8V
1.0
VDD = 5V
ALL DIGITAL INPUTS
SHORTED TOGETHER
4.5
SUPPLY CURRENT (mA)
VREF = 2.4V
3.0
VDD = 5V
5.0
MAX5532 toc08
VREF = 3.9V
3.5
CS = LOGIC LOW
CODE = 0
SUPPLY CURRENT (µA)
4.5
4.0
1000
MAX5532 toc07
5.0
4.0
85
MAX5532 toc09
6
100
1000
SHUTDOWN SUPPLY CURRENT (nA)
7
1000
MAX5532 toc05
MAX5532 toc04
8
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.5
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
TEMPERATURE (°C)
9
0
2
SUPPLY VOLTAGE (V)
10
SUPPLY CURRENT (µA)
10
SUPPLY CURRENT (µA)
SUPPLY CURRENT (µA)
4.0
4.5
SHUTDOWN SUPPLY CURRENT (nA)
SUPPLY CURRENT (µA)
4.5
STANDBY SUPPLY CURRENT (µA)
5.0
MAX5532 toc01
5.0
SUPPLY CURRENT vs. SUPPLY VOLTAGE
(MAX5533/MAX5535)
MAX5532 toc03
SUPPLY CURRENT vs. SUPPLY VOLTAGE
(MAX5532/MAX5534)
-40
-15
10
35
TEMPERATURE (°C)
www.analog.com
60
85
1
0.01
0.1
1
10
100 1000 10000 100000
FREQUENCY (kHz)
0
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
LOGIC INPUT VOLTAGE (V)
Analog Devices │ 7
MAX5532–MAX5535
Dual, Ultra-Low-Power,
12-Bit, Voltage-Output DACs
Typical Operating Characteristics (continued)
(VDD = 5.0V, VREF = 4.096V (MAX5532/MAX5534), VREF = 3.9V (MAX5533/MAX5535), TA = +25°C, unless otherwise noted.)
0.15
-2
DNL (LSB)
-1
-1
-2
0.10
0.05
-3
-3
0
-4
-4
-0.05
-5
500 1000 1500 2000 2500 3000 3500 4000 4500
OFFSET VOLTAGE (mV)
0.8
0.10
0.05
0
-0.05
OFFSET VOLTAGE vs. TEMPERATURE
GAIN ERROR CHANGE vs. TEMPERATURE
VDD = 5V
VREF = 3.9V
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.10
0
500 1000 1500 2000 2500 3000 3500 4000 4500
OUT
50mV/div
20µs/div
www.analog.com
DAC OUTPUT VOLTAGE (V)
0
-0.1
-0.2
-0.4
0.6050
DIN
5V/div
0.1
-0.5
-40
-15
10
35
60
DAC OUTPUT LOAD REGULATION
vs. OUTPUT CURRENT
SCLK
5V/div
0.2
-1.0
DIGITAL FEEDTHROUGH RESPONSE
CS
5V/div
0.3
-0.3
TEMPERATURE (°C)
MAX5532 toc16
0.6048
VDD = 5V
VREF = 3.9V
0.4
-0.8
DIGITAL INPUT CODE
ZERO SCALE
0.5
GAIN ERROR CHANGE (LSB)
MAX5532 toc13
1.0
DIGITAL INPUT CODE
VDD = 1.8V
DAC CODE = MIDSCALE
VREF = 1.2V
85
-15
-40
10
35
60
85
TEMPERATURE (°C)
DAC OUTPUT LOAD REGULATION
vs. OUTPUT CURRENT
0.6046
0.6044
0.6042
1.9440
1.9435
DAC OUTPUT VOLTAGE (V)
DNL vs. INPUT CODE
(VDD = VREF = 5V)
0.15
-0.15
500 1000 150 2000 2500 3000 3500 4000 4500
0
DIGITAL INPUT CODE
DIGITAL INPUT CODE
0.20
-0.10
500 1000 1500 2000 2500 3000 3500 4000 4500
0
MAX5532 toc14
0
MAX5532 toc17
-5
DNL (LSB)
0.20
0
INL (LSB)
INL (LSB)
0
MAX5532 toc12
1
MAX5532 toc15
1
DNL vs. INPUT CODE
(VDD = VREF = 1.8V)
0.25
MAX5532 toc11
2
MAX5532 toc10
2
INL vs. INPUT CODE
(VDD = VREF = 5V)
1.9430
MAX5532 toc18
INL vs. INPUT CODE
(VDD = VREF = 1.8V)
VDD = 5.0V
DAC CODE = MIDSCALE
VREF = 3.9V
1.9425
1.9420
1.9415
1.9410
1.9405
0.6040
-1000-800 -600 -400 -200 0 200 400 600 800 1000
DAC OUTPUT CURRENT (µA)
1.9400
-10 -8
-6
-4
-2
0
2
4
6
8
10
DAC OUTPUT CURRENT (mA)
Analog Devices │ 8
MAX5532–MAX5535
Dual, Ultra-Low-Power,
12-Bit, Voltage-Output DACs
Typical Operating Characteristics (continued)
(VDD = 5.0V, VREF = 4.096V (MAX5532/MAX5534), VREF = 3.9V (MAX5533/MAX5535), TA = +25°C, unless otherwise noted.)
2
VDD = 3V
1
VDD = 1.8V
0
0.001
0.010
0.100
3.5
2.5
VOUT
200mV/div
VDD = 3V
2.0
1.5
1.0
0.5
1
10
0
0.001
100
VDD = 1.8V
0.01
OUTPUT LARGE-SIGNAL STEP RESPONSE
(VDD = 5V, VREF = 3.9V)
600
VOUT
500mV/div
MINIMUM SERIES RESISTANCE (Ω)
MAX5532 toc22
1
10
100
100µs/div
OUTPUT MINIMUM SERIES RESISTANCE
vs. LOAD CAPACITANCE
FOR NO OVERSHOOT
500
POWER-UP OUTPUT VOLTAGE GLITCH
MAX5532 toc24
VDD
2V/div
400
300
200
VOUT
10mV/div
100
0
0.0001 0.001
200µs/div
0.01
0.1
1
10
100
20ms/div
CAPACITANCE (µF)
MAJOR CARRY OUTPUT VOLTAGE GLITCH
(CODE 7FFh TO 800h)
(VDD = 5V, VREF = 3.9V)
3.940
REFERENCE OUTPUT VOLTAGE (V)
VOUT
AC-COUPLED
5mV/div
REFERENCE OUTPUT VOLTAGE
vs. REFERENCE OUTPUT CURRENT
REFERENCE OUTPUT VOLTAGE
vs. TEMPERATURE
MAX5532 toc25
3.935
VDD = 5V
3.930
3.925
3.920
3.915
3.910
3.905
3.900
100µs/div
0.1
OUTPUT SINK CURRENT (mA)
OUTPUT SOURCE CURRENT (mA)
www.analog.com
MAX5532 toc20
VDD = 5V
3.0
-40
-15
10
25
TEMPERATURE (°C)
60
85
1.220
1.219
MAX5532 toc27
VDD = 5V
4.0
MAX5532 toc21
REFERENCE OUTPUT VOLTAGE (V)
3
VREF = VDD
CODE = MIDSCALE
4.5
MAX5532 toc26
4
5.0
OUTPUT LARGE-SIGNAL STEP RESPONSE
(VDD = 1.8V, VREF = 1.2V)
MAX5532 toc23
VREF = VDD
CODE = MIDSCALE
DAC OUTPUT VOLTAGE (V)
MAX5532 toc19
5
OUTPUT VOLTAGE (V)
DAC OUTPUT VOLTAGE
vs. OUTPUT SINK CURRENT
DAC OUTPUT VOLTAGE
vs. OUTPUT SOURCE CURRENT
VDD = 1.8V
1.218
1.217
1.216
1.215
1.214
-500
1500
3500
5500
7500
REFERENCE OUTPUT CURRENT (µA)
Analog Devices │ 9
MAX5532–MAX5535
Dual, Ultra-Low-Power,
12-Bit, Voltage-Output DACs
Typical Operating Characteristics (continued)
(VDD = 5.0V, VREF = 4.096V (MAX5532/MAX5534), VREF = 3.9V (MAX5533/MAX5535), TA = +25°C, unless otherwise noted.)
REFERENCE OUTPUT VOLTAGE
vs. REFERENCE OUTPUT CURRENT
3.91
3.90
3.89
3.88
-500
2000
4500 7000
9500 12,000 14,500
1.21748
NO LOAD
1.21746
MAX5532 toc30
MAX5532 toc29
VDD = 5V
1.21750
REFERENCE OUTPUT VOLTAGE (V)
MAX5532 toc28
REFERENCE OUTPUT VOLTAGE (V)
3.92
REFERENCE LINE-TRANSIENT RESPONSE
(VREF = 1.2V)
REFERENCE OUTPUT VOLTAGE
vs. SUPPLY VOLTAGE
2.8V
VDD
1.21744
1.21742
1.8V
1.21740
VREF
500mV/div
1.21738
1.21736
1.21734
1.21732
1.21730
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
REFERENCE OUTPUT CURRENT (µA)
100µs/div
SUPPLY VOLTAGE (V)
REFERENCE LINE-TRANSIENT RESPONSE
(VREF = 3.9V)
MAX5532 toc31
REFERENCE LOAD TRANSIENT
(VDD = 1.8V)
MAX5532 toc32
5.5V
VDD
REFOUT
SOURCE
CURRENT
0.5mA/div
4.5V
VREF
500mV/div
VREF
500mV/div
3.9V
100µs/div
200µs/div
REFERENCE LOAD TRANSIENT
(VDD = 5V)
REFERENCE LOAD TRANSIENT
(VDD = 1.8V)
MAX5532 toc33
200µs/div
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MAX5532 toc34
REFOUT
SOURCE
CURRENT
0.5mA/div
REFOUT
SINK
CURRENT
50µA/div
VREF
500mV/div
3.9V
VREF
500mV/div
200µs/div
Analog Devices │ 10
MAX5532–MAX5535
Dual, Ultra-Low-Power,
12-Bit, Voltage-Output DACs
Typical Operating Characteristics (continued)
(VDD = 5.0V, VREF = 4.096V (MAX5532/MAX5534), VREF = 3.9V (MAX5533/MAX5535), TA = +25°C, unless otherwise noted.)
MAX5532 toc35
VREF
500mV/div
3.9V
POWER-SUPPLY REJECTION RATIO (dB)
80
REFOUT
SINK
CURRENT
100µA/div
60
50
40
30
20
10
0.1
1
10
100
1000
REFERENCE OUTPUT NOISE
(0.1Hz TO 10Hz) (VDD = 1.8V, VREF = 1.2V)
MAX5532 toc38
MAX5532 toc37
POWER-SUPPLY REJECTION RATIO (dB)
0.01
FREQUENCY (kHz)
REFERENCE PSRR
vs. FREQUENCY
VDD = 5V
70
VDD = 1.8V
70
0
200µs/div
80
REFERENCE PSRR
vs. FREQUENCY
MAX5532 toc36
REFERENCE LOAD TRANSIENT
(VDD = 5V)
60
50
40
100µV/div
30
20
10
0
0.01
0.1
1
10
100
1000
FREQUENCY (kHz)
REFERENCE OUTPUT NOISE
(0.1Hz TO 10Hz) (VDD = 5V, VREF = 3.9V)
1s/div
DAC-TO-DAC CROSSTALK
MAX5532 toc39
MAX5532 toc40
OUTA
1V/div
100µV/div
OUTB
AC-COUPLED
10mV/div
OUTB AT FULL SCALE
1s/div
www.analog.com
400µs/div
Analog Devices │ 11
MAX5532–MAX5535
Dual, Ultra-Low-Power,
12-Bit, Voltage-Output DACs
Pin Description
PIN
NAME
FUNCTION
MAX5532
MAX5533
MAX5534
MAX5535
1
1
1
1
CS
2
2
2
2
SCLK
Serial-Interface Clock Input
3
3
3
3
DIN
Serial-Interface Data Input
4
—
4
—
REFIN
—
4
—
4
REFOUT
—
—
5, 11
5, 11
N.C.
No Connection. Leave N.C. inputs unconnected
(floating) or connected to GND.
—
—
6
6
FBB
Channel B Feedback Input
5
5
7
7
OUTB
6
6
8
8
VDD
Power Input. Connect VDD to a 1.8V to 5.5V power
supply. Bypass VDD to GND with a 0.1µF capacitor.
7
7
9
9
GND
Ground
8
8
10
10
OUTA
Channel A Analog Voltage Output
—
—
12
12
FBA
—
—
EP
EP
Exposed Paddle
Active-Low Digital Chip-Select Input
Reference Input
Reference Output
Channel B Analog Voltage Output
Channel A Feedback Input
Exposed Paddle. Connect EP to GND.
Functional Diagrams
VDD
POWERDOWN
CONTROL
SCLK
DIN
CS
CONTROL
LOGIC
AND
SHIFT
REGISTER
REFIN
MAX5532
INPUT
REGISTER
DAC
REGISTER
12-BIT DAC
INPUT
REGISTER
DAC
REGISTER
12-BIT DAC
OUTA
OUTB
GND
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Analog Devices │ 12
MAX5532–MAX5535
Dual, Ultra-Low-Power,
12-Bit, Voltage-Output DACs
Functional Diagrams (continued)
VDD
POWERDOWN
CONTROL
SCLK
DIN
CS
CONTROL
LOGIC
AND
SHIFT
REGISTER
2-BIT
PROGRAMMABLE
REFERENCE
REF
BUF
REFOUT
MAX5533
INPUT
REGISTER
DAC
REGISTER
12-BIT DAC
INPUT
REGISTER
DAC
REGISTER
12-BIT DAC
OUTA
OUTB
GND
VDD
POWERDOWN
CONTROL
SCLK
DIN
CS
CONTROL
LOGIC
AND
SHIFT
REGISTER
REFIN
MAX5534
INPUT
REGISTER
DAC
REGISTER
INPUT
REGISTER
DAC
REGISTER
12-BIT DAC
OUTA
FBA
12-BIT DAC
OUTB
FBB
GND
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Analog Devices │ 13
MAX5532–MAX5535
Dual, Ultra-Low-Power,
12-Bit, Voltage-Output DACs
Functional Diagrams (continued)
VDD
POWERDOWN
CONTROL
SCLK
DIN
CS
CONTROL
LOGIC
AND
SHIFT
REGISTER
2-BIT
PROGRAMMABLE
REFERENCE
INPUT
REGISTER
DAC
REGISTER
INPUT
REGISTER
DAC
REGISTER
REF
BUF
REFOUT
MAX5535
12-BIT DAC
OUTA
FBA
12-BIT DAC
OUTB
FBB
GND
Detailed Description
The MAX5532–MAX5535 dual, 12-bit, ultra-low-power,
voltage-output DACs offer rail-to-rail buffered voltage
outputs. The DACs operate from a 1.8V to 5.5V supply
and require only 5μA (max) supply current. These
devices feature a shutdown mode that reduces overall
current, including the reference input current, to just
0.18μA (max). The MAX5533/MAX5535 include an
internal reference that saves additional board space
and can source up to 8mA, making it functional as a
system reference. The 16MHz, 3-wire serial interface is
compatible with SPI, QSPI, and MICROWIRE protocols.
When VDD is applied, all DAC outputs are driven to
zero scale with virtually no output glitch. The MAX5532/
MAX5533 output buffers are configured in unity gain
and come in μMAX packages. The MAX5534/MAX5535
output buffers are configured in force sense allowing
users to externally set voltage gains on the output
(an output-amplifier inverting input is available). The
MAX5534/MAX5535 come in 4mm x 4mm thin QFN
packages.
Digital Interface
The MAX5532–MAX5535 use a 3-wire serial interface
that is compatible with SPI/QSPI/MICROWIRE protocols
(Figures 1 and 2).
The MAX5532–MAX5535 include a single, 16-bit, input
shift register. Data loads into the shift register through
the serial interface. CS must remain low until all 16
bits are clocked in. The 16 bits consist of 4 control bits
(C3–C0) and 12 data bits (D11–D0) (Table 1). Following
the control bits, the data loads MSB first, D11–D0. The
control bits C3–C0 control the MAX5532–MAX5535, as
outlined in Table 2.
Each DAC channel includes two registers: an input
register and a DAC register. The input register holds input
data. The DAC register contains the data updated to the
DAC output.
The double-buffered register configuration allows any of
the following:
● Loading the input registers without updating the DAC
registers
● Updating the DAC registers from the input registers
● Updating all the input and DAC registers simultaneously
www.analog.com
Analog Devices │ 14
MAX5532–MAX5535
Dual, Ultra-Low-Power,
12-Bit, Voltage-Output DACs
Table 1. Serial Write Data Format
CONTROL
DATA BITS
MSB
C3
LSB
C2
C1
C0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
tCH
SCLK
tCL
tDS
C3
DIN
tCS0
C2
C1
D0
tDH
tCSS
tCSH
CS
tCSW
tCS1
Figure 1. Timing Diagram
SCLK
DIN
1
C3
2
C2
3
C1
CONTROL BITS
CS
4
C0
5
D11
6
D10
7
D9
8
D8
9
D7
10
D6
11
D5
12
D4
13
D3
14
D2
15
D1
16
D0
DATA BITS
COMMAND
EXECUTED
Figure 2. Register Loading Diagram
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Analog Devices │ 15
MAX5532–MAX5535
Dual, Ultra-Low-Power,
12-Bit, Voltage-Output DACs
Table 2. Serial-Interface Programming Commands
CONTROL BITS
INPUT DATA
FUNCTION
C3
C2
C1
C0
D11–D0
0
0
0
0
XXXXXXXXXXXX
0
0
0
1
12-bit data
Load input register A from shift register; DAC registers unchanged; DAC
outputs unchanged.
0
0
1
0
12–bit data
Load input register B from shift register; DAC registers unchanged; DAC
outputs unchanged.
0
0
1
1
—
Command reserved. Do not use.
0
1
0
0
—
Command reserved. Do not use.
0
1
0
1
—
Command reserved. Do not use.
0
1
1
0
—
Command reserved. Do not use.
0
1
1
1
—
Command reserved. Do not use.
1
0
0
0
12-bit data
Load DAC registers A and B from respective input registers; DAC outputs A
and B updated; MAX5533/MAX5535 enter normal operation if in standby or
shutdown; MAX5532/MAX5534 enter normal operation if in shutdown.
12-bit data
Load input register A and DAC register A from shift register; DAC output A
updated; Load DAC register B from input register B; DAC output B updated;
MAX5533/MAX5535 enter normal operation if in standby or shutdown;
MAX5532/MAX5534 enter normal operation if in shutdown.
Load input register B and DAC register B from shift register; DAC output B
updated; Load DAC register A from input register A; DAC output A updated;
MAX5533/MAX5535 enter normal operation if in standby or shutdown;
MAX5532/MAX5534 enter normal operation if in shutdown.
1
0
0
1
No operation; command is ignored.
1
0
1
0
12-bit data
1
0
1
1
—
1
1
0
0
D11, D10,
XXXXXXXXXX
MAX5533/MAX5535 enter standby*, MAX5532/MAX5534 enter shutdown. For
the MAX5533/MAX5535, D11 and D10 configure the internal reference voltage
(Table 3).
1
1
0
1
D11, D10,
XXXXXXXXXX
MAX5532–MAX5535 enter normal operation; DAC outputs reflect existing
contents of DAC registers. For the MAX5533/MAX5535, D11 and D10
configure the internal reference voltage (Table 3).
1
1
1
0
D11, D10,
XXXXXXXXXX
MAX5532–MAX5535 enter shutdown; DAC outputs set to high impedance. For
the MAX5533/MAX5535, D11 and D10 configure the internal reference voltage
(Table 3).
1
1
1
1
12-bit data
Command reserved. Do not use.
Load input registers A and B and DAC registers A and B from shift register;
DAC outputs A and B updated; MAX5533/MAX5535 enter normal operation
if in standby or shutdown; MAX5532/MAX5534 enter normal operation if in
shutdown.
X = Don’t care.
*Standby mode can be entered from normal operation only. It is not possible to enter standby mode from shutdown.
www.analog.com
Analog Devices │ 16
MAX5532–MAX5535
Power Modes
The MAX5532–MAX5535 feature two power modes to
conserve power during idle periods. In normal operation,
the device is fully operational. In shutdown mode, the
device is completely powered down, including the internal
voltage reference in the MAX5533/MAX5535. The
MAX5533/MAX5535 also offer a standby mode in which
all circuitry is powered down except the internal voltage
reference. Standby mode keeps the reference powered
up while the remaining circuitry is shut down, allowing it to
be used as a system reference. It also helps reduce the
wake-up delay by not requiring the reference to power up
when returning to normal operation.
Shutdown Mode
The MAX5532–MAX5535 feature a software-programmable shutdown mode that reduces the supply current
and the reference input current to 0.18μA (max).
Writing an input control word with control bits C[3:0] =
1110 (Table 2) places the device in shutdown mode. In
shutdown, the MAX5532/MAX5534 reference input and
DAC output buffers go high impedance. Placing the
MAX5533/MAX5535 into shutdown turns off the internal
reference and the DAC output buffers go high impedance.
The serial interface still remains active for all devices.
Table 2 shows several commands that bring the
MAX5532–MAX5535 back to normal operation. The
power-up time from shutdown is required before the DAC
outputs are valid.
Note: For the MAX5533/MAX5535, standby mode cannot
be entered directly from shutdown mode. The device must
be brought into normal operation first before entering
standby mode.
Standby Mode (MAX5533/MAX5535 Only)
The MAX5533/MAX5535 feature a software-programmable standby mode that reduces the typical supply
current to 3μA (max). Standby mode powers down all
circuitry except the internal voltage reference. Place
the device in standby mode by writing an input control
word with control bits C[3:0] = 1100 (Table 2). The
internal reference and serial interface remain active
while the DAC output buffers go high impedance.
www.analog.com
Dual, Ultra-Low-Power,
12-Bit, Voltage-Output DACs
For the MAX5533/MAX5535, standby mode cannot be
entered directly from shutdown mode. The device must
be brought into normal operation first before entering
standby mode. To enter standby from shutdown, issue
the command to return to normal operation followed
immediately by the command to go into standby.
Table 2 shows several commands that bring the
MAX5533/MAX5535 back to normal operation. When
transitioning from standby mode to normal operation,
only the DAC power-up time is required before the DAC
outputs are valid.
Reference Input
The MAX5532/MAX5534 accept a reference with a
voltage range extending from 0 to VDD. The output voltage
(VOUT) is represented by a digitally programmable voltage
source as:
VOUT = (VREF x N / 4096) x gain
where N is the numeric value of the DAC’s binary input
code (0 to 4095), VREF is the reference voltage, gain
is the externally set voltage gain for the MAX5534, and
gain is one for the MAX5532.
In shutdown mode, the reference input enters a highimpedance state with an input impedance of 2.5GΩ (typ).
Reference Output
The MAX5533/MAX5535 internal voltage reference is
software configurable to one of four voltages. Upon powerup, the default reference voltage is 1.214V. Configure the
reference voltage using D10 and D11 data bits (Table 3)
when the control bits are as follows C[3:0] = 1100, 1101, or
1110 (Table 2). VDD must be kept at a minimum of 200mV
above VREF for proper operation.
Table 3. Reference Output Voltage
Programming
D11
D10
REFERENCE VOLTAGE (V)
0
0
1.214
0
1
1.940
1
0
2.425
1
1
3.885
Analog Devices │ 17
MAX5532–MAX5535
Dual, Ultra-Low-Power,
12-Bit, Voltage-Output DACs
Applications Information
Programmable Current Source
1-Cell and 2-Cell Circuits
See Figure 3 for an illustration of how to power the
MAX5532–MAX5535 with either one lithium-ion battery
or two alkaline batteries. The low current consumption
of the devices make the MAX5532–MAX5535 ideal for
battery-powered applications.
See the circuit in Figure 4 for an illustration of how to
configure the MAX5534/MAX5535 as a programmable
current source for driving an LED. The MAX5534/
MAX5535 drive a standard NPN transistor to program the
current source. The current source (ILED) is defined in the
equation in Figure 4.
VDD
536kΩ
1.8V ≤ VALKALINE ≤ 3.3V
2.2V ≤ VLITHIUM ≤ 3.3V
+1.25V
REFIN
DAC
VOUT
0.1µF
0.01µF
MAX6006
V
xN
VOUT = REFIN DAC
4096
1/2 MAX5534
(1µA, 1.25V
SHUNT
REFERENCE)
VOUT (0.30mV / LSB)
NDAC IS THE NUMERIC VALUE
OF THE DAC INPUT CODE.
GND
Figure 3. Portable Application Using Two Alkaline Cells or One Lithium Coin Cell
V+
LED
REFIN
DAC
VOUT
ILED
DAC
REFIN
1/2 MAX5534
V
xN
ILED = REFIN DAC
4096 x R
VOUT
2N3904
R
FB
NDAC IS THE NUMERIC VALUE
OF THE DAC INPUT CODE.
Figure 4. Programmable Current Source Driving an LED
www.analog.com
1/2 MAX5534
FB
R
VOUT
VOUT = VBIAS + (IT x R)
TRANSDUCER
VBIAS
IT
V
xN
VBIAS = REFIN DAC
4096
NDAC IS THE NUMERIC VALUE
OF THE DAC INPUT CODE.
Figure 5. Transimpedance Configuration for a Voltage-Biased
Current-Output Transducer
Analog Devices │ 18
MAX5532–MAX5535
Dual, Ultra-Low-Power,
12-Bit, Voltage-Output DACs
Voltage Biasing a
Current-Output Transducer
VOUTA = [(VREFIN x NA) / 4096] x [1 + (R2 / R1)]
See the circuit in Figure 5 for an illustration of how to
configure the MAX5534/MAX5535 to bias a currentoutput transducer. In Figure 5, the output voltage of the
MAX5534/MAX5535 is a function of the voltage drop
across the transducer added to the voltage drop across
the feedback resistor R.
Unipolar Output
Figure 6 shows the MAX5534 in a unipolar output
configuration with unity gain. Table 4 lists the unipolar
output codes.
Bipolar Output
The MAX5534 output can be configured for bipolar
operation as shown in Figure 7. The output voltage is
given by the following equation:
VOUT_ = VREFIN x [(NA - 2048) / 2048]
where NA represents the decimal value of the DAC’s
binary input code. Table 5 shows the digital codes (offset
binary) and the corresponding output voltage for the
circuit in Figure 7.
Configurable Output Gain
The MAX5534/MAX5535 have force-sense outputs, which
provide a connection directly to the inverting terminal
of the output op-amp, yielding the most flexibility. The
advantage of the force-sense output is that specific gains
can be set externally for a given application. The gain
error for the MAX5534/MAX5535 is specified in a unitygain configuration (op-amp output and inverting terminals
connected), and additional gain error results from external
resistor tolerances. Another advantage of the force-sense
DAC is that it allows many useful circuits to be created
with only a few simple external components.
An example of a custom fixed gain using the MAX5534/
MAX5535 force-sense output is shown in Figure 8. In this
example, R1 and R2 set the gain for VOUTA.
where NA represents the numeric value of the DAC input
code.
Self-Biased Two-Electrode
Potentiostat Application
See the circuit in Figure 10 for an illustration of how to use
the MAX5535 to bias a two-electrode potentiostat on the
input of an ADC.
Power Supply and
Bypassing Considerations
Bypass the power supply with a 0.1μF capacitor to GND.
Minimize lengths to reduce lead inductance. If noise
becomes an issue, use shielding and/or ferrite beads to
increase isolation. For the thin QFN package, connect the
exposed pad to ground.
Layout Considerations
Digital and AC transient signals coupling to GND can
create noise at the output. Use proper grounding
techniques, such as a multilayer board with a low-inductance
ground plane. Wire-wrapped boards and sockets are not
recommended. For optimum system performance, use
printed circuit (PC) boards. Good PC board ground layout
minimizes crosstalk between DAC outputs, reference
inputs, and digital inputs. Reduce crosstalk by keeping
analog lines away from digital lines.
Table 4. Unipolar Code Table (Gain = +1)
DAC CONTENTS
MSB
LSB
ANALOG OUTPUT
1111
1111
1111
+VREF (4095/4096)
1000
0000
0001
+VREF (2049/4096)
1000
0000
0000
+VREF (2048/4096) = +VREF / 2
0111
1111
1111
+VREF (2047/4096)
0000
0000
0001
+VREF (1/4096)
0000
0000
0000
0V
Table 5. Bipolar Code Table (Gain = +1)
REFIN
DAC
MAX5534
OUT_
FB_
V
xN
VOUT = REFIN A
4096
NA IS THE DAC INPUT CODE
(0 TO 4095 DECIMAL).
Figure 6. Unipolar Output Circuit
www.analog.com
DAC CONTENTS
MSB
LSB
ANALOG OUTPUT
1111
1111
1111
+VREF (2047/2048)
1000
0000
0001
+VREF (1/2048)
1000
0000
0000
0V
0111
1111
1111
-VREF (1/2048)
0000
0000
0001
-VREF (2047/2048)
0000
0000
0000
-VREF (2048/2048) = -VREF
Analog Devices │ 19
MAX5532–MAX5535
Dual, Ultra-Low-Power,
12-Bit, Voltage-Output DACs
(
10kΩ
10kΩ
1.8V ≤ VDD ≤ 5.5V
REFIN
V+
REFIN
DAC
VOUT
VOUT
DAC
CS1
OUT_
VOUT
H
1/2 MAX5534
MAX5401
SOT-POT
100kΩ
V-
1/2 MAX5534
)
VREFIN x NDAC
255 - NPOT
1+
4096
255
NDAC IS THE NUMERIC VALUE OF THE DAC INPUT CODE.
NPOT IS THE NUMERIC VALUE OF THE POT INPUT CODE.
VOUT =
FB
FB_
W
SCLK
5PPM/°C
RATIOMETRIC
TEMPCO
DIN
CS2
L
Figure 7. Bipolar Output Circuit
Figure 9. Software-Configurable Output Gain
REF
REFIN
DAC
DAC
VOUTA
VOUT1
R2
FBA
MAX5534
DAC
R1
(
VREFIN x NDACA
R2
VOUT1 =
1+
4096
R1
NDACA IS THE NUMERIC VALUE
OF THE DAC A INPUT CODE.
TO ADC
IF
)
RF
FB_
TO ADC
WE
1/2 MAX5535
SENSOR
VOUTB
FBB
CE
VOUT2
VREFIN x NDACB
VOUT2 =
4096
NDACB IS THE NUMERIC VALUE
OF THE DAC B INPUT CODE.
Figure 8. Separate Force-Sense Outputs Create Unity and
Greater-than-Unity DAC Gains Using the Same Reference
www.analog.com
OUT_
BAND
GAP
REFOUT
TO ADC
CL
Figure 10. Self-Biased Two-Electrode Potentiostat Application
Analog Devices │ 20
MAX5532–MAX5535
Dual, Ultra-Low-Power,
12-Bit, Voltage-Output DACs
Pin Configurations (continued)
REF
TOP VIEW
OUTA
DAC
TO ADC
IF
RF
FBA
WE
MAX5535
CE
SCLK
2
DIN
3
OUTB
OUTA
11
10
MAX5534
MAX5535
4
REFIN(MAX5534)
REFOUT(MAX5535)
FBB
BAND
GAP
1
N.C.
12
SENSOR
REF
DAC
CS
FBA
5
6
N.C.
FBB
9
GND
8
VDD
7
OUTB
THIN QFN
REFOUT
TO ADC
CL
Figure 11. Driven Two-Electrode Potentiostat Application
Chip Information
TRANSISTOR COUNT: 10,688
PROCESS: BiCMOS
www.analog.com
Analog Devices │ 21
MAX5532–MAX5535
Dual, Ultra-Low-Power,
12-Bit, Voltage-Output DACs
Package Information
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
www.analog.com
Analog Devices │ 22
MAX5532–MAX5535
Dual, Ultra-Low-Power,
12-Bit, Voltage-Output DACs
Package Information (continued)
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
www.analog.com
Analog Devices │ 23
MAX5532–MAX5535
Dual, Ultra-Low-Power,
12-Bit, Voltage-Output DACs
Package Information (continued)
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
www.analog.com
Analog Devices │ 24
MAX5532–MAX5535
Dual, Ultra-Low-Power,
12-Bit, Voltage-Output DACs
Package Information (continued)
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
α
α
www.analog.com
Analog Devices │ 25
MAX5532–MAX5535
Dual, Ultra-Low-Power,
12-Bit, Voltage-Output DACs
Revision History
REVISION
NUMBER
REVISION
DATE
PAGES
CHANGED
1
1/07
—
2
3/20
Changed DAC power-up time unit from µs to ms in the Electrical Characteristics table
DESCRIPTION
1, 6, 14, 21, 24
4
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is
assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that
may result from its use.Specifications subject to change without notice. No license is granted by implicationor
otherwise under any patent or patent rights of Analog Devices. Trademarks andregistered trademarks are the
property of their respective owners.
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Analog Devices │ 26
