EVALUATION KIT AVAILABLE
MAX5854
Dual, 10-Bit, 165Msps, Current-Output DAC
General Description
Features
The MAX5854 dual, 10-bit, 165Msps digital-to-analog
converter (DAC) provides superior dynamic performance
in wideband communication systems. The device integrates two 10-bit DAC cores, and a 1.24V reference. The
MAX5854 supports single-ended and differential modes
of operation. The dynamic performance is maintained
over the entire 2.7V to 3.6V power-supply operating
range. The analog outputs support a -1.0V to +1.25V
compliance voltage.
●● 2.7V to 3.6V Single Supply
The MAX5854 can operate in interleaved data mode to
reduce the I/O pin count. This allows the converter to be
updated on a single, 10-bit bus.
●● Programmable Channel Gain Matching
19-3197; Rev 0; 2/04
●● Interleaved Data Mode
●● Single-Ended and Differential Clock Input Modes
●● Miniature 40-Pin TQFN Package, 6mm x 6mm
●● EV Kit Available—MAX5854 EV Kit
Ordering Information
PART
MAX5854ETL
TEMP RANGE
PIN-PACKAGE
-40°C to +85°C
40 Thin QFN-EP*
*EP = Exposed paddle.
REFO
AVDD
REFR
OUTNB
OUTPB
AGND
OUTPA
OUTNA
TOP VIEW
AVDD
Pin Configuration
40 39 38 37 36 35 34 33 32 31
30 CVDD
DA9/PD
1
DA8/DACEN
2
DA7/IDE
3
28 CLK
DA6/REN
4
27 CVDD
DA5/G3
5
DA4/G2
6
DA3/G1
7
24 DCE
DA2/G0
8
23 CW
DA1
9
22 DB0
DA0
10
21 DB1
EP
29 CGND
26 CLKXN
MAX5854
25 CLKXP
TQFN
DB2
DB3
DB4
DGND
DB5
11 12 13 14 15 16 17 18 19 20
DVDD
●● Communications
SatCom, LMDS, MMDS, HFC, DSL, WLAN,
Point-to-Point Microwave Links
●● Wireless Base Stations
●● Quadrature Modulation
●● Direct Digital Synthesis (DDS)
●● Instrumentation/ATE
●● Single-Resistor Gain Control
DB6
Applications
●● Integrated 1.24V Low-Noise Bandgap Reference
DB7
Pin-compatible, lower speed, and lower resolution versions are also available. Refer to the MAX5853 (10bit, 80Msps), the MAX5852 (8-bit, 165Msps), and the
MAX5851 (8-bit, 80Msps) data sheets for more information. See Table 4 at the end of the data sheet.
●● Superior Dynamic Performance
• 73dBc SFDR at fOUT = 40MHz
• UMTS ACLR = 65.5dB at fOUT = 30.7MHz
AGND
The MAX5854 is packaged in a 40-pin TQFN with
exposed paddle (EP) and is specified for the extended
(-40°C to +85°C) temperature range.
●● Full Output Swing and Dynamic Performance at
2.7V Supply
DB9
The MAX5854 features full-scale current outputs of 2mA
to 20mA and operates from a 2.7V to 3.6V single supply.
The DAC supports three modes of power-control operation: normal, low-power standby, and complete powerdown. In power-down mode, the operating current is
reduced to 1μA.
●● Low Power
• 190mW with IFS = 20mA at fCLK = 165MHz
DB8
The MAX5854 features digital control of channel gain
matching to within ±0.4dB in sixteen 0.05dB steps.
Channel matching improves sideband suppression in
analog quadrature modulation applications. The on-chip
1.24V bandgap reference includes a control amplifier that
allows external full-scale adjustments of both channels
through a single resistor. The internal reference can be
disabled and an external reference can be applied for
high-accuracy applications.
●● 10-Bit, 165Msps Dual DAC
MAX5854
Dual, 10-Bit, 165Msps, Current-Output DAC
Absolute Maximum Ratings
AGND to DGND, DGND to CGND,
AGND to CGND................................................-0.3V to +0.3V
Maximum Current into Any Pin
(excluding power supplies)............................................±50mA
Continuous Power Dissipation (TA = +70°C)
40-Pin TQFN-EP (derate 23.3mW/°C
above +70°C)...............................................................1.860W
Operating Temperature Range............................ -40°C to +85°C
Storage Temperature Range............................. -65°C to +150°C
Junction Temperature.......................................................+150°C
AVDD, DVDD, CVDD to AGND, DGND, CGND........-0.3V to +4V
DA9–DA0, DB9–DB0, CW, DCE to AGND,
DGND, CGND......................................................-0.3V to +4V
CLKXN, CLKXP to CGND........................................-0.3V to +4V
OUTP_, OUTN_ to AGND..................... -1.25V to (AVDD + 0.3V)
CLK to DGND..........................................-0.3V to (DVDD + 0.3V)
REFR, REFO to AGND........................... -0.3V to (AVDD + 0.3V)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Electrical Characteristics
(AVDD = DVDD = CVDD = 3V, AGND = DGND = CGND = 0, fDAC = 165Msps, differential clock, external reference, VREF = 1.2V,
IFS = 20mA, output amplitude = 0dB FS, differential output, TA = TMIN to TMAX, unless otherwise noted. TA ≥ +25°C guaranteed by
production test. TA < +25°C guaranteed by design and characterization. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
STATIC PERFORMANCE
Resolution
N
10
Bits
Integral Nonlinearity
INL
RL = 0
-1.0
±0.25
+1.0
LSB
Guaranteed monotonic, RL = 0
-0.5
±0.2
+0.5
LSB
-0.5
±0.1
+0.5
LSB
Internal reference (Note1)
-11.0
±1.5
+6.8
External reference
-6.25
±0.7
+4.10
Differential Nonlinearity
DNL
Offset Error
VOS
Gain Error (See Also Gain Error
Definition Section)
GE
Gain-Error Temperature Drift
Internal reference
±150
External reference
±100
%FSR
ppm/°C
DYNAMIC PERFORMANCE
Spurious-Free Dynamic Range
to Nyquist
Spurious-Free Dynamic Range
Within a Window
Multitone Power Ratio to Nyquist
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SFDR
SFDR
MTPR
fOUT = 10MHz
69.4
78
fCLK = 165MHz,
AOUT = -1dBFS
fOUT = 20MHz
77
fOUT = 40MHz
73
fCLK = 100MHz,
AOUT = -1dBFS
fOUT = 10MHz
77
fOUT = 20MHz
77
fOUT = 30MHz
76
fCLK = 25MHz,
AOUT = -1dBFS
fOUT = 1MHz
79
fCLK = 165MHz, fOUT = 10MHz,
AOUT = -1dBFS, span = 10MHz
83
fCLK = 100MHz, fOUT = 5MHz,
AOUT = -1dBFS, span = 4MHz
84
fCLK = 25MHz, fOUT = 1MHz,
AOUT = -1dBFS, span = 2MHz
82
8 tones at 400kHz spacing, fCLK = 78MHz,
fOUT = 15MHz to 18.2MHz
74
dBc
dBc
dBc
Maxim Integrated │ 2
MAX5854
Dual, 10-Bit, 165Msps, Current-Output DAC
Electrical Characteristics (continued)
(AVDD = DVDD = CVDD = 3V, AGND = DGND = CGND = 0, fDAC = 165Msps, differential clock, external reference, VREF = 1.2V,
IFS = 20mA, output amplitude = 0dB FS, differential output, TA = TMIN to TMAX, unless otherwise noted. TA ≥ +25°C guaranteed by
production test. TA < +25°C guaranteed by design and characterization. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
Multitone Spurious-Free
Dynamic Range Within a
Window
Adjacent Channel Power Ratio
with UMTS
CONDITIONS
8 tones at 2.1MHz spacing,
fCLK = 165MHz, fOUT = 28.3MHz to 45.2MHz,
span = 50MHz
ACLR
fOUT = 30.72MHz, RBW = 30kHz,
fCLK = 122.88MHz
fCLK = 165MHz,
AOUT = -1dBFS
Total Harmonic Distortion to
Nyquist (2nd- Through 8th-Order
Harmonics Included)
THD
fCLK = 100MHz,
AOUT = -1dBFS
fCLK = 25MHz,
AOUT = -1dBFS
Output Channel-to-Channel
Isolation
fOUT = 10MHz
Channel-to-Channel Gain
Mismatch
Channel-to-Channel Phase
Mismatch
Signal-to-Noise Ratio to Nyquist
Maximum DAC Conversion Rate
MIN
SNR
fDAC
tS
MAX
UNITS
70
dBc
65.5
dB
fOUT = 10MHz
-76
fOUT = 20MHz
-74
fOUT = 40MHz
-71
fOUT = 10MHz
-75
fOUT = 20MHz
-74
fOUT = 30MHz
-73
fOUT = 1MHz
-76
dBc
90
dB
fOUT = 10MHz, G[3:0] = 1000
0.025
dB
fOUT = 10MHz
0.05
Degrees
fCLK = 165MHz, fOUT = 10MHz, IFS = 20mA
60.5
fCLK = 165MHz, fOUT = 10MHz, IFS = 5mA
61
fCLK = 65MHz, fOUT = 10MHz, IFS = 20mA
62
fCLK = 65MHz, fOUT = 10MHz, IFS = 5mA
62
Interleaved mode disabled, IDE = 0
165
200
Interleaved mode enabled, IDE = 1
82.5
100
Glitch Impulse
Output Settling Time
TYP
dB
Msps
5
pV-s
To ±0.1% error band (Note 3)
12
ns
Output Rise Time
10% to 90% (Note 3)
2.2
ns
Output Fall Time
90% to 10% (Note 3)
2.2
ns
ANALOG OUTPUT
Full-Scale Output Current
Range
IFS
Output Voltage Compliance
Range
Output Leakage Current
Shutdown or standby mode
2
20
mA
-1.00
+1.25
V
-5
+5
µA
1.32
V
REFERENCE
Internal-Reference Output
Voltage
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VREFO
REN = 0
1.13
1.24
Maxim Integrated │ 3
MAX5854
Dual, 10-Bit, 165Msps, Current-Output DAC
Electrical Characteristics (continued)
(AVDD = DVDD = CVDD = 3V, AGND = DGND = CGND = 0, fDAC = 165Msps, differential clock, external reference, VREF = 1.2V,
IFS = 20mA, output amplitude = 0dB FS, differential output, TA = TMIN to TMAX, unless otherwise noted. TA ≥ +25°C guaranteed by
production test. TA < +25°C guaranteed by design and characterization. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
Internal-Reference Supply
Rejection
CONDITIONS
MIN
MAX
UNITS
0.5
mV/V
TCVREFO REN = 0
±50
ppm/°C
Internal-Reference Output Drive
Capability
REN = 0
50
µA
External-Reference Input
Voltage Range
REN = 1
Internal-Reference OutputVoltage Temperature Drift
Current Gain
AVDD varied from 2.7V to 3.6V
TYP
0.10
IFS/IREF
1.2
1.32
32
LOGIC INPUTS (DA9–DA0, DB9–DB0, CW)
mA/mA
0.65 x
DVDD
Digital Input-Voltage High
VIH
Digital Input-Voltage Low
VIL
Digital Input Current
IIN
Digital Input Capacitance
CIN
Digital Input-Voltage High
VIH
DCE = 1
Digital Input-Voltage Low
VIL
DCE = 1
Digital Input Current
IIN
DCE = 1
Digital Input Capacitance
CIN
DCE = 1
Digital Output-Voltage High
VOH
DCE = 0, ISOURCE = 0.5mA, Figure 1
Digital Output-Voltage Low
VOL
DCE = 0, ISINK = 0.5mA, Figure 1
V
-1
0.3 x
DVDD
V
+1
µA
3
SINGLE-ENDED CLOCK INPUT/OUTPUT AND DCE INPUT (CLK, DCE)
V
pF
0.65 x
CVDD
V
-1
0.3 x
CVDD
V
+1
µA
3
pF
0.9 x
CVDD
V
0.1 x
CVDD
V
DIFFERENTIAL CLOCK INPUTS (CLKXP/CLKXN)
Differential Clock Input Internal
Bias
CVDD/2
Differential Clock Input Swing
V
0.5
Clock Input Impedance
Measured single ended
V
5
kΩ
POWER REQUIREMENTS
Analog Power-Supply Voltage
AVDD
2.7
3
3.6
V
Digital Power-Supply Voltage
DVDD
2.7
3
3.6
V
Clock Power-Supply Voltage
CVDD
2.7
3
3.6
V
www.maximintegrated.com
Maxim Integrated │ 4
MAX5854
Dual, 10-Bit, 165Msps, Current-Output DAC
Electrical Characteristics (continued)
(AVDD = DVDD = CVDD = 3V, AGND = DGND = CGND = 0, fDAC = 165Msps, differential clock, external reference, VREF = 1.2V,
IFS = 20mA, output amplitude = 0dB FS, differential output, TA = TMIN to TMAX, unless otherwise noted. TA ≥ +25°C guaranteed by
production test. TA < +25°C guaranteed by design and characterization. Typical values are at TA = +25°C.)
PARAMETER
Analog Supply Current
SYMBOL
IAVDD
CONDITIONS
MIN
TYP
MAX
IFS = 20mA (Note 2), single-ended clock mode
43.2
46
IFS = 20mA (Note 2), differential clock mode
43.2
IFS = 2mA (Note 2), single-ended clock mode
5
IFS = 2mA (Note 2), differential clock mode
Digital Supply Current
IDVDD
Clock Supply Current
ICVDD
Total Standby Current
Total Shutdown Current
6.2
IFS = 20mA (Note 2), differential clock mode
6.2
Single-ended clock mode (DCE = 1) (Note 2)
13.7
Total Power Dissipation
PTOT
7.5
16.5
24
Differential clock mode (DCE = 0) (Note 2)
3.1
IAVDD + IDVDD + ICVDD
Single-ended clock
mode (DCE = 1)
mA
5
IFS = 20mA (Note 2), single-ended clock mode
ISTANDBY IAVDD + IDVDD+ ICVDD
ISHDN
UNITS
3.7
1
IFS = 20mA (Note 2)
190
IFS = 2mA (Note 2)
mA
mA
mA
µA
210
75
Differential clock mode IFS = 20mA (Note 2)
(DCE = 0)
IFS = 2mA (Note 2)
220
Standby
9.3
mW
106
Shutdown
11.1
0.003
TIMING CHARACTERISTICS (Figure 5, Figure 6)
Propagation Delay
1
Single-ended clock mode (DCE = 1) (Note 4)
1.2
Differential clock mode (DCE = 0) (Note 4)
2.7
Clock
cycles
DAC Data to CLK Rise/Fall
Setup Time
tDCS
DAC Data to CLK Rise/Fall Hold
Time
tDCH
Control Word to CW Rise Setup
Time
tCS
2.5
ns
Control Word to CW Rise Hold
Time
tCW
2.5
ns
CW High Time
tCWH
5
ns
CW Low Time
tCWL
5
ns
DACEN = 1 to VOUT Stable
Time (Coming Out of Standby)
tSTB
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Single-ended clock mode (DCE = 1) (Note 4)
0.8
Differential clock mode (DCE = 0) (Note 4)
-0.5
ns
ns
3
µs
Maxim Integrated │ 5
MAX5854
Dual, 10-Bit, 165Msps, Current-Output DAC
Electrical Characteristics (continued)
(AVDD = DVDD = CVDD = 3V, AGND = DGND = CGND = 0, fDAC = 165Msps, differential clock, external reference, VREF = 1.2V,
IFS = 20mA, output amplitude = 0dB FS, differential output, TA = TMIN to TMAX, unless otherwise noted. TA ≥ +25°C guaranteed by
production test. TA < +25°C guaranteed by design and characterization. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
PD = 0 to VOUT Stable Time
(Coming Out of Power-Down)
tSHDN
Maximum Clock Frequency at
CLKXP/CLKXN Input
fCLK
CONDITIONS
MIN
165
TYP
MAX
UNITS
500
µs
200
MHz
Clock High Time
tCXH
CLKXP or CLKXN input
1.5
ns
Clock Low Time
tCXL
CLKXP or CLKXN input
1.5
ns
CLKXP Rise to CLK Output Rise
Delay
tCDH
DCE = 0
2.7
ns
CLKXP Fall to CLK Output Fall
Delay
tCDL
DCE = 0
2.7
ns
Note
Note
Note
Note
1: Including the internal reference voltage tolerance and reference amplifier offset.
2: fDAC = 165Msps, fOUT = 10MHz.
3: Measured single-ended with 50Ω load and complementary output connected to AGND.
4: Guaranteed by design, not production tested.
0.5mA
TO OUTPUT
PIN
1.6V
5pF
0.5mA
Figure 1. Load Test Circuit for CLK Outputs
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Maxim Integrated │ 6
MAX5854
Dual, 10-Bit, 165Msps, Current-Output DAC
Typical Operating Characteristics
(AVDD = DVDD = CVDD = 3V, AGND = DGND = CGND = 0, external reference, differential clock, IFS = 20mA, differential output,
TA = +25°C, unless otherwise noted.)
35
30
10 20 30 40 50 60 70 80 90 100
-6dBFS
-12dBFS
0
10 15 20 25 30 35 40 45 50
5
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY (fCLK = 25MHz)
MAX5854 toc03
90
85
MAX5854 toc02
80
75
70
65
60
55
50
45
40
30
0dBFS
80
75
70
65
60
55
50
45
40
35
30
-12dBFS
3
1
-6dBFS
5
7
9
11
13
fOUT (MHz)
fOUT (MHz)
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY (fCLK = 200MHz)
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY (fCLK = 165MHz)
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY (fCLK = 165MHz)
40
35
30
10 20 30 40 50 60 70 80 90 100
0
fOUT (MHz)
20
30
40
50
60
70
79.0
78.0
77.5
77.0
76.5
0
0
10
20
-20
-30
-70
75.0
60
85
60
70
80
90
fOUT2
fOUT1
2fOUT1 - fOUT2
2fOUT2 - fOUT1
-60
-90
35
50
-50
-100
10
40
-40
75.5
TEMPERATURE (°C)
30
fOUT1 = 4.8541MHz
fOUT2 = 5.0555MHz
-10
-80
76.0
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AVDD = DVDD = CVDD = 3V
TWO-TONE INTERMODULATION DISTORTION
(fCLK = 165MHz, 1MHz WINDOW)
AMPLITUDE (dB)
78.5
-15
AVDD = DVDD = CVDD = 2.7V
fOUT (MHz)
SFDR vs. TEMPERATURE (fCLK = 165MHz,
fOUT = 10MHz, AOUT = 0dBFS)
-40
65
60
55
50
45
40
35
30
90
80
AVDD = DVDD = CVDD = 3.6V
75
70
fOUT (MHz)
79.5
SFDR (dBc)
10
MAX5854 toc07
80.0
MAX5854 toc05
IOUT = 10mA
AVDD = DVDD = CVDD = 3.3V
80
MAX5854 toc08
0
IOUT = 5mA
75
70
65
60
55
50
45
90
85
SFDR (dBc)
-6dBFS
IOUT = 20mA
80
SFDR (dBc)
0dBFS
-12dBFS
90
85
MAX5854 toc06
fOUT (MHz)
80
75
70
65
60
55
50
45
40
35
30
0dBFS
85
35
0
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY (fCLK = 100MHz)
SFDR (dBc)
-6dBFS
-12dBFS
90
SFDR (dBc)
80
75
70
65
60
55
50
45
40
90
85
SFDR (dBc)
0dBFS
MAX5854 toc04
SFDR (dBc)
85
MAX5854 toc04
90
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY (fCLK = 200MHz)
4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5
fOUT (MHz)
Maxim Integrated │ 7
MAX5854
Dual, 10-Bit, 165Msps, Current-Output DAC
Typical Operating Characteristics (continued)
(AVDD = DVDD = CVDD = 3V, AGND = DGND = CGND = 0, external reference, differential clock, IFS = 20mA, differential output,
TA = +25°C, unless otherwise noted.)
fT2
-50
fT7
fT1
-60
fT8
-70
0
-30
-40
-50
-60
-70
-20
-30
-40
-50
-60
-70
-80
-90
-90
-90
-100
-100
-100
9.7
14.7
19.7 24.7 29.7 34.7
fOUT (MHz)
0
-20
-80
4
6
7
8
9
10 11 12 13
SINGLE-TONE SFDR
(fCLK = 25MHz, 2MHz WINDOW)
fOUT = 1.0152MHz
AOUT = -1dBFS
-50
-60
-70
0
4.5 5.0 5.5
fOUT (MHz)
6.0
6.5
7.0
-30
-40
-50
-60
-70
-80
-90
-90
0.4
0.6
0.9 1.1 1.4
fOUT (MHz)
1.6
-100
1.9
1.0
-20
0.4
0.3
0.2
-40
0.1
INL (LSB)
-30
-50
-60
-0.1
-0.2
-80
-0.3
-90
-0.4
-100
-0.5
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8.2MHz/div
fOUT (MHz)
82.5
21.0
0
-70
0.5
17.0
MAX5854 toc15
0.5
MAX5854 toc14
0
-10
13.0
9.0
fOUT (MHz)
5.0
INTEGRAL NONLINEARITY
vs. DIGITAL INPUT CODE
SINGLE-TONE FFT PLOT (fCLK = 165MHz,
fOUT = 10MHz, AOUT = 0dBFS, NYQUIST WINDOW)
OUTPUT POWER (dBm)
4.0
fOUT = 11.0333MHz
AOUT = -1dBFS
-20
-80
0.1
3.5
3.0
SINGLE-TONE SFDR
(fCLK = 78MHz, 20MHz WINDOW)
-10
AMPLITUDE (dB)
-40
-100
14
fOUT (MHz)
-30
AMPLITUDE (dB)
5
fT5 = 24.035MHz
fT6 = 25.087MHz
fT7 = 26.741MHz
fT8 = 27.869MHz
fT1 = 17.493MHz
fT2 = 18.997MHz
fT3 = 20.200MHz
fT4 = 21.253MHz
-10
39.7
fOUT1 = 5.0533MHz
AOUT = -1dBFS
-10
-80
4.7
MAX5854 toc11
-20
SINGLE-TONE SFDR
(fCLK = 100MHz, 4MHz WINDOW)
MAX5854 toc13
-40
fOUT1 = 9.1040MHz
AOUT = -1dBFS
AMPLITUDE (dB)
fT6
fT3
-30
0
-10
MAX5854 toc12
AMPLITUDE (dB)
-20
fT5
AMPLITUDE (dB)
fT4
-10
MAX5854 toc09
0
SINGLE-TONE SFDR
(fCLK = 165MHz, 10MHz WINDOW)
MAX5854 toc10
8-TONE SFDR PLOT
(fCLK = 165MHz, 35MHz WINDOW)
0
150
300
450
600
750
900 1050
DIGITAL INPUT CODE
Maxim Integrated │ 8
MAX5854
Dual, 10-Bit, 165Msps, Current-Output DAC
Typical Operating Characteristics (continued)
(AVDD = DVDD = CVDD = 3V, AGND = DGND = CGND = 0, external reference, differential clock, IFS = 20mA, differential output,
TA = +25°C, unless otherwise noted.)
0.1
0
-0.1
-0.2
-0.3
210
200
190
180
SINGLE-ENDED
CLOCK DRIVE
170
0
150
300
450
600
750
150
900 1050
240
220
200
SINGLE-ENDED
CLOCK DRIVE
180
45
20
70
95
120
145
160
170
2.70
2.85
1.22230
1.22200
1.22190
1.22180
1.22170
3.15
3.30
3.45
3.60
DYNAMIC RESPONSE RISE TIME
MAX5854 toc21
MAX5854 toc20
1.22230
REFERENCE VOLTAGE vs. TEMPERATURE
1.25
REFERENCE VOLTAGE (V)
MAX5854 toc19
1.22230
3.00
SUPPLY VOLTAGES (V)
fCLK (MHz)
REFERENCE VOLTAGE vs. SUPPLY VOLTAGES
(fCLK = 165MHz, fOUT = 10MHz)
1.24
100mV/div
1.23
1.22
1.21
1.20
1.22160
3.00
3.15
3.30
3.45
1.19
3.60
-15
-40
SUPPLY VOLTAGES (V)
DYNAMIC RESPONSE FALL TIME
MAX5854 toc22
-20
-30
100mV/div
10ns/div
www.maximintegrated.com
10
35
60
85
10ns/div
TEMPERATURE (°C)
ACLR PLOT
(fCLK = 122.88MHz, fOUT = 30.72MHz)
ACLR = 65.5dB
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
23.38
90
85
1.468MHz/div
fOUT (MHz)
38.06
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY (fCLK = 165MHz)
0dBFS
80
75
70
65
60
55
50
45
40
35
30
MAX5854 toc24
2.85
SFDR (dBc)
2.70
AMPLITUDE (dB)
REFEENCE VOLTAGE (V)
DIFFERENTIAL
CLOCK DRIVE
260
160
DIGITAL INPUT CODE
1.22150
280
160
-0.4
MAX5854 toc18
DIFFERENTIAL
CLOCK DRIVE
MAX5854 toc23
DNL (LSB)
0.2
220
300
POWER DISSIPATION (mW)
0.3
230
MAX5854 toc17
MAX5854 toc16
0.4
POWER DISSIPATION (mV)
0.5
-0.5
POWER DISSIPATION vs. SUPPLY VOLTAGES
(fCLK = 165MHz, fOUT = 10MHz)
POWER DISSIPATION vs. CLOCK FREQUENCY
(fOUT = 10MHz, AOUT = 0dBFS)
DIFFERENTIAL NONLINEARITY
vs. DIGITAL INPUT CODE
-6dBFS
-12dBFS
SINGLE-ENDED
CLOCK DRIVE
0
10
20
30
40
50
60
70
80
90
fOUT (MHz)
Maxim Integrated │ 9
MAX5854
Dual, 10-Bit, 165Msps, Current-Output DAC
Pin Description
PIN
NAME
1
DA9/PD
Channel A Input Data Bit 9 (MSB)/Power-Down
FUNCTION
2
DA8/DACEN
Channel A Input Data Bit 8/DAC Enable Control
3
DA7/IDE
Channel A Input Data Bit 7/Interleaved Data Enable
4
DA6/REN
Channel A Input Data Bit 6/Reference Enable. Setting REN = 0 enables the internal reference. Setting
REN = 1 disables the internal reference.
5
DA5/G3
Channel A Input Data Bit 5/Channel A Gain Adjustment Bit 3
6
DA4/G2
Channel A Input Data Bit 4/Channel A Gain Adjustment Bit 2
7
DA3/G1
Channel A Input Data Bit 3/Channel A Gain Adjustment Bit 1
8
DA2/G0
9
DA1
Channel A Input Data Bit 2/Channel A Gain Adjustment Bit 0
Channel A Input Data Bit 1
10
DA0
Channel A Input Data Bit 0 (LSB)
11
DB9
Channel B Input Data Bit 9 (MSB)
12
DB8
Channel B Input Data Bit 8
13
DB7
Channel B Input Data Bit 7
14
DB6
Channel B Input Data Bit 6
Channel B Input Data Bit 5
15
DB5
16
DVDD
Digital Power Input. See the Power Supplies, Bypassing, Decoupling, and Layout section for more details.
17
DGND
Digital Ground
18
DB4
Channel B Input Data Bit 4
19
DB3
Channel B Input Data Bit 3
20
DB2
Channel B Input Data Bit 2
21
DB1
Channel B Input Data Bit 1
22
DB0
Channel B Input Data Bit 0 (LSB)
23
CW
Active-Low Control Word Write Pulse. The control word is latched on the rising edge of CW.
24
DCE
Active-Low Differential Clock Enable Input. Drive DCE low to enable the differential clock inputs
CLKXP and CLKXN. Drive DCE high to disable the differential clock inputs and enable the singleended CLK input.
25
CLKXP
Positive Differential Clock Input. With DCE = 0, CLKXP and CLKXN are enabled. With DCE = 1, CLKXP
and CLKXN are disabled. Connect CLKXP to CGND when the differential clock is disabled.
26
CLKXN
Negative Differential Clock Input. With DCE = 0, CLKXP and CLKXN are enabled. With DCE = 1, CLKXP
and CLKXN are disabled. Connect CLKXN to CVDD when the differential clock is disabled.
27, 30
CVDD
Clock Power Input. See the Power Supplies, Bypassing, Decoupling, and Layout section for more details.
28
CLK
Single-Ended Clock Input/Output. With the differential clock disabled (DCE = 1), CLK becomes a singleended conversion clock input. With the differential clock enabled (DCE = 0), CLK is a single-ended output
that mirrors the differential clock inputs CLKXP and CLKXN. See the Clock Modes section for more
information on CLK.
29
CGND
Clock Ground
31
REFO
Reference Input/Output. REFO serves as a reference input when the internal reference is disabled. If
the internal 1.24V reference is enabled, REFO serves as an output for the internal reference. When the
internal reference is enabled, bypass REFO to AGND with a 0.1µF capacitor
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Maxim Integrated │ 10
MAX5854
Dual, 10-Bit, 165Msps, Current-Output DAC
Pin Description (continued)
PIN
NAME
FUNCTION
32
REFR
Full-Scale Current Adjustment. To set the output full-scale current, connect an external resistor RSET
between REFR and AGND. The output full-scale current is equal to 32 x VREFO/RSET.
33, 39
AVDD
Analog Power Input. See the Power Supplies, Bypassing, Decoupling, and Layout section for more details.
34
OUTNB
Channel B Negative Analog Current Output
35
OUTPB
Channel B Positive Analog Current Output
36, 40
AGND
Analog Ground
37
OUTNA
Channel A Negative Analog Current Output
38
OUTPA
Channel A Positive Analog Current Output
—
EP
Exposed Paddle. Connect EP to the common point of all ground planes.
Detailed Description
Figure 2
DVDD
DGND
DIGITAL
POWER
MANAGEMENT
ANALOG
POWER
MANAGEMENT
AVDD
AGND
CW
MAX5854
DACA INPUT REGISTER
CONTROL WORD
DA0
DA1
DA2/G0
DA3/G1
DA4/G2
DA5/G3
DA6/REN
DA7/IDE
DA8/DACEN
DA9/PD
CHANNEL A
GAIN
CONTROL
DCE
CLKXP
CLKXN
CLK
CVDD
CGND
DACB INPUT REGISTER
INPUT DATA
INTERLEAVER
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
OUTPA
OUTNA
10-BIT
DACA
The MAX5854 accepts an input data and a DAC conversion rate of 165MHz. The inputs are latched on the rising
edge of the clock whereas the output latches on the following rising edge.
G0
G1
G2
G3
The MAX5854 features three modes of operation: normal, standby, and power-down (Table 2). These modes
allow efficient power management. In power-down, the
MAX5854 consumes only 1μA of supply current. Wake-up
time from standby mode to normal DAC operation is 3μs.
IDE
OPERATING
MODE
CONTROLLER
CLOCK
DISTRIBUTION
CLOCK
POWER
MANAGEMENT
DACEN
PD
OUTPB
OUTNB
10-BIT
DACB
1.24V REFERENCE
AND CONTROL
AMPLIFIER
The MAX5854 dual, high-speed, 10-bit, current-output
DAC provides superior performance in communication
systems requiring low-distortion analog-signal reconstruction. The MAX5854 combines two DACs and an on-chip
1.24V reference (Figure 2). The current outputs of the
DACs can be configured for differential or single-ended
operation. The full-scale output current range is adjustable from 2mA to 20mA to optimize power dissipation and
gain control.
Programming the DAC
An 8-bit control word routed through channel A’s data port
programs the gain matching, reference, and the operational mode of the MAX5854. The control word is latched
on the rising edge of CW. CW is independent of the DAC
clock. The DAC clock can always remain running, when
the control word is written to the DAC. Table 1 and Table
2 represent the control word format and function.
REFO
REFR
RSET
REN
AGND
The gain on channel A can be adjusted to achieve gain
matching between two channels in a user’s system. The
gain on channel A can be adjusted from -0.4dB to 0.35dB
in steps of 0.05dB by using bits G3 to G0 (Table 3).
Figure 2. Simplified Diagram
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Maxim Integrated │ 11
MAX5854
Dual, 10-Bit, 165Msps, Current-Output DAC
Table 1. Control Word Format and Function
MSB
LSB
PD
DACEN
IDE
G3
REN
CONTROL WORD
PD
DACEN
G2
G1
G0
X
X
FUNCTION
Power-Down. The part enters power-down mode if PD = 1.
DAC Enable. When DACEN = 0 and PD = 0, the part enters standby mode.
IDE
Interleaved Data Mode. IDE = 1 enables the interleaved data mode. In this mode, digital data for both channels
is applied through channel A in a multiplexed fashion. Channel B data is written on the falling edge of the clock
signal and channel A data is written on the rising edge of the clock signal.
REN
Reference Enable Bit. REN = 0 activates the internal reference. REN = 1 disables the internal reference and
requires the user to apply an external reference between 0.1V to 1.32V.
G3
Bit 3 (MSB) of Gain Adjust Word
G2
Bit 2 of Gain Adjust Word
G1
Bit 1 of Gain Adjust Word
G0
Bit 0 (LSB) of Gain Adjust Word
Table 2. Configuration Modes
PD
DACEN
IDE
REN
Normal operation;
noninterleaved inputs;
internal reference active
0
1
0
0
Normal operation;
noninterleaved inputs;
internal reference disabled
0
1
0
1
Normal operation;
interleaved inputs; internal
reference disabled
0
1
1
1
Standby
0
0
X
X
Power-down
1
X
X
X
Power-up
0
1
X
X
MODE
The MAX5854 allows both single-ended CMOS and differential clock mode operation, and supports update rates
of up to 165Msps. These modes are selected through an
active-low control line called DCE. In single-ended clock
mode (DCE = 1), the CLK pin functions as an input, which
accepts a user-provided single-ended clock signal. Data
is written to the converter on the rising edge of the clock.
The DAC outputs (previous data) are updated simultaneously on the same edge.
Table 3. Gain Difference Setting
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At power-up, the MAX5854’s default configuration is
internal reference noninterleaved input mode with a gain
of 0dB and a fully operational converter. In shutdown, the
MAX5854 consumes only 1μA of supply current, and in
standby the current consumption is 3.1mA. Wake-up time
from standby mode to normal operation is 3μs.
Clock Modes
X = Don’t care.
GAIN ADJUSTMENT ON
CHANNEL A (dB)
+0.4
0
-0.35
Device Power-Up and
States of Operation
G3
G2
G1
G0
0
1
1
0
0
1
0
0
1
0
0
1
If the DCE pin is pulled low, the MAX5854 will operate
in differential clock mode. In this mode, the clock signal
has to be applied to differential clock input pins CLKXP/
CLKXN. The differential input accepts an input range of
≥0.5VP-P and a common-mode range of 1V to (CVDD 0.5V), making the part ideal for low-input amplitude clock
drives. CLKXP/CLKXN also help to minimize the jitter,
and allow the user to connect a crystal oscillator directly
to MAX5854.
Maxim Integrated │ 12
MAX5854
Dual, 10-Bit, 165Msps, Current-Output DAC
AVDD
OPTIONAL EXTERNAL BUFFER
FOR HEAVIER LOADS
MAX4040
10µF
1.24V
BANDGAP
REFERENCE
AGND
REN = 0
MAX6520
CURRENT- IFS
SOURCE
ARRAY
IREF
AGND
IREF =
VREF
EXTERNAL
1.2V
REFERENCE
AGND
REFR
MAX5854
REN = 1
REFO
RSET
RSET
1.24V
BANDGAP
REFERENCE
AVDD
REFO
CCOMP*
REFR
0.1µF
AGND
CURRENT- IFS
SOURCE
ARRAY
IREF
RSET
*COMPENSATION CAPACITOR (CCOMP ≈ 100nF).
AGND
MAX5854
Figure 3. Setting IFS with the Internal 1.24V Reference and the
Control Amplifier
Figure 4. MAX5854 with External Reference
The CLK pin now becomes an output, and provides a
single-ended replica of the differential clock signal, which
can be used to synchronize the input data. Data is written
to the device on the rising edge of the CLK signal.
External Reference
Internal Reference and Control Amplifier
The MAX5854 provides an integrated 50ppm/°C, 1.24V,
low-noise bandgap reference that can be disabled and
overridden with an external reference voltage. REFO
serves either as an external reference input or an integrated reference output. If REN = 0, the internal reference
is selected and REFO provides a 1.24V (50μA) output.
Buffer REFO with an external amplifier, when driving a
heavy load.
The MAX5854 also employs a control amplifier designed
to simultaneously regulate the full-scale output current
(IFS) for both outputs of the devices. Calculate the output
current as:
IFS = 32 x IREF
where IREF is the reference output current (IREF = VREFO/
RSET) and IFS is the full-scale output current. RSET is the
reference resistor that determines the amplifier output current of the MAX5854 (Figure 3). This current is mirrored
into the current-source array where IFS is equally distributed between matched current segments and summed to
valid output current readings for the DACs.
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To disable the internal reference of the MAX5854, set
REN = 1. Apply a temperature-stable, external reference to drive the REFO pin and set the full-scale output
(Figure 4). For improved accuracy and drift performance,
choose a fixed output voltage reference such as the 1.2V,
25ppm/°C MAX6520 bandgap reference.
Detailed Timing
The MAX5854 accepts an input data and the DAC conversion rate of up to 165Msps. The input latches on the
rising edge of the clock, whereas the output latches on the
following rising edge.
Figure 5 depicts the write cycle of the two DACs in noninterleaved mode.
The MAX5854 can also operate in an interleaved data
mode. Programming the IDE bit with a high level activates
this mode (Table 1 and Table 2). In interleaved mode,
data for both DAC channels is written through input port
A. Channel B data is written on the falling edge of the
clock signal and then channel A data is written on the following rising edge of the clock signal. Both DAC outputs
(channel A and B) are updated simultaneously on the
next following rising edge of the clock. In interleaved data
mode, the maximum input data rate per channel is half
of the rate in noninterleaved mode. The interleaved data
mode is attractive for applications where lower data rates
are acceptable and interfacing on a single 10-bit bus is
desired (Figure 6).
Maxim Integrated │ 13
MAX5854
Dual, 10-Bit, 165Msps, Current-Output DAC
tCXH
tCXL
CLKXN
CLKXP
tCDL
tCDH
CLK
OUTPUT
tCWL
CW
tDCS
DA0–DA9
DACA - 1
tCS
tDCH
DACA + 1
DACA
tCW
CONTROL
WORD
DACA + 2
DACA + 3
OUTNA
DACA - 1
OUTPA
DB0–DB9
tDCS
DACB - 1
DACA
DACA + 1
XXXX
DACA + 2
(CONTROL WORD DATA)
DACA + 3
tDCH
DACB
DACB + 1
DACB + 2
XXXX
DACB + 3
OUTNB
DACB - 1
DACB
DACB + 1
DACB + 2
XXXX
DACB + 3
OUTPB
Figure 5. Timing Diagram for Noninterleaved Data Mode (IDE = 0)
tCXL
tCXH
CLKXN
CLKXP
tCDL
tCDH
CLK
OUTPUT
tCWL
CW
tDCS
DA0–DA9
DACA
tDCH
DACB + 1
tDCS
tDCH
DACA + 1
tCS
tCW
CONTROL
WORD
DACB + 2
DACA + 2
OUTNA
DACA - 1
DACA
DACA + 1
DACB - 1
DACB
DACB + 1
OUTPA
OUTNB
OUTPB
Figure 6. Timing Diagram for Interleaved Data Mode (IDE = 1)
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Maxim Integrated │ 14
MAX5854
Dual, 10-Bit, 165Msps, Current-Output DAC
AVDD DVDD CVDD
AVDD DVDD CVDD
50Ω
OUTPA
DA0–DA9
10
1/2
MAX5854
VOUTA,
SINGLE ENDED
50Ω
DA0–DA9
100Ω
10
OUTPA
1/2
MAX5854
OUTNA
OUTNA
50Ω
50Ω
OUTPB
DB0–DB9
10
1/2
MAX5854
50Ω
50Ω
VOUTB,
SINGLE ENDED
DB0–DB9
100Ω
10
OUTPB
1/2
MAX5854
OUTNB
OUTNB
50Ω
50Ω
AGND DGND CGND
AGND DGND CGND
Figure 7. Application with Output Transformer Performing
Differential-to-Single-Ended Conversion
Figure 8. Application with DC-Coupled Differential Outputs
Applications Information
applications, information bandwidth can extend from
10MHz down to several hundred kilohertz. DC-coupling is
desirable to eliminate long discharge time constants that
are problematic with large, expensive coupling capacitors.
Analog quadrature upconverters have a DC commonmode input requirement of typically 0.7V to 1.0V. The
MAX5854 differential I/Q outputs can maintain the desired
full-scale level at the required 0.7V to 1.0V DC commonmode level when powered from a single 2.85V (±5%)
supply. The MAX5854 meets this low-power requirement
with minimal reduction in dynamic range while eliminating
the need for level-shifting resistor networks.
Differential-to-Single-Ended Conversion
The MAX5854 exhibits excellent dynamic performance to
synthesize a wide variety of modulation schemes, including high-order QAM modulation with OFDM.
Figure 7 shows a typical application circuit with output
transformers performing the required differential-to-single-ended signal conversion. In this configuration, the
MAX5854 operates in differential mode, which reduces
even-order harmonics, and increases the available output
power.
Differential DC-Coupled Configuration
Figure 8 shows the MAX5854 output operating in differential, DC-coupled mode. This configuration can be used
in communications systems employing analog quadrature
upconverters and requiring a baseband sampling, dualchannel, high-speed DAC for I/Q synthesis. In these
www.maximintegrated.com
Power Supplies, Bypassing,
Decoupling, and Layout
Grounding and power-supply decoupling strongly influence the MAX5854 performance. Unwanted digital crosstalk can couple through the input, reference, power-supply,
and ground connections, which can affect dynamic specifications, like signal-to-noise ratio or spurious-free dynamic
Maxim Integrated │ 15
MAX5854
Dual, 10-Bit, 165Msps, Current-Output DAC
range. In addition, electromagnetic interference (EMI)
can either couple into or be generated by the MAX5854.
Observe the grounding and power-supply decoupling
guidelines for high-speed, high-frequency applications.
Follow the power supply and filter configuration to realize
optimum dynamic performance.
Use of a multilayer printed circuit (PC) board with separate ground and power-supply planes is recommended.
Run high-speed signals on lines directly above the ground
plane. The MAX5854 has separate analog and digital
ground buses (AGND, CGND, and DGND, respectively).
Provide separate analog, digital, and clock ground sections on the PC board with only one point connecting
the three planes. The ground connection points should
be located underneath the device and connected to the
exposed paddle. Run digital signals above the digital
ground plane and analog/clock signals above the analog/
clock ground plane. Digital signals should be kept away
from sensitive analog, clock, and reference inputs. Keep
digital signal paths short and metal trace lengths matched
to avoid propagation delay and data skew mismatch.
The MAX5854 includes three separate power-supply
inputs: analog (AVDD), digital (DVDD), and clock (CVDD).
Use a single linear regulator power source to branch
out to three separate power-supply lines (AVDD, DVDD,
CVDD) and returns (AGND, DGND, CGND).Filter each
power-supply line to the respective return line using LC
filters comprising ferrite beads and 10μF capacitors. Filter
each supply input locally with 0.1μF ceramic capacitors to
the respective return lines.
Note: To maintain the dynamic performance of the
Electrical Characteristics, ensure the voltage difference between DVDD, AVDD, and CVDD does not
exceed 150mV.
Thermal Characteristics and Packaging
Thermal Resistance
40-lead thin QFN-EP:
θJA = 38°C/W
The MAX5854 is packaged in a 40-pin thin QFN-EP
package, providing greater design flexibility, increased
thermal efficiency, and optimized AC performance of the
DAC. The EP enables the implementation of grounding
techniques, which are necessary to ensure highest performance operation.
In this package, the data converter die is attached to an
EP leadframe with the back of this frame exposed at the
package bottom surface, facing the PC board side of the
package. This allows a solid attachment of the package
to the PC board with standard infrared (IR) flow soldering
techniques. A specially created land pattern on the PC
board, matching the size of the EP (4.1mm x 4.1mm),
ensures the proper attachment and grounding of the
DAC. Designing vias* into the land area and implementing large ground planes in the PC board design allows for
highest performance operation of the DAC. Use an array
of 3 x 3 vias (≤ 0.3mm diameter per via hole and 1.2mm
pitch between via holes) for this 40-pin thin QFN-EP package (package code: T4066-1).
Dynamic Performance Parameter Definitions
Adjacent Channel Leakage Ratio (ACLR)
Commonly used in combination with wideband codedivision multiple-access (WCDMA), ACLR reflects the
leakage power ratio in dB between the measured power
within a channel relative to its adjacent channel. ACLR
provides a quantifiable method of determining out-of-band
spectral energy and its influence on an adjacent channel
when a bandwidth-limited RF signal passes through a
nonlinear device.
Total Harmonic Distortion (THD)
THD is the ratio of the RMS sum of all essential harmonics (within a Nyquist window) of the input signal to the
fundamental itself. This can be expressed as:
THD
= 20 × log
(V2 2 + V3 2 + V4 2... + ...VN 2)
V1
where V1 is the fundamental amplitude, and V2 through
VN are the amplitudes of the 2nd through Nth order harmonics. The MAX5854 uses the first seven harmonics for
this calculation.
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio of RMS amplitude of the carrier frequency (maximum signal component) to the RMS value
of their next-largest spectral component. SFDR is usually
measured in dBc with respect to the carrier frequency
amplitude or in dBFS with respect to the DAC’s full-scale
range. Depending on its test condition, SFDR is observed
within a predefined window or to Nyquist.
*Vias connect the land pattern to internal or external copper planes.
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Maxim Integrated │ 16
MAX5854
Dual, 10-Bit, 165Msps, Current-Output DAC
Multitone Power Ratio (MTPR)
Gain Error
A series of equally spaced tones are applied to the DAC
with one tone removed from the center of the range.
MTPR is defined as the worst-case distortion (usually a
3rd-order harmonic product of the fundamental frequencies), which appears as the largest spur at the frequency
of the missing tone in the sequence. This test can be performed with any number of input tones; however, four and
eight tones are among the most common test conditions
for CDMA- and GSM/EDGE-type applications.
A gain error is the difference between the ideal and the
actual full-scale output current on the transfer curve, after
nullifying the offset error. This error alters the slope of the
transfer function and corresponds to the same percentage error in each step. The ideal current is defined by
reference voltage at VREFO/IREF x 32.
Intermodulation Distortion (IMD)
The two-tone IMD is the ratio expressed in dBc of either
output tone to the worst 3rd-order (or higher) IMD products.
Static Performance Parameter Definitions
Integral Nonlinearity (INL)
Integral nonlinearity (INL) is the deviation of the values on
an actual transfer function from a line drawn between the
end points of the transfer function, once offset and gain
errors have been nullified. For a DAC, the deviations are
measured at every individual step.
Differential Nonlinearity (DNL)
Differential nonlinearity (DNL) is the difference between
an actual step height and the ideal value of 1 LSB. A DNL
error specification no more negative than -1 LSB guarantees monotonic transfer function.
Offset Error
Offset error is the current flowing from positive DAC output when the digital input code is set to zero. Offset error
is expressed in LSBs.
Settling Time
The settling time is the amount of time required from the
start of a transition until the DAC output settles to its new
output value to within the converter’s specified accuracy.
Glitch Impulse
A glitch is generated when a DAC switches between two
codes. The largest glitch is usually generated around the
midscale transition, when the input pattern transitions
from 011…111 to 100…000. This occurs due to timing
variations between the bits. The glitch impulse is found
by integrating the voltage of the glitch at the midscale
transition over time. The glitch impulse is usually specified in pV-s.
Table 4. Part Selection Table
PART
SPEED (Msps)
RESOLUTION
MAX5851
80
8-bit, dual
MAX5852
165
8-bit, dual
MAX5853
80
10-bit, dual
MAX5854
165
10-bit, dual
Chip Information
TRANSISTOR COUNT: 9,035
PROCESS: CMOS
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Maxim Integrated │ 17
MAX5854
Dual, 10-Bit, 165Msps, Current-Output DAC
Package Information
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
© 2004 Maxim Integrated Products, Inc. │ 18
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