MAX5857EVKIT#

Evaluates: MAX5857 MAX5857 Evaluation Kit General Description The MAX5857 evaluation kit (EV Kit) contains a single MAX5857 wideband interpolating and modulating RF digital-to-analog converter (DAC) which can directly synthesize 1.2GHz of instantaneous bandwidth from DC to frequencies greater than 2.6GHz. The MAX5857 EV kit provides a complete system for evaluating MAX5857 performance, as well as developing an FPGA plus DAC transmitter solution. The MAX5857 accepts input data through a six-lane JESD204B serializer/deserializer (SerDes) interface up to 9.8304Gbps that is Subclass-0 compliant. The MAX5857 EV kit connects to one FMC connector on the Xilinx VC707 evaluation kit, allowing the VC707 to communicate with the MAX5857’s JESD204B serial link interface. The evaluation kit includes Windows® 7/10-compatible software that provides a simple graphical user interface (GUI) for configuration of all the MAX5857 registers through the SPI interface, control of the VC707 FPGA and temperature monitoring. Features ●● Evaluates the MAX5857 RF DAC Performance, Capability, and Feature Set ●● Single 3.3V Input Voltage Supply ●● Direct Interface with Xilinx VC707 Data Source Board ●● Windows 7/10-compatible Software ●● Optional On-Board SPI Interface Control for the MAX5857 ●● On-Board SMBus™ Interface Control for the MAX6654 Temperature Sensor ●● Integrated GUI Controls for VC707 Operation ●● Proven 10-Layer PCB Design ●● Fully Assembled and Tested Ordering Information appears at end of data sheet. Single-ended Output Module with SMA Connector MAX5857 EV Kit Board Single 3.3V/4A Supply Connection Single-ended Input Clock Module with SMA Connector VC707 Main Power Switch USB Mini-B (Optional USB to SPI/I2C bridge) 12V/5A Power Supply (brick) FMC Interface USB Mini-B (Control/Bulk Data) USB Micro-B (JTAG Interface) VC707 Development Board Figure 1. MAX5857 EV Kit and VC707 System Xilinx is a registered trademark and registered service mark of Xilinx, Inc. Windows is a registered trademark and registered service mark of Microsoft Corporation. 319-100209; Rev 0; 6/18 Evaluates: MAX5857 MAX5857 Evaluation Kit MAX5857 EV Kit Files FILE DESCRIPTION MAX5857EVKITSoftwareController.exe Application program AppFiles Directory Directory application support files including the USB_MS_Bulk_Transfer driver DeviceScripts Directory Directory with sample MAX5857 configuration scripts and PERL scripts for generating additional scripts PatternFiles Directory Directory with sample pattern files VC707Files Directory Directory with FPGA programming file and supporting documentation Screenshots Directory Directory with example spectrum analyzer screen captures Miscellaneous DLLs to include FTD2XX_NET. dll, ftd2xx.dll, LibUsbDotNet.dll, libMPSSE.dll, StatusIndicatorTest.dll and MaximStyle.dll Supporting DLL files for software operation Maxim recommends using the default installation path (c:\MaximIntegrated\MAX5857EVKIT). If an alternate path is desired, it must NOT contain any spaces or the Xilinx LabTools will not be accessed properly. This step should take approximately 2 minutes. The EV kit is fully assembled and tested. Follow the steps below to verify board operation: Initial Setup Required Equipment ●● Window PC (Win-7, Win-10), with one or two available USB 2.0 ports ●● Spectrum Analyzer (Agilent PXA or equivalent) ●● RF Signal Generator (R & S® SMF100A or equivalent) ●● 3.3V, 4A power supply for MAX5857 EV Kit ●● User-Supplied Xilinx VC707 EV Kit • VC707 board • 12V/5A power cube • 1 each USB-A to Mini-B cable for interfacing with the VC707 and MAX5857 • 1 each USB-A to Micro-B cable for programming the VC707 ●● Low-loss SMA/SMA cables as needed for connections to the Spectrum Analyzer and Signal Generator ●● Included in the MAX5857 EV Kit: • MAX5857 Evaluation Kit board • Two 1” stand-offs with screws • USB-A to Mini-B cable, for interfacing with the VC707 / MAX5857 or directly to the EV Kit board Required Software and Drivers The MAX5857 EV Kit software controller application requires the following third-party software components and drivers to be installed. Refer to Appendix I of this document for additional information on this installation process. It is highly recommended that the target PC be connected to a local area network and have access to the Internet, this allows for automatic download and updates of some drivers. This process may take 30 minutes or more to complete. ●● Xilinx ISE 14.7 LabTools This is a free tool set used for programming the VC707 evaluation board. No software license is required to use these tools. However, a Xilinx Login will be required for downloading. ●● Xilinx Drivers After the LabTools have been installed on a PC, the VC707 USB interface drivers can be installed. ●● LIB USB Driver Manual installation of this driver is required after the VC707 is programmed enabling the USB 2.0 bulk transfer port. ●● Microsoft .NET Framework 4 The Microsoft .NET Framework 4 is required by the MAX5857EVKITsoftwareController application. The Win-7 operating system requires manually installing the .NET Framework package using the installer copied to the {installation path}\MAX5857EVKIT\AppFiles\ ThirdParty during the EV Kit software installation. Agilent is a registered trademark and registered service mark of Agilent Technologies, Inc. R&S is a registered trademark and registered service mark of Rohde & Schwarz GmbH & Co. KG. www.maximintegrated.com Maxim Integrated │  2 Evaluates: MAX5857 MAX5857 Evaluation Kit Install the MAX5857 EV Kit Software The MAX5857 EV Kit Software Controller application can be obtained from the www.maximintegrated.com website. Access the MAX5857RFDACEVKitSoftwareInstaller. exe file to install the software. Maxim recommends using the default installation path (c:\MaximIntegrated\MAX5857EVKIT). If an alternate path is desired, it must NOT contain any spaces or the Xilinx LabTools will not be accessed properly. This step should take less than 2 minutes. Setup and Connect the MAX5857 EV Kit Hardware 1) Install the two 1” stand-offs included with the MAX5857 EV kit. Stand-offs should be installed on the RF DAC output side of the board. 2) Verify all jumpers on the MAX5857 EV kit board are in the default position; refer to Table 1. 3) Connect the MAX5857 EV kit board to the VC707 board using the FMC Interface connector shown, as shown in Figure 1. 4) Connect the 3.3V/4A supply to the MAX5857 EV kit board and enable the supply’s output. Verify the four, green, LED board supply indicators are lit. 5) Connect the RF generator to the CLK input with a lowloss SMA cable and set the frequency to 491.52MHz with output power at +2dBm, and enable the output. 6) Turn on the VC707 by sliding the VC707 Main Power Switch (SW12) to the ON position. Verify ALL the LEDs on the VC707 are momentarily lit; the GPIO LEDs should then begin sequencing. 7) Make the USB connections, see Figure 1 for locations a. Connect the USB A – micro B cable (JTAG) from Xilinx VC707 Eval board to the PC b. Connect the USB A – mini B cable (Ctrl/Bulk) from Xilinx VC707 Eval board to the PC Ensure that all the required third-party software and drivers are installed before proceeding to the next section. Configure the MAX5857 EV Kit Graphical User Interface A few items need to be configured during the first execution of the GUI software. 1) Start the MAX5857 EV Kit software. Double-click on the desktop icon or the MAX5857EVKITsoftwareController.exe executable located in the C:\ MaximIntegrated\MAX5857EVKIT folder. A splash screen will be displayed while the USB connections are established (Figure 2) followed by the window shown in Figure 3. 2) Click the button and the primary GUI software window will be loaded (see Figure 4). Table 1. MAX5857 EV Kit Jumper Settings JUMPERS POSITION JU1 Installed* Normal Operation Installed* Power for U4 – MAX6161 – external reference JU4 Not Installed Installed* JU5 Not Installed EV KIT FUNCTION MAX6161 NOT powered MAX5857 external reference connected MAX5857 using internal reference 1-2* SPI control connected through FPGA 2-3 SPI control connected to on-board USB J4 1-2*, 4-5* J10 2-3, 5-6 SCL, SDA connected through FPGA Figure 2. Splash Screen SCL, SDA connected to on-board USB *Default position www.maximintegrated.com Maxim Integrated │  3 MAX5857 Evaluation Kit Evaluates: MAX5857 Figure 3. Communications Selection Window Figure 4. MAX5857 EV Kit GUI – Initial View www.maximintegrated.com Maxim Integrated │  4 Evaluates: MAX5857 MAX5857 Evaluation Kit 3) Load the FPGA configuration a. Click on the checkbox and a File Browser window will open i. Browse to the directory where the impact.exe program is located. If the default installation location was used for the Xilinx Lab Tools, the path will be: • For a 32-bit OS – C:\Xilinx\14.7\LabTools\ LabTools\bin\nt • For a 64-bit OS – C:\Xilinx\14.7\LabTools\ LabTools\bin\nt64 ii. Select the impact.exe file b. Click the button. A file browser will open in the C:\maximintegrated\MAX5857EVKIT\VC707Files folder. c. Select the MAX585X_VC707Prog_15Jun2017. bit file. A progress bar will display while the FPGA is configured, which should take < 2 minutes. After completing the FPGA configuration, the PC will establish a connection to the new USB2.0 port on the FPGA. It should appear as a USB Mass Storage Device in Device Manager (Figure 6). NOTE: Before proceeding, ensure any USB flash drives have been ejected from the PC. 4) Update the USB 2.0 port driver a. Open the Windows Device Manager b. Select the USB Mass Storage Device and right click to select the “Update Driver Software…” option c. Select “Browse my computer for driver software” d. Select “Let me pick from a list of devices on my computer” e. Click the button f. Click the button in the “Load from Disk” pop-up window g. Browse to: C:\MaximIntegrated\MAX5857EVKIT\ AppFiles\ThirdParty\USB_MS_Bulk_Transfer and select the USB_MS_Bulk_Transfer.inf file. h. A window will appear showing Maxim Integrated as the signature for the LIBUSB2 driver. Click on the button. j. The MAX5857 software may show a window indicating it has encountered a problem; click on the button to continue 5) Reboot the PC and power-cycle the FPGA system a. Turn off the VC707 by sliding switch VC707 Main Power Switch to the OFF position b. Disable the RF generator output (clock signal) c. Turn off the DC 3.3V/4A power supply to the EV Kit d. Reboot the PC After the PC has booted, the drivers will be properly configured for use with the MAX5857 software. i. Under Control Panel click on Device Manager or search for “Device Manager” Figure 5. FPGA Configuration Figure 6. Device Manager Window www.maximintegrated.com Maxim Integrated │  5 MAX5857 Evaluation Kit Evaluates: MAX5857 Figure 7. FPGA Connected Quick Start Procedure Power-Up the MAX5857 EV Kit Hardware 1) Set the RF Generator to the desired baseband clock rate (491.52MHz) and the power to +2dBm, DO NOT ENABLE the RF output yet 2) Connect the DAC output to the spectrum analyzer 3) Enable the 3.3V power supply. Verify the four, green, LED board supply indicators are lit 4) Enable the RF generator output 5) Turn on the VC707 by sliding the VC707 Main Power Switch to the ON position (see Figure 1) 6) Verify all LEDs on the VC707 are lit, and the GPIO LEDs are sequencing (for an un-programmed FPGA) Run the MAX5857 EV Kit Software 1) Start the MAX5857 EV Kit software. 2) If the VC707 was powered cycled without a programmed EEPROM, reload the FPGA configuration a. Click the Xilinx Impact Tool Installed check box b. Click the button i. A file browser opens in the VC707 folder ii. Select the MAX5857_DataSource.bit file and click the button c. Verify that the lower-left corner of the window states “FPGA Programmed”; this indicates the GUI is connected to the MAX5857 EV Kit through the FPGA (Figure 6) d. Verify lower-right corner of the app states “FPGA: USB2 Connected, JTAG Connected” indicating these specific port connections have been established (Figure 6). The USB2 should not indicate a connection until the FPGA has been programmed. NOTE: These status notes indicate when FPGA bulk USB 2.0 port and JTAG interfaces are connected and operating properly. www.maximintegrated.com 3) To quickly load a default pattern… a. Click on the tab of the GUI b. Click on one of the buttons c. Example: i. Click on the button ii. Set the center frequency of the spectrum analyzer to 800GHz iii. Click on the “Display Screenshot” selector switch iv. Confirm that the spectrum displayed on the analyzer matches the screenshot example (Figure 8) Loading a Pattern Manually 1) Click on the tab of the GUI 2) Click the button 3) Select a configuration file. For example: MAX585x_ DAC5898p24_CLK491p52_6L10G_RCLKDIV2_ SRAMEN.cfg 4) Click on the tab of the GUI 5) Click on the button 6) Select a pattern list file, for example: TestLoadPatterns.txt a) Wait for the patterns to load 7) Click on the “Select Pattern” drop-down list 8) Select a pattern, for example: “MAX585X_AnxB_8Ch_ fs_1.2288E+009__-12dB.csv” 9) Click on the button 10) Click on the tab 11) If the signal is not visible on the spectrum analyzer a. Check if the output is muted by clicking on the tab and unmute the device, by clicking on the “Hardware Mute” switch b. Check that the center frequency of the spectrum analyzer matches the center frequency of the config file/NCO settings Maxim Integrated │  6 MAX5857 Evaluation Kit Evaluates: MAX5857 Figure 8. Spectral Output – 8 SCQAM at 800MHz www.maximintegrated.com Maxim Integrated │  7 Evaluates: MAX5857 MAX5857 Evaluation Kit Detailed Description which in-turn use CMOS switches and level translators to route the incoming control signals as needed. Detailed Description of Hardware MAX5857 EV Kit Printed Circuit Board The MAX5857 EV Kit board is manufactured on a 10-layer, 1oz copper, FR4 and Rogers 4350B dielectric stack-up PCB. Layers 2, 4, 6, and 9 are ground planes matched to controlled impedance, 50Ω differential, highspeed traces on the outer layers. All internal power planes (layers 5 and 7) and signal routing planes (layers 3 and 8) have copper ground pours in the unused areas to provide additional decoupling and to ease manufacturability. Control Interface The MAX5857 EV kit board provides two forms of communication and control interfacing to the RF DAC and the temperature monitor: a pass-through from the FPGA system and an on-board USB Interface. The FPGA passthrough provides a Serial Port Interface (SPI) to control the MAX5857 RF DAC, and a SMBus interface to control the MAX6654 (temperature monitor). The on-board USB interface uses an FTDI4232 device which provides the SPI and I2C bus signals, as well as GPIO controls for the hardwired MUTE, INTB and RESETB signals on the MAX5857. The FPGA pass-through and the on-board FTDI interface are selected with jumpers J4 and J10 The default settings of J4 and J10 are for using the FPGA pass-through interface. To use the on-board FTDI, switch the J4 and J10 jumpers as shown in Figure 10b. Interface Modules The evaluation kit employs two modules to allow for easy interfacing to Signal Generators and Spectrum Analyzers. The Clock Input Module (RFDAC_XFMR_CLK_MODULE) converts a single ended Signal Generator output to a differential signal which in-turn, drives the CLKP/CLKN inputs of the MAX5857. The Clock Input Module can be removed from the MAX5857 EV Kit board and a differential signal path can be substituted. The method for reconfiguring the clock input is the following: 1) De-solder and remove the Clock Input Module from the MAX5857 EV Kit 2) Populate R61 and R62 with 0Ω resistors 3) Mechanically connect two Rosenberger, edge-launch SMAs to the MAX5857 EV Kit at J7 and J8 4) Solder the center conductors of J7 and J8 to the differential traces (OPTIONAL) MAX5857 EV KIT FPGA FMC DDR3 MEMORY FMC PC INTERFACE FPGA BOARD (VC707) PC INTERFACE POWER MAX5857 OUTPUT MODULE 3V POWER SUPPLY SPECTRUM ANALYZER CLOCK MODULE SIGNAL GENERATOR Figure 9. MAX5857 Evaluation System Block Diagram www.maximintegrated.com Maxim Integrated │  8 MAX5857 Evaluation Kit The Output Module (RFDAC_XFMR_OUT_MODULE) converts the differential output of the MAX5857 RF DAC to a single ended 50Ω output suitable for driving the input of a 50Ω Spectrum Analyzer. The Output Module can be removed from the MAX5857 EV Kit board and a differential signal path can be substituted. The method for reconfiguring the DAC output is the following: 10a. Evaluates: MAX5857 1) De-solder and remove the Output Module from the MAX5857 EV Kit 2) Populate C93 and C99 with 0.01μF capacitors 3) Mechanically connect two Rosenberger, edge-launch SMAs to the MAX5857 EV Kit at J2 and J6 4) Solder the center conductors of J2 and J6 to the differential traces 10b. Figure 10. MAX5857 EV Kit Jumpers. 10a – default FPGA pass-through interface; 10b – on-board FTDI interface Figure 11. MAX5857 Differential Clock Input www.maximintegrated.com Figure 12. MAX5857 Differential DAC Output Maxim Integrated │  9 Evaluates: MAX5857 MAX5857 Evaluation Kit Power Temperature Monitoring The MAX5857 EV kit board requires a single +3.3V, 4A power supply connected to the board through two “banana” jacks (marked +3.3V and GND) or a set of wire loops that can be used with EZ-Hooks (also marked +3.3V and GND). The +3.3V supply is used by the various support circuits including two MAX8527 linear regulators (LDOs) which provide the 1.8V supply rails for the MAX5857 and various support circuitry plus a MAX8556 LDO which supplies the 1.0V level to the MAX5857. One LDO is used for each supply rail, however the LDO outputs are isolated between analog and digital domains by on board filter networks. The PLL supplies for the MAX5857 are isolated from the analog domain through additional filtering. The operational status of each supply can be visually identified by LEDs on the board. When primary power is supplied to the 3.3V VIN on the board, D4 will light green immediately. When the 1.8V and 1.0V rails are within 10% of their nominal output voltages Power-OK lines will light their respective LED indicators. As described in the Detailed Description of Software – Status Tab section, an alarm threshold can be set for the MAX5857 device temperature. When this threshold temperature is exceeded, the ALERT output of the MAX6654 Temperature Monitor is asserted (active-low) and D1 is lit as a visual warning. This is a latched output, so the alert needs to be cleared manually with the GUI software. DAC Reference The MAX5857 EV Kit includes a MAX6161 precision reference for use as an external voltage level for the RF DAC. Power for the MAX6161 is supplied through jumper JU4, while JU5 connects the MAX6161 output to the MAX5857 VREF input. Data Interface The MAX5857 EV Kit directly connects to the VC707 FPGA board through the HPC-1 FMC connector, providing a high-quality interconnect which can support up to 9.8304Gbps data rates for the JESD204B interface. Schematic and layout files for the MAX5857 EV Kit board are included with the software installation and can be found in the MAX5857\EVKIT Info folder Xilinx VC707 FPGA Evaluation Board The Xilinx VC707 board acts as the data source for the MAX5857, allowing for user defined signal generation. Test patterns, generated externally, are stored in the VC707’s on-board DDR memory and subsequently transmitted through six lanes of JESD204B to the MAX5857. A total of 1GB of pattern(s) can be stored, allowing for the use of very long patterns, or multiple patterns consecutively. Multiple patterns allow the user to easily change patterns without repetitive upload commands. The USB2.0 (BULK) interface minimizes the time requirement for uploading the test patterns. Integrated commands allow the VC707 to properly drive all lane rate and speed combinations supported by the MAX5857. Figure 13. MAX5857 EV Kit LEDs Table 2. MAX5857 EV Kit LED Descriptions LED COLOR D1 Red D5 Green Normally On; Auxiliary 1.8V Power Indicator (U9 POK) D2 Green Normally On; DUT 1.0V Power Indicator (U12 POK) D3 Green Normally On; DUT 1.8V Power Indicator (U2 POK) D4 Green Normally On; Main MAX5857 EV Kit 3.3V Power Indicator www.maximintegrated.com DESCRIPTION Normally Off; Temperature alert based on threshold setting in GUI Maxim Integrated │  10 Evaluates: MAX5857 MAX5857 Evaluation Kit The MAX5857 EV Kit GUI software also provides a simple interface for controlling the VC707 board. Use the VC707 tab in the GUI to upload the firmware file which configures the on-board Virtex7 FPGA. The firmware design incorporates the MicroBlaze microcontroller function in the FPGA, which is used to manipulate the operation of the FPGA as well as pass-through commands for the MAX5857 EV Kit. The supported set of MicroBlaze commands are listed in Appendix II for reference, however all required commands for normal operation are incorporated into specific controls in the GUI software. the user has programmed the EEPROM on the VC707 with the MAX5857EVKIT.mcs file (see the Programming the EEPROM section), all of the LEDs will be ON except for GPIO LED number 6 when it first starts-up. As soon as the MAX5857 device is configured, the device will go on Mute until the system or user “unmutes” the output. The GPIO LEDS can be used to identify various states of the FPGA-to-MAX5857 interface. Table 3 describes these states. When the VC707 board is first powered up, the INIT, DONE, and Supply LEDs will be solidly lit green while the GPIO LEDS will flash ON, cycling from 0 through 7 (see Figure 14a). Once the FPGA has been programmed using the .bit file as noted in the Quick Start Procedure for running the MAX5857 EV Kit software, all of the LEDs will be solid-ON, including all eight of the GPIO LEDS (see Figure 14b). If All jumpers and switches on VC707 should be used in its default configuration for normal operation of the MAX5857 EV Kit software. Occasionally jumpers may have been changed during use with other systems, so it is recommended the user confirm jumper J44 (near the USB 2.0 port) be connected 1-2 as in Figure 15a. Likewise, the user should confirm that Master BPI Programming switch bank, SW11 (near the FPGA and LCD display) be set to 00010 as in Figure 15b. 14a. 14b. Figure 14. VC707 LEDs 14a – before FPGA is programmed; 14b – after FPGA is programmed Table 3. VC707 LED Descriptions LED COLOR STANDARD OPERATION 0 Green On FPGA JESD PLL Locked 1 Green On DAC RX SYNCN Done 2 Green On FPGA MMCM Locked 3 Green On FPGA ResetN 4 Green On DAC Temp AlertB, active-low 5 Green On DAC IntrB, active-low 6 Green Off DAC Mute 7 Green On DAC ResetB, active-low www.maximintegrated.com DESCRIPTION Maxim Integrated │  11 MAX5857 Evaluation Kit 15a. Evaluates: MAX5857 15b. Figure 15. VC707 Jumpers and Switches 15a – J44; 15b – SW11; Programming the EEPROM Rather than programming the FPGA after each power cycle of the VC707, the on-board flash memory can be used to store the default RTL for the MAX5857 evaluation system. Once the EEPROM has been programmed, the USB cable connecting to the JTAG port (USB micro-B) will no longer be necessary. For more information on programming the VC707 EEPROM, see the VC707 FPGA Programming section in the Detailed Description of Software. Detailed Description of Software The MAX5857 EV Kit Software Controller GUI is designed to control the MAX5857 EV Kit board and the VC707 board as shown in Figure 9. The software includes USB controls that provide SPI and SMBus communication to the MAX5857 and the MAX6654 interfaces. The GUI also controls the VC707 through the USB 2.0 control and bulk transfer port on the VC707 board. The Communications Selection window (Figure 3) allows the user to select between the FPGA pass-through interface or the on-board FTDI interface for software control of the MAX5857 and the peripheral components. When selecting a communication path for the first time, the “Remember Selection, Do Not Show Again” check box will simplify the startup process by setting the selection as the default communication path. If the user wishes to reset this selection, this can be done by deleting the file stored in the MAX5857 EV Kit working directory. Browse to C:\MaximIntegrated\ www.maximintegrated.com MAX5857EVKIT directory, find and delete the FPGAPathSelection.txt or FTDIPathSelection.txt file. This will cause the SPI Communication Path window to be displayed the next time the GUI is executed. The MAX5857 EV Kit Software Controller GUI features four window tabs for configuration and control of the MAX5857 and the VC707. The specific tabs are: ●● Setup • Load and Reload MAX5857 Configurations • Hardware and Software MUTE Control • Various Reset Functions ●● Clock & NCO • DAC Configuration Status • NCO Programming ●● VC707 • VC707 FGPA Programming • VC707 MicroBlaze Interface • VC707 Pattern Control ●● Status • Temperature Readings and Control of the MAX6654 Temperature Sensor IC • Status of the MAX5857 EV Kit Device Under Test • Automation Support Through TCP/IP Port ●● Register Access • User Access to Read/Write MAX5857 Configuration and Status Registers The EV Kit GUI software begins on the tab if the FPGA has not been programmed (Figure 4), otherwise the tab will be active. Maxim Integrated │  12 Evaluates: MAX5857 MAX5857 Evaluation Kit Logging Results The MAX5857 EV Kit GUI software automatically logs interactions between the GUI software, the MAX5857 EV Kit board, the MAX5857 DAC, and the VC707 FPGA system. The Results Log block is displayed independently of the tab selection, so it remains visible within the window. Logging of most commands can be turned on or off by clicking on the check box. The user can manually enter additional logging information into the text box and the whole log can be copied to the Windows clipboard or cleared by clicking on the or buttons respectively. Setup Tab The Setup tab (Figure 16) allows the user to load a MAX5857 device configuration file, provides basic operational controls, and has one-click “Quick Start” routines. Figure 16. MAX5857 EV Kit GUI – Setup www.maximintegrated.com Maxim Integrated │  13 Evaluates: MAX5857 MAX5857 Evaluation Kit DAC Configuration The DAC Configuration block allows for fast programming of the MAX5857 registers by using pre-sequenced, SPI register writes, consolidated into a text-based configuration file. Sample configuration files are included with the software installation and stored in the C:\MaximIntegrated\MAX5857EVKIT\DeviceScripts\ folder. Clicking the button will cause a file selection window to open in the \DeviceScripts directory. The user then selects the .cfg file and clicks the button. This causes the software to assert, and then clear, a prior to transferring the configuration (SPI writes) to the MAX5857. Once the configuration is complete, the function is left ON to suppress the DAC output until the user is ready to observe the generated signal(s). The configuration file contains a scripted and ordered set of commands that are sent to the MAX5857. These commands include register writes and “wait” directives. For additional information on the configuration file, reference the Configuration Sequence section of the MAX5857 Data Sheet. Clicking on the button will cause the GUI software to use the same configuration file already selected in the text box and reload the MAX5857 registers with those initial configuration settings. If the user wishes to load the configuration setting or reload the existing configuration without the software automatically resetting the device or muting the DAC output, select the “No Reset/Mute” switch. Asserting this switch will prevent any pre-cursor resets but will not prevent any soft reset commands that are within the configuration file itself. To “dump” the MAX5857 registers to a file, click on the button. This will cycle through the DAC’s internal registers and write them out to a file in numerical order. The allregread.txt file will be located in the main operating directory of the software. Basic Controls The Basic Controls block contains various switches including , , and . The user is NOT normally required to drive these controls. www.maximintegrated.com Additional switches include , a GPIO controlled pin on the DAC, is automatically asserted at startup. The , a register-based control, is asserted every time a new configuration is loaded. The mute controls are used to protect downstream devices (PA) or equipment while the RF DAC is being configured and prior to the generation of valid test signals. Test Setup – One Button Configuration The quick-start buttons allow for a oneclick configuration of the MAX5857, assuming the FPGA has been programmed. Four buttons are provided, each with a different default data pattern. Clicking on one of the Test Setup buttons will begin a sequence of commands both for the VC707 data source system and the MAX5857 RF DAC to properly configure the device through the SPI port and deliver data over the high-speed interface, resulting in a pre-defined output signal. A basic example of the output signal can be displayed by clicking on the switch. This will open another window which shows a matching Spectrum Analyzer screen shot that matches the “Quick-Start” pattern output selected with the buttons. Clock and NCO Tab The Clock and NCO tab (Figure 17) displays the clock settings that have been loaded during configuration of the MAX5857. The configuration script also sets the NCO for a specific value, which is displayed in the Final fNCO text box. Updating the NCO requires multiple steps. First, determine if the Extended NCO (fractional mode) is desired; click the Extended NCO Enable toggle button if needed. Select the NCO update mode from the drop-down list. Options are a) Immediate, b) Wait with Timeout, c) Increment/Decrement and d) Wait without Timeout. Please refer to the MAX5857 device data sheet for details on the various NCO operating modes. Next, enter the desired NCO frequency in the Target fNCO (MHz) text box. Click the Calculate Values button to determine the nearest possible programmed frequency for the selected NCO mode. The values written to the MAX5857 will be displayed in the CfgNCOF text box. The final step is to click the Apply Values button which writes the values to the MAX5857 registers and updates the Final fNCO text box. Maxim Integrated │  14 MAX5857 Evaluation Kit Evaluates: MAX5857 Figure 17. MAX5857 EV Kit GUI – Clock and NCO www.maximintegrated.com Maxim Integrated │  15 MAX5857 Evaluation Kit Evaluates: MAX5857 VC707 Tab The VC707 tab (Figure 18) allows the user to monitor the DAC configurations and interact with the VC707 FPGA system. Figure 18. MAX5857 EV Kit GUI – VC707 www.maximintegrated.com Maxim Integrated │  16 Evaluates: MAX5857 MAX5857 Evaluation Kit VC707 FPGA Programming The FPGA Programming block allows the user to interact with the Xilinx FPGA at a basic, bit-file level. As already discussed in the Configure the MAX5857 EV Kit Graphical User Interface section, the VC707 is initially programed through this interface. The FPGA fabric provided with this evaluation system configures the FPGA to control and communicate with the MAX5857. The Virtex chip also acts as a data source system, loading pattern data into memory and transferring that data across the high-speed SerDes interface to the DAC. By using the VC707’s on-board flash, the user can permanently transfer the FPGA configuration file into memory allowing the FPGA to start in a pre-configured state, ready to operate with the MAX5857 EV kit. To program the EEPROM: 1) Be sure the Xilinx Impact Tool box is checked 2) Click on the button. This will open a browser window in the C:\MaximIntegrated\MAX5857EVKIT\VC707Files\ directory to load the .mcs file. 3) Select the MAX585x_VC707Prog_xxJun2017.mcs (or similar) file and click the button 4) If an “Exception” window opens (see Figure 19), simply click the button to continue 5) Loading the .mcs file into the EEPROM may take from 5 to 10 minutes After the VC707 has been configured with the .mcs file, the MAX5857 EV Kit GUI software no longer needs to use the Xilinx Impact Tools. Note the following improvements: ●● Xilinx Impact Tools check box does not need to be clicked and the FPGA no longer needs to be loaded with a configuration file ●● The JTAG/USB connection is no longer needed. The USB Micro-B cable can be removed, requiring only one USB Mini-B cable (USB2 Control/Bulk port) for full communication and control of the MAX5857 evaluation system. VC707 MicroBlaze Interface The MicroBlaze Control block provides the user with a means to control and communicate with both the VC707 system and the MAX5857 using the pass-through SPI interface. The user is able to type commands into the text box, and can directly execute those commands by clicking on the button. Any results that are returned, such as values or simply an “ACK#” response, will be displayed in the text box. The “LED” indicator to the right of the block will be green when an “ACK#” response is received and will turn red, when a “NAK#” response is received. VC707 Pattern Control The Pattern Control block allows the user to load different patterns by first opening a Pattern List file. The software utilizes these list files for loading test patterns into the VC707 memory, such as the example TestLoadPatterns. txt located in the MAX5857\PatternFiles folder. The list file simply contains an unordered list of names of test pattern files, including extensions. The format is simple ASCII text with one pattern file name on each line. Any line within the list that contains a ‘#’ character will cause it to be skipped when the list is loaded by the GUI. The list can contain multiple patterns with up to 1MB in total pattern length, but only one pattern list can be loaded at a time; loading a new list will cause the previously loaded patterns to be overwritten. The MAX5857 EV Kit software includes many pattern list files including: TestLoadPatterns. txt, Patterns_4xInterp_24Ch_DiffSampleRates.txt and Patterns_Bypass_2949QAM.txt Figure 19. Exception Window www.maximintegrated.com Maxim Integrated │  17 Evaluates: MAX5857 MAX5857 Evaluation Kit Pattern files contain the raw waveform data used by the RF DAC to generate an analog RF output. A collection of example patterns used to drive the MAX5857 RF DAC have been provided with the MAX5857 EV kit software. The user may have different types of patterns they wish to test with the evaluation system. To generate other pattern files, it is recommended the user have access to MathWorks MATLAB software. For additional information on the Pattern File format used with the VC707 FPGA and the MAX5857 software, please refer to Appendix III. Status Tab The Status tab (Figure 20) allows the user to monitor DAC conditions such as temperature, internal lane states, and buffer status. It also provides the user with a means to control the GUI and the MAX5857 evaluation system remotely. Figure 20. MAX5857 EV Kit GUI – Status www.maximintegrated.com Maxim Integrated │  18 Evaluates: MAX5857 MAX5857 Evaluation Kit Temperature The Temperature block displays the MAX5857 DAC temperature on request. To read the temperature from the MAX6654 via the SMBus serial interface, click on the button. If the user would like a visual indicator of an over-temperature fault (ALERT), enter the threshold temperature into the text box and click the button. This will cause the MAX6654 to set (active low) the ALERT output pin when the threshold temperature is exceeded. This will light the red, D1 LED on the MAX5857 EV Kit board as a visual warning. This is a latched output so the alert needs to be cleared manually with the GUI software. To clear the temperature fault, click on the button. Device Status The Device Status block shows various operating states of the MAX5857. To update the device status, click on the button. The GUI software will read out the flag bits / registers for each of the six JESD lanes, including the FIFO overflow and underflow flags, the 8b/10b error indicator, and the lane alignment status bits. These are all displayed in the easy-to-read Device Status panel. If the user wishes to check the individual status bits, the Register Access Tab section describes how to interface directly with the MAX5857’s internal registers. Automation Options The Automation block contains the “Enable TCP/IP Control” switch and a text box for entering a port number. This utility feature allows the user to run many of the GUIbased operations without the actual GUI. This TCP/IP command option turns the MAX5857 evaluation system into a valuable tool for automated evaluation or characterization of different DAC configurations typically used in automated bench testing. See Appendix II for a list of supported TCP/IP, remotecontrol commands. www.maximintegrated.com Register Access Tab The Register Access tab (Figure 21) allows the user to interact directly with the MAX5857 through the SPI interface. The use of register read and write functions follows a simple, step-by-step procedure. 1) In the Select Device Register Blocks and then Select the Desired Register section a) Select a register block of interest by clicking on the “Block” drop-down and clicking on the block name b) Select the individual register of interest by clicking on the “Register” drop-down and clicking on the register name 2) In the Select Command section, choose a radio button to “Read” or “Write” to the previously selected register 3) In the Select Options section, if “Write” was selected then enter the intended value in this text box as a hexadecimal number (“0x” prefix is not necessary) 4) In the Execute Command section, after the desired “write” command has been assembled, the user simply clicks on the button to write or read the selected register 5) In the Results section, the GUI will provide any feedback received from the MAX5857 through the FPGA interface. If only a “write” operation was executed, a read-back will be reflected in this text box. If a “read” operation was executed then the value is displayed in this text box. Also note that the command that was written and the resultant read-back with be logged in the “Results Log” text in the lower portion of the GUI window. To capture the state of all the internal registers (“dump the register map”), refer to the discussion of the button in the Status Tab section above. Maxim Integrated │  19 MAX5857 Evaluation Kit Evaluates: MAX5857 Figure 21. MAX5857 EV Kit GUI – Register Access www.maximintegrated.com Maxim Integrated │  20 Evaluates: MAX5857 MAX5857 Evaluation Kit Ordering Information Component Suppliers PART TYPE SUPPLIER MAX5857EVKIT# EV Kit Fairchild Semiconductor www.fairchildsemi.com Hong Kong X’tals Ltd. www.hongkongcrystal.com Murata Electronics North America, Inc. www.murata-northamerica.com Panasonic Corp. www.panasonic.com Taiyo Yuden www.t-yuden.com TDK Corp. www.component.tdk.com EK-V7-V707-G Xilinx Virtex 7 FPGA Board* #Denotes RoHS compliant. *Order from Xilinx or authorized distributor. WEBSITE Note: Indicate that you are using the MAX5857 when contacting these component suppliers. MAX5857 EV Kit Component List PART QTY GND, +3.3V 2 CONNECTOR; MALE; PANELMOUNT; BANANA JACK; STRAIGHT; 1PIN 1 CAPACITOR; SMT (CASE_D); ALUMINUM-ELECTROLYTIC; 150UF; 10V; TOL = 20%; MODEL = FK SERIES C1 C3, C4, C15, C23, C29, C30, C38, C53, C62, C70, C173, C180 C5, C6, C18, C20-C22, C42, C57, C59, C60, C63, C65, C95, C97, C179 C8, C13, C16, C17, C19, C26-C28, C35, C36, C39, C45, C46, C51, C54-C56, C58, C61, C64, C68, C69, C71, C82, C83, C94, C96, C174, C181 12 15 29 www.maximintegrated.com DESCRIPTION CAPACITOR; SMT (0402); CERAMIC CHIP; 1UF; 6.3V; TOL = 10%; TG = -55°C TO +85°C; TC=X5R; CAPACITOR; SMT (0402); CERAMIC CHIP; 100PF; 50V; TOL = 5%; TG = -55°C TO +125°C; TC = C0G CAPACITOR; SMT (0402); CERAMIC CHIP; 0.01UF; 10V; TOL = 10%; MODEL = GRM SERIES; TG = -55°C TO +85°C; TC = X5R PART QTY DESCRIPTION C9, C11, C14, C24, C37, C49, C50, C67, C76-C78, C84, C116, C117, C172 15 CAPACITOR; SMT (0805); CERAMIC CHIP; 10UF; 6.3V; TOL = 20%; TG = -55°C TO +85°C; TC = X5R C10, C31, C47, C48 4 CAPACITOR; SMT (6032); TANTALUM CHIP; 47UF; 16V; TOL = 20%; MODEL = TPS SERIES 18 CAPACITOR; SMT (0402); CERAMIC CHIP; 0.1UF; 10V; TOL = 10%; MODEL = GRM SERIES; TG = -55°C TO +125°C; TC = X7R; C52 1 CAPACITOR; SMT (0402); CERAMIC CHIP; 2200PF; 50V; TOL = 10%; TG = -55°C TO +125 °C; TC = X7R C1000, C1001 2 CAPACITOR; SMT (3528); TANTALUM CHIP; 4.7UF; 16V; TOL = 20% 2 CAPACITOR; SMT (0402); CERAMIC CHIP; 8PF; 50V; TOL = ±0.25PF; MODEL = C0G; TG = -55°C TO +125°C; TC C34, C40, C41, C43, C44, C86, C88, C90, C92, C1002-C1010 C1011, C1012 Maxim Integrated │  21 Evaluates: MAX5857 MAX5857 Evaluation Kit MAX5857 EV Kit Component List (continued) PART C1013 C2, C7, C32, C33, C93, C99 QTY 1 DESCRIPTION CAPACITOR; SMT (0402); CERAMIC CHIP; 3.3UF; 6.3V; TOL = 20%; MODEL = C SERIES; TG = -55°C TO +85°C; TC = X5R 0 CAPACITOR; SMT (0402); OPEN D1 1 DIODE; LED; STANDARD; RED; SMT (0603); PIV = 2V; IF = 0.02A D2-D5 4 DIODE; LED; WATER CLEAR GREEN; SMT (0603); VF = 2.1V; IF = 0.03A; -55°C TO +85°C 3 TEST POINT; PIN DIA = 0.1IN; TOTAL LENGTH = 0.3IN; BOARD HOLE = 0.04IN; BLACK; PHOSPHOR BRONZE WIRE SILVER PLATE FINISH; GND3, GND10, REF-GND V1A, V1D, V2A, V2D, GND6-GND9, VIN1, VIN2, GND11, GND12 J4 J5 12 1 1 EVK KIT PARTS; MAXIM PAD; WIRE; NATURAL; SOLID; WEICO WIRE; SOFT DRAWN BUS TYPE-S; 20AWG CONNECTOR; MALE; THROUGH HOLE; BREAKAWAY; STRAIGHT; 3PINS CONNECTOR; MALE; SMT; HIGH SPEED/HIGH DENSITY OPEN PIN FIELD TERMINAL ARRAY; STRAIGHT; 400PINS J10 1 CONNECTOR; MALE; THROUGH HOLE; BREAKAWAY; STRAIGHT; 6PINS JU4, JU5 2 CONNECTOR; MALE; THROUGH HOLE; BREAKAWAY; STRAIGHT; 2PINS J2, J6-J8 J9 0 0 www.maximintegrated.com CONNECTOR; FEMALE; SMT; SMA JACK PCB; RIGHT ANGLE; 2PINS; FOR NELCO 4000-13SI BOARD MATERIAL CONNECTOR; MALE; THROUGH HOLE; BREAKAWAY; STRAIGHT; 4PINS PART QTY DESCRIPTION JU1 0 CONNECTOR; MALE; THROUGH HOLE; BREAKAWAY; STRAIGHT; 2PINS L1, L2, L10-L13 6 INDUCTOR; SMT (1812); FERRITEBEAD; 120; TOL = ±25%; 3A L8, L9 2 INDUCTOR; SMT (1008); CERAMIC CHIP; 2.2UH; TOL = ±5%; 0.28A; -40ۣ°C TO +125 °C L1000, L1001 2 INDUCTOR; SMT (0603); FERRITEBEAD; 28; TOL = ±25%; 4A N1-N4 4 TRAN; ; NCH; SOT-23; PD-(0.33W); IC-(0.5A); VCEO-(60V); R1, R19, R25, R26, R28, R43 6 RESISTOR; 0603; 499Ω; 1%; 100PPM; 0.10W; THICK FILM R2, R3, R18, R21, R34-R36, R38, R41, R44, R1003-R1005 13 RESISTOR; 0603; 10KΩ; 5%; 200PPM; 0.10W; THICK FILM R6 1 RESISTOR; 0603; 4.22K; 1%; 100PPM; 0.10W; THICK FILM R7, R9, R15 3 RESISTOR; 0603; 4.02K; 1%; 100PPM; 0.10W; THICK FILM R8, R14 2 RESISTOR; 0603; 10.5KΩ; 1%; 100PPM; 0.063W; THICK FILM R13 1 RESISTOR; 0603; 25.5KΩ; 1%; 100PPM; 0.10W; THICK FILM R17, R33, R46, R56, R63 5 RESISTOR; 0603; 0Ω; 5%; JUMPER; 0.10W; THICK FILM R20 1 RESISTOR; 0603; 976Ω; 1%; 100PPM; 0.10W; THICK FILM R22, R23 2 RESISTOR; 0603; 4.7K; 1%; 100PPM; 0.10W; THICK FILM R24 1 RESISTOR; 0603; 47Ω; 5%; 200PPM; 0.10W; THICK FILM R27, R29 2 RESISTOR; 0603; 100K; 1%; 100PPM; 0.10W; THICK FILM R1001 1 RESISTOR; 0603; 1KΩ; 5%; 200PPM; 0.10W; THICK FILM R1002 1 RESISTOR, 0603, 12KΩ, 1%, 100PPM, 0.10W, THICK FILM Maxim Integrated │  22 Evaluates: MAX5857 MAX5857 Evaluation Kit MAX5857 EV Kit Component List (continued) PART QTY R1006 1 RESISTOR; 0603; 2.2KΩ; 5%; 200PPM; 0.10W; THICK FILM R16, R45 0 RESISTOR; 0603; OPEN R42, R59, R61, R62 0 RESISTOR; 0402; OPEN R1000 0 RESISTOR; 0603; 0Ω; 5%; JUMPER; 0.10W; THICK FILM 3 TEST POINT; PIN DIA = 0.1IN; TOTAL LENGTH = 0.3IN; BOARD HOLE = 0.04IN; RED; PHOSPHOR BRONZE WIRE SILVER PLATE FINISH; REFIO, USB3V3, TP_1V8AUX SU1-SU5 SW1, SW2 5 2 DESCRIPTION TEST POINT; JUMPER; STR; TOTAL LENGTH=0.256IN; BLACK; INSULATION = PBT CONTACT = PHOSPHOR BRONZE; COPPER PLATED TIN OVERALL SWITCH; SPST; SMT; 24V; 0.05A; NORMALLY OPEN-SURFACE MOUNT TACTILE SWITCH; RCOIL = Ω U1 1 EV Kit PART- IC; BGA 10X10; 144 PINS; PKG. DWG. NO.: 21-0732 U2, U9 2 IC; VREG; 0.2V DROPOUT LDO REGULATOR; TSSOP14-EP U3, U6, U14, U16 U4 U5 U7 4 1 IC; TXRX; 4-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUT; TSSOP16 IC; VREF; LOW-COST; MICROPOWER; PRECISION; 3-TERMINA; 1.2V VOLTAGEREFERENCE; SOT23-3 1 IC; SNSR; ACCURATE TEMPERATURE SENSOR WITH SMBUS SERIAL INTERFACE; QSOP16 1 IC; VSUP; LOW-POWER TRIPLE-VOLTAGE uP SUPERVISORY CIRCUIT; SC70-5 www.maximintegrated.com PART QTY DESCRIPTION U10 1 IC; VREG; ULTRA-LOW-NOISE, HIGH PSRR, LOW-DROPOUT, LINEAR REGULATOR; SC70-5 ; -40°C TO +85°C U12 1 IC; VREG; ULTRA-LOW-INPUTVOLTAGE LDO REGULATOR; TQFN16-EP U17, U18 2 IC; ASW; HIGH-BANDWIDTH; QUAD DPDT SWITCH; TQFN36-EP U1000 1 IC; USB; QUAD HIGH SPEED USB TO MULTIPURPOSE UART/ MPSSE IC; LQFP64 12X12 U1001 1 IC; EEPROM; 2K; 16-BIT MICROWIRE COMPATIBLE SERIAL EEPROM; NSOIC8 150MIL USB 1 CONNECTOR; FEMALE; SMT; USB MINI B-TYPE SMT CONNECTOR WITH DOWEL PINS; RIGHT ANGLE; 9PINS Y1000 1 CRYSTAL; SMT NO DATA; 18PF; 12MHZ; ±30PPM; ±50PPM W1, W2 2 CONNECTOR; MALE; USB; USB 2.0 MINI CABLE; STRAIGHT; 5PINS X20, X28 2 STANDOFF; FEMALE-THREADED; HEX; 4-40IN; 1IN; NYLON X22, X23 2 MACHINE SCREW; PHILLIPS; PAN; 4-40; 3/4IN; 18-8 STAINLESS STEEL X24, X25 2 MACHINE SCREW; PHILLIPS; PAN; 4-40; 3/8IN; 18-8 STAINLESS STEEL X26, X27 2 NUT; HEX; 4-40; #4; STAINLESS STEEL PCB 1 PCB: MAX5857 MODULE1 1 MAXXFMROUT_OPT1#; RFDAC_ XFMROUT_OPT1_EVKIT_A MODULE2 1 XFMR_CLK_MODULE Maxim Integrated │  23 Evaluates: MAX5857 MAX5857 Evaluation Kit DAC Output Module Component List PART QTY DESCRIPTION DAC Output Module Component List PART QTY R1-R2 2 49.9Ω 1% resistor (0603) 2 CAPACITOR; SMT (0402); CERAMIC CHIP; 0.01UF; 16V; TOL = 10%; MODEL = ; TG = -55°C TO +125°C; TC = X7R T1-T3 3 TRANSFORMER; SMT; 4.5-3000 MHZ; RF TRANSFORMER 1 CONNECTOR; FEMALE; SMT; SMA JACK PCB; RIGHT ANGLE; 2PINS CLK 1 CONNECTOR; FEMALE; SMT; SMA JACK PCB; RIGHT ANGLE; 2PINS PCB 1 PCB: EPCB_RXCM T2 1 TRANSFORMER; SMT; 4.5-3000 MHZ; RF TRANSFORMER PCB 1 PCB: MAXRFDACXFMROUTOPT1 C28, C31 OUT www.maximintegrated.com DESCRIPTION Maxim Integrated │  24 www.maximintegrated.com DN0 IN DP0 IN DN1 IN DP1 IN DN2 IN DP2 IN DN3 IN DP3 IN DN4 IN DP4 IN DN5 IN DP5 IN 2 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF C36 C35 C28 C69 C68 C26 C27 C83 C82 10UF C67 2 10UF C72 2 10UF C79 2 1UF C180 10UF C172 C45 L2 120 L3 120 L4 120 L13 120 C54 1 1 1 1 C55 V2D V2A V1A V1A V2A C74 0.01UF C81 0.01UF C179 100PF C174 0.01UF 1 1UF C70 2 IN V1V_P 25.5K R42 V1D V2D TESTN TESTP SYNCNN SYNCNP IN IN OUT OUT IN IN RVDD2_A5 RVDD2_A8 RVDD2_B5 RVDD2_B8 A5 A8 B5 B8 VDD2_G4 VDD2_G9 VDD2_H4 VDD2_H9 VDD2_J4 VDD2_J9 VDD_F5 VDD_F6 VDD_F7 VDD_F8 VDD_G5 VDD_G8 VSSPLL GND_E6 GND_E7 F5 F6 F7 F8 G5 G8 M7 E6 E7 JRES PLL_COMP SYNCNN SYNCNP TESTN TESTP J1 H1 J12 H12 DN0 DP0 DN1 DP1 DN2 DP2 DN3 DP3 DN4 DP4 DN5 DP5 NC NC U1 MAX5857 J2 H2 M1 L1 M3 L3 M10 L10 M12 L12 J11 H11 J3 H3 M5 A12 M8 L7 L6 L5 (UNDER CAPT BALL) CAPT NC NC TESTEN VDD2PLL L8 AVDD_E4 AVDD_E9 G4 G9 H4 H9 J4 J9 E4 E9 VCOBYP_B11 AVDD2_A4 AVDD2_A9 AVDD2_B4 AVDD2_B9 AVDD2_C2 AVDD2_C3 A4 A9 B4 B9 C2 C3 B11 AVDD1_PLL E11 AVDD2_PLL AVCLK_A3 AVCLK_A10 A3 A10 U1 GND_M9 GND_M6 GND_M4 GND_L11 GND_L9 GND_L4 GND_L2 GND_K12 GND_K10 GND_K9 GND_K8 GND_K5 GND_K4 GND_K3 GND_K1 GND_J10 GND_J8 GND_J7 GND_J6 GND_J5 GND_H10 GND_H8 GND_H7 GND_H6 GND_H5 GND_G12 GND_G7 GND_G6 GND_F12 GND_F11 GND_F10 GND_F9 GND_F4 GND_F3 GND_E10 GND_E8 GND_E5 GND_E3 GND_D10 GND_D9 GND_D8 GND_D7 GND_D6 GND_D5 GND_D4 GND_C12 GND_C11 GND_C10 GND_C9 GND_C8 GND_C7 GND_C6 GND_C5 GND_C4 GND_B10 GND_B3 VCORTN_A11 MAX5857 D11 AVCLK2_B12 B12 0.01UF C8 V2A V1D OPEN PLL_COMP_U1 R13 TESTEN PEC02SAAN DNI JU1 IN IN V2V_P C71 0.01UF VCOBYP_U1 1UF C73 1UF C80 C181 0.01UF 1UF C173 M9 M6 M4 L11 L9 L4 L2 K12 K10 K9 K8 K5 K4 K3 K1 J10 J8 J7 J6 J5 H10 H8 H7 H6 H5 G12 G7 G6 F12 F11 F10 F9 F4 F3 E10 E8 E5 E3 D10 D9 D8 D7 D6 D5 D4 C12 C11 C10 C9 C8 C7 C6 C5 C4 B10 B3 A11 R2 R12 430PF C25 R4 2.7K OPEN OPEN R10 OPEN DNI C66 0.22UF 0 R11 DNI 4700PF C12 IN IN VCOBYP_U1 PLL_COMP_U1 SCLK CSB SDI RESETB SDO INTB MUTE IN IN IN IN IN IN IN CSB R44 10K SCLK TDA TDC K6 K7 D12 E12 TDA TDC K11 M11 U1 MAX5857 GND GND GND GND GND GND GND GND A7 B7 A6 B6 OUT OUT OUTN OUTP GND 5. MINIMIZE LENGTHS OF THE FOLLOWING NETWORKS/TRACES/CONNECTIONS: U1.B1-R20-U1.B2 U1.B11-C66-U1.A11(GND) U1.A12-C12-R11-U1.B11 U1.M7-C8-U1.M8 R42-C8 4. FLOOD TOP LAYER WITH GND, INCLUDING AROUND U1, TO MAXIMIZE THERMAL CONDUCTIVITY FOR U1. HOWEVER, ALL VIAS MUST HAVE THERMAL RELIEF FOR EASE OF ASSEMBLY. 3. R20 SHOULD BE PLACED NEAR U1. 2. MINIMIZE TRACE LENGTHS FOR PLL_COMP_U1 AND VCOBYP_U1. 1. M7 CONNECTS TO GND THROUGH VIA AS CLOSE TO BALL AS POSSIBLE. C8 IS PLACED IMMEDIATELY BELOW AND BETWEEN M7 & M8. R42 SHOULD BE AS CLOSE TO M8 AS POSSIBLE. LAYOUT NOTES: IN IN U1 OUTN_A7 OUTN_B7 OUTP_A6 OUTP_B6 MAX5857 SCLK CSB SDI RESETB SDO INTB MUTE C1 D1 D2 D3 M2 K2 G11 G10 E1 E2 F1 F2 G1 G2 G3 10K RCLKP RCLKN CLKP CLKN U1 MAX5857 REFIO CSBP DACREF FSADJ R38 V2D V2D OUT OUT IN IN IO IN IN IN RESETB SDO INTB MUTE SDI RCLKP RCLKN CLKP CLKN REFIO CSBP DACREF FSADJ A1 A2 B1 B2 MAX5857 Evaluation Kit Evaluates: MAX5857 MAX5857 EV Kit Schematic Maxim Integrated │  25 DUT1.8V DUT1V N4 2N7002 K K A D3 LTST-C190GKT N3 2N7002 D2 LTST-C190GKT A S D G 2 G 499 R28 2 3 S D 3 499 R25 1 1 100K R29 R27 100K OUT VIN OUT VIN POK_2V C9 10UF IN IN IN IN IN 2 3 4 5 6 POK EN IN 12 C1 150UF N1 2N7002 7 8 9 10 11 13 OUT OUT OUT OUT OUT FB IN IN POK T.P. 4 5 6 7 T.P. IN IN 3 EN 2 GND EP 13 12 11 10 9 OUT OUT OUT OUT FB U2 MAX8527EUD+ 1 14 U12 MAX8556ETE+ K A D4 LTST-C190GKT DEVICE POWER 2 1 1 16 POK_1V 10UF C116 GND GND GND 108-0740-001 +3.3V (+3.3V) NC 15 +3.3V VIN MAIN BOARD POWER EP 17 +3.3V 108-0740-001 + GND 14 8 S D R6 4.22K 10UF 1 C117 R15 10.5K R14 C11 10UF 4.02K R7 G 4.02K 2 3 499 R19 C84 10UF 10UF C76 10K R18 C16 0.01UF 0.01UF C13 0 R46 100PF C22 0 R17 IN R16 OPEN IN R45 OPEN V2V_DUT 100PF C21 V1V_DUT V2V_P (U1_H9) V1V_P (U1_F7) 1 V2V_DUT 1 V2V_DUT 1 V1V_DUT 1 V1V_DUT L12 120 L10 120 L11 120 L1 120 2 2 2 2 2 1 V2D 2 1 V2A 2 1 V1D 2 1 V1A + + + + www.maximintegrated.com 15 C31 47UF C53 C37 10UF 1UF C38 1UF C50 C47 47UF 10UF 1UF 10UF C15 C62 1UF C14 10UF C49 C10 47UF C48 47UF 0.01UF C64 G4/G9 0.01UF C58 A4-5/B4-5 0.01UF C17 F5-6/G5 GND V1A 100PF C65 100PF C59 100PF C18 DEVICE POWER FILTERING C61 0.01UF J9/H9 C56 0.01UF C2/C3 C19 0.01UF F7-8/G8 C63 100PF 100PF C57 100PF C20 0.01UF C46 J4/H4 0.01UF C39 A8-9/B8-9 0.01UF C94 E4 C60 100PF 100PF C42 100PF C95 GND V2D GND V2A 0.01UF C96 E9 100PF C97 GND V1D MAX5857 Evaluation Kit Evaluates: MAX5857 MAX5857 EV Kit Schematic (continued) Maxim Integrated │  26 AUX1.8V N2 2N7002 K A D5 LTST-C190GKT S D 2 3 G 499 R43 1 R21 499 R1 POK_AUX 10UF C77 NO SW1 B3S-1000P COM VIN OUT 2 1 IN OUT 10K RESET_IN RESETB 4 3 VCC2 4 GND RSTIN 2 IN IN IN POK T.P. 3 4 5 6 7 T.P. IN 14 EN 1 2 GND EP 13 12 11 10 9 OUT OUT OUT OUT FB U9 MAX8527EUD+ AUXILIARY POWER 3 VCC1 RST R9 R8 10.5K 10UF C78 TP_1V8AUX V1V_DUT V2V_DUT 4.02K IN IN V2V_AUX VIN SCL R23 IN JU4 4.7K PEC02SAAN VIN GND VOUT U4 MAX6120EUR 2 SMBCLK STBY 15 ADD1 6 14 ADD0 10 C51 0.01UF VIN VCC 3 DXP 2 C32 OPEN IO SDA 2200PF C52 ALERTB D1 LTST-C190EKT K A OUT REF-GND C7 OPEN REFIO 1. PLACE U5 CLOSE TO U1 TO MINIMIZE TRACES FOR TDC AND TDA. 12 4 DXN SMBDATA 11 ALERT U5 MAX6654MEE+ R24 47 JU5 PEC02SAAN C2 OPEN 1 TEMPERATURE MONITOR 0.1UF C34 1 LAYOUT NOTES: 1 2 VIN GND 7 5 GND 8 U7 MAX6740XKWED3+ NC 1 1 8 3 NC 5 R41 15 2 NC 9 10K NC 13 POWER ON RESET CIRCUIT NC 16 www.maximintegrated.com V2V_DUT 4.7K R22 0 R63 0 R33 499 R26 C33 OPEN 976 R20 TDC 1UF C3 VIN IN TDA IN VIN 1UF C4 IN IN IN IO DNI J9 PEC04SAAN FSADJ DACREF CSBP REFIO 4 3 2 1 IN IN TDA TDC MAX5857 Evaluation Kit Evaluates: MAX5857 MAX5857 EV Kit Schematic (continued) Maxim Integrated │  27 www.maximintegrated.com DP0 DN0 DP2 DN2 DP4 DN4 DP5 DN5 IN IN IN IN IN IN IN IN A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 J5 ASP-134488-01 DP1 DN1 DP3 DN3 IN IN IN IN B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 J5 ASP-134488-01 SCLK_FPGA IN C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 J5 ASP-134488-01 TESTEN_FPGA SYNCNP SYNCNN TESTP TESTN RCLKP RCLKN IN IN IN IN IN IN IN DATA INTERFACE D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 J5 ASP-134488-01 IN IN IN IN RESETB_FPGA IN MUTE_FPGA IN INTB_FPGA ALERTB_FPGA IN MISO_FPGA CSBA_FPGA CSBB_FPGA G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 G23 G24 G25 G26 G27 G28 G29 G30 G31 G32 G33 G34 G35 G36 G37 G38 G39 G40 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 J5 ASP-134488-01 SCL_FPGA SDA_FPGA MOSI_FPGA LA19P LA15P LA15N SPISEL_FPGA IN IN IN IN IN IN IN H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 H23 H24 H25 H26 H27 H28 H29 H30 H31 H32 H33 H34 H35 H36 H37 H38 H39 H40 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 J5 ASP-134488-01 MAX5857 Evaluation Kit Evaluates: MAX5857 MAX5857 EV Kit Schematic (continued) Maxim Integrated │  28 3 34 7 12 9 13 27 31 25 30 21 16 19 15 CSBB_FPGA3V MOSI_USB MOSI_FPGA3V MISO_USB MISO_FPGA3V SCLK_U3 SCLK_FPGA CSB_U3 CSBA_FPGA SDI_U3 MOSI_FPGA SDO_U3 MISO_FPGA 33 CSBB_USB SCLK_FPGA3V NO8 NC8 NO7 NC7 NO6 NC6 NO5 NC5 NO4 NC4 NO3 NC3 NO2 NC2 NO1 NC1 36 2 8 10 28 26 20 18 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 N.C. INA EP 35 1 EN 22 37 4 GND 23 SCLK_USB 6 N.C. 11 N.C. 14 N.C. 17 N.C. SDO SDI CSB SCLK MISO_OMOD MOSI_OMOD CSB_OMOD SCLK_OMOD 25 30 21 INTB_USB INTB_FPGA TESTEN_USB 15 31 MUTE_FPGA GPIO_0_3_F 27 16 NO6 13 RESETB_FPGA MUTE_USB 19 NC6 9 GPIO_0_7_USB NO3 12 GPIO_0_2_F RESETB_USB TESTEN_FPGA NC3 7 NO8 NC8 NO7 NC7 NO5 NC5 NO4 NC4 NO2 GPIO_0_2_USB NC2 3 34 33 GPIO_0_0_F NO1 NC1 INA GPIO_0_1_F 1 GPIO_0_1_USB 4 USBN_FPGA GPIO_0_0_USB 5 V+ 5 V+ N.C. 24 N.C. 29 N.C. 32 N.C. USBN_FPGA 6 N.C. 11 N.C. 14 N.C. 17 N.C. 24 MAX4761ETX+ U18 36 2 8 10 28 26 20 18 COM2 COM3 COM4 COM5 COM6 COM7 COM8 MAX4761ETX+ COM1 N.C. 35 VIN EP 37 U17 EN 22 VIN 32 N.C. 29 N.C. GND 23 ALERTB TESTEN INTB MUTE RESET_IN POK_AUX POK_2V POK_1V SCL_FPGA SCL SDA_FPGA SDA IO IO OUT IN VIN 2 4 5 2 4 5 6 J10 PEC06SAAN 3 1 6 3 IN IO 2 USBN_FPGA 1 PEC03SAAN J4 1 www.maximintegrated.com 3 CONTROL PATH SELECTION SDA_USB SCL_USB MAX5857 Evaluation Kit Evaluates: MAX5857 MAX5857 EV Kit Schematic (continued) Maxim Integrated │  29 IN IN OUT CSBB_FPGA MOSI_FPGA MISO_FPGA IN INTB_USB IO OUT MUTE_USB TESTEN_USB OUT RESETB_USB DIR4 A1 A2 A3 A4 8 3 4 5 6 C40 V2V_AUX DIR3 7 DIR4 A1 A2 A3 8 3 4 5 B4 11 IO OUT IN B2 13 B3 12 IN C41 0.1UF IN OUT OUT OUT B1 14 U6 DIR3 7 VIN SN74AVC4T774PW DIR2 2 GND DIR1 1 A4 VCCA VCCB OE 9 6 B4 11 B3 12 B2 13 B1 14 0 R56 SN74AVC4T774PW DIR2 2 U14 DIR1 1 GND VCCA VCCB OE C88 0.1UF OPEN R59 9 0.1UF C86 0.1UF V2V_AUX IN SCLK_FPGA SPISEL_FPGA IN 10K R5 16 16 V2V_AUX 15 15 GPIO_0_6_USB GPIO_0_5_USB GPIO_0_4_USB GPIO_0_3_USB MISO_FPGA3V MOSI_FPGA3V CSBB_FPGA3V SCLK_FPGA3V VIN MISO_USB MOSI_USB CSBA_USB SCLK_USB OUT IN IN IN VIN GPIO_1_0_USB IN VIN 10K OUT R3 OUT LA19P OUT LA15N ALERTB_FPGA OUT LA15P A1 A2 A3 A4 3 4 5 6 C43 DIR4 8 DIR4 6 5 4 A4 A3 A2 A1 DIR3 8 3 DIR2 GND IN IN IN B2 13 B3 12 B4 11 0.1UF C44 SN74AVC4T774PW B4 11 B3 12 B2 13 B1 14 U3 DIR1 1 7 VCCA VCCB OE 2 IN B1 14 V2V_AUX 9 VIN DIR3 7 VIN SN74AVC4T774PW DIR2 2 U16 DIR1 1 GND VCCA VCCB OE C92 0.1UF 9 0.1UF VIN C90 0.1UF V2V_AUX 16 16 V2V_AUX 10K R35 10 LEVEL TRANSLATORS 10K R34 10 10 10K R36 15 15 www.maximintegrated.com 10 GPIO_0_0_F IN OUT OUT OUT GPIO_0_3_F GPIO_0_2_F GPIO_0_1_F SDO_U3 SDI_U3 CSB_U3 SCLK_U3 MAX5857 Evaluation Kit Evaluates: MAX5857 MAX5857 EV Kit Schematic (continued) Maxim Integrated │  30 0 DNI R1000 1 2 3 4 5 1 2 3 4 5 897-43-005-00-100001 USB 9 8 7 6 9 8 7 6 1UF C23 USB_3V3 VCC R1004 2.2K R1006 R1005 10K 10UF C24 U1001 93LC56BT-I/SN DO 4 VSS NC NC 1 CS 2 CLK 3 DI 10K R1003 10K MAX8511EXK33 2 1 1 L1001 28 L1000 28 GND 8PF C1000 4.7UF + 2 1 SW2 12K R1002 RESET# 13 3 2 TEST OSCO OSCI EECS EECLK EEDATA REF 6 14 63 62 61 DM DP VREGOUT 7 8 VREGIN 49 +1.8V 26 27 28 29 30 32 33 34 38 39 40 41 43 44 45 46 48 52 53 54 55 57 58 59 BDBUS0 BDBUS1 BDBUS2 BDBUS3 BDBUS4 BDBUS5 BDBUS6 BDBUS7 CDBUS0 CDBUS1 CDBUS2 CDBUS3 CDBUS4 CDBUS5 CDBUS6 CDBUS7 DDBUS0 DDBUS1 DDBUS2 DDBUS3 DDBUS4 DDBUS5 DDBUS6 DDBUS7 PWREN# 60 SUSPEND# 36 16 17 18 19 21 22 23 24 ADBUS0 ADBUS1 ADBUS2 ADBUS3 ADBUS4 ADBUS5 ADBUS6 ADBUS7 FT4232HL C1006 0.1UF U1000 USB_3V3 C1005 0.1UF IN IN IN IN IN IN IN IN IN IN IN IN IN OUT IN IN C1007 0.1UF USB_3V3 C1009 0.1UF GPIO_1_0_USB GPIO_0_0_USB GPIO_0_1_USB GPIO_0_2_USB GPIO_0_3_USB GPIO_0_4_USB GPIO_0_5_USB GPIO_0_6_USB GPIO_0_7_USB SCL_USB SDA_USB SCLK_USB MOSI_USB MISO_USB CSBA_USB CSBB_USB C1008 0.1UF NEXT REVISION SHOULD CHANGE BUSSES C AND D TO ALL INPUTS ON ONE AND ALL OUTPUTS ON THE OTHER. 8PF 3 C1012 4 2 Y1000 12MHZ 4 1K R1001 3.3UF C1003 0.1UF C1004 0.1UF +1.8V FTDI USB INTERFACE 50 C1002 0.1UF +1.8V C1013 C1001 4.7UF + 1 B3S-1000P NO 3 USB_3V3 2 1 COM 2 2 C1011 2 1 USB3V3 USB_3V3 USB_3V3 OUT 5 SHDN GND N.C. IN U10 USB_3V3 3 4 1 5 VPHY 4 VPLL 9 AGND 8 6 VCCCORE 12 VCCCORE 37 VCCCORE 64 10 USB POWER 7 20 31 42 56 VCCIO VCCIO VCCIO VCCIO GND GND GND GND GND GND GND GND www.maximintegrated.com 1 5 11 15 25 35 47 51 C1010 0.1UF MAX5857 Evaluation Kit Evaluates: MAX5857 MAX5857 EV Kit Schematic (continued) Maxim Integrated │  31 1 1 1 1 1 1 1 1 1 GND GND GND GND GND GND GND GND GND GND IN CLKP 1 IN CLKN C6 100PF C5 100PF 1 1 CLKP CLKN OPEN R62 OPEN 1 1 DNI J8 32K243-40ML5 2 2 R61 32K243-40ML5 3 3 www.maximintegrated.com DNI J7 MATCH EXISITNG MODULE FOOTPRINTS, XFMR_CLK_MODULE , DIFF_CLK_MODULE CLK MODULE INTERCONNECT MAX5857 Evaluation Kit Evaluates: MAX5857 MAX5857 EV Kit Schematic (continued) Maxim Integrated │  32 IN OUTN OUTN OUTP IN C99 OPEN C93 OPEN 1 1 DNI J2 1 32K243-40ML5 C30 1UF V2A 1 V2A 32K243-40ML5 DNI J6 3 OUTP C29 1UF 2 2 www.maximintegrated.com 3 L9 2.2UH L8 2.2UH 2 2 V2A GND GND GND GND GND GND GND GND GND GND GND GND GND OUTN OUTP GND GND SCL SDA MISO_OMOD IN IO IN OUT OUT MOSI_OMOD V2A SCLK_OMOD OUT CSB_OMOD V2A GND DAC OUT MODULE INTERCONNECT VIN SCL SCL_USB2 IN IO IN OUT FOR EXPANSION PURPOSES SDA MISO_OMOD SCLK_OMOD SDA_USB2 NC MISO_USB2 SCLK_USB2 MOSI_OMOD MOSI_USB2 SCL_USB3 SDA_USB3 NC MISO_USB3 SCLK_USB3 MOSI_USB3 CSBB_USB3 CSB_OMOD CSBB_USB2 OUT +3.3V +3.3V OUT +3.3V +3.3V VIN MAX5857 Evaluation Kit Evaluates: MAX5857 MAX5857 EV Kit Schematic (continued) Maxim Integrated │  33 Evaluates: MAX5857 MAX5857 Evaluation Kit XFMROUT Module Schematic T2 TC1-1-13MA+ C28 0.01UF 1 4 NC 3 1 32K243-40ML5 1 3 2 4 1:1 6 OUT P 2 6 S 3 C31 0.01UF OUTP OUTN GND GND GND GND VDAC GND GND VDAC GND GND GND GND XFMRCLK Module Schematic www.maximintegrated.com Maxim Integrated │  34 Evaluates: MAX5857 MAX5857 Evaluation Kit Revision History REVISION NUMBER REVISION DATE 0 6/18 DESCRIPTION Initial release PAGES CHANGED — For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com. Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc. © 2018 Maxim Integrated Products, Inc. │  35 MAX5857 Evaluation Kit Evaluates: MAX5857 Appendix I – Software and Driver References Third-Party Software and Driver Installation For the MAX5857 EV Kit software to fully operate with the Xilinx VC707 FPGA platform, software and drivers need to be installed on the target PC. It is highly recommended that the PC be connected to a local area network and have access to the Internet, this will allow for automatic download and updates of some drivers. This process may take 30 minutes or more to complete. Xilinx ISE 14.7 LabTools Installation This is a free tool set used for programming the VC707 Evaluation Board, no software registration or license is required. Xilinx ISE LabTools can be downloaded directly from the web at www.xilinx.com; Type “Lab Tools 14.7 Download” in the site search bar. Open the download folder from the search result, scroll down page and download file “Windows 7/XP/ Server and Linux”. This tool is compatible for both Windows 7 and Windows 10 OS. Note: You may need to register or sign on to an account and verify company information to download files from Xilinx. Figure A1-1. Xilinx ISE LabTools Installation www.maximintegrated.com Maxim Integrated │  36 MAX5857 Evaluation Kit Evaluates: MAX5857 1) Double-click on the xsetup.exe program to start installation of the Xilinx ISE LabTools software 2) Windows may prompt to allow the fallowing program to make changes, click to “Allow Changes” 3) The ISE Design Suite splash screen will appear, then the Welcome Page, click Next > to continue Figure A1-2. Various LabTools Installation screens www.maximintegrated.com Maxim Integrated │  37 MAX5857 Evaluation Kit Evaluates: MAX5857 4) Two “Accept License Agreement” pages appear, check the boxes and click Next > to continue Figure A1-2. Various LabTools Installation screens (continued) www.maximintegrated.com Maxim Integrated │  38 MAX5857 Evaluation Kit Evaluates: MAX5857 5) The “Select Products to Install” page appears, the “Lab Tools – Standalone Installation” should be selected, click Next > to continue Figure A1-2. Various LabTools Installation screens (continued) www.maximintegrated.com Maxim Integrated │  39 MAX5857 Evaluation Kit Evaluates: MAX5857 6) The “Select Installation Options” page will appear (Figure A1-3), uncheck the “Acquire or Manage a License Key” option and click Next > to continue Figure A1-3. LabTools Installation – uncheck “Acquire or Manage License Keys” www.maximintegrated.com Maxim Integrated │  40 MAX5857 Evaluation Kit Evaluates: MAX5857 7) The “Select Destination Directory” page will appear. It is highly recommended the default directory be used for the Xilinx LabTools. Click Next > to continue. 8) The “Installation” summary page will appear, click on the Install button to continue Figure A1-4. Various LabTools Installation screens www.maximintegrated.com Maxim Integrated │  41 MAX5857 Evaluation Kit Evaluates: MAX5857 Figure A1-4b. Various LabTools Installation screens www.maximintegrated.com Maxim Integrated │  42 MAX5857 Evaluation Kit Evaluates: MAX5857 Figure A1-4c. Various LabTools Installation screens www.maximintegrated.com Maxim Integrated │  43 MAX5857 Evaluation Kit 9) Evaluates: MAX5857 The ISE installation may require Microsoft Visual C++ 2008 Redistribution files, install these during the process if necessary a. On the “…Redistribution Setup” page Click on Next > to continue b. The “License Terms” page will appear, check the box and click on the button to continue c. When the “Setup Complete” page appears, click on the button to continue 10) The installation may also require Jungo software to be installed separately, if prompted by Windows Security click on the button to continue 11) The installation will also prompted Windows Security to install “Xilinx” software, click on the button to continue 12) A final “Install Completed” page will appear, click on to complete the ISE LabTools installation process Note: Notifications may vary slightly for Windows 10 OS. Figure A1-5a. Microsoft Visual C++ Installation and ISE Completion www.maximintegrated.com Maxim Integrated │  44 MAX5857 Evaluation Kit Evaluates: MAX5857 Figure A1-5b. Microsoft Visual C++ Installation and ISE Completion (continued) www.maximintegrated.com Maxim Integrated │  45 MAX5857 Evaluation Kit Evaluates: MAX5857 Figure A1-5c. Microsoft Visual C++ Installation and ISE Completion (continued) www.maximintegrated.com Maxim Integrated │  46 Evaluates: MAX5857 MAX5857 Evaluation Kit Xilinx Drivers Installation After the LabTools have been installed on a PC, the VC707 USB interface drivers need to be installed to access the JTAG port. 1) Browse to the Xilinx folder created during the installation of LabTools: for 32-bit OS - C:\Xilinx\14.7\LabTools\LabTools\bin\nt for 64-bit OS - C:\Xilinx\14.7\LabTools\LabTools\bin\nt64 (64-bit OS) 2) Execute the install_drivers.exe application Figure A1-6. Driver Installation 3) A Command Prompt window may briefly flash, and a message may appear stating “This program might not have installed correctly”, click on “This program installed correctly” to continue. Note that messages might vary slightly for Windows 10 OS. After these drivers are installed the JTAG port on the VC707 will be registered to the PC’s Device Manager. LIBUSB Driver Installation This driver is needed to properly interface to the USB 2.0 bulk port on the VC707. This port provides fast, bulk data transfers stored in the DDR and used to generate DAC data patterns. The USB 2.0 port is also used to control the FPGA and as a pass-through control port for the MAX5857 SPI. A \USB_MS_Bulk_Transfer folder can be found on the flash drive and is also created during the MAX5857 EV Kit software installation. This contains the “libusb-win32 devices” driver for the bulk port. Since the VC707 does not inherently use the USB 2.0 (ULPI) port, this driver can only be installed after the .bit file has been programmed into the Virtex FPGA. www.maximintegrated.com Removal / Uninstallation of the MAX5857 EV Kit Software The MAX5857EVKIT Software Controller application can be removed from the system by running the unins000. exe executable located with the C:\MaximIntegrated\ MAX5857EVKIT folder. This will remove any files placed on the system by the installation program. There may be residual files created after the installation process that can be removed by deleting the MAX5857EVKIT directory after running the uninstall program. Upgrading / Updating the MAX5857 EV Kit Software Occasionally upgrades or updates may be available for the MAX5857 EV Kit Controller Software. Be sure to check the www.maximintegrated.com website from time-to-time for information on the MAX5857 evaluation system. Applying upgraded software may require the removal of previous versions. This document was written based on Revision 1.1.1 (FEB 2018) of the MAX5857 RF DAC EV Kit Software. Maxim Integrated │  47 Evaluates: MAX5857 MAX5857 Evaluation Kit Appendix II – Interface Commands List of VC707 Control Commands COMMAND help DESCRIPTION Prints help. Use -a flag for all commands. Try “help -a” now! mem Memory operation usb USB operation reg Read / Write a register capture Manage capture DMA channel play Manage play DMA channel ping Does nothing but ack baudrate Set baud rate spi SPI commands to the MAX5857 i2c I2C commands to the MAX6654 temperature sensor gpio GPIO commands which control or read pins on the MAX5857 EV Kit board init Initialization quit Quits this program Description and Syntax of VC707 Control Commands Help Online help is provided for all commands. Short and long version are available. COMMAND SYNTAX EXAMPLES help ,…,, help mem help -all ARGUMENTS/FLAGS -all -a www.maximintegrated.com DESCRIPTION Name of command, or command and subcommand to request help information about Print help for all the commands Maxim Integrated │  48 Evaluates: MAX5857 MAX5857 Evaluation Kit Memory Operations The mem commands are for reading and writing the DDR memory used for test data. Read a specific number of 32 bit words from a given address of DDR memory or write a specific number of bytes to a given address of DDR memory. Flags allow different communication formats. The default mode is to send data in ASCII format. Use the -b flag to send/ receive in binary mode. When the FPGA is sending in binary mode, the proper number of bytes will be sent, followed by an ACK. There will not be a CR/LF between the data and the ACK. Follow the -b flag on a write request with a CR and LF. There will not be an ACK at this point. Then send the proper amount of binary data. Do not follow the binary data with a CR/LF. After the proper number of bytes has been received, an ACK will be sent. COMMAND SYNTAX EXAMPLES mem read [adr] [num bytes] mem read 0x100 8 -c mem write [adr] [num bytes] [word1] … [wordN] mem write 0x100 8 -c 0x64636261 0x68676665 ARGUMENTS/FLAGS [adr] [num bytes] -binary -b -chksum -c [word] DESCRIPTION Address to read from or write to, in any format that strtoul will parse Number of bytes to read or write in multiples of 4 Send data in binary mode Send 16 bit IPv4 checksum at the end of the data 32 bit values in any format that strtoul will parse USB Operations The usb commands are for reading and writing the DDR memory used for test data. Read a specific number of bytes from a given address of DDR memory or write a specific number of bytes to a given address of DDR memory. The data are transferred using a USB BULK OUT or USB BULK IN format. After the proper number of bytes has been received or sent, an ACK will be returned. COMMAND SYNTAX EXAMPLES usb read [adr] [num bytes] usb read 0x100 8 -c usb write [adr] [num bytes] [word1] … [wordN] usb write 0x100 8 -c 0x64636261 0x68676665 ARGUMENTS/FLAGS [adr] [num bytes] [word] www.maximintegrated.com DESCRIPTION Address to read from or write to, in any format that strtoul will parse Number of bytes to read or write in multiples of 4 32 bit values in any format that strtoul will parse Maxim Integrated │  49 Evaluates: MAX5857 MAX5857 Evaluation Kit Register Operations The reg commands are for reading and writing registers in the MAX5857. Read and write transactions use a 32-bit word. The list operation returns a list of the register or register spaces and when used with the set operation, it allows the user to write to control register fields by name. Only the bits of that field within the control register are modified. After the proper number of bytes has been received or sent, an ACK will be returned. COMMAND SYNTAX EXAMPLES reg read [adr] reg read 0x800 [adr] [word] reg write 0x800 0xA002007F reg list [value] reg set reg write reg list reg set ARGUMENTS/FLAGS [adr] [word] [value] DESCRIPTION Address to read from or write to, in any format that strtoul will parse 32 bit values in any format that strtoul will parse List the hierarchical register spaces, or the registers in a register space. For the set command, is optional name of the control register field to set value to write to the control register field Valid register names are shown in the GUI software under the Register Access Tab. Capture Operations The capture commands are for configuring, starting, and stopping the capture DMA channel. This set of operations is not commonly used with the RF DACs. The buffer operation allows the user to configure the base address or starting address, and length of the capture buffer. The base address must start on a 64-byte alignment and be a multiple of 512 bytes. The RX DMA engine must be stopped before using this command. The dumpregs operation will print the capture channel registers, effectively dumping the contents of the RX DMA engine. The start operation will begin the capture channel or start the RX DMA engine. The capture buffer command must be used first to define the buffer. The stop operation will close the capture channel or stop the RX DMA engine. COMMAND SYNTAX EXAMPLES capture buffer [adr] [num bytes] capture buffer 0x400 512 capture dumpregs capture dumpregs capture start capture start capture stop ARGUMENTS/FLAGS [adr] [num bytes] www.maximintegrated.com capture stop DESCRIPTION Address to read from or write to, in any format that strtoul will parse Number of bytes to read or write in multiples of 512 Maxim Integrated │  50 Evaluates: MAX5857 MAX5857 Evaluation Kit Play Operations The play commands are for configuring, starting, and stopping the play / TX DMA channel. The buffer operation allows the user to configure the base address or starting address, and length of the play buffer. The base address must start on a 64-byte alignment and be a multiple of 512 bytes. The TX DMA engine must be stopped before using this command. The dumpregs operation will print the play channel registers, effectively dumping the contents of the TX DMA engine. The start operation will begin the play channel or start the TX DMA engine. The play buffer command must be used first to define the buffer. The stop operation will close the play channel or stop the TX DMA engine. COMMAND play buffer play dumpregs SYNTAX EXAMPLES [adr] [num bytes] play buffer 0x400 512 play dumpregs play start play start play stop play stop play reset play reset ARGUMENTS/FLAGS [adr] [num bytes] DESCRIPTION Address to read from or write to, in any format that strtoul will parse Number of bytes to read or write in multiples of 512 Ping Command The ping command is a non-operation which simply returns an ACK from the system Baudrate Command The baudrate command sets the communication rate for the UART interface. SPI Operations The spi commands are for reading and writing to the SPI bus which only interfaces to the MAX5857 RF DAC. The read operation will receive one byte from a given register address whereas the read multiple bytes will receive N bytes from the registers starting at the base address provided. The write operation will transmit a single byte to a given register address whereas the write multiple bytes operation will transmit N bytes to the registers starting at the address provided. After the proper number of bytes has been received or sent, an ACK will be returned. COMMAND SYNTAX EXAMPLES spi read multiple bytes [adr] spi read 0x100 [adr] [N bytes] spi read multiple bytes 0x100 4 spi write multiple bytes [adr] [byte] spi write 0x100 0x24 [adr] [N bytes] [word] spi read spi write ARGUMENTS/FLAGS [adr] spi write multiple bytes 0x100 4 0x64636261 DESCRIPTION Address to read from or write to, in any format that strtoul will parse [N bytes] Number of bytes to read or write in multiples of 4 [word] 32 bit values in any format that strtoul will parse [byte] www.maximintegrated.com 8 bit value in an format that strtoul will parse Maxim Integrated │  51 Evaluates: MAX5857 MAX5857 Evaluation Kit I2C Operations The i2c commands are for reading and writing to the I2C bus which only interfaces to the MAX6654 temperature monitor. The read operation will receive one byte from a given register address whereas the read multiple bytes will receive N bytes from the registers starting at the base address provided. The write operation will transmit a single byte to a given register address whereas the write multiple bytes operation will transmit N bytes to the registers starting at the address provided. After the proper number of bytes has been received or sent, an ACK will be returned. COMMAND SYNTAX EXAMPLES i2c read [adr] i2c read 0x08 [adr] [N bytes] i2c read multiple bytes 0x08 4 [adr] [byte] i2c write 0x08 0x24 [adr] [N bytes] [word] i2c write multiple bytes 0x08 4 0x22320010 i2c read multiple bytes i2c write i2c write multiple bytes ARGUMENTS/FLAGS [adr] [N bytes] [byte] [word] DESCRIPTION Address to read from or write to, in any format that strtoul will parse Number of bytes to read or write in multiples of 4 8 bit value in an format that strtoul will parse 32 bit values in any format that strtoul will parse GPIO Operations The gpio commands are for controlling or reading the status of the general purpose I/O lines which are used to drive or are connected to pins on the MAX5857 EV Kit board. The resetb operation is active-low signal, using the -y flag will reset the DAC, using the -n flag will disable reset. The mute operation is an active-high signal, using the -y flag will mute the DAC, using the -n flag will unmute the DAC. The intb line is connected to the active-low interrupt pin of the DAC, using the intb operation will read the status of the INTB pin. The altb line is connected to the alarm (alert) pin of the MAX6654, using the altb operation will read the status of the ALARMB pin of the temperature sensor. COMMAND SYNTAX EXAMPLES gpio resetb [-y|-n] gpio restb -y [-y|-n] gpio mute -n gpio mute gpio intb gpio intb gpio altb gpio altb ARGUMENTS/FLAGS [-y|-n] www.maximintegrated.com DESCRIPTION Set (-y) or clear (-n) the appropriate line Maxim Integrated │  52 Evaluates: MAX5857 MAX5857 Evaluation Kit Init Command The init command is used to initiate communication with the FPGA. Quit Command The quite command closes communication with the FPGA. List of JESD Commands COMMAND resync scramble loopback DESCRIPTION Resynchronize the JESD204 interface. Turn JESD204B scrambling on or off for RX and TX Set JESD204B internal loopback. Use -y to turn on loopback, and use -n to turn it off. jesdreset Reset JESD204B PLL and resynchronize all lanes. configure Set the JESD204B configuration to 623, 545, 422, or 343. This command will set the mapper mode, number of lanes, number of octets per frame, and number of frames per multi-frame. The parameter is a three digit number corresponding to the mapper mode desired. Each digit represents the following: a -> Number of Lanes b -> Octets per Frame c -> Samples per Frame per Converter Sets the JESD204B lane rates. The parameters and [d] are integers that represent the following: f -> Full Lane Rate (1 => 6.144Gbps, 2 => 7.3728Gbps, 3 => 9.8304Gbps) d-> Lane Rate Divider (Lane Rate will equal Full Lane Rate divided by ‘d’) The [d] parameter is optional and will default to 1 for full lane rate if omitted. Examples: jesd204 rate www.maximintegrated.com JESD204 COMMAND LANE RATE SETTING ACHIEVED jesd204 rate 1 2 6.144Gbps / 2 = 3.072Gbps jesd204 rate 2 or jesd204 rate 2 1 7.3728Gbps / 1 = 7.3728Gbps jesd204 rate 3 4 9.8304Gbps / 4 = 2.4576Gbps Maxim Integrated │  53 MAX5857 Evaluation Kit Evaluates: MAX5857 Appendix III – Pattern Files Creating Pattern Files The MAX5857 EV Kit Software Controller is provided with a limited number of sample patterns. The provided patterns allow the user to generate a two-tone, CW signal with a 1MHz spacing between the tones. Typically, the user will want to generate signals with other properties, including modulated signals. The pattern file can use any extension, such as csv, txt, etc., as long as the contents are simple text and conform to the format expected by the MAX5857EV Kit Software Controller. The specific format is as follows: ●● The first line contains only the total number of I/Q data points, N, in the pattern. ●● The total number of lines in the pattern file will be N + 1. ●● The second through N lines contain four, comma separated integer values. These values represent, in order: • the I data Least Significant BYTE (LS BYTE) • the I data Most Significant BYTE (MS BYTE) • the Q data LS BYTE • the Q data MS BYTE. NOTE: I/Q data is in decimal format, offset binary with the 14-bits of data being LSB-justified. That is, the MSB values can range from 0 to 63 and the LSB values can range from 0 to 255. For example, the first few lines of the file could look something like this: 65536 19, 62, 253, 37 19, 62, 250, 37 17, 62, 248, 37 15, 62, 245, 37 13, 62, 242, 37 10, 62, 239, 37 7, 62, 236, 37 3, 62, 234, 37 www.maximintegrated.com Maxim Integrated │  54