MAX7321ATE+TG104

I2C Port Expander with 8 Open-Drain I/Os MAX7321 General Description The MAX7321 2-wire serial-interfaced peripheral features eight open-drain I/O ports with selectable internal pullups and transition detection. Any port may be used as a logic input or an open-drain output. Ports are overvoltage protected to +6V independent of supply voltage. All I/O ports configured as inputs are continuously monitored for state changes (transition detection). State changes are indicated by the open-drain INT output. The interrupt is latched, allowing detection of transient changes. When the MAX7321 is subsequently accessed through the serial interface, any pending interrupt is cleared. The open-drain outputs are rated to sink 20mA and are capable of driving LEDs. The RST input clears the serial interface, terminating any I2C communication to or from the MAX7321. The MAX7321 uses two address inputs with four-level logic to allow 16 I2C slave addresses. The slave address also determines the power-up logic state for the I/O ports, and enables or disables internal 40kΩ pullups in groups of four ports. The MAX7321 is one device in a family of pin-compatible port expanders with a choice of input ports, open-drain I/O ports, and push-pull output ports (see Table 1). The MAX7321 is available in 16-pin QSOP and TQFN packages, and is specified over the automotive temperature range (-40°C to +125°C). Applications ●● Cell Phones ●● SAN/NAS ●● Servers ●● Notebooks ●● Satellite Radio Pin Configurations AD0 1 + RST 2 ●● +1.71V to +5.5V Operating Voltage ●● 8 Open-Drain I/O Ports Rated to 20mA Sink Current ●● I/O Ports Are Overvoltage Protected to +6V ●● Any Port Can Be a Logic Input or an Open-Drain Output ●● Selectable I/O Port Power-Up Default Logic States ●● Transient Changes Are Latched, Allowing Detection Between Read Operations ●● INT Output Alerts Change on Inputs ●● AD0 and AD2 Inputs Select from 16 Slave Addresses ●● Low 0.6µA (typ) Standby Current ●● -40°C to +125°C Operating Temperature Ordering Information PART MAX7321ATE+ -40°C to +125°C 16 TQFN-EP* — ADC OPENPUSH-PULL DRAIN OUTPUTS OUTPUTS PART INPUTS INTERRUPT MASK MAX7319 8 Yes — — MAX7320 — — — 8 MAX7321 Up to 8 — Up to 8 — MAX7322 4 Yes — 4 15 SDA MAX7323 Up to 4 — Up to 4 4 Up to 8 — Up to 8 — Up to 8 — Up to 8 — 12 P7 P2 6 11 P6 MAX7329 P3 7 10 P5 9 QSOP TOP MARK Selector Guide 13 INT GND 8 PINPACKAGE +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. P1 5 MAX7321 TEMP RANGE MAX7321AEE+ -40°C to +125°C 16 QSOP MAX7328 P0 4 19-3738; Rev 4; 7/14 ●● 400kHz I2C Serial Interface 16 V+ 14 SCL AD2 3 Features P4 Pin Configurations are continued at end of data sheet. Typical Application Circuit and Functional Diagram appear at end of data sheet. I2C Port Expander with 8 Open-Drain I/Os MAX7321 Absolute Maximum Ratings (All voltages referenced to GND.) Supply Voltage V+....................................................-0.3V to +6V SCL, SDA, AD0, AD2, RST, INT, P0–P7................-0.3V to +6V P0–P7 Sink Current........................................................ 25mA SDA Sink Current............................................................... 10mA INT Sink Current.................................................................10mA Total V+ Current..................................................................50mA Total GND Current ............................................................100mA Continuous Power Dissipation (TA = +70°C) 16-Pin QSOP (derate 8.3mW/°C above +70°C)..........667mW 16-Pin TQFN (derate 15.6mW/°C above +70°C).......1250mW Operating Temperature Range.......................... -40°C to +125°C Junction Temperature.......................................................+150°C Storage Temperature Range............................. -65°C to +150°C Lead Temperature (soldering, 10s).................................. +300°C Soldering Temperature (reflow) QSOP...........................................................................+240°C TQFN............................................................................+260°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Electrical Characteristics (V+ = +1.71V to +5.5V, TA = -40°C to +125°C, unless otherwise noted. Typical values are at V+ = +3.3V, TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP UNITS 5.50 V 1.6 V Operating Supply Voltage V+ Power-On Reset Voltage VPOR V+ falling Standby Current (Interface Idle) ISTB SCL and SDA and other digital inputs at V+ 0.6 1.5 µA fSCL = 400kHz; other digital inputs at V+ 23 55 µA Supply Current (Interface Running) I+ Input High Voltage SDA, SCL, AD0, AD2, RST, P0–P7 VIH Input Low Voltage SDA, SCL, AD0, AD2, RST, P0–P7 VIL Input Leakage Current SDA, SCL, AD0, AD2, RST, P0–P7 IIH, IIL 1.71 MAX V+ < 1.8V 0.8 x V+ V+ ≥ 1.8 0.7 x V+ V+ < 1.8V 0.2 x V+ V+ ≥ 1.8V 0.3 x V+ SDA, SCL, AD0, AD2, RST, P0–P7 at V+ or GND, internal pullup disabled -0.2 Input Capacitance SDA, SCL, AD0, AD2, RST, P0–P7 Output Low Voltage P0–P7 VOL 90 180 V+ = +2.5V, ISINK = 10mA 110 210 V+ = +3.3V, ISINK = 15mA 130 230 V+ = +5V, ISINK = 20mA 140 250 ISINK = 6mA Output Low Voltage INT VOLINT ISINK = 5mA RPU 25 V µA pF V+ = +1.71V, ISINK = 5mA VOLSDA www.maximintegrated.com +0.2 10 Output Low Voltage SDA Port Input Pullup Resistor V mV 250 mV 130 250 mV 40 55 kW Maxim Integrated │  2 I2C Port Expander with 8 Open-Drain I/Os MAX7321 Port and Interrupt INT Timing Characteristics (V+ = +1.71V to +5.5V, TA = -40°C to +125°C, unless otherwise noted. Typical values are at V+ = +3.3V, TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 4 µs Port Output Data Valid tPPV CL ≤ 100pF Port Input Setup Time tPSU CL ≤ 100pF 0 Port Input Hold Time tPH CL ≤ 100pF 4 INT Input Data Valid Time tIV CL ≤ 100pF 4 µs INT Reset Delay Time from STOP tIP CL ≤ 100pF 4 µs INT Reset Delay Time from Acknowledge tIR CL ≤ 100pF 4 µs µs µs Timing Characteristics (V+ = +1.71V to +5.5V, TA = -40°C to +125°C, unless otherwise noted. Typical values are at V+ = +3.3V, TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 400 kHz Serial-Clock Frequency fSCL Bus Free Time Between a STOP and a START Condition tBUF 1.3 µs Hold Time (Repeated) START Condition tHD, STA 0.6 µs Repeated START Condition Setup Time tSU, STA 0.6 µs STOP Condition Setup Time tSU, STO Data Hold Time Data Setup Time SCL Clock Low Period SCL Clock High Period tHD, DAT 0.6 µs (Note 2) 0.9 µs tSU, DAT 100 ns 1.3 µs tHIGH 0.7 tLOW Rise Time of Both SDA and SCL Signals, Receiving tR Fall Time of Both SDA and SCL Signals, Receiving Fall Time of SDA, Transmitting µs (Notes 3, 4) 20 + 0.1Cb 300 ns tF (Notes 3, 4) 20 + 0.1Cb 300 ns tF,TX (Notes 3, 4) 20 + 0.1Cb 250 ns Pulse Width of Spike Suppressed tSP (Note 5) Capacitive Load for Each Bus Line Cb (Note 3) RST Pulse Width tW 500 ns tRST 1 µs RST Rising to START Condition Setup Time Note Note Note Note Note 50 ns 400 pF 1: All parameters tested at TA = +25°C. Specifications over temperature are guaranteed by design. 2: A master device must provide a hold time of at least 300ns for the SDA signal (referred to VIL of the SCL signal) in order to bridge the undefined region of SCL’s falling edge. 3: Guaranteed by design. 4: Cb = total capacitance of one bus line in pF. ISINK ≤ 6mA. tR and tF measured between 0.3 x V+ and 0.7 x V+. 5: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns. www.maximintegrated.com Maxim Integrated │  3 I2C Port Expander with 8 Open-Drain I/Os MAX7321 Typical Operating Characteristics (TA = +25°C, unless otherwise noted.) 1.4 1.2 V+ = +5.0V 1.0 V+ = +2.5V 0.8 V+ = +3.3V 0.6 0.4 V+ = +1.71V 0.2 0 V+ = +5.0V 50 40 V+ = +3.3V 30 20 V+ = +2.5V 10 -40 -25 -10 5 20 35 50 65 80 95 110 125 0 0.40 0.35 0.30 V+ = +5.0V ISINK = 20mA 0.25 0.20 0.15 V+ = +2.5V V+ = +3.3V ISINK = 10mA ISINK = 15mA 0.10 0.05 V+ = +1.71V -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) TEMPERATURE (°C) OUTPUT VOLTAGE LOW vs. TEMPERATURE MAX7321 toc03 fSCL = 400kHz OUTPUT VOLTAGE LOW (V) STANDBY CURRENT (µA) 1.6 60 SUPPLY CURRENT (µA) fSCL = 0kHz 1.8 MAX7321 toc01 2.0 SUPPLY CURRENT vs. TEMPERATURE MAX7321 toc02 STANDBY CURRENT vs. TEMPERATURE 0 V+ = +1.71V ISINK = 5mA -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) Pin Description PIN NAME FUNCTION QSOP TQFN 1, 3 15, 1 AD0, AD2 Address Inputs. Select device slave address with AD0 and AD2. Connect AD0 and AD2 to either GND, V+, SCL, or SDA to give four logic combinations (see Table 3). 2 16 RST Reset Input, Active Low. Drive RST low to clear the 2-wire interface. 4–7, 9–12 2–5, 7–10 P0–P7 8 6 GND 13 11 INT Interrupt Output. INT is an open-drain output. 14 12 SCL I2C-Compatible Serial-Clock Input 15 13 SDA I2C-Compatible Serial-Data I/O 16 14 V+ Positive Supply Voltage. Bypass V+ to GND with a ceramic capacitor of at least 0.047µF as close to the device as possible. — EP EP Exposed Pad. Connect exposed pad to GND. www.maximintegrated.com Input/output Ports. P0 to P7 are open-drain I/Os. Ground Maxim Integrated │  4 I2C Port Expander with 8 Open-Drain I/Os MAX7321 Detailed Description Functional Overview MAX7319–MAX7329 Family Comparison The MAX7319–MAX7323 family consists of five pincompatible, eight-port expanders. Each version is optimized for different applications. The MAX7328 and MAX7329 are industry standard parts. The MAX7324–MAX7327 family consists of four pincompatible, 16-port expanders that integrate the functions of the MAX7320 and one of either the MAX7319, MAX7321, MAX7322, or MAX7323. The MAX7321 is a general-purpose port expander operating from a +1.71V to +5.5V supply that provides eight open-drain I/O ports. Each open-drain output is rated to sink 20mA, and the entire device is rated to sink 100mA into all ports combined. The outputs drive loads connected to supplies up to +5.5V, independent of the MAX7321’s supply voltage. The MAX7321 is set to one of 16 I2C slave addresses (0x60 to 0x6F) using the address select inputs AD0 and AD2, and is accessed over an I2C serial interface up to 400kHz. The RST input clears the serial interface in Table 1. MAX7319–MAX7329 Family Comparison PART I2C INPUT SLAVE INPUTS INTERRUPT ADDRESS MASK OPENDRAIN OUTPUTS PUSHPULL OUTPUTS APPLICATION 8-PORT EXPANDERS Input-only versions: 8 input ports with programmable latching transition detection interrupt and selectable pullups. MAX7319 110xxxx 8 Yes — — Offers maximum versatility for automatic input monitoring. An interrupt mask selects which inputs cause an interrupt on transitions, and transition flags identify which inputs have changed (even momentarily) since the ports were last read. MAX7320 101xxxx — — — 8 Output-only versions: 8 push-pull outputs with selectable power-up default levels. Push-pull outputs offer faster rise time than openrain outputs, and require no pullup resistors. I/O versions: 8 open-drain I/O ports with latching transition detection interrupt and selectable pullups. MAX7321 MAX7322 110xxxx 110xxxx www.maximintegrated.com Up to 8 4 — Yes Up to 8 — — 4 Open-drain outputs can level shift the logic-high state to a higher or lower voltage than V+ using external pullup resistors. Any port can be used as an input by setting the open-drain output to logic-high. Transition flags identify which inputs have changed (even momentarily) since the ports were last read. 4 input-only, 4 output-only versions: 4 input ports with programmable latching transition detection interrupt and selectable pullups; 4 push-pull outputs with selectable power-up default levels. Maxim Integrated │  5 I2C Port Expander with 8 Open-Drain I/Os MAX7321 Table 1. MAX7319–MAX7329 Family Comparison (continued) PART MAX7323 I2C INPUT SLAVE INPUTS INTERRUPT ADDRESS MASK 110xxxx Up to 4 — OPENDRAIN OUTPUTS Up to 4 PUSHPULL OUTPUTS 4 APPLICATION 4 I/O, 4 output-only versions: 4 open-drain I/O ports with latching transition detection interrupt and selectable pullups. 4 push-pull outputs with selectable power-up default levels. 8 open-drain I/O ports with nonlatching transition detection interrupt and pullups on all ports. MAX7328 MAX7329 0100xxx 0111xxx Up to 8 — Up to 8 — All ports power up as inputs (or logic-high outputs). Any port can be used as an input by setting the opendrain output to logic-high. 16-PORT EXPANDERS MAX7324 MAX7325 MAX7326 MAX7327 101xxxx And 110xxxx 8 Yes — 8 Software equivalent to a MAX7320 plus a MAX7319. Up to 8 — 4 Yes Up to 8 8 Software equivalent to a MAX7320 plus a MAX7321. — 12 Software equivalent to a MAX7320 plus a MAX7322. Up to 4 — Up to 4 12 Software equivalent to a MAX7320 plus a MAX7323. case of a bus lockup, terminating any serial transaction to or from the MAX7321. Any port can be configured as a logic input by setting the port output logic-high (logic-high for an open-drain output is high impedance). When the MAX7321 is read through the serial interface, the actual logic levels at the ports are read back. The open-drain ports offer latching transition detection when used as inputs. All input ports are continuously monitored for changes. An input change sets 1 of 8 flag bits that identify changed input(s). All flags are cleared upon a subsequent read or write transaction to the MAX7321. A latching interrupt output (INT) is programmed to flag logic changes on ports used as inputs. Data changes on any input port forces INT to a logic-low. Changing the I/O port level through the serial interface does not cause an interrupt. The interrupt output INT is deasserted when the MAX7321 is next accessed through the serial interface. Internal pullup resistors to V+ are selected by the address select inputs (AD0 and AD2). Pullups are enabled on the input ports in groups of four (see Table 3). Use the slave address selection to ensure that I/O ports used as inputs are logic-high on power-up. I/O ports with www.maximintegrated.com internal pullups enabled default to a logic-high output state. Ports with internal pullups disabled default to a logic-low output state. Output port power-up logic states are selected by the address select inputs AD0 and AD2. Ports default to logic-high or logic-low on power-up in groups of four (see Table 3). Initial Power-Up On power-up, the transition detection logic is reset, and INT is deasserted. The transition flags are cleared to indicate no data changes. The power-up default states of the eight I/O ports are set according to the I2C slave address selection inputs, AD0 and AD2 (Table 3). For I/O ports used as inputs, ensure that the default states are logic-high so that the I/O ports power up in the high-impedance state. All I/O ports configured with pullups enabled also have a logic-high power-up state. Power-On Reset The MAX7321 contains an integral power-on reset (POR) circuit that ensures all registers are reset to a known state on power-up. When V+ rises above VPOR (1.6V max), the POR circuit releases the registers and 2-wire interface for normal operation. When V+ drops to less than VPOR, the MAX7321 resets all register contents to the POR defaults (Table 3). Maxim Integrated │  6 I2C Port Expander with 8 Open-Drain I/Os MAX7321 Table 2. Read and Write Access to Eight-Port Expander Family PART I2C SLAVE ADDRESS INPUTS INTERRUPT MASK OPENDRAIN OUTPUTS PUSHPULL OUTPUTS I2C DATA WRITE I2C DATA READ MAX7319 110xxxx 8 Yes — — MAX7320 101xxxx — — — 8 MAX7321 110xxxx Up to 8 — Up to 8 — 4 MAX7322 110xxxx 4 Yes — MAX7323 110xxxx Up to 4 — Up to 4 4 MAX7328 0100xxx Up to 8 — Up to 8 — MAX7329 0111xxx Up to 8 — Up to 8 — RST Input The RST input voids any I2C transaction involving the MAX7321, forcing the MAX7321 into the I2C STOP condition. A reset does not affect the INT interrupt output. Standby Mode When the serial interface is idle, the MAX7321 automatically enters standby mode, drawing minimal supply current. Slave Address, Power-Up Default Logic Levels, and Input Pullup Selection Address inputs AD0 and AD2 determine the MAX7321 slave address, set the power-up I/O state for the ports, and select which inputs have pullup resistors. Internal pullups and power-up default states are set in groups of four (Table 3). The MAX7319, MAX7321, MAX7322, and MAX7323 use a different range of slave addresses (110xxxx) than the MAX7320 (101xxxx) (Table 2). The MAX7321 slave address is determined on each I2C transmission, regardless of whether the transmission is actually addressing the MAX7321. The MAX7321 distinguishes whether address inputs AD2 and AD0 are connected to SDA or SCL instead of fixed logic levels V+ or GND during this transmission. This means that the www.maximintegrated.com MAX7321 slave address can be configured dynamically in the application without cycling the device supply. On initial power-up, the MAX7321 cannot decode address inputs AD0 and AD2 fully until the first I2C transmission. AD0 and AD2 initially appear to be connected to V+ or GND. This is important because the address selection is used to determine the power-up logic state and whether pullups are enabled. However, at power-up, the I2C SDA and SCL bus interface lines are high impedance at the pins of every device (master or slave) connected to the bus, including the MAX7321. This is guaranteed as part of the I2C specification. Therefore, address inputs AD2 and AD0 that are connected to SDA or SCL normally appear at power-up to be connected to V+. The power-up logic uses AD0 to select the power-up state and whether pullups are enabled for ports P3–P0, and AD2 for ports P7–P4. The rule is that a logic-high, SDA, or SCL connection selects the pullups and sets the default logic state to high. A logic-low deselects the pullups and sets the default logic state to low (Table 3). The port configuration is correct on power-up for a standard I2C configu ration, where SDA or SCL are pulled up to V+ by the external I2C pullup resistors. Maxim Integrated │  7 I2C Port Expander with 8 Open-Drain I/Os MAX7321 Table 3. MAX7321 Address Map PIN CONNECTION DEVICE ADDRESS 40kW INPUT PULLUP ENABLES AD2 AD0 A6 A5 A4 A3 A2 A1 A0 I7 I6 I5 I4 I3 I2 I1 I0 SCL GND 1 1 0 0 0 0 0 Y Y Y Y — — — — SCL V+ 1 1 0 0 0 0 1 Y Y Y Y Y Y Y Y SCL SCL 1 1 0 0 0 1 0 Y Y Y Y Y Y Y Y SCL SDA 1 1 0 0 0 1 1 Y Y Y Y Y Y Y Y SDA GND 1 1 0 0 1 0 0 Y Y Y Y — — — — SDA V+ 1 1 0 0 1 0 1 Y Y Y Y Y Y Y Y SDA SCL 1 1 0 0 1 1 0 Y Y Y Y Y Y Y Y SDA SDA 1 1 0 0 1 1 1 Y Y Y Y Y Y Y Y GND GND 1 1 0 1 0 0 0 — — — — — — — — GND V+ 1 1 0 1 0 0 1 — — — — Y Y Y Y GND SCL 1 1 0 1 0 1 0 — — — — Y Y Y Y GND SDA 1 1 0 1 0 1 1 — — — — Y Y Y Y V+ GND 1 1 0 1 1 0 0 Y Y Y Y — — — — V+ V+ 1 1 0 1 1 0 1 Y Y Y Y Y Y Y Y V+ SCL 1 1 0 1 1 1 0 Y Y Y Y Y Y Y Y V+ SDA 1 1 0 1 1 1 1 Y Y Y Y Y Y Y Y There are circumstances where the assumption that SDA = SCL = V+ on power-up is not true (e.g., in applications in which there is legitimate bus activity during power-up). Also, if SDA and SCL are terminated with pullup resistors to a different supply voltage than the MAX7321’s supply voltage, and if that pullup supply rises later than the MAX7321’s supply, then SDA or SCL may appear at power-up to be connected to GND. In such applications, use the four address combinations that are selected by connecting address inputs AD2 and AD0 to V+ or GND (shown in bold in Table 3). These selections are guaranteed to be correct at power-up, independent of SDA and SCL behavior. If one of the other 12 address combinations is used, an unexpected combination of pullups might be asserted until the first I2C transmission (to any device, not necessarily the MAX7321) is put on the bus, and an unexpected combination of ports may initialize as logic-low outputs instead of inputs or logic-high outputs. www.maximintegrated.com Port Inputs I/O port inputs switch at the CMOS-logic levels, as determined by the expander’s supply voltage, and are overvoltage tolerant to +6V, independent of the expander’s supply voltage. I/O Port Input Transition Detection All I/O ports configured as inputs are monitored for changes since the expander was last accessed through the serial interface. The state of the input ports is stored in an internal “snapshot” register for transition monitoring. The snapshot is continuously compared with the actual input conditions, and if a change is detected for any port, INT is asserted to signal a state change. An internal transition flag is set for that port. The input is sampled (internally latched into the snapshot register) and the old transition flags cleared during the I2C acknowledge of every MAX7321 read and write access. The previous port transition flags are read through the serial interface as the second byte of a 2-byte read sequence. Maxim Integrated │  8 I2C Port Expander with 8 Open-Drain I/Os MAX7321 SDA tSU,STA tSU,DAT tLOW tHD,DAT tBUF tHD,STA tSU,STO tHIGH SCL tHD,STA tR tF START CONDITION REPEATED START CONDITION STOP CONDITION START CONDITION Figure 1. 2-Wire Serial Interface Timing Details Serial Interface Serial Addressing SDA The MAX7321 operates as a slave that sends and receives data through an I2C interface. The interface uses a serial-data line (SDA) and a serial-clock line (SCL) to achieve bidirectional communication between master(s) and slave(s). The master initiates all data transfers to and from the MAX7321 and generates the SCL clock that synchronizes the data transfer (Figure 1). SCL SDA operates as both an input and an open-drain output. A pullup resistor, typically 4.7kΩ, is required on SDA. SCL operates only as an input. A pullup resistor, typically 4.7kΩ, is required on SCL if there are multiple masters on the 2-wire interface, or if the master in a single-master system has an open-drain SCL output. Each transmission consists of a START condition sent by a master, followed by the MAX7321’s 7-bit slave address plus R/W bit, 1 or more data bytes, and finally a STOP condition (Figure 2). START and STOP Conditions Both SCL and SDA remain high when the interface is not busy. A master signals the beginning of a transmission with a START (S) condition by transitioning SDA from high to low while SCL is high. When the master has finished communicating with the slave, the master issues a STOP (P) condition by transitioning SDA from low to high while SCL is high. The bus is then free for another transmission (Figure 2). Bit Transfer One data bit is transferred during each clock pulse. The data on SDA must remain stable while SCL is high (Figure 3). www.maximintegrated.com S P START CONDITION STOP CONDITION Figure 2. START and STOP Conditions Acknowledge The acknowledge bit is a clocked 9th bit the recipient uses to acknowledge receipt of each byte of data (Figure 4). Each byte transferred effectively requires 9 bits. The master generates the 9th clock pulse, and the recipient pulls down SDA during the acknowledge clock pulse, such that the SDA line is stable low during the high period of the clock pulse. When the master is transmitting to the MAX7321, the MAX7321 generates the acknowledge bit because the device is the recipient. When the MAX7321 is transmitting to the master, the master generates the acknowledge bit because the master is the recipient. Slave Address The MAX7321 has a 7-bit-long slave address (Figure 5). The eighth bit following the 7-bit slave address is the R/W bit. It is low for a write command, and high for a read command. The first (A6), second (A5), and third (A4) bits of the MAX7321 slave address are always 1, 1, and 0. Connect AD2 and AD0 to GND, V+, SDA, or SCL to select slave address bits A3, A2, A1, and A0. The MAX7321 has 16 possible slave addresses (Table 3), allowing up to 16 MAX7321 devices on an I2C bus. Maxim Integrated │  9 MAX7321 I2C Port Expander with 8 Open-Drain I/Os Accessing the MAX7321 The MAX7321 is accessed through an I2C interface. The transition flags are cleared, and INT is deasserted each time the device acknowledges the I2C slave address. A single-byte read from the MAX7321 returns the status of the eight I/O ports. A 2-byte read returns first the status of the eight I/O ports (as for a single-byte read), followed by the transition flags. A multibyte read (more than 2 bytes before the I2C STOP bit) repeatedly returns the port data, alternating with the transition flags. As the port data is resampled for each transmission, and the transition flags are reset each time, a multibyte read continuously returns the current data and identifies any changing ports. If a port data change occurs during the read sequence, INT is reasserted after the I2C STOP bit. The MAX7321 does not generate another interrupt during a single-byte or multibyte read. Port data is sampled during the preceding I2C acknowledge bit (the acknowledge bit for the I2C slave address in the case of a single-byte or 2-byte read). A single-byte write to the MAX7321 sets the logic state of all eight I/O ports. A multibyte write to the MAX7321 repeatedly sets the logic state of all eight I/O ports. Reading from the MAX7321 A read from the MAX7321 starts with the master transmitting the MAX7321’s slave address with the R/W bit set high. The MAX7321 acknowledges the slave address, and samples the ports during the acknowledge bit. INT deasserts during the slave address acknowledge. SDA SCL DATA LINE STABLE; CHANGE OF DATA DATA VALID ALLOWED Figure 3. Bit Transfer START CONDITION SCL CLOCK PULSE FOR ACKNOWLEDGMENT 1 2 8 9 SDA BY TRANSMITTER SDA BY RECEIVER S Figure 4. Acknowledge transmission are detected. INT remains high until the STOP condition. The master can read 2 bytes from the MAX7321 and then issue a STOP condition (Figure 7). In this case, the MAX7321 transmits the current port data, followed by the change flags. The change flags are then cleared, and transition detection resets. INT goes high (high impedance if an external pullup resistor is not fitted) during the slave acknowledge. The new snapshot data is the current port data transmitted to the master; therefore, port changes occurring during the transmission are detected. INT remains high until the STOP condition. Typically, the master reads 1 or 2 bytes from the MAX7321, each byte being acknowledged by the master upon reception with the exception of the last byte. When the master reads 1 byte from the MAX7321 and subsequently issues a STOP condition (Figure 6), the MAX7321 transmits the current port data, clears the change flags, and resets the transition detection. INT deasserts during the slave acknowledge. The new snapshot data is the current port data transmitted to the master; therefore, port changes ocurring during the www.maximintegrated.com Maxim Integrated │  10 I2C Port Expander with 8 Open-Drain I/Os MAX7321 1 SDA 1 0 A2 A3 A1 A0 R/W ACK LSB MSB SCL Figure 5. Slave Address PORT I/O P6 P7 S 1 1 0 MAX7321 SLAVE ADDRESS 1 A R/W D7 P5 D6 P4 P3 DATA D5 D4 P1 P2 D3 D2 P0 D1 D0 N P PORT SNAPSHOT PORT SNAPSHOT SCL tPH PORT I/O tIV tPSU tIR INT OUTPUT tIP INT REMAINS HIGH UNTIL STOP CONDITION Figure 6. Reading the MAX7321 (1 Data Byte) PORT I/O I7 S 1 1 0 MAX7321 SLAVE ADDRESS 1 A D7 R/W I6 D6 I5 I4 D5 PORT SNAPSHOT D4 I3 INTERRUPT FLAGS I1 I2 D3 D2 D1 I0 D0 F7 A PORT SNAPSHOT D7 F6 D6 F5 D5 F4 D4 F3 D3 F2 D2 F1 F0 D1 D0 N P PORT SNAPSHOT SCL PORTS tIV INT OUTPUT tPH tIR tPSU INT REMAINS HIGH UNTIL STOP CONDITION tIP S = START CONDITION P = STOP CONDITION SHADED = SLAVE TRANSMISSION N = NOT ACKNOWLEDGE Figure 7. Reading the MAX7321 (2 Data Bytes) www.maximintegrated.com Maxim Integrated │  11 I2C Port Expander with 8 Open-Drain I/Os MAX7321 1 SCL 2 3 4 5 6 7 8 DATA TO PORT SLAVE ADDRESS SDA S 0 START CONDITION A DATA TO PORT DATA 1 A DATA 2 A R/W tPV INTERNAL WRITE TO PORT DATA OUT FROM PORT tPV DATA 1 VALID tPV DATA 2 VALID tPV S = START CONDITION SHADED = SLAVE TRANSMISSION P = STOP CONDITION N = NOT ACKNOWLEDGE Figure 8. Writing to the MAX7321 Writing to the MAX7321 A write to the MAX7321 starts with the master transmitting the MAX7321’s slave address with the R/W bit set low. The MAX7321 acknowledges the slave address, and samples the ports (takes a snapshot) during acknowledge. INT goes high (high impedance if an external pullup resistor is not fitted) during the slave acknowledge. Typically, the master proceeds to transmit 1 or more bytes of data. The MAX7321 acknowledges these subsequent bytes of data and updates the I/O ports with each new byte until the master issues a STOP condition (Figure 8). Applications Information Port Input and I2C Interface Level Translation from Higher or Lower Logic Voltages The MAX7321’s SDA, SCL, AD0, AD2, RST, INT, and I/O ports P0–P7 are overvoltage protected to +6V independent of V+. This allows the MAX7321 to operate from a lower supply voltage, such as +3.3V, while the I2C interface and/or any of the eight I/O ports are driven as inputs driven from a higher logic level, such as +5V. The MAX7321 can operate from a higher supply voltage, such as +3V, while the I2C interface and/or some of the I/O ports (P0–P7) are driven from a lower logic level, such as +2.5V. Apply a minimum voltage of 0.7 x V+ to assert a logic-high on any I/O port (e.g., a MAX7321 operating from a +5V supply may not recognize a +3.3V nominal logic-high). One solution for input-level translation is to drive MAX7321 I/Os from open-drain outputs. Use a pullup resistor to V+ or a www.maximintegrated.com higher supply to ensure a high logic voltage greater than 0.7 x V+. Port-Output Port-Level Translation The open-drain output architecture allows for level translation to higher or lower voltages than the MAX7321’s supply. Use an external pullup resistor on any output to convert the high-impedance logic-high condition to a positive voltage level. The resistor can be connected to any voltage up to +6V, and the resistor value chosen to ensure no more than 20mA is sunk in the logic-low condition. For interfacing CMOS inputs, a pullup resistor value of 220kΩ is a good starting point. Use a lower resistance to improve noise immunity, in applications where power consumption is less critical, or where a faster rise time is needed for a given capacitive load. Each of the I/O ports (P0–P7) has a protection diode to GND (Figure 9). When a port is driven to a voltage lower than GND, the protection diode clamps the voltage to a diode drop below GND. Each of the P0–P7 I/O ports also has a 40kΩ (typ) pullup resistor that can be enabled or disabled. When a port is driven to a voltage higher than V+, the body diode of the pullup enable switch conducts and the 40kΩ pullup resistor is enabled. When the MAX7321 is powered down (V+ = 0), each I/O port appears as a 40kΩ resistor in series with a diode connected to zero. I/O ports are protected to +6V under any of these circumstances (Figure 9). Maxim Integrated │  12 I2C Port Expander with 8 Open-Drain I/Os MAX7321 Functional Diagram AD0 P7 P6 P5 P4 P3 P2 P1 P0 AD2 SCL SDA RST INPUT I2 C CONTROL FILTER I/O PORTS INT POWERON RESET MAX7321 Driving LED Loads When driving LEDs, a resistor must be fitted in series with the LED to limit the LED current to no more than 20mA. Connect the LED cathode to the MAX7321 port, and the LED anode to V+ through the series currentlimiting resistor (RLED). Set the port output low to illuminate the LED. Choose the resistor value according to the following formula: RLED = (VSUPPLY - VLED - VOL)/ILED V+ V+ MAX7321 PULLUP ENABLE 40kΩ P0–P7 INPUT OUTPUT where: RLED is the resistance of the resistor in series with the LED (Ω). Figure 9. MAX7321 I/O Structure VSUPPLY is the supply voltage used to drive the LED (V). VLED is the forward voltage of the LED (V). VOL is the output-low voltage of the MAX7321 when sinking ILED (V). ILED is the desired operating current of the LED (A). For example, to operate a 2.2V red LED at 10mA from a +5V supply: RLED = (5 - 2.2 - 0.07)/0.010 = 270Ω. www.maximintegrated.com Maxim Integrated │  13 Typical Application Circuit 0.047µF SCL SCL SDA SDA RST RST INT INT P5 P4 P3 P2 I/O I/O I/O I/O P1 P0 GND P6 TOP VIEW P7 Pin Configurations (continued) 12 11 10 9 SDA 13 V+ 14 MAX7321 AD0 15 1 2 3 4 P2 RST 16 The MAX7321 clears data stored in the interrupt flag and deasserts the corresponding interrupt when an I2C master reads any I2C slave on the same bus. + *EP P1 Description of Problem 8 P5 7 P4 6 GND 5 P3 TQFN *EXPOSED PAD, CONNECTED TO GND Workaround Package Information For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE www.maximintegrated.com P6 MAX7321 AD0 AD2 Issue: I2C Flag Clearing Deassertion Anomaly To keep the interrupt flag data valid, the user must read the MAX7321 device BEFORE any other device on the I2C bus, after a pending interrupt. This limits the bus to only one MAX7321 device. P7 INT The MAX7321 operates with a supply voltage of +1.71V to +5.5V over the -40°C to +125°C temperature range. Bypass the supply to GND with a ceramic capacitor of at least 0.047µF as close as possible to the device. For the TQFN version, additionally connect the exposed pad to GND. V+ µC The MAX7321 must be protected from the negative voltage transient generated when switching off inductive loads (such as relays), by connecting a reverse-biased diode across the inductive load. Choose the peak current for the diode to be greater than the inductive load’s operating current. Power-Supply Considerations +5V +3.3V P0 The MAX7321 can be used to drive loads, such as relays, that draw more than 20mA by paralleling outputs. Use at least one output per 20mA of load current; for example, a 5V, 330mW relay draws 66mA, and therefore, requires four paralleled outputs. Any combination of outputs can be used as part of a load-sharing design because any combination of ports can be set or cleared at the same time by writing the MAX7321. Do not exceed a total sink current of 100mA for the device. SCL Driving Load Currents Higher than 20mA I2C Port Expander with 8 Open-Drain I/Os AD2 MAX7321 PACKAGE OUTLINE NO. CODE LAND PATTERN NO. 16 QSOP E16+4 21-0055 90-0167 16 TQFN-EP T1633+4 21-0136 90-0031 Maxim Integrated │  14 I2C Port Expander with 8 Open-Drain I/Os MAX7321 Revision History REVISION NUMBER REVISION DATE 0 7/05 Initial release 1 4/06 Updates to data sheet 2 7/13 Added the I2C Flag Clearing Deassertion Anomaly section 14 3 5/14 No /V OPNs; removed automotive reference from Applications section 1 7/14 Revised the Issue: I2C Flag Clearing Deassertion Anomaly section 14 4 PAGES CHANGED DESCRIPTION — 1–17 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com. Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc. © 2014 Maxim Integrated Products, Inc. │  15