MAX77642ANA+

厂商：
AD(亚德诺)
封装：
WLP25_2.06X2.06MM
描述：
电源管理(PMIC) 2.7V~5.5V WLP25_2.06X2.06MM

数据手册：

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MAX77642ANA+ 数据手册

EVALUATION KIT AVAILABLE Click here to ask an associate for production status of specific part numbers. MAX77642/MAX77643 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output BuckBoost, 1-LDO for Long Battery Life General Description Benefits and Features The MAX77642/MAX77643 provide power supply solutions for low-power applications where size and efficiency are critical. The IC features a SIMO buck-boost regulator that provides three independently programmable power rails from a single inductor to minimize total solution size. A 150mA LDO provides ripple rejection for audio and other noise-sensitive applications. The LDO can also be configured as load switches to manage power consumption by disconnecting external blocks when not required. ● Highly Integrated • 3x Output, Single-Inductor Multiple-Output (SIMO) Buck-Boost Regulator • Supports Wide Output Voltage Range from 0.5V to 5.5V for all SIMO Channels • 1x 150mA LDO • 100mA in LSW mode • 2x GPIOs (MAX77643) • Watchdog Timer (MAX77643) The MAX77642's SIMO and LDO output voltages are individually programmable through resistors. A peak current limit input is used to set both the inductor's peak current limits of the device with a single resistor. Individual enable pins combined with the flexible resistor programmability allows the device to be tailored for many applications. ● Ultra Low-Power SIMO • 5μA Operating Current (3x SIMO Channels + 1x LDOs) • 1μA Operating Current per SIMO Channel • 0.3μA Shutdown Current • 93% Peak Efficiency in Boost-Only Mode • 91% Peak Efficiency in Buck-Only Mode • Less Than 20mVpp Output Ripple at VOUT = 1.8V • Automatic Low-Power Mode to Normal-Power Mode Transition This MAX77643's SIMO and LDO output voltages are individually programmable through I2C and in addition, includes two GPIOs with alternate modes for scalability. A bidirectional I2C serial interface allows for configuring and checking the status of the devices. An internal on/off controller provides a controlled startup sequence for the regulators and provides supervisory functionality while they are on. Numerous factory programmable options allow the device to be tailored for many applications, enabling faster time to market. Applications ● ● ● ● ● Flexible and Configurable • Ultra-Configurable Resistor Programmable Output Voltages (MAX77642) • I2C-Programmable Output Voltages (MAX77643) ● Small Size • 4.24mm2 Wafer-Level Package (WLP) • 25-Bump, 0.4mm Pitch, 5 x 5 Array Next Generation Hearables Fitness, Health, and Activity Monitors Safety and Security Monitors Portable Consumer Devices Ordering Information appears at end of data sheet. 19-100912; Rev 4; 10/21 © 2021 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. One Analog Way, Wilmington, MA 01887 U.S.A. | Tel: 781.329.4700 | © 2021 Analog Devices, Inc. All rights reserved. MAX77642/MAX77643 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output Buck-Boost, 1-LDO for Long Battery Life Applications Simplified Block Diagram MAX77643* SIMO EFFICIENCY 100 IN_SBB SYSA 2.7V TO 5.5V + DC INPUT *GPIO/nRST/NIRQ NOT SHOWN 95 PGND GND IN_LDO LXA LXB SBB0 2.0V BST SBB1 1.2V SBB2 3.3V APPLICATION PROCESSOR 90 85 VIO LDO 1.8V VOUT= 1.8V 80 75 nEN PROGRAMMABLE PUSH-BUTTON MODES EFFICIENCY (%) ULTRA CONFIGURABLE SIMO FEATURING 91% PEAK EFFICIENCY VOUT = 1.2V VSYSA = VIN_SBB = 3.7V L = 1.5µH IPEAK = 0.5A 70 0.0001 0.001 VOUT = 0.8V 0.01 0.1 IOUT (A) MAX77642 Li-Ion + SYSA GND LXA LXB BST RSET_SBB0 IN_SBB PGND IN_LDO SBB0 2.0V SBB1 1.2V SBB2 3.3V LDO 1.8V RSET_SBB1 RSET_SBB2 RSET_LDO EN0 EN1 RSET_IPK SYSTEM RESOURCES EN2 ENABLE LOGIC INPUTS ENLDO www.analog.com Analog Devices | 2 MAX77642/MAX77643 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output Buck-Boost, 1-LDO for Long Battery Life Applications MAX77643 Li-Ion + SYSA GND IN_SBB PGND IN_LDO LXA LXB SBB0 2.0V SBB1 1.2V SBB2 3.3V VIO LDO 1.8V SYSTEM RESOURCES BST VIO/POWER nEN GPIO0 GPIO1 SDA SCL nIRQ nRST www.analog.com GPIO GPIO SDA SCL nRST nIRQ APPLICATION PROCESSOR Analog Devices | 3 MAX77642/MAX77643 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output Buck-Boost, 1-LDO for Long Battery Life Applications TABLE OF CONTENTS General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Benefits and Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Simplified Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 WLP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Electrical Characteristics—Global Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Electrical Characteristics—SIMO Buck-Boost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Electrical Characteristics—Low Dropout Linear Regulator (LDO)/Load Switch (LSW) . . . . . . . . . . . . . . . . . . . . . . . . . 14 Electrical Characteristics—I2C Serial Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 MAX77642 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 MAX77643 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Part Number Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Detailed Description—Global Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Features and Benefits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Voltage Monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 SYSA POR Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 SYSA Undervoltage-Lockout Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 SYSA Overvoltage-Lockout Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Thermal Monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Chip Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 nEN Enable Input (MAX77643) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 EN Enable Input (MAX77642) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 nEN Manual Reset (MAX77643) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 nEN Triple-Functionality: Push-Button vs. Slide-Switch vs. Logic (MAX77643) . . . . . . . . . . . . . . . . . . . . . . . . . . 32 nEN Internal Pullup Resistors to VSYSA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Interrupts (nIRQ) (MAX77643) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Reset Output (nRST) (MAX77643) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 General-Purpose Input Output (GPIO) (MAX77643) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Alternate Mode (MAX77643) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 On/Off Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Top Level On/Off Controller (MAX77642) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 On/Off Controller Transition Table (MAX77642) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 www.analog.com Analog Devices | 4 MAX77642/MAX77643 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output Buck-Boost, 1-LDO for Long Battery Life Applications TABLE OF CONTENTS (CONTINUED) Top Level On/Off Controller (MAX77643) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 On/Off Controller Transition Table (MAX77643) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Internal Wake-Up Flags (MAX77643) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Reset, Off, and Auto Wake-Up Sequences (MAX77643) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Power-Up/Down Sequence (MAX77643) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Flexible Power Sequencer (FPS) (MAX77643) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Startup Timing Diagram Due to nEN (MAX77643) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Force Enabled/Disabled Channels (MAX77643) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Debounced Inputs (nEN, GPI) (MAX77643) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Watchdog Timer (WDT) (MAX77643) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Detailed Description—SIMO Buck-Boost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 SIMO Features and Benefits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 SIMO Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 SIMO Control Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Drive Strength (MAX77643) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 SIMO Output Voltage Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Peak Current Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 SIMO Soft-Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 SIMO Registers (MAX77643) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 SIMO Active Discharge Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 SIMO Buck Mode (MAX77643) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 SIMO Boost Mode (MAX77643) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 SIMO Available Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Inductor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Input Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Boost Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Output Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 SIMO Switching Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Unused Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 PCB Layout Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Input Capacitor at IN_SBB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Output Capacitors at SBBx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Inductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Ground Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Example PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Detailed Description—Low Dropout Linear Regulator (LDO)/Load Switch (LSW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Features and Benefits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 www.analog.com Analog Devices | 5 MAX77642/MAX77643 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output Buck-Boost, 1-LDO for Long Battery Life Applications TABLE OF CONTENTS (CONTINUED) LDO/LSW Simplified Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 LDO Output Voltage Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 LDO/LSW Active-Discharge Resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 LDO/LSW Soft-Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Load Switch Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Input Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Output Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Detailed Description—I2C Serial Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 I2C Simplified Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 I2C System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 I2C Interface Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 I2C Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 I2C Start and Stop Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 I2C Acknowledge Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 I2C Slave Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 I2C Clock Stretching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 I2C General Call Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 I2C Device ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 I2C Communication Speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 I2C Communication Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Writing to a Single Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Writing Multiple Bytes to Sequential Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Reading from a Single Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Reading from Sequential Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Engaging HS-Mode for Operation up to 3.4MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 MAX77643 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Register Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Typical Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Typical Applications Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 www.analog.com Analog Devices | 6 MAX77642/MAX77643 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output Buck-Boost, 1-LDO for Long Battery Life Applications LIST OF FIGURES Figure 1. Part Number Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 2. EN Pulldown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 3. nEN Usage Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 4. nEN Pullup Resistor Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 5. GPIOx Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Figure 6. Top Level On/Off Controller State Diagram (MAX77642) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Figure 7. Top Level On/Off Controller State Diagram (MAX77643) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 8. On/Off Controller Reset and Off-Action Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Figure 9. Power-Up/Down Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Figure 10. Flexible Power Sequencer Basic Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Figure 11. Startup Timing Diagram Due to nEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 12. Debounced Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Figure 13. Watchdog Timer State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Figure 14. SIMO Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Figure 15. PCB Top-Layer and Component Placement Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Figure 16. LDO Simplified Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Figure 17. LDO to LSW Transition Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Figure 18. I2C Simplified Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Figure 19. I2C System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Figure 20. I2C Start and Stop Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Figure 21. Acknowledge Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Figure 22. Slave Address Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Figure 23. Writing to a Single Register with the Write Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Figure 24. Writing to Sequential Registers X to N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Figure 25. Reading from a Single Register with the Read Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Figure 26. Reading Continuously from Sequential Registers X to N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Figure 27. Engaging HS Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Figure 28. Typical Applications Circuit - RSEL Version (MAX77642) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Figure 29. Typical Applications Circuit - I2C Version (MAX77643) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 www.analog.com Analog Devices | 7 MAX77642/MAX77643 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output Buck-Boost, 1-LDO for Long Battery Life Applications LIST OF TABLES Table 1. Regulator Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 2. Variants Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 3. OTP Options Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 4. GPIO MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 5. On/Off Controller Transition/State (MAX77642) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 6. On/Off Controller Transition/State (MAX77643) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 7. Watchdog Timer Factory-Programmed Safety Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 8. SBB0 Output Voltage Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table 9. SBB1/2 Output Voltage Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Table 10. Inductor Peak Current Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Table 11. SIMO Available Output Current for Common Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Table 12. Switching Frequency Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Table 13. LDO Output Voltage Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Table 14. I2C Slave Address Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 www.analog.com Analog Devices | 8 MAX77642/MAX77643 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output Buck-Boost, 1-LDO for Long Battery Life Applications Absolute Maximum Ratings nEN, nIRQ, nRST, RSET_SBB0, RSET_SBB1, RSET_SBB2, RSET_LDO, RSET_IPK, EN0, EN1, EN3 to GND ...........-0.3V to VSYSA + 0.3V SCL, SDA to GND ..........................................-0.3V to VIO + 0.3V VSYSA to GND ....................................................... -0.3V to +6.0V nIRQ, nRST, SDA, GPIO Continuous Current .................. ±20mA IN_SBB Continuous Current (Note 1) ............................ 1.2ARMS IN_SBB to GND ..................................................... -0.3V to +6.0V LDO to GND .......................................... -0.3V to VIN_LDO + 0.3V IN_LDO to GND ....................................... -0.3V to VSYSA + 0.3V LXA Continuous Current (Note 2) .................................. 1.2ARMS LXB Continuous Current (Note 2) .................................. 1.2ARMS SBB0, SBB1, SBB2 to PGND ............................... -0.3V to +6.0V BST to IN ............................................................... -0.3V to +6.0V BST to LXB ............................................................ -0.3V to +6.0V SBB0, SBB1, SBB2 Short-Circuit Duration .................Continuous PGND to GND........................................................ -0.3V to +0.3V Operating Temperature Range ...........................-40°C to +125°C Junction Temperature ....................................................... +150°C Storage Temperature Range ..............................-65°C to +150°C Soldering Temperature (reflow) ........................................ +260°C Continuous Power Dissipation (Multilayer Board, TA = +70°C, derate 20.4mW/°C above +70°C) ...................................1632mW GPIO0/1 to GND ........................................... -0.3V to VIO + 0.3V SYSA to GND ........................................................ -0.3V to +6.0V VIO ............................................................. -0.3V to SYSA + 0.3V Note 1: Do not repeatedly hot-plug a source to the IN terminal at a rate greater than 10Hz. Hot plugging low impedance sources results in an ~8A momentary (~2μs) current spike. Note 2: Do not externally bias LXA or LXB. LXA has internal clamping diodes to PGND and IN. LXB has an internal low-side clamping diode to PGND and an internal high-side clamping diode that dynamically connects to a selected SIMO output. It is normal for these diodes to briefly conduct during switching events. When the SIMO regulator is disabled, the LXB to PGND absolute maximum voltage is -0.3V to VSBB0 + 0.3V. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Package Information WLP Package Code N252B2+1 Outline Number 21-100480 Land Pattern Number Refer to Application Note 1891 Thermal Resistance, Four-Layer Board: Junction to Ambient (θJA) 49ºC/W (2s2p board) For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial. www.analog.com Analog Devices | 9 MAX77642/MAX77643 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output Buck-Boost, 1-LDO for Long Battery Life Applications Electrical Characteristics (VIN_SBB = VIN_LDO = VSYSA = 3.7V, VIO = 1.8V, limits are 100% production tested at TA = +25°C. Limits over the operating temperature range (TA = -40°C to +125°C) are guaranteed by design and characterization, unless otherwise noted.) PARAMETER Operating Voltage Range Shutdown Supply Current SYMBOL CONDITIONS VIN ISHDN Main Bias Quiescent Current Quiescent Supply Current MIN TYP 2.7 Current measured into IN_SBB and IN_LDO, all resources are off (LDO, SBB0, SBB1, SBB2), TA = +25°C Main bias is off; this is the standby state 0.3 IQ Main bias is in normal-power mode (CNFG_GLBL.SBIA_LPM = 0) 28 IQ Current measured into IN_SBB and IN_LDO. LDO0, SBB0, SBB1, SBB2 are enabled with no load watchdog timer disabled 4.5 Main bias is in lowpower mode (CNFG_GLBL.SBI A_LPM = 1) MAX UNITS 5.5 V 1 μA μA 11 μA Electrical Characteristics—Global Resources (VIN_SBB = VIN_LDO = VSYSA = 3.7V, limits are 100% production tested at TA = +25°C, limits over the operating temperature range (TA = -40°C to +125°C) are guaranteed by design and characterization, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS GENERAL CHARACTERISTICS Main Bias Enable Time tSBIAS_EN 0.5 ms 1.55 V 150 mV VOLTAGE MONITORS / POWER-ON RESET (POR) POR Threshold VPOR VSYSA falling POR Threshold Hysteresis VOLTAGE MONITORS / UNDERVOLTAGE LOCKOUT (UVLO) UVLO Threshold VSYSAUVLO UVLO Threshold Hysteresis VSYSAUVLO_H YS VSYSA falling, UVLO_F[3:0] = 0xA (Note 3) 2.45 TUVH[3:0] = 0x5 (Note 3) 2.6 2.73 300 V mV VOLTAGE MONITORS / OVERVOLTAGE LOCKOUT (OVLO) OVLO Threshold VSYSAOVLO VSYSA rising 5.70 5.85 6.00 V THERMAL MONITORS Overtemperature Lockout Threshold TOTLO TJ rising 145 °C Thermal Alarm Temperature 1 TJAL1 TJ rising 80 °C Thermal Alarm Temperature 2 TJAL2 TJ rising 100 °C www.analog.com Analog Devices | 10 MAX77642/MAX77643 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output Buck-Boost, 1-LDO for Long Battery Life Applications Electrical Characteristics—Global Resources (continued) (VIN_SBB = VIN_LDO = VSYSA = 3.7V, limits are 100% production tested at TA = +25°C, limits over the operating temperature range (TA = -40°C to +125°C) are guaranteed by design and characterization, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN Thermal Alarm Temperature Hysteresis TYP MAX 15 UNITS °C ENABLE INPUT (nEN, ENx) nEN Input Leakage Current InEN_LKG VnEN = VSYSA = 5.5V nEN Input Falling Threshold VTH_nEN_F nEN Falling nEN Input Rising Threshold VTH_nEN_R nEN rising TA = +25°C Voltage threshold, rising EN Input Threshold, Low VIL Voltage threshold, falling Manual Reset Time nEN Internal Pullup EN Internal Pulldown tMRST RnEN-PU REN-PD +1 ±0.01 1.4 500 CNFG_GLBL0.DBEN_nEN = 1 30 ms 3 4 5 CNFG_GLBL0.T_MRST = 0 7 8 10.5 CNFG_GLBL0.PU_ DIS = 0 200 CNFG_GLBL0.PU_ DIS = 1 10000 V μs CNFG_GLBL0.T_MRST = 1 Pullup to VSYSA V V 0.4 CNFG_GLBL0.DBEN_nEN = 0 μA V 1.4 VIH tDBNC_nEN ±0.001 0.4 EN Input Threshold, High Debounce Time -1 TA = +85°C s kΩ Pulldown to GND 50 nA OPEN-DRAIN INTERRUPT OUTPUT (nIRQ) Output Voltage Low VOL ISINK = 2mA Output Falling Edge Time tf_nIRQ CIRQ = 25pF Leakage Current InIRQ_LKG VSYSA = VIO = 5.5V nIRQ is high impedance (no interrupts) VnIRQ = 0V and 5.5V 0.4 2 TA = +25°C TA = +85°C -1 ±0.001 V ns +1 μA ±0.01 OPEN-DRAIN RESET OUTPUT (nRST) Output Voltage Low VOL ISINK = 2mA Output Falling Edge Time tf_nRST CRST = 25pF nRST Deassert Delay Time tRSTODD nRST Assert Delay Time tRSTOAD www.analog.com See Figure 11 for more information 0.4 V 2 ns 5.12 ms 10.24 ms Analog Devices | 11 MAX77642/MAX77643 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output Buck-Boost, 1-LDO for Long Battery Life Applications Electrical Characteristics—Global Resources (continued) (VIN_SBB = VIN_LDO = VSYSA = 3.7V, limits are 100% production tested at TA = +25°C, limits over the operating temperature range (TA = -40°C to +125°C) are guaranteed by design and characterization, unless otherwise noted.) PARAMETER Leakage Current SYMBOL InRST_LKG CONDITIONS VSYSA = VIO = 5.5V nRST is high impedance (no reset) VnRST = 0V and 5.5V TA = +25°C VSYS = VIO = 5.5V nRST is high impedance (no reset) VnRST = 0V and 5.5V TA = +85°C MIN TYP MAX -1 ±0.001 +1 UNITS μA ±0.01 GENERAL PURPOSE INPUT/OUTPUT (GPIO) GPIO Supply Voltage Range VIO Input Voltage Low VIL VIO = 1.8V Input Voltage High VIH VIO = 1.8V Input Leakage Current IGPI_LKG CNFG_GPIOx.DIR =1 VIO = 5.5V VGPIO = 0V and 5.5V Output Voltage Low VOL ISINK = 2mA Output Voltage High VOH ISOURCE = 1mA Input Debounce Time tDBNC_GPI Output Falling Edge Time Output Rising Edge Time V 0.3 x VIO 0.7 x VIO TA = +25°C -1 TA = +85°C V V ±0.001 +1 μA ±0.01 0.4 0.8 x VIO V V CNFG_GPIOx.DBEN_GPI = 1 30 ms tf_GPIO CGPIO = 25pF 3 ns tr_GPIO CGPIO = 25pF 3 ns 1.43 ms FLEXIBLE POWER SEQUENCER FPS Startup Delay tFPS_DLY Power-Up Event Periods tEN See Figure 10 1.28 ms Power-Down Event Periods tDIS See Figure 10 2.56 ms 3 ms RSET (MAX77642) Select Resistor Detection Time Required Select Resistor Accuracy tRSET RSEL_TOL Total time to detect all five resistors VIN_SBB = 2.7V, CRSET < 2pF Use the nearest ±1% resistor from the RSEL Selection Table. -1 +1 % Note 3: Programmed at Maxim's factory. www.analog.com Analog Devices | 12 MAX77642/MAX77643 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output Buck-Boost, 1-LDO for Long Battery Life Applications Electrical Characteristics—SIMO Buck-Boost (VIN_SBB = VIN_LDO = VSYSA = 3.7V, CSBBx = 10μF, L = 1.5μH, limits are 100% production tested at TA = +25°C, limits over the operating temperature range (TA = -40°C to +125°C) are guaranteed by design and characterization, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 5.5 V GENERAL CHARACTERISTICS / OUTPUT VOLTAGE RANGE (SBB0) Programmable Output Voltage Range 0.5 Output DAC Bits Output DAC LSB Size 0.5V to 5.5V 8 bits 25 mV GENERAL CHARACTERISTICS / OUTPUT VOLTAGE RANGE (SBB1) Programmable Output Voltage Range 0.5 Output DAC Bits Output DAC LSB Size 0.5V to 5.5V 5.5 V 8 bits 25 mV GENERAL CHARACTERISTICS / OUTPUT VOLTAGE RANGE (SBB2) Programmable Output Voltage Range 0.5 Output DAC Bits Output DAC LSB Size 0.5V to 5.5V 5.5 V 8 bits 25 mV OUTPUT VOLTAGE ACCURACY VSBBx falling, threshold where LXA switches high. Specified as a percentage of target output voltage. Output Voltage Accuracy OUT Over-Regulation Threshold VOV TA = -40°C to +125°C -2.0 +2.0 % 3.3 % TA = +25°C 1.7 Delay time from the SIMO receiving its first enable signal to when it begins to switch in order to service that output 10 μs IPK = 1A, COUT = 10μF 5.0 mV/μs TIMING CHARACTERISTICS Enable Delay Soft-Start Slew Rate dV/dtSS POWER STAGE CHARACTERISTICS TA = +25°C LXA Leakage Current SBB0, SBB1, SBB2 are disabled, VIN_SBB = 5.5V, VLXA = 0V, or 5.5V TA = +25°C LXB Leakage Current SBB0, SBB1, SBB2 are disabled, VIN_SBB = 5.5V, VLXA = 0V or 5.5V, all VSBBx = 5.5V TA = +85°C ±1.0 VIN_SBB = 5.5V, VLXB = 5.5V, VBST = 11V TA = +25°C +0.01 BST Leakage Current TA = +85°C +0.1 www.analog.com -1.0 TA = +85°C ±0.1 +1.0 μA ±1.0 -1.0 ±0.1 +1.0 μA +1.0 μA Analog Devices | 13 MAX77642/MAX77643 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output Buck-Boost, 1-LDO for Long Battery Life Applications Electrical Characteristics—SIMO Buck-Boost (continued) (VIN_SBB = VIN_LDO = VSYSA = 3.7V, CSBBx = 10μF, L = 1.5μH, limits are 100% production tested at TA = +25°C, limits over the operating temperature range (TA = -40°C to +125°C) are guaranteed by design and characterization, unless otherwise noted.) PARAMETER SYMBOL SBB0, SBB1, SBB2 are disabled, active-discharge disabled (CNFG_SBBx_B.A DE_SBBx = 0), VSBBx = 5.5V, VLXB = 0V, VSYSA = VIN_SBB = VBST = 5.5V Disabled Output Leakage Current Active Discharge Resistance CONDITIONS RAD_SBBx TYP MAX TA = +25°C +0.1 +1.0 TA = +85°C +0.2 SBB0, SBB1, SBB2 are disabled, active discharge enabled (CNFG_SBBx_B.ADE_SBBx = 1) MIN UNITS μA 60 120 180 CNFG_SBBx_B.IP_SBBx[1:0] = 0b11 -18% 0.335 +18% CNFG_SBBx_B.IP_SBBx[1:0] = 0b10 -14% 0.500 +14% CNFG_SBBx_B.IP_SBBx[1:0] = 0b01 -8% 0.750 +8% CNFG_SBBx_B.IP_SBBx[1:0] = 0b00 -7% 1.000 +7% Ω CONTROL SCHEME Peak Current Limit IP_SBB (Note 4) A Note 4: Typical values align with bench observations using the stated conditions with an inductor. Minimum and maximum values are tested in production with DC currents without an inductor. See the Typical Operating Characteristics SIMO switching waveforms to gain more insight on this specification. Electrical Characteristics—Low Dropout Linear Regulator (LDO)/Load Switch (LSW) (VIN_SBB = VIN_LDO = VSYSA = 3.7V, limits are 100% production tested at TA = +25°C, limits over the operating temperature range (TA = -40°C to +125°C) are guaranteed by design and characterization, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS LDO Input Voltage Range VIN_LDO Quiescent Supply Current IIN_LDO Quiescent Supply Current In Dropout IIN_DRP_LDO LDO mode 1.71 5.5 Switch mode 1.2 5.5 IOUT_LDOx = 0 1.4 2.4 IOUT_LDOx = 0, switch mode 0.5 1.2 IOUT_LDOx = 0, VIN_LDOx = 2.9V, VLDOx = 3V 2.1 4.6 VIN_LDOx > 1.8V 150 VIN_LDOx = 1.8V or lower 100 V µA µA Maximum Output Current IOUT_LDO Output Voltage (MAX77642) VOUT_LDO 0.5 3.975 V Output Voltage (MAX77643) VOUT_LDO 0.5 5.0 V -3.1 +3.1 % 100 mV VIN_LDOx = (VOUT_LDOx + 0.5V) or higher, IOUT_LDOx = 1mA Output Accuracy Dropout Voltage www.analog.com VDRP_LDO VIN_LDOx = 3V, LDOx programmed to 3V, IOUT_LDOx = 100mA mA Analog Devices | 14 MAX77642/MAX77643 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output Buck-Boost, 1-LDO for Long Battery Life Applications Electrical Characteristics—Low Dropout Linear Regulator (LDO)/Load Switch (LSW) (continued) (VIN_SBB = VIN_LDO = VSYSA = 3.7V, limits are 100% production tested at TA = +25°C, limits over the operating temperature range (TA = -40°C to +125°C) are guaranteed by design and characterization, unless otherwise noted.) CONDITIONS MIN Line Regulation PARAMETER SYMBOL VIN_LDOx = (VOUT_LDOx + 0.5 V) to 5.5V -0.5 Load Regulation VIN_LDOx = 1.8V or higher, IOUT_LDOx = 100μA to 100mA Line Transient VIN_LDOx = 4V to 5V, 5µs rise time ± 35 IOUT_LDOx = 100μA to 10mA, 200ns rise time 100 IOUT_LDOx = 100μA to 100mA, 200ns rise time 200 Load Transient Active Discharge Resistance RAD_LDO Switch Mode OnResistance RON_LDO Slew Rate Short Circuit Current Limit Output Noise TYP 0.001 MAX UNITS +0.5 %/V 0.005 %/mA mV mV 42 80 200 VIN_LDOx = 2.7V, IOUT_LDOx = 100mA 0.5 VIN_LDOx = 1.8V, IOUT_LDOx = 50mA 0.8 VIN_LDOx = 1.2V, IOUT_LDOx = 5mA 1.2 IOUT_LDO = 0mA, time from 10% to 90% of final register value, COUT_LDO = 1μF 2.2 IOUT_LDO = 0mA, time from 10% to 90% of final register value, COUT_LDO = 1μF, switch mode 2.2 Ω Ω V/ms VIN_LDOx = 2.7V, VOUT_LDOx = GND 230 550 VIN_LDOx = 2.7V, VOUT_LDOx = 2.55V, switch mode 230 550 10Hz to 100kHz, VIN_LDOx = 5V, VOUT_LDOx = 3.3V 150 10Hz to 100kHz, VIN_LDOx = 5V, VOUT_LDOx = 2.5V 125 10Hz to 100kHz, VIN_LDOx = 5V, VOUT_LDOx = 1.2V 90 10Hz to 100kHz, VIN_LDOx = 5V, VOUT_LDOx = 0.9V 80 880 mA µVRMS Output DAC Bits 8 bits Output DAC LSB Size 25 mV Electrical Characteristics—I2C Serial Communication (VIN = 3.7V, VIO = 1.8V, limits are 100% production tested at TA = +25°C, limits over the operating temperature range (TA = -40°C to +125°C) are guaranteed by design and characterization, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 1.7 1.8 3.6 V VIO = 3.6V, VSDA = VSCL = 0V or 3.6V, TA = +25°C -1 0 +1 VIO = 1.7V, VSDA = VSCL= 0V or 1.7V -1 0 +1 POWER SUPPLY VIO Voltage Range VIO Bias Current www.analog.com VIO μA Analog Devices | 15 MAX77642/MAX77643 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output Buck-Boost, 1-LDO for Long Battery Life Applications Electrical Characteristics—I2C Serial Communication (continued) (VIN = 3.7V, VIO = 1.8V, limits are 100% production tested at TA = +25°C, limits over the operating temperature range (TA = -40°C to +125°C) are guaranteed by design and characterization, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SDA AND SCL I/O STAGE SCL, SDA Input High Voltage VIH VIO = 1.7V to 3.6V SCL, SDA Input Low Voltage VIL VIO = 1.7V to 3.6V SCL, SDA Input Hysteresis VHYS SCL, SDA Input Leakage Current II SDA Output Low Voltage VOL SCL, SDA Pin Capacitance Output Fall Time from VIH to VIL 0.7 x VIO V 0.3 x VIO 0.05 x VIO VIO = 3.6V, VSCL = VSDA = 0V and 3.6V -10 Sinking 20mA CI V +10 μA 0.4 V 10 tOF (Note 5) V pF 120 ns 1000 kHz I2C COMPATIBLE INTERFACE TIMING (STANDARD, FAST AND FAST MODE PLUS) (Note 5) Clock Frequency Hold Time (REPEATED) START Condition fSCL 0 tHD_STA 0.26 μs SCL Low Period tLOW 0.5 μs SCL High Period tHIGH 0.26 μs Setup Time REPEATED START Condition tSU_STA 0.26 μs Data Hold Time tHD_DAT 0 μs Data Setup Time tSU_DAT 50 ns Setup Time for STOP Condition tSU_STO 0.26 μs Bus Free Time between STOP and START Condition tBUF 0.5 μs Pulse Width of Suppressed Spikes tSP Maximum pulse width of spikes that must be suppressed by the input filter 50 ns I2C COMPATIBLE INTERFACE TIMING (HIGH-SPEED MODE, CB = 100pF) (Note 5) Clock Frequency fSCL 3.4 MHz Setup Time REPEATED START Condition tSU_STA 160 ns Hold Time (REPEATED) START Condition tHD_STA 160 ns SCL Low Period tLOW 160 ns SCL High Period tHIGH 60 ns Data Setup Time tSU_DAT 10 Data Hold Time tHD_DAT 0 70 ns SCL Rise Time trCL 10 40 ns www.analog.com TA = +25°C ns Analog Devices | 16 MAX77642/MAX77643 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output Buck-Boost, 1-LDO for Long Battery Life Applications Electrical Characteristics—I2C Serial Communication (continued) (VIN = 3.7V, VIO = 1.8V, limits are 100% production tested at TA = +25°C, limits over the operating temperature range (TA = -40°C to +125°C) are guaranteed by design and characterization, unless otherwise noted.) PARAMETER SYMBOL Rise Time of SCL Signal After REPEATED START Condition and After Acknowledge Bit trCL1 TA = +25°C SCL Fall Time tfCL SDA Rise Time SDA Fall Time Setup Time for STOP Condition Bus Capacitance Pulse Width of Suppressed Spikes CONDITIONS MAX UNITS 10 80 ns TA = +25°C 10 40 ns trDA TA = +25°C 10 80 ns tfDA TA = +25°C 10 80 ns tSU_STO MIN TYP 160 ns CB tSP 100 Maximum pulse width of spikes that must be suppressed by the input filter 10 pF ns I2C COMPATIBLE INTERFACE TIMING (HIGH-SPEED MODE, CB = 400pF) (Note 5) Clock Frequency fSCL 1.7 MHz Setup Time REPEATED START Condition tSU_STA 160 ns Hold Time (REPEATED) START Condition tHD_STA 160 ns tLOW 320 ns SCL High Period tHIGH 120 ns Data Setup Time tSU_DAT 10 ns Data Hold Time tHD_DAT 0 150 ns SCL Rise Time tRCL TA = +25°C 20 80 ns Rise Time of SCL Signal After REPEATED START Condition and After Acknowledge Bit tRCL1 TA = +25°C 20 80 ns SCL Fall Time tFCL TA = +25°C 20 80 ns SDA Rise Time tRDA TA = +25°C 20 160 ns SDA Fall Time tFDA TA = +25°C 20 160 ns SCL Low Period Setup Time for STOP Condition tSU_STO Bus Capacitance CB Pulse Width of Suppressed Spikes tSP 160 ns 400 Maximum pulse width of spikes that must be suppressed by the input filter 10 pF ns Note 5: Design guidance only. Not production tested. www.analog.com Analog Devices | 17 MAX77642/MAX77643 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output Buck-Boost, 1-LDO for Long Battery Life Applications Typical Operating Characteristics (Typical Applications Circuit. VSYSA = 3.7V, VIO = 1.8V, TA = +25°C, unless otherwise noted. Inductor = DFE201612E-1R5M, 1.5μH, 72mΩ) www.analog.com Analog Devices | 18 MAX77642/MAX77643 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output Buck-Boost, 1-LDO for Long Battery Life Applications Typical Operating Characteristics (continued) (Typical Applications Circuit. VSYSA = 3.7V, VIO = 1.8V, TA = +25°C, unless otherwise noted. Inductor = DFE201612E-1R5M, 1.5μH, 72mΩ) www.analog.com Analog Devices | 19 MAX77642/MAX77643 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output Buck-Boost, 1-LDO for Long Battery Life Applications Typical Operating Characteristics (continued) (Typical Applications Circuit. VSYSA = 3.7V, VIO = 1.8V, TA = +25°C, unless otherwise noted. Inductor = DFE201612E-1R5M, 1.5μH, 72mΩ) www.analog.com Analog Devices | 20 MAX77642/MAX77643 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output Buck-Boost, 1-LDO for Long Battery Life Applications Typical Operating Characteristics (continued) (Typical Applications Circuit. VSYSA = 3.7V, VIO = 1.8V, TA = +25°C, unless otherwise noted. Inductor = DFE201612E-1R5M, 1.5μH, 72mΩ) www.analog.com Analog Devices | 21 MAX77642/MAX77643 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output Buck-Boost, 1-LDO for Long Battery Life Applications Typical Operating Characteristics (continued) (Typical Applications Circuit. VSYSA = 3.7V, VIO = 1.8V, TA = +25°C, unless otherwise noted. Inductor = DFE201612E-1R5M, 1.5μH, 72mΩ) www.analog.com Analog Devices | 22 MAX77642/MAX77643 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output Buck-Boost, 1-LDO for Long Battery Life Applications Pin Configurations MAX77642 TOP VIEW (BUMP SIDE DOWN) MAX77642 1 2 4 5 SYSA RSET_SBB2 RSET_SBB1 LDO IN_LDO SYSA RSET_LDO RSET_SBB0 GND GND ENLDO RSET_IPK SBB1 LXB SBB0 EN1 EN0 SBB2 LXB BST EN2 GND IN_SBB LXA PGND + 3 A B C D E WLP (2.06mm x 2.06mm X 0.5mm, 0.4mm Pitch) www.analog.com Analog Devices | 23 MAX77642/MAX77643 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output Buck-Boost, 1-LDO for Long Battery Life Applications MAX77643 TOP VIEW (BUMP SIDE DOWN) MAX77643 1 2 4 5 VIO SCL SDA LDO IN_LDO SYSA GPIO0 NC GND GND NC GPIO1 SBB1 LXB SBB0 nIRQ nEN SBB2 LXB BST nRST GND IN_SBB LXA PGND + 3 A B C D E WLP (2.06mm x 2.06mm x 0.5mm, 0.4mm Pitch) www.analog.com Analog Devices | 24 MAX77642/MAX77643 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output Buck-Boost, 1-LDO for Long Battery Life Applications Pin Description PIN MAX77642 MAX77643 NAME FUNCTION TYPE TOP LEVEL — A1 VIO I2C Interface and GPIO Driver Power Power Input — D2 nEN Active-Low Enable Input. EN supports push-button or slide-switch configurations. If not used, connect nEN to SYS and use the CNFG_SBBx_B.EN_SBBx[2:0] and CNFG_LDO_B.EN_LDO[2:0] bitfields to enable channels. Digital Input — D1 nIRQ Active-Low, Open-Drain Interrupt Output. Connect a 100kΩ pullup resistor between IRQ and a voltage equal to or less than VSYSA. Digital Output — E1 nRST Active-Low, Open-Drain Reset Output. Connect a 100kΩ pullup resistor between nRST and a voltage equal to or less than VSYSA. Digital Output — C2 GPIO1 General Purpose Input/Output. The GPIO I/O stage is internally biased with VIO. Digital I/O — B2 GPIO0 General Purpose Input/Output. The GPIO I/O stage is internally biased with VIO. Digital I/O — A2 SCL I2C Clock Digital Input — A3 SDA I2C Data Digital I/O B4, B5, E2 B4, B5, E2 GND Quiet Ground. Connect GND to PGND, and the low-impedance ground plane of the PCB. Ground A2 — RSET_SBB2 Select Resistor Pin SBB2. Connect a resistor from this pin to GND, using the value to configure the output voltage of SBB2. Resistor Input A3 — RSET_SBB1 Select Resistor Pin SBB1. Connect a resistor from this pin to GND, using the value to configure the output voltage of SBB1. Resistor Input B3 — RSET_SBB0 Select Resistor Pin SBB0. Connect a resistor from this pin to GND, using the value to configure the output voltage of SBB0. Resistor Input B2 — RSET_LDO Select Resistor Pin LDO. Connect a resistor from this pin to GND, using the value to configure the output voltage of LDO0. Resistor Input C2 — RSET_IPK Select Resistor Pin IPK. Connect a resistor from this pin to GND, using the value to configure the peak inductor current. Resistor Input D2 — EN0 Enable Input for SBB0. Hold high to enable output regulation. Hold low to disable the output. Digital Input D1 — EN1 Enable Input for SBB1. Hold high to enable output regulation. Hold low to disable the output. Digital Input E1 — EN2 Enable Input for SBB2. Hold high to enable output regulation. Hold low to disable the output. Digital Input — C1, B3 NC Not Connected No Connect Digital Input — ENLDO Enable Input for LDO. Hold high to enable output regulation. Hold low to disable the output. C5 C5 SBB0 SIMO Buck-Boost Output 0. SBB0 is the power output for channel 0 of the SIMO buck-boost. Bypass SBB0 to PGND with a 10μF ceramic capacitor. If not used, see the Unused Outputs section. Power Output C3 C3 SBB1 SIMO Buck-Boost Output 1. SBB1 is the power output for channel 1 of the SIMO buck-boost. Bypass SBB1 to PGND with a 10μF ceramic capacitor. If not used, see the Unused Outputs section. Power Output C1 SIMO BUCK-BOOST www.analog.com Analog Devices | 25 MAX77642/MAX77643 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output Buck-Boost, 1-LDO for Long Battery Life Applications Pin Description (continued) PIN NAME FUNCTION TYPE D3 SBB2 SIMO Buck-Boost Output 2. SBB2 is the power output for channel 2 of the SIMO buck-boost. Bypass SBB0 to PGND with a 10μF ceramic capacitor. If not used, see the Unused Outputs section. Power Output D5 D5 BST SIMO Power Input for the High-Side Output NMOS Drivers. Connect a 10nF ceramic capacitor between BST and LXB. Power Input C4, D4 C4, D4 LXB Switching Node B. LXB is driven between PGND and SBBx when SBBx is enabled. LXB is driven to PGND when all SIMO channels are disabled. Connect a 1.5μH inductor between LXA and LXB. Power Input Switching Node A. LXA is driven between PGND and IN_SBB when any SIMO channel is enabled. LXA is driven to PGND when all SIMO channels are disabled. Connect a 1.5μH inductor between LXA and LXB. Power I/O MAX77642 MAX77643 D3 E4 E4 LXA E5 E5 PGND Power Ground for the SIMO Low-Side FETs. Connect PGND to GND, and the low-impedance ground plane of the PCB. A1, B1 B1 SYSA Analog Input Supply. Connect to VIN_SBB. Power Input IN_SBB SIMO Power Input. Connect IN_SBB to SYSA and bypass to PGND with a minimum of 10μF ceramic capacitor as close as possible to the IN_SBB pin. Power Input Linear Regulator Input. If connected to a SIMO output with a short trace, IN_LDO can share the output's capacitor. Otherwise, bypass with a 2.2μF ceramic capacitor to ground. If not used, connect to ground or leave unconnected. Power Input E3 E3 Ground LDO A5 A5 IN_LDO A4 A4 LDO www.analog.com Linear Regulator Output. Bypass with a 1.0μF ceramic capacitor to GND. If not used, disable LDO and connect this pin to ground or leave unconnected. Power Output Analog Devices | 26 MAX77642/MAX77643 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output Buck-Boost, 1-LDO for Long Battery Life Applications Detailed Description The MAX77642/MAX77643 provide highly-integrated power management solutions for low-power applications. Four regulators are integrated within this device (see Table 1). A single-inductor, multiple output (SIMO) buck-boost regulator efficiently provides three independently programmable power rails. A 150mA low-dropout linear regulator (LDO) provides ripple rejection for audio and other noise sensitive applications. The MAX77643 includes other features such as two GPIOs with alternate modes for various system requirements. A bidirectional I2C serial interface allows for configuring and checking the status of the device. An internal on/off controller provides regulator sequencing and supervisory functionality for the device. Table 1. Regulator Summary REGULATOR NAME REGULATOR TOPOLOGY SBB0 SIMO SBB1 SIMO SBB2 SIMO LDO PMOS LDO MAXIMUM IOUT (mA) Up to 500* 150 VIN RANGE (V) MAX77643 VOUT RANGE/ RESOLUTION 2.7 to 5.5 0.5V to 5.5V in 25mV steps 2.7 to 5.5 0.5V to 5.5V in 25mV steps 2.7 to 5.5 0.5V to 5.5V in 25mV steps 1.7 to 5.5 0.5V to 5.0V in 25mV steps *Shared capacity with other SBBx channels. See the SIMO Available Output Current section for more information. Part Number Decoding The MAX77643 has different one-time programmable (OTP) options and variants to support a variety of applications. The OTP options set default settings such as output voltage. Variants are versions of the MAX77643 with different features. See Figure 1 for how to identify these. Table 2 and Table 3 list all available OTP options and variants. Refer to Maxim Products Naming Convention for more details. MAX77643 x A N A + T BASE PART NUMBER OTP OPTION OPERATING TEMP. RANGE TAPE-AND-REEL LEAD-FREE (RoHS) PACKAGE TYPE NUMBER OF PINS Figure 1. Part Number Decode Table 2. Variants Table www.analog.com PART NUMBER MAX77642 MAX77643 Resistor Programmable Output Voltages Yes No Resistor Programmable Peak Current Yes No Supports LDO/LSW Yes Yes Include GPIOs No Yes Individual Enable Pins for LDO and SIMO Outputs Yes No Analog Devices | 27 MAX77642/MAX77643 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output Buck-Boost, 1-LDO for Long Battery Life Applications Table 2. Variants Table (continued) PART NUMBER MAX77642 MAX77643 Programmable Flexible Power Sequencer No Yes Watchdog Timer No Yes Supports I2C Serial Communication No Yes Table 3. OTP Options Table OTP LETTER AND SETTINGS BLOCK Global BIT FIELD NAME A B C E D S PU_DIS nEN Internal, Strong Pullup Disable Weak (10MΩ) Weak (10MΩ) Weak (10MΩ) Weak (10MΩ) Weak (10MΩ) Weak (10MΩ) MRST Manual Reset Time 4s 4s 4s 4s 4s 4s SBIA_LPM Bias Power Mode LowPower Mode LowPower Mode LowPower Mode LowPower Mode LowPower Mode LowPower Mode nEN_MODE On-Key Default Configuration LogicMode LogicMode LogicMode LogicMode LogicMode LogicMode DBEN_nEN Debounce Timer for nEN 500μs 500μs 500μs 500μs 500μs 500μs ALT_GPIO0 GPIO0 Mode GPIO GPIO GPIO GPIO GPIO Alt. ALT_GPIO1 GPIO1 Mode GPIO GPIO GPIO GPIO GPIO GPIO ADDR I2C Address (7-bit) 0x48 0x4C 0x44 0x40 0x48 0x48 UVLO_F[3:0] UVLO Falling 2.6V 2.6V 2.6V 2.6V 2.6V 2.6V UVLO_H[3:0] UVLO Hysteresis 0.3V 0.3V 0.3V 0.3V 0.3V 0.3V CID[4:0] Chip ID 0x02 0x7 0x8 0x9 0xB 0x05 WDT_LOCK Watchdog Timer Disable Control Unlocked Unlocked Unlocked Unlocked Unlocked Unlocked WDT_EN Watchdog Timer Enable Disabled Disabled Disabled Disabled Disabled Disabled TV_SBB0[7:0] SBB0 VOUT 3.050V 1.200V 1.200V 2.500V 3.050V 0.650V IP_SBB0[1:0] SBB0 Inductor Current Peak Limit 0.750A 0.333A 0.333A 0.333A 0.750A 0.333A OP_MODE[1:0] (SBB0) SBB0 Operating Mode BuckBoost Buck Buck Buck Buck BuckBoost ADE_SBB0 Active-Discharge Resistor Enable Enabled Enabled Enabled Enabled Enabled Enabled EN_SBB0[2:0] SBB0 Enable Control FPS Slot 0 Off Off Off Off FPS Slot 1 TV_SBB1[7:0] SBB1 VOUT 1.800V 2.500V 2.500V 1.100V 1.800V 0.800V IP_SBB1[1:0] SBB1 Inductor Current Peak Limit 0.333A 0.333A 0.333A 0.500A 0.333A 0.333A OP_MODE[1:0] (SBB1) SBB1 Operating Mode BuckBoost Buck Buck Buck BuckBoost Buck ADE_SBB1 Active-Discharge Resistor Enable Enabled Enabled Enabled Enabled Enabled Enabled EN_SBB1[2:0] SBB1 Enable Control On Off Off Off On FPS Slot 2 TV_SBB2[7:0] SBB2 VOUT 1.200V 1.500V 1.500V 1.500V 1.075V 1.800V Watchdog SIMO SETTING NAME www.analog.com Analog Devices | 28 MAX77642/MAX77643 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output Buck-Boost, 1-LDO for Long Battery Life Applications Table 3. OTP Options Table (continued) OTP LETTER AND SETTINGS LDO IP_SBB2[1:0] SBB2 Inductor Current Peak Limit OP_MODE[1:0] (SBB2) SBB2 Operating Mode ADE_SBB2 Active-Discharge Resistor Enable EN_SBB2[2:0] 0.333A 0.333A 0.333A 0.333A 0.500A 0.333A BuckBoost Buck Buck Buck BuckBoost Buck Enabled Enabled Enabled Enabled Enabled Enabled SBB2 Enable Control FPS Slot 2 Off Off Off Off FPS Slot 0 TV_OFS_LDO LDO VOUT Offset No Offset No Offset No Offset No Offset No Offset No Offset TV_LDO[6:0] LDO VOUT 2.800V 1.800V 1.800V 1.800V 2.825V 1.800V LDO_MD LDO or LSW Mode LDO LDO LDO LDO LDO LDO ADE_LDO Active-Discharge Resistor Enable Enabled Enabled Enabled Enabled Enabled Enabled EN_LDO[2:0] LDO Enable Control FPS Slot 1 On On On Off FPS Slot 3 www.analog.com Analog Devices | 29 MAX77642/MAX77643 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output Buck-Boost, 1-LDO for Long Battery Life Applications Detailed Description—Global Resources The global resources encompass a set of circuits that serve the entire device and ensure safe, consistent, and reliable operation. Features and Benefits ● Voltage Monitors • IN power-on-reset (POR) comparator generates a reset signal upon power-up • IN undervoltage ensures repeatable behavior when power is applied to and removed from the device • IN overvoltage monitor inhibits operation with overvoltage power sources to ensure reliability in faulty environments ● Thermal Monitors • +145°C junction temperature shutdown ● Manual Reset • 4s or 8s period ● Wake-Up Events • nEN input assertion ● Interrupt Handler • Interrupt output (nIRQ) • All interrupts are maskable ● Push-Button/Slide-Switch/Logic Mode On-Key (nEN) • Configurable push-button/slide-switch functionality • 500μs or 30ms debounce timer interfaces directly with mechanical switches ● On/Off Controller • Startup/shutdown sequencing • Programmable sequencing delay ● GPIO, nRST Digital I/Os Voltage Monitors The device monitors the system voltage (VSYSA) to ensure proper operation using three comparators (POR, UVLO, and OVLO). These comparators include hysteresis to prevent their outputs from toggling between states during noisy system transitions. SYSA POR Comparator The SYSA POR comparator monitors VSYSA and generates a power-on reset (POR) signal. When VSYSA is below VPOR, the device is held in reset (SYSARST = 1). When VSYSA rises above VPOR, internal signals and on-chip memory stabilize and the device is released from reset (SYSRST = 0). SYSA Undervoltage-Lockout Comparator The SYSA undervoltage-lockout (UVLO) comparator monitors VSYSA and generates a SYSAUVLO signal when the VSYSA falls below UVLO threshold. The SYSAUVLO signal is provided to the top-level digital controller. See Figure 6, Table 5, Figure 7, and Table 6 for additional information regarding the UVLO comparator. SYSA Overvoltage-Lockout Comparator The device is rated for 5.5V maximum operating voltage (VSYSA) with an absolute maximum input voltage of 6.0V. An overvoltage-lockout monitor increases the robustness of the device by inhibiting operation when the supply voltage is greater than VSYSAOVLO. See Figure 6, Table 5, Figure 7, and Table 6 for additional information regarding the OVLO comparator. Thermal Monitors The MAX77643 has three global on-chip thermal sensors: www.analog.com Analog Devices | 30 MAX77642/MAX77643 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output Buck-Boost, 1-LDO for Long Battery Life Applications ● Junction Temperature Alarm 1 → 80°C ● Junction Temperature Alarm 2 → 100°C ● Junction Temperature Shutdown → 145°C The junction temperature alarms have maskable rising interrupts as well as status bits (see the Register Map section for more information). Unmasking these thermal alarms is recommended for all systems. If the first alarm is triggered, the system software should attempt to lower system power dissipation. If the second alarm is triggered, then attempts to lower the power dissipation were unsuccessful and the system software should turn the device off. Finally, if the junction temperature rises to junction temperature shutdown, then the MAX77643 sets the ERCFLAG.TOVLD bit and automatically turns itself off. After a junction temperature shutdown event, the system can be enabled again. The system software can read the ERCFLAG register during initialization to see ERCFLAG.TOVLD = 1 and log that an extreme thermal event has occurred. Chip Identification The MAX77643 offers different one-time-programmable (OTP) options to, for example, set the default output voltages. These options are identified by the chip identification number, which can be read in the CID register. nEN Enable Input (MAX77643) The nEN is an active-low internally debounced digital input that typically comes from the system’s on-key. The debounce time is programmable with CNFG_GLBLx.DBEN_nEN. The primary purpose of this input is to generate a wake-up signal for the PMIC that turns on the regulators. Maskable rising/falling interrupts are available for nEN (INT_GLBLx.nEN_R and INT_GLBLx.nEN_F) for alternate functionality. The nEN input can be configured to work either with a push-button (CNFG_GLBL0.nEN_MODE = 0b00), a slideswitch (CNFG_GLBL0.nEN_MODE = 0b01), or Logic Mode (CNFG_GLBL0.nEN_MODE = 0b10). See Figure 3 for more information. In both push-button mode and slide-switch mode, the on/off controller looks for a falling edge on the nEN input to initiate a power-up sequence. EN Enable Input (MAX77642) The MAX77642 features three enable pins to individually control the on/off state of the SIMO outputs. Drive each enable pin high to turn its respective SIMO output on. Each enable pin has a 50nA pulldown current to ground (as shown in Figure 2). The pins can be tied high for always on-applications. Do not leave the EN pins unconnected. Logic EN 50nA Figure 2. EN Pulldown nEN Manual Reset (MAX77643) The nEN works as a manual reset input when the on/off controller is in the "Resource-On" state. The manual reset function is useful for forcing a power-down in case communication with the processor fails. When nEN is configured for www.analog.com Analog Devices | 31 MAX77642/MAX77643 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output Buck-Boost, 1-LDO for Long Battery Life Applications push-button mode and the input is asserted (nEN = LOW) for an extended period (tMRST), the on/off controller initiates a power-down sequence and goes to shutdown mode. When nEN is configured for slide-switch mode and the input is deasserted (nEN = HIGH) for an extended period (tMRST), the on/off controller initiates a power-down sequence and goes to standby mode. When nEN is configured as a logic mode, the on/off controller initiates a power-up sequence and goes into Resource ON mode when the input is asserted (nEN = LOW). When the input is deasserted (nEN = LOW), the on/off controller initiates a power-down sequence and goes into shutdown mode. nEN Triple-Functionality: Push-Button vs. Slide-Switch vs. Logic (MAX77643) The nEN digital input can be configured to work with a push-button, a slide-switch, or a logic input. Figure 3 shows nEN's triple functionality for power-on sequencing and manual reset. The default configuration of the device is push-button mode (CNFG_GLBL0.nEN_MODE = 0b00) and no additional programming is necessary. Applications that use a slideswitch on-key and logic configuration must set CNFG_GLBL0.nEN_MODE = 0b01 and CNFG_GLBL0.nEN_MODE = 0b10 respectively within tMRST. NOT DRAWN TO SCALE STATE SHUTDOWN POWER-ON SEQUENCE RESOURCE ON POWER-DOWN SEQUENCE INPUT VOLTAGE APPLIED VIN MAX77643 IN tDBNC_nEN nEN tDBNC_nEN tDBNC_nEN tMRST PUSH-BUTTON MODE MAX77643 IN tDBNC_nEN nEN tMRST tDBNC_nEN SLIDE-SWITCH MODE MAX77643 DRIVEN BY LOGIC SIGNAL nEN LOGIC MODE MAX77642 DRIVEN BY LOGIC SIGNAL ENx LOGIC MODE Figure 3. nEN Usage Timing Diagram www.analog.com Analog Devices | 32 MAX77642/MAX77643 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output Buck-Boost, 1-LDO for Long Battery Life Applications nEN Internal Pullup Resistors to VSYSA The nEN logic thresholds are referenced to VSYSA. There are internal pullup resistors between nEN and VSYSA (RnEN_PU), which can be configured with the CNFG_GLBL0.PU_DIS bit. See Figure 4. While PU_DIS = 0, the pullup value is approximately 200kΩ. While PU_DIS = 1, the pullup value is 10MΩ. Applications using a slide-switch on-key or push-pull digital output connected to nEN can reduce quiescent current consumption by changing pullup strength to 10MΩ. Applications using normally-open, momentary, and push-button onkeys (as shown in Figure 4) do not create this leakage path and should use the stronger 200kΩ pullup option. VCCINT 10MΩ 200kΩ ON-KEY SWITCH CONTROL PU_DIS SWITCH 0b0 CLOSED 0b1 OPEN RnEN nEN__PU ~200kΩ 10MΩ nEN Figure 4. nEN Pullup Resistor Configuration Interrupts (nIRQ) (MAX77643) The nIRQ (MAX77643) is an active-low, open-drain output that is typically routed to the host processor's interrupt input to signal an important change in device status. See the Register Map section for a comprehensive list of all interrupt bits and status registers. A pullup resistor to a voltage less than or equal to VSYSA is required for this node. The nIRQ is the logical NOR of all unmasked interrupt bits in the register map. All interrupts are masked by default. Masked interrupt bits do not cause the nIRQ pin to change. Unmask the interrupt bits to allow the nIRQ to assert. Reset Output (nRST) (MAX77643) The nRST (MAX77643) is an open-drain, active-low output that is typically used to hold the processor in a reset state when the device is powered down. During a power-up sequence, the nRST deasserts after the last regulator in the power-up chain is enabled (tRSTODD). During a power-down sequence, the nRST output asserts before any regulator is powered down (tRSTOAD). See Figure 11 for nRST timing. A pullup resistor to a voltage less than or equal to VSYSA is required for this node. www.analog.com Analog Devices | 33 MAX77642/MAX77643 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output Buck-Boost, 1-LDO for Long Battery Life Applications General-Purpose Input Output (GPIO) (MAX77643) The MAX77643 provides two general-purpose input/output (GPIO) pins increase system flexibility. See Figure 5 for more details. Clear CNFG_GPIOx.DIR = 0b0 to configure GPIO as a general-purpose output (GPO). The GPO can either be in pushpull mode (CNFG_GPIOx.DRV = 1) or open-drain mode (CNFG_GPIOx.DRV = 0). ● The push-pull output mode is ideal for applications that need fast (~2ns) edges and low power consumption. ● The open-drain mode requires an external pullup resistor (typically 10kΩ to 100kΩ). Connect the external pullup resistor to a bias voltage that is less than or equal to VIO. • The open-drain mode can be used to communicate to different logic domains. For example, to send a signal from the GPO on a 1.8V logic domain (VIO = 1.8V) to a device on a 1.2V logic domain, connect the external pullup resistor to 1.2V. • The open-drain mode can be used to connect several open-drain (or open-collector) devices together on the same bus to create wired logic (wired AND logic is positive-true; wired OR logic is negative-true). ● The general-purpose input (GPI) functions are still available while the pin is configured as a GPO. In other words, the CNFG_GPIOx.DI (input status) bit still functions and does not collide with the state of the CNFG_GPIOx.DIR bit. Set CNFG_GPIOx.DIR to have the GPIO function as a GPI. The GPI features a 30ms debounce timer (tDBNC_GPI) that can be enabled or disabled with DBEN_GPI. ● Enable the debounce timer (CNFG_GPIOx.DBEN_GPI = 1) if the GPI is connected to a device that can bounce or chatter, like a mechanical switch. ● If the GPI is connected to a circuit with clean logic transitions and no risk of bounce, disable the debounce timer (CNFG_GPIOx.DBEN_GPI = 0) to eliminate logic delays. With no debounce timer, the GPI input logic propagates to nIRQ in 10ns. A dedicated internal oscillator is used to create the 30ms (tDBNC_GPI) debounce timer. To obtain low VIO supply current, ensure the GPIO voltage is either logic high or logic low. If the GPIO pin is unconnected (either as a GPI or an open-drain GPO) and VIO is powered, the GPIO voltage trends towards the logic level gray area (0.3 x VIO < VGPIO < 0.7 x VIO). If VGPIO is in the gray area, VIO current can be more than 10μA. The GPI features edge detectors that feed into the the top-level interrupt system of the chip. This allows software to use interrupts to service events associated with a GPI change instead of polling for these changes. ● If the application wants nIRQ to go low only on a GPI rising edge, then it should clear the GPI rising edge interrupt mask bit (INTM_GLBLx.GPI_RM = 0) and set the GPI falling edge interrupt mask bit (INTM_GLBLx.GPI_FM = 1). ● If the application wants nIRQ to go low only on a GPI falling edge, then it should set the GPI rising edge interrupt mask bit (INTM_GLBLx.GPI_RM = 1) and clear the GPI falling edge interrupt mask bit (INTM_GLBLx.GPI_FM = 0). ● If the application wants nIRQ to go low on both GPI falling and rising edges, then it should clear the GPI rising edge interrupt mask bit (INTM_GLBLx.GPI_RM = 0) and clear the GPI falling edge interrupt mask bit (INTM_GLBLx.GPI_FM = 0). www.analog.com Analog Devices | 34 MAX77642/MAX77643 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output Buck-Boost, 1-LDO for Long Battery Life Applications SYSA COMM CNFG_GPIOx DRVx DIRx DOx GPIx_RM GPIx_FM DBNC_EN DIx GPIx_R GPIx_F GPIx_R GPIx_RM nIRQ Q VIO DBNC_EN R IRQ OTHER nIRQ ASSERTION SOURCES NOT SHOWN GPIx_FM GPIx_F DRVx D 1 Q READ (GPIx_R) DIx 0 1 30ms DEBOUNCE (tDBNC_GPI) DIRx DOx D 1 R GPIOx LOGIC READ (GPIx_F) GND Figure 5. GPIOx Block Diagram Alternate Mode (MAX77643) The GPIO in the MAX77643 can be configured to have a different function. Whether the GPIO is in GPIO mode or alternate mode can be checked by reading the CNFG_GPIOx.ALT_GPIOx bit. Table 4 summarizes the alternate functions for each GPIO. Table 4. GPIO MODE CNFG_GPIOx REGISTER GPIOx ALT_GPIOx = 0 ALT_GPIOx = 1 GPIO0 Standard GPIO Active-high input, controls the DVS feature for SBB0. GPIO1 Standard GPIO Active-high output of SBB2's flexible power sequencer (FPS) slot. www.analog.com Analog Devices | 35 MAX77642/MAX77643 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output Buck-Boost, 1-LDO for Long Battery Life Applications On/Off Controller The on/off controller monitors multiple power-up (wake-up) and power-down (shutdown) conditions to enable or disable resources that are necessary for the system and its processor to move between its operating modes. Many systems have one power management controller and one processor and rely on the on/off controller to be the master controller. In this case, the on/off controller receives wake-up events and enables some or all of the regulators to power up a processor. That processor then manages the system. To conceptualize this master operation, see Figure 7 and Table 6. A typical path through the on/off controller is: 1. Apply a battery and start in the shutdown state. 2. Press the system's on-key (nEN = LOW) and follow transitions 3 and 4 to the resource-on state. If any resources are on the FPS, transitions 5A and 5B are followed. 3. The device performs its desired functions in the resource-on state. when it is ready to turn off, a manual reset first drives the transition through transitions 6A and 6B for FPS power down then through the 7 and 0 states to the shutdown state. Some systems have several power management blocks, a main processor, and subprocessors. These systems can use this device as a subpower management block for a peripheral portion of circuitry as long as there is an I2C port available from a higher level processor. To conceptualize this operation, see Figure 7 and Table 6. A typical path through the on/ off controller used in this way is: 1. Apply a battery to the system and start in the shutdown state. 2. The higher level processor can now control this device's resources with I2C commands (e.g., turn on/off regulators). 3. When the higher level processor is ready to turn this device off, it turns off everything through I2C to transition along path 7 to the shutdown state. Note that in this style of operation, the CNFG_GLBL0.SFT_CTRL[1:0] bits should not be used to turn the device off. The CNFG_GLBL0.SFT_CTRL[1:0] bits establish directives to the on/off controller itself that does not make sense in this subpower management block operation. If the processor uses I2C commands to enable the device's resources, the processor should also use I2C commands to disable them. www.analog.com Analog Devices | 36 MAX77642/MAX77643 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output Buck-Boost, 1-LDO for Long Battery Life Applications Top Level On/Off Controller (MAX77642) ANY STATE POWER-ON RESET (SYSAPOR = 1) 1 STATE POWER-ON RESET (POR) X 2 TRANSITION NAME. SEE TABLE 4 SHUTDOWN (BIAS OFF) ALL RESOURCES OFF 3 BIAS ENABLE 4 7 7 ADC CONVERSION 5 RESOURCE OFF BIAS ON, RESOURCES OFF 8 RESOURCE ON BIAS AND AT LEAST ONE RESOURCE IS ON 6 Figure 6. Top Level On/Off Controller State Diagram (MAX77642) www.analog.com Analog Devices | 37 MAX77642/MAX77643 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output Buck-Boost, 1-LDO for Long Battery Life Applications On/Off Controller Transition Table (MAX77642) Table 5. On/Off Controller Transition/State (MAX77642) TRANSITION CONDITION (TRANSITION HAPPENS WHEN...) 1 System voltage is above the POR threshold (VSYSA > VPOR) 2 VSYSA ≥ VSYSA(UVLO_R) 3 First ENx transitions from low to high 4 Main Bias enable time expires (tSBIAS_EN) 5 ADC detection time expires (tRSET) 6 Additional ENx transitions from low to high OR ENx transitions from high to low (as long as one SIMO channel or the LDO is enabled) 7 Last ENx transitions from high to low (all SIMO channels and the LDO are disabled) 8 Chip overtemperature lockout (TJ > TOTLO) OR SYSA undervoltage lockout (VSYSA < VSYSAUVLO) OR SYSA overvoltage lockout (VSYSA > VSYSAOVLO) www.analog.com Analog Devices | 38 MAX77642/MAX77643 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output Buck-Boost, 1-LDO for Long Battery Life Applications Top Level On/Off Controller (MAX77643) ANY STATE2 ANY STATE2 2 1 STATE POWER-ON RESET (SYSPOR = 1) SHUTDOWN ((BIAS OFF) ALL RESOURCES OFF ACTION SEQUENCE 0F X 0D TRANSITION NAME. SEE ON/OFF CONTROLLER TRANSITION/STATE TABLE 0B OFF/RESET/ AUTO-WAKEUP ACTIONS 0E 0C 0A 3 BIAS ENABLE BIAS DISABLE 4 7 6B FPS POWER-DOWN RESOURCE ON SPS CONTROL BIAS AND AT LEAST ONE RESOURCE IS ON 6A 5B 5A FPS POWER-UP Figure 7. Top Level On/Off Controller State Diagram (MAX77643) www.analog.com Analog Devices | 39 MAX77642/MAX77643 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output Buck-Boost, 1-LDO for Long Battery Life Applications On/Off Controller Transition Table (MAX77643) Table 6. On/Off Controller Transition/State (MAX77643) TRANSITION CONDITION (TRANSITION HAPPENS WHEN...) 0A Software cold reset (CNFG_GLBL0.SFT_CTRL[1:0] = 0b01) OR Watchdog timer expired and caused reset (ERCFLAG.WDT_RST = 1, CNFG_WDT.WDT_MODE = 1) 0B Reset actions completed 0C Software power-off (CNFG_GLBL0.SFT_CTRL[1:0] = 0b10) OR Watchdog expired and caused power-off (ERCFLAG.WDT_OFF = 1, CNFG_WDT.WDT_MODE = 0) OR Chip overtemperature lockout (TJ > TOTLO) OR SYSA undervoltage lockout (VSYSA < VSYSAUVLO + VSYSAUVLO_HYS) OR SYSA overvoltage lockout (VSYSA > VSYSAOVLO) OR Manual reset occurred (ERCFLAG.MRST = 1) 0D Off actions completed 0E Software auto wake-up (CNFG_GLBL0.SFT_CTRL = 0b11 0F Auto wake-up actions completed 1 System voltage is above the POR threshold (VSYSA > VPOR). Chip overtemperature lockout (TJ > TOTLO) OR 2 SYSA undervoltage lockout (VSYSA < VSYSAUVLO + VSYSUVLO_HYS) OR SYSA overvoltage lockout (VSYSA > VSYSAOVLO) 3 Any resources force enabled OR Internal wake-up flags are set (see the Internal Wake-Up Flags (MAX77643) section) 4 Main bias enable time expires (tSBIAS_EN) AND Conditions in Transition 2 are not met. FPS power-up sequence has not happened yet AND 5A Resources are not forced off AND Internal wake-up flags are set (see the Internal Wake-Up Flags (MAX77643) section) 5B FPS power-up sequence completed 6A FPS power-up sequence completed AND Software cold reset (CNFG_GLBL0.SFT_CTRL[1:0] = 0b01) OR Software power-off (CNFG_GLBL0.SFT_CTRL[1:0] = 0b10) OR Software auto wake-up (CNFG_GLBL0.SFT_CTRL = 0b11 OR Watchdog timer expired OR Manual reset occurred (ERCFLAG.MRT = 1) OR CNFG_GLBL1.SBB_F_SHUTDN = 0b1 AND SBB fault occurs 6B FPS power-down sequence finished 7 Last resource turned off Internal Wake-Up Flags (MAX77643) After transitioning to the shutdown state because of a reset, to allow the device to power up again, internal wake-up flags are set to remember the wake-up request. In Figure 7 and Table 6, these internal wake-up flags trigger transition 3. The internal wake-up flags are set when any of the following happen: ● nEN is debounced (see the nEN Enable Input (MAX77643) section) • For example, after a push-button is pressed or a slide-switch switched to HIGH. ● Software cold reset command sent (CNFG_GLBL0.SFT_CTRL[1:0] = 0b01) www.analog.com Analog Devices | 40 MAX77642/MAX77643 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output Buck-Boost, 1-LDO for Long Battery Life Applications Reset, Off, and Auto Wake-Up Sequences (MAX77643) RESET ACTIONS OFF ACTIONS AUTO WAKE-UP ACTIONS 0A 0C 0E EVENT RECORDER (ERCFLAG) LOGS RESET CAUSE EVENT RECORDER (ERCFLAG) LOGS POWER-OFF CAUSE EVENT RECORDER (ERCFLAG) LOGS POWER-OFF CAUSE RESET FLAGS CLEARED: WDT_EXP = 0 OFF FLAGS CLEARED: WDT_EXP = 0 RESET FLAGS CLEARED: WDT_EXP = 0 WAIT 60ms WAIT 60ms WAIT AUTO WAKE-UP TIME RESET REGISTERS RESET REGISTERS REGISTERS NOT RESET INTERNAL WAKE-UP FLAGS SET INTERNAL WAKE-UP FLAGS CLEARED INTERNAL WAKE-UP FLAGS SET 0B 0D 0F Figure 8. On/Off Controller Reset and Off-Action Sequences www.analog.com Analog Devices | 41 MAX77642/MAX77643 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output Buck-Boost, 1-LDO for Long Battery Life Applications Power-Up/Down Sequence (MAX77643) FPS POWER-UP ACTIONS FPS POWER-DOWN ACTIONS START FROM TOP LEVEL #5A START FROM TOP LEVEL #6A FPS ENABLE PULSE 0 ASSERT nRST WAIT tEN WAIT tRSTOAD FPS ENABLE PULSE 1 FPS DISABLE PULSE 3 WAIT tEN WAIT tDIS FPS ENABLE PULSE 2 FPS DISABLE PULSE 2 WAIT tEN WAIT tDIS FPS ENABLE PULSE 3 FPS DISABLE PULSE 1 WAIT tRSTODD WAIT tDIS DE-ASSERT nRST FPS DISABLE PULSE 0 END TO TOP LEVEL #5B END TO TOP LEVEL #6B Figure 9. Power-Up/Down Sequence www.analog.com Analog Devices | 42 MAX77642/MAX77643 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output Buck-Boost, 1-LDO for Long Battery Life Applications Flexible Power Sequencer (FPS) (MAX77643) The FPS allows resources to power up under hardware or software control. Additionally, each resource can power up independently or among a group of other regulators with adjustable power-up/down delays (sequencing). Figure 10 shows four resources powering up under the control of the flexible power sequencer. The flexible sequencing structure consists of one master sequencing timer and four slave resources (SBB0, SBB1, SBB2 and LDO). When the FPS is enabled, a master timer generates four sequencing events for device power-up/down. NOT DRAWN TO SCALE ENFPS tDIS SAME FOR ALL FPS DISABLE PULSES. tDIS = 2x tEN tEN SAME FOR ALL FPS ENABLE PULSES. PLSFPS 0 1 2 3 3 2 1 0 FPS RESOURCES SBB0 LDO0 SBB1 SBB2 Figure 10. Flexible Power Sequencer Basic Timing Diagram www.analog.com Analog Devices | 43 MAX77642/MAX77643 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output Buck-Boost, 1-LDO for Long Battery Life Applications Startup Timing Diagram Due to nEN (MAX77643) NOT DRAWN TO SCALE STATE NO POWER POR STANDBY POWER-UP SEQUENCE RESOURCE ON BATTERY INSERTION VSYS VPOR~1.9V tPOR~100µs tDBNC_nEN nEN NOTE 1 tDBNC_nEN NOTE 2 STAT_EN nEN_F nEN_R tSBIA_EN tFPS_DLY BIAS EN (INTERNAL) FPS0 FPS1 tEN FPS2 tEN FPS3 tEN REGULATORS nIRQ NOTE 3 tRSTODD nRST NOTES: 1 – nEN LOGIC INPUT IS CONFIGURED TO PUSH-BUTTON MODE AND HAS AN INTERNAL PULLUP TO SYSA. 2 – nEN ASSERTION RESULTS IN A WAKE-UP EVEN AFTER A DEBOUNCE TIME (tDBNC_nEN). NOTE 4 3 – nIRQ HAS AN EXTERNAL PULLUP TO VIO WHICH IS ENABLED IN FLEXIBLE POWER SEQUENCER SLOT #1. 4 – AS PART OF ITS INITIALIZATION ROUTINE, SOFTWARE READS THE INTERRUPT REGISTERS (CLEAR ON READ) AND PROGRAMS THE INTERRUPT MASKS AS DESIRED. Figure 11. Startup Timing Diagram Due to nEN Force Enabled/Disabled Channels (MAX77643) Force enable SIMO and LDO output channels by setting CNFG_SBBx_B.EN_SBBx[2:0] (SIMO) or CNFG_LDOx_B.EN_LDOx[2:0] (LDO) = 0x6. Depending on the OTP, output channels may already be force enabled by default. Output channels configured this way are independent of the flexible power sequence and start up as soon as SYS > UVLO rising. The main bias also automatically turns on. Likewise, output channels can be force disabled by setting EN_SBBx[2:0] or EN_LDOx[2:0] = 0x4. www.analog.com Analog Devices | 44 MAX77642/MAX77643 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output Buck-Boost, 1-LDO for Long Battery Life Applications Debounced Inputs (nEN, GPI) (MAX77643) The nEN and GPIO (when operating as an input) have programmable debounce timers on both the rising and falling edges to reject undesired transitions. The input must be at a stable logic level for the entire debounce period for the output to change its logic state. Figure 12 shows an example timing diagram for the nEN debounce. NOT DRAWN TO SCALE BOUNCING IS REJECTED STABLE SIGNAL IS ACCEPTED BOUNCING IS REJECTED STABLE SIGNAL IS ACCEPTED nEN tDBUF tDBUF tDBNC_nEN tDBNC_nEN EN (INTERNAL) DBEN (INTERNAL) Figure 12. Debounced Inputs www.analog.com Analog Devices | 45 MAX77642/MAX77643 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output Buck-Boost, 1-LDO for Long Battery Life Applications Watchdog Timer (WDT) (MAX77643) The IC features a watchdog timer function for operational safety. If this timer expires without being cleared, the on/off controller causes the IC to enter the shutdown state and resets configuration registers. See the On/Off Controller and On/Off Controller Transition Table (MAX77643) sections (transitions 0A and 0C) for more details. Write CNFG_WDT.WDT_EN = 1 through the I2C interface to enable the timer. The watchdog timer period (tWD) is configurable from 16 seconds to 128 seconds in four steps with CNFG_WDT.WDT_PER[1:0]. The default timer period is 128 seconds. While the watchdog timer is enabled, the CNFG_WDT.WDT_CLR bit must be set through the I2C interface periodically (within tWD) to reset the timer and prevent shutdown. See the Register Map and Figure 13 for additional details. WATCHDOG TIMER RESET INTERNAL COUNT = tWD WDT_CLR = 0 CLEAR CONTROL SET (WDT_CLR = 1) OR TIMER DISABLED (WDT_EN = 0) OR SHUTDOWN (BIAS OFF) STATE* OR tWD CHANGED (NEW BITS IN WDT_PER[1:0]) TIME ELAPSED < tWD SHUTDOWN (BIAS OFF) STATE** (THE ON/OFF CONTROLLER FORCES THIS TRANSITION WHEN THE TIMER EXPIRES) CLEAR CONTROL NOT SET (WDT_CLR = 0) AND TIMER ENABLED (WDT_EN = 1) AND NOT IN SHUTDOWN (BIAS OFF) STATE* WATCHDOG TIMER ENABLED AND OK TIMER COUNTING DOWN INTENAL COUNT < tWD TIME ELAPSED = tWD WATCHDOG TIMER EXPIRED INTERNAL COUNT = 0 *WATCHDOG TIMER DOES NOT RUN WHILE IN SHUTDOWN STATE. WDT_MODE BIT CAN CAUSE THE ON/OFF CONTROLLER TO EXIT SHUTDOWN AUTOMATICALLY. SEE REGISTER MAP. **SEE ON/OFF CONTROLLER STATE MACHINE Figure 13. Watchdog Timer State Machine The timer can be factory-programmed to be enabled by default, disabled by default, or locked from accidental disable. The CNFG_WDT.WDT_LOCK bit is read-only and must be configured at the factory. See Table 7 for a full description. Table 7. Watchdog Timer Factory-Programmed Safety Options WDT_LOCK WDT_EN 0 0 Watchdog timer is disabled by default. Timer can be enabled or disabled by I2C writes. 0 1 Watchdog timer is enabled by default. Timer can be enabled or disabled by I2C writes. 1 0 Watchdog timer is disabled by default. Timer can be enabled by an I2C write, but only a SYSRST can reset the CNFG_WDT.WDT_EN value back to 0. Timer can not be disabled by direct I2C writes to CNFG_WDT.WDT_EN (write from 1 → 0 is ignored, write from 0 → 1 is accepted). 1 1 Watchdog timer is enabled by default. Nothing can disable the timer. www.analog.com FUNCTION Analog Devices | 46 MAX77642/MAX77643 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output Buck-Boost, 1-LDO for Long Battery Life Applications Detailed Description—SIMO Buck-Boost The device has a micropower single-inductor, multiple-output (SIMO) buck-boost DC-to-DC converter designed for applications that emphasize low supply current and small solution size. A single inductor is used to regulate three separate outputs, saving board space while delivering better total system efficiency than equivalent power solutions using one buck and linear regulators. The buck-boost configuration utilizes the entire battery voltage range due to its ability to create output voltages that are above, below, or equal to the input voltage. Peak inductor current for each output is programmable to optimize the balance between efficiency, output ripple, EMI, PCB design, and load capability. To further boost efficiency when the output voltage is always lower than the input, individual channels of the SIMO buckboost converter can be configured to be in buck-only or boost-only mode, reducing switching losses by toggling less switches compared to buck-boost mode. See the SIMO Buck Mode (MAX77643) and SIMO Boost Mode (MAX77643) sections for more details. SIMO Features and Benefits ● Three Output Channels ● Ideal for Low-Power Designs • Delivers up to 500mA at 1.8V from a 3.7V Input • ±2% Accurate Output Voltage ● Small Solution Size • Multiple Outputs from a Single 1.5μH Inductor • Small 10μF (0402) Output Capacitors ● Flexible and Easy to Use • Single Mode of Operation • Glitchless Transitions Between Buck, Boost, and Buck-Boost Modes • Programmable Peak Inductor Current • Programmable On-Chip Active Discharge • Programmable Buck-Only and Boost-Only Mode (MAX77643) • Resistor Programmable Output Voltages (MAX77642) ● Long Battery Life • High Efficiency, > 91% at 1.8V Output • Better Total System Efficiency than Buck + LDOs • Low Quiescent Current, 1μA per Output • Low Input Operating Voltage, 2.7V (min) www.analog.com Analog Devices | 47 MAX77642/MAX77643 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output Buck-Boost, 1-LDO for Long Battery Life Applications SIMO Detailed Block Diagram 10nF (0201) 1.5µH (0806) LXA LXB BST IN_SBB MAIN POWER STAGE IN_SBB SYS 10µF (0402) SYNCHRONOUS RECTIFIER REVERSE BLOCKING ILIM PGND SBB0 M1 BST DRV_SBB M3_0 IZX DRV_SBB CHG DIS M2 REG0 ACTIVE-DISCHARGE SIMO CONTROLLER CHG DIS DIS_SBB[2:0] REG1 AD_SBB1 RAD_SSB0 (140Ω) SYNCHRONOUS RECTIFIER (M3_1) AND ERROR COMPARATOR AND ACTIVE-DISCHARGE SBB1 BST DRV_SBB DIS_SBB1 10µF (0402) / VREF VIREF DIS_SBB1 ERROR COMPARATOR M4 AD_SBB0 I.LIM I.ZX REG[2:0] 10µF (0402) COMM FPS SYS_RST DIGITAL AND REGISTERS CNFG_SBB_TOP, CNFG_SBBX_A, CNFG_SBBX_B DRV_SBB AD_SBB[2:0] REG2 AD_SBB2 SYNCHRONOUS RECTIFIER (M3_2) AND ERROR COMPARATOR AND ACTIVE-DISCHARGE SBB2 BST DRV_SBB DIS_SBB2 10µF (0402) Figure 14. SIMO Detailed Block Diagram www.analog.com Analog Devices | 48 MAX77642/MAX77643 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output Buck-Boost, 1-LDO for Long Battery Life Applications SIMO Control Scheme The SIMO buck-boost is designed to service multiple outputs simultaneously. A proprietary controller ensures that all outputs get serviced in a timely manner, even while multiple outputs are contending for the energy stored in the inductor. When no regulator needs service, the state machine rests in a low-power rest state. When the controller determines that a regulator requires service, it charges the inductor (M1 + M4) until the peak current limit is reached (ILIM = CNFG_SBBx_B.IP_SBB[1:0]). The inductor energy then discharges (M2 + M3_x) into the output until the current reaches zero (IZX). In the event that multiple output channels need servicing at the same time, the controller ensures that no output utilizes all of the switching cycles. Instead, cycles interleave between all the outputs that are demanding service, while outputs that do not need service are skipped. Drive Strength (MAX77643) The SIMO regulator's drive strength for its internal power MOSFETs is adjustable using the CNFG_SBB_TOP.DRV_SBB[1:0] bit field. The ideal value is determined experimentally for each application. For a PCB layout comparable to the MAX77642/MAX77643 evaluation kit, 0x1 is the best setting and represents a balance between efficiency and EMI. Faster settings result in higher efficiency but generally require stricter layout rules or shielding to avoid additional EMI. Slower settings limit EMI in non-ideal settings (e.g., contained layout, antennae adjacent to the device, etc.). Change the drive strength only once during system initialization. www.analog.com Analog Devices | 49 MAX77642/MAX77643 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output Buck-Boost, 1-LDO for Long Battery Life Applications SIMO Output Voltage Configuration Each of the SIMO outputs are independently configurable. To set the output voltages at SBB0/1/2 for the MAX77642, connect the appropriate resistors from RSET_SBB0/1/2 to GND as shown in Table 8 and Table 9. The RSET_SBB0/ 1/2 resistors should have 1% or better tolerance. To set the output voltages at SBB0/1/2 for the MAX77643, use the I2C interface to load the configuration registers CNFG_SBBx_A.TV_SBBx[7:0]. This 8-bit configuration is a linear transfer function that starts at 0.5V and ends at 5.5V with 25mV increments, and sets the output voltage as: SBBx = 0.5V + 25mV x TV_SBBx[7:0] (decimal). Table 8. SBB0 Output Voltage Settings RSET_SBB0 (kΩ) OUTPUT VOLTAGE - SBB0 (V) 0.001 0.50 4.99 0.60 6.00 0.70 7.15 0.80 8.45 0.90 10.0 1.00 11.8 1.05 14.0 1.10 16.9 1.20 20.0 1.30 23.7 1.40 28.0 1.60 34.0 1.75 40.2 1.80 47.5 1.85 56.2 2.00 66.5 2.20 www.analog.com 80.6 2.40 95.76 2.80 113.0 3.00 133.0 3.20 162.0 3.25 191.0 3.30 226.0 3.35 267.0 3.40 324.0 3.80 383.0 4.00 452.0 4.20 536.0 4.40 634.0 4.60 768.0 5.00 909.0 5.20 Analog Devices | 50 MAX77642/MAX77643 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output Buck-Boost, 1-LDO for Long Battery Life Applications Table 9. SBB1/2 Output Voltage Settings RSET_SBB1/2 (kΩ) OUTPUT VOLTAGE - SBB1/2 (V) 0.001 0.50 4.99 0.60 6.00 0.70 7.15 0.80 8.45 0.90 10.0 1.00 11.8 1.10 14.0 1.20 16.9 1.30 20.0 1.40 23.7 1.60 28.0 1.80 34.0 2.00 40.2 2.20 47.5 2.40 56.2 2.60 66.5 2.80 80.6 3.00 95.76 3.20 113.0 3.30 133.0 3.40 162.0 3.60 191.0 3.80 226.0 4.00 267.0 4.20 324.0 4.40 383.0 4.60 452.0 4.80 536.0 5.00 634.0 5.20 768.0 5.40 909.0 5.50 www.analog.com Analog Devices | 51 MAX77642/MAX77643 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output Buck-Boost, 1-LDO for Long Battery Life Applications Peak Current Configuration The peak inductor current limit corresponding to each SIMO output are independently configurable. To set the inductor peak current for the MAX77642, connect the appropriate resistors from RSET_IPK to GND as shown in Table 10. The RSET_IPK resistors should have a 1% or better tolerance. To set the inductor peak current for the MAX77643, use the I2C interface to load the configuration registers CNFG_SBBx_B.IP_SBBx[5:4]. Table 10. Inductor Peak Current Setting RSET_IPK (kΩ) SBB_PK2 (A) SBB_PK1 (A) SBB_PK0 (A) Short 0.5 0.5 0.5 4.99 0.5 0.5 1.0 6.00 0.5 1.0 0.5 7.15 1.0 0.5 0.5 8.45 1.0 1.0 0.5 10.0 1.0 0.5 1.0 11.8 0.5 1.0 1.0 14.0 1.0 1.0 1.0 SIMO Soft-Start The soft-start feature of the SIMO limits inrush current during startup. The soft-start feature is achieved by limiting the slew rate of the output voltage during startup (dV/dtSS). More output capacitance results in higher input current surges during startup. The following equations and example describe the input current surge phenomenon during startup. In buck-boost mode, the current into the output capacitor (ICSBB) during soft-start is: dV ( ICSBB = CSBB × dt Equation 1 SS ) where: ● CSBB is the capacitance on the output of the regulator ● dV/dtSS is the voltage change rate of the output The input current (IIN) during soft-start is: IIN = (ICSBB + ILOAD) ξ VSBBx VIN ( ) Equation 2 where: ● ● ● ● ● www.analog.com ICSBB is calculated using Equation 1 ILOAD is current consumed from the external load VSBBx is the output voltage VIN is the input voltage ξ is the efficiency of the regulator Analog Devices | 52 MAX77642/MAX77643 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output Buck-Boost, 1-LDO for Long Battery Life Applications For example, given the following conditions, the peak input current (IIN) during soft-start is ~71mA: Given: ● ● ● ● ● ● VIN is 3.5V VSBB2 is 3.3V CSBB2 = 10µF dV/dtSS = 5mV/µs RLOAD2 = 330Ω (ILOAD2 = 3.3V/330Ω = 10mA) ξ is 80% Calculation: ● ICSBB = 10µF x 5mV/µs (from Equation 1) ● ICSBB = 50mA 3.3V (50mA + 10mA) 3.5V ● IIN = 0.85 ● IIN ~ 71mA (from Equation 1) SIMO Registers (MAX77643) Each SIMO buck-boost channel has a dedicated register to program its target output voltage (CNFG_SBBx_A.TV_SBBx[7:0]) and its peak current limit (CNFG_SBBx_B.IP_SBBx[1:0]). Additional controls are available for enabling/disabling the active-discharge resistors (CNFG_SBBx_B.ADE_SBBx), buck-only, boost-only, buckboost only, and automatic mode (CNFG_SBBx_B.OP_MODE) as well as enabling/disabling the SIMO buck-boost channels (CNFG_SBBx_B.EN_SBBx[2:0]). For a full description of bits, registers, default values, and reset conditions, see the Register Map. SIMO Active Discharge Resistance Each SIMO buck-boost channel has an active-discharge resistor (RAD_SBBx) that is automatically enabled/disabled based on a CNFG_SBBx_B.ADE_SBBx bit and the status of the SIMO regulator. The active discharge feature may be enabled (CNFG_SBBx_B.ADE_SBBx = 1) or disabled (CNFG_SBBx_B.ADE_SBBx = 0) independently for each SIMO channel. Enabling the active discharge feature helps ensure a complete and timely power down of all system peripherals. If the active-discharge resistor is enabled by default, then the active-discharge resistor is on whenever VSYSA is below VSYSAUVLO and above VPOR. These resistors discharge the output when CNFG_SBBx_B.ADE_SBBx = 1, and their respective SIMO channel is off. If the regulator is forced on through CNFG_SBBx_B.EN_SBBx[2:0] = 0b110 or 0b111, then the resistors do not discharge the output even if the regulator is disabled by the main-bias. Note that when VSYSA is less than 1.0V, the NMOS transistors that control the active-discharge resistors lose their gate drive and become open. www.analog.com Analog Devices | 53 MAX77642/MAX77643 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output Buck-Boost, 1-LDO for Long Battery Life Applications SIMO Buck Mode (MAX77643) If the input voltage at IN_SBB never falls below the output voltage of one or more SIMO converter channels, individual channels can be configured to be in buck mode with the CNFG_SBBx_B.OP_MODE bit. In buck mode, when an output needs service, switch M3_x remains closed and M4 remains open (see Figure 14). Only M1 and M2 are toggled as in a traditional buck converter. Efficiency is boosted due to three major factors: ● Reduced switching loss: Buck mode toggles only two switches versus the four in buck-boost mode. Therefore, there are less switching events during which power is consumed. ● Lower inductor core losses: Inductor current changes from 0A to peak current. The larger the change in current the inductor experiences, the more energy is lost in the inductor core in the form of heat. In buck mode, the peak current can be reduced since less inductor current is needed to support a load. Less inductor current is needed because of direct energy transfer. Direct energy transfer occurs while the inductor is charged, when the input (IN_SBB) is connected directly to the output (SBBx) through the inductor. Therefore, the input not only provides energy to charge the inductor, energy is also supplied to the output capacitor and load devices. Therefore, less current is needed to charge the inductor, which is used to charge the output capacitor in the next switching state. ● Less frequent charging cycles: In buck-boost mode, the output capacitor is charged only while the inductor is being discharged. Again because of direct energy transfer, the output capacitor is charged during both the inductor charge and discharge times. In addition, with the same peak current limit, the inductor charge time is longer with buck mode. Therefore, the output capacitor can support the output voltage longer before needing to be recharged. Maintain a minimum headroom of 0.7V between IN_SBB and SBBx in buck mode because inductor charge time (dt = L x IP_SBBx/(VIN_SBB - VSBBx)) increases as the difference between the IN_SBB and SBBx voltages shrinks. As the inductor current takes longer to reach its peak, the output voltage might take too long to reach its target voltage, and the MAX77643 might trigger a fault flag. SIMO Boost Mode (MAX77643) If the input voltage at IN_SBB never rises above the output voltage of one or more SIMO converter channels, individual channels can be configured to be in boost mode with the CNFG_SBBx_B.OP_MODE bit. In boost mode, when an output needs service, switch M1 remains closed and M2 remains open (see Figure 14). Only M3x and M4 are toggled as in a traditional boost converter. Efficiency is boosted due to three major factors: ● Reduced switching loss: Boost mode toggles only two switches versus the four in buck-boost mode. Therefore, there are less switching events during which power is consumed. ● Lower inductor core losses: Inductor current changes from 0A to peak current. The larger the change in current the inductor experiences, the more energy is lost in the inductor core in the form of heat. In boost mode, the peak current can be reduced since less inductor current is needed to support a load. Less inductor current is needed because of direct energy transfer. Direct energy transfer occurs while the inductor is discharged, when the input (IN_SBB) is connected directly to the output (SBBx) through the inductor. Therefore, the input not only provides energy to charge the inductor, energy is also supplied to the output capacitor and load devices. Therefore, less current is needed to charge the inductor, which is used to charge the output capacitor in the next switching state. ● Less frequent charging cycles: The inductor discharge time is longer with boost mode. Therefore, the output capacitor can support the output voltage longer before needing to be recharged. www.analog.com Analog Devices | 54 MAX77642/MAX77643 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output Buck-Boost, 1-LDO for Long Battery Life Applications Applications Information SIMO Available Output Current The available output current on a given SIMO channel is a function of the input voltage, output voltage, the peak current limit setting, and the output current of the other SIMO channels. Maxim offers a calculator found in the design resources tab of the MAX77642/MAX77643's webpage that outlines the available capacity for specific conditions. Table 11 is an extraction from the calculator. Table 11. SIMO Available Output Current for Common Applications PARAMETERS EXAMPLE 1 EXAMPLE 2 EXAMPLE 3 EXAMPLE 4 EXAMPLE 5 VIN_MIN 2.7V 2.7V 3.2V 3.4V 3.6V RL_DCR 0.1Ω 0.1Ω 0.1Ω 0.12Ω 0.12Ω SBB0 1.0V at 100mA 1.0V at 80mA 1.2V at 50mA 1.2V at 20mA 1.2V at 20mA SBB1 1.2V at 75mA 1.2V at 50mA 2.05V at 100mA 2.05V at 80mA 2.05V at 80mA SBB2 1.8V at 50mA 1.8V at 40mA 3.3V at 30mA 3.3V at 10mA 2.05V at 5mA Operating Mode Buck-Boost Buck Buck-Boost Buck-Boost Buck IP_SBB0 1A 1A 1A 0.5A 1A IP_SBB1 1A 1A 0.75A 0.5A 1A IP_SBB2 1A 1A 1A 0.5A 0.5A Utilized Capacity 73% 77% 79% 73% 79% *ESRC_IN = ESRC_OUT = 5mΩ, L = 1.5μH Inductor Selection Choose an inductance from 1.0μH to 2.2μH; 1.5μH inductors work best for most designs. Larger inductances transfer more energy to the output for each cycle and typically result in larger output voltage ripple and better efficiency. See the Output Capacitor Selection section for more information on how to size your output capacitor in order to control ripple. Choose the inductor saturation current to be greater than or equal to the maximum peak current limit setting that is used for all of the SIMO buck-boost channels (IP_SBBx). For example, if SBB0 is set for 0.5A, SBB1 is set for 0.75A, and SBB2 is set for 1.0A, then choose the saturation current to be greater than or equal to 1.0A. Choose the RMS current rating of the inductor (typically the current at which the temperature rises appreciably) based on the expected load currents for the system. For systems where the expected load currents are not well known, be conservative and choose the RMS current to be greater than or equal to half the higher maximum peak current limit setting [IRMS ≥ MAX (IP_SBB0, IP_SBB1, IP_SBB2) / 2]. This is a conservative choice because the SIMO buck-boost regulator implements a discontinuous conduction mode (DCM) control scheme, which returns the inductor current to zero each cycle. www.analog.com Analog Devices | 55 MAX77642/MAX77643 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output Buck-Boost, 1-LDO for Long Battery Life Applications Consider the DC-resistance (DCR), AC-resistance (ACR), and solution size of the inductor. Typically, smaller sized inductors have larger DC-resistance and larger AC-resistance that reduces efficiency and the available output current. Note that many inductor manufacturers have inductor families which contain different versions of core material in order to balance trade-offs between DCR, ACR (i.e., core losses), and component cost. For this SIMO regulator, inductors with the lowest ACR in the 1.0MHz to 2.0MHz region tend to provide the best efficiency. Input Capacitor Selection Choose the input bypass capacitance (CIN_SBB) to be 10µF. Larger values of CIN_SBB improve the decoupling for the SIMO regulator. The CIN_SBB reduces the current peaks drawn from the battery or input power source during SIMO regulator operation and reduces switching noise in the system. The ESR/ESL of the input capacitor should be very low (i.e., ESR ≤ 5mΩ and ESL ≤ 500pH) for frequencies up to 2MHz. Ceramic capacitors with X5R or X7R dielectric are highly recommended due to their small size, low ESR, and small temperature coefficients. To fully utilize the available input voltage range of the SIMO (5.5V, max), use a capacitor with a voltage rating of 6.3V at minimum. Boost Capacitor Selection Choose the boost capacitance (CBST) to be 10nF. Smaller values of CBST (< 1nF) result in insufficient gate drive for M3. Larger values of CBST (> 10nF) have the potential to degrade the startup performance. Ceramic capacitors with 0201 or 0402 case size are recommended. Output Capacitor Selection Choose each output bypass capacitance (CSBBx) based on the target output voltage ripple (∆VSBBx). Typical values are 22μF. Larger values of CSBBx improve the output voltage ripple but increase the input surge currents during soft-start and output voltage changes. The output voltage ripple is a function of the inductance (L), the output voltage (VSBBx), and the peak current limit setting (IP_SBBx). See Equation 3 to estimate required, effective capacitance. 2×L I CSBBx = P_SBBx 2 × VSBBx × ∆ VSBBx(Equation 3) Maxim also offers a calculator to aid in the selection of the output capacitance found in the design resources tab of the MAX77642/MAX77643 product page. Note that most designs concern themselves with having enough capacitance on the output but there is also a maximum capacitance limitation that is calculated within the SIMO calculator; take care not to exceed the maximum capacitance. The CSBBx is required to keep the output voltage ripple small. The impedance of the output capacitor (ESR, ESL) should be very low (i.e., ESR ≤ 5mΩ and ESL ≤ 500pH) for frequencies up to 2MHz. Ceramic capacitors with X5R or X7R dielectric are highly recommended due to their small size, low ESR, and small temperature coefficients. A capacitor's effective capacitance decreases with increased DC bias voltage. This effect is more pronounced as capacitor case sizes decrease. Due to this characteristic, it is possible for an 0603 case size capacitor to perform well, while an 0402 case size capacitor of the same value performs poorly. The SIMO regulator is stable with low output capacitance (1μF) but the output voltage ripple would be large; consider the effective output capacitance value after initial tolerance, bias voltage, aging, and temperature derating. SIMO Switching Frequency The SIMO buck-boost regulator uses a pulse frequency modulation (PFM) control scheme. The switching frequency for each output is a function of the operating mode, input voltage, output voltage, load current, and inductance. Output capacitance is a minor factor in SIMO switching frequency. Maxim offers a SIMO calculator found in the design resources tab of the MAX77642/MAX77643 product page to estimate expected switching frequency. Table 12 lists how different factors increase or decrease switching frequency. Table 12. Switching Frequency Control FACTOR www.analog.com INCREASING FREQUENCY DECREASING FREQUENCY Analog Devices | 56 MAX77642/MAX77643 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output Buck-Boost, 1-LDO for Long Battery Life Applications Table 12. Switching Frequency Control (continued) Inductor Current Peak Limit Lower peak limit Higher peak limit Operating Mode Buck-boost mode Buck mode or boost mode Inductor Decrease inductance Increase inductance Output Capacitor Decrease capacitance Increase capacitance Input Voltage Higher voltage Lower voltage Output Voltage Higher voltage Lower voltage Load Current Higher current Lower current Unused Outputs Do not leave unused outputs unconnected. If an output left unconnected is accidentally enabled, the charged inductor experiences an open circuit, and the output voltage soars above the absolute maximum rating, damaging the device. If an output is not used, do one of the following: 1. Disable the output (CNFG_SBBx_B.EN_SBBx[2:0] = 0x4 or 0x5) and connect the output to ground. If an unused output is default enabled or can be accidentally enabled, do one of the other recommendations instead. 2. Bypass the unused output with a 1μF capacitor to ground. 3. Connect the unused output to IN_SBB or a different output channel if the unused output is programmed to a lower voltage. Since the output voltage is higher than the unused output, the regulator does not service the unused output even if it is unintentionally enabled. • Note that some OTP options have the active-discharge resistors enabled by default. Connecting an unused output to IN_SBB is not recommended if the active discharge is enabled by default. If connecting the unused output to a different channel, disable the active-discharge resistor (CNFG_SBBx_B.ADE_SBBx = 0) of the unused channel. PCB Layout Guide Capacitors Place decoupling capacitors as close as possible to the IC such that connections from capacitor pads to pin and from capacitor pads to ground pins are short. Keeping the connections short lowers parasitic inductance and resistance, improving performance and shrinking the physical size of hot loops. If connections to the capacitors are through vias, use multiple vias to minimize parasitics. Also, connect loads to the capacitor pads rather than the device pins. Most critical are the capacitors for the switching regulator: input capacitor at IN_SBB and output capacitors at SBBx. Input Capacitor at IN_SBB Minimize the parasitic inductance from PGND to input capacitor to IN_SBB to reduce ringing on the LXA voltage. Output Capacitors at SBBx The output capacitors experience large changes in current as the regulator charges (buck mode) and discharges (both modes) the inductor. In buck mode, the capacitor current ramps up at the same rate as mentioned in the Input Capacitor at IN_SBB section. In buck-boost mode, the capacitor current ramps up very quickly. In both modes, the capacitor current dI ramps down at a rate of C_SBBx dt V = SBBx L from inductor peak current. Since the ramp down can occur in less than 1μs, and the current increases rapidly for buck-boost mode, minimize parasitic inductance from SBBx to output capacitor to PGND. www.analog.com Analog Devices | 57 MAX77642/MAX77643 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output Buck-Boost, 1-LDO for Long Battery Life Applications Inductor Keep the inductor close to the IC to reduce trace resistance; however, prioritize any regulator input/output capacitors over the inductor. Use the appropriate trace width from LXA to inductor to LXB to support the peak inductor current. Likewise, if there are vias in the path, use an appropriate amount of vias to support the peak current. Ground Connections As the switching regulator charges and discharges the inductor, current flows from PGND to the input capacitor ground, from output capacitor ground to PGND, or from output capacitor ground to input capacitor ground. Therefore, use a wide, continuous copper plane to connect PGND to the capacitor grounds. When connecting the GND and PGND pins together, ensure noise from the power ground does not enter the analog ground (where GND is connected). For example, assuming the ground pins are connected through a solid ground plane on an internal layer, one via connecting GND to the internal ground plane may be sufficient to protect GND from most of the noise in the power-ground plane. Likewise, if there are other higher current or noisy circuitry near this device, avoid connecting the GND pin directly to their grounds. For more guidelines on proper grounding, visit: https://www.maximintegrated.com/en/design/partners-and-technology/ design-technology/ground-layout-board-designers.html. Example PCB Layout Figure 15 shows an example layout of the top layer. LDO SDA SCL GND nEN nIRQ nRST GPIO0 GPIO1 CIN_SBB INLDO CSYSA SYS CVIO VIO GND CLDOIN CLDO CSBB0 SBB0 CSBB1 SBB1 CSBB2 SBB2 CBST L GND GND GND Figure 15. PCB Top-Layer and Component Placement Example www.analog.com Analog Devices | 58 MAX77642/MAX77643 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output Buck-Boost, 1-LDO for Long Battery Life Applications Detailed Description—Low Dropout Linear Regulator (LDO)/Load Switch (LSW) The device includes an on-chip low-dropout linear regulator (LDO0) that can also be configured as load switches. The LDO is optimized to have low-quiescent current. The input voltage range (VIN_LDO) allows it to be powered directly from the main energy source such as a Li-Poly battery or from an intermediate regulator. The linear regulator delivers up to 150mA. Features and Benefits ● ● ● ● ● ● ● 1x 150mA LDO LDO Input Voltage Range: 1.71V to 5.5V LSW Input Voltage Range: 1.20V to 5.5V Resistor Adjustable Output Voltage (MAX77642) I2C Adjustable Output Voltage (MAX77643) 100mV Maximum Dropout Voltage at ECT Conditions Programmable On-Chip Active Discharge LDO/LSW Simplified Block Diagram The LDO/LSW block has one input (IN_LDO) and one output (LDO) and several ports that exchange information with the rest of the device (VREF, EN_LDO, ADE_LDO). The VREF comes from the main bias circuits. The CNFG_LDO0_B.EN_LDO and CNFG_LDO0_B.ADE_LDO are register bits for controlling the enable and activedischarge feature, respectively. See the Register Map for more information. IN_LDOx VREF EN_LDOx ADE_LDOx 150mA LDOx LDOx_F SBB0 10µF* (0402) *THE FLOOR PLAN IS SUCH THAT THE SBB0 OUTPUT CAPACITOR IS ALSO THE IN_LDOX INPUT CAPACITOR. LDOx DOD_x_R RADE_LDOx 2.2µF (0402) LDOx Figure 16. LDO Simplified Block Diagram LDO Output Voltage Configuration To set the output voltages for the on-chip LDO for the MAX77642, connect the appropriate resistor from RSET_LDO to GND as shown in Table 13. RSET_LDO resistor should have 1% or better tolerance. To set the output voltages for the on-chip LDO for the MAX77643, use the I2C interface to load the configuration register TV_LDO[7:0]. TV_LDO[7] is used to enable (TV_LDO[7] = 1) or disabled (TV_LDO[7] = 0) a 1.325mV offset to the LDO's output voltage. The bits TV_LDO[6:0] are used to set the output voltage as: LDO = 0.5V + TV_LDO[7] + (25mV x TV_LDO[6:0] (decimal)) www.analog.com Analog Devices | 59 MAX77642/MAX77643 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output Buck-Boost, 1-LDO for Long Battery Life Applications Table 13. LDO Output Voltage Setting RSET_LDO (kΩ) LDO OUTPUT VOLTAGE (V) Short 0.50 4.99 0.60 6.00 0.70 7.15 0.80 8.45 0.90 10.0 0.95 11.8 1.00 14.0 1.05 16.9 1.10 20.0 1.15 23.7 1.20 28.0 1.25 34.0 1.30 40.2 1.40 47.5 1.50 56.2 1.60 66.5 1.70 80.6 1.80 95.76 1.90 113.0 2.00 133.0 2.10 162.0 2.20 191.0 2.40 226.0 2.50 267.0 2.60 324.0 2.80 383.0 3.00 452.0 3.20 536.0 3.40 634.0 3.60 768.0 3.80 909.0 4.00 LDO/LSW Active-Discharge Resistor The LDO/LSW block has an active-discharge resistor (RAD_LDO) that is enabled if CNFG_LDO0_B.ADE_LDO = 1 and LDO is disabled. Enabling the active discharge feature helps ensure a complete and timely power down of the resource. During power up, if VSYSA > VPOR and CNFG_LDO_B.ADE_LDO = 1, the active-discharge resistor is enabled. www.analog.com Analog Devices | 60 MAX77642/MAX77643 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output Buck-Boost, 1-LDO for Long Battery Life Applications LDO/LSW Soft-Start The soft-start feature limits inrush current during startup, and is achieved by limiting the slew rate of the output voltage during startup (dVOUT_LDO/dtSS). More output capacitance results in higher input current surges during startup. The following equation and example describe the input current surge phenomenon during startup. The input current (IIN_LDO) during soft-start is calculated as: IIN_LDOx = CLDOx dVOUT_LDOx dtSS + IOUT_LDOx where: ● CLDO is the capacitance on the output of the regulator ● dVOUT_LDO/dtSS is the voltage change rate of the output For example, given the following conditions, the input current (IIN_LDO) during soft-start is 13.08mA: Given: ● ● ● ● CLDO = 2.2µF dVOUT_LDO/dtSS = 2.2mV/µs LDO programmed to 1.85V RLDO = 185Ω (IOUT_LDO = 1.85V/185Ω = 10mA) Calculation: ● IIN = 2.2µF x 2.2mV/µs + 10mA ● IIN = 14.84mA Load Switch Configuration The LDO0 can be configured as load switches with the CNFG_LDO0_B.LDO_MD bit. As shown in Figure 17, the transition from LDO to LSW mode is controlled by a defined slew rate until dropout is detected. Once dropout is detected, the load switch is fully closed and the dropout interrupt flag (INT_GLBL.DOD_R) is set. NOT DRAWN TO SCALE DOD DETECTED LSW TO LDO SLEW DEPENDS ON LOAD LDO STARTS IN LDO MODE LDO CONFIGURED TO BE IN LSW MODE LDO CONFIGURED TO BE IN LDO MODE Figure 17. LDO to LSW Transition Waveform www.analog.com Analog Devices | 61 MAX77642/MAX77643 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output Buck-Boost, 1-LDO for Long Battery Life Applications Applications Information Input Capacitor Selection Make sure the input bypass capacitance (CIN_LDO) is at least 2.2µF. Larger values of CIN_LDO improve the decoupling for LDO. The floor plan of the device is such that SBB0 is adjacent to IN_LDO and if the SIMO channel 0 output powers the input of LDO, then its output capacitor (CSBB0) can also serve as CIN_LDO such that only one capacitor is required. The CIN_LDO reduces the current peaks drawn from the battery or input power source during operation. The impedance of the input capacitor (ESR, ESL) should be very low (i.e., ESR ≤ 50mΩ and ESL ≤ 5nH) for frequencies up to 0.5MHz. Ceramic capacitors with X5R or X7R dielectric are highly recommended due to their small size, low ESR, and small temperature coefficients. Output Capacitor Selection For both LDO and LSW modes, choose the output bypass capacitance (CLDO) to be 1μF. In LDO mode, larger values of CLDO improve output PSRR but increase input surge currents during soft-start and output voltage changes. The effective output capacitance should not exceed 2.8μF to maintain stability. While in LDO mode, CLDO is required to keep stability. The series inductance of the output capacitor and its series resistance should be low (i.e., ESR ≤ 10mΩ and ESL ≤ 1nH) for frequencies up to 0.5MHz. Ceramic capacitors with X5R or X7R dielectric are highly recommended due to their small size, low ESR, and small temperature coefficients. A capacitor's effective capacitance decreases with increased DC bias voltage. This effect is more pronounced with smaller capacitor case sizes. Due to this characteristic, 0603 case size capacitors tend to perform well while 0402 case size capacitors of the same value perform poorly. www.analog.com Analog Devices | 62 MAX77642/MAX77643 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output Buck-Boost, 1-LDO for Long Battery Life Applications Detailed Description—I2C Serial Communication General Description The IC features a revision 3.0 I2C-compatible, 2-wire serial interface consisting of a bidirectional serial data line (SDA) and a serial clock line (SCL). This device acts as a slave-only device, relying on the master to generate a clock signal. SCL clock rates from 0Hz to 3.4MHz are supported. The I2C is an open-drain bus and therefore SDA and SCL require pullups. Optional resistors (24Ω) in series with SDA and SCL protect the device inputs from high-voltage spikes on the bus lines. Series resistors also minimize crosstalk and undershoot on bus signals. Figure 18 shows the functional diagram for the I2C-based communications controller. For additional information on I2C, refer to the I2C Bus Specification and User Manual which is available for free through the internet. Features ● ● ● ● ● ● I2C Revision 3.0 Compatible Serial Communications Channel 0Hz to 100kHz (Standard Mode) 0Hz to 400kHz (Fast Mode) 0Hz to 1MHz (Fast-Mode Plus) 0Hz to 3.4MHz (High-Speed Mode) Does not utilize I2C Clock Stretching I2C Simplified Block Diagram There are three pins (aside from GND) for the I2C-compatible interface. The VIO determines the logic level, SCL is the clock line, and SDA is the data line. Note that the interface does not have the ability to drive the SCL line. COMMUNICATIONS CONTROLLER VIO SCL INTERFACE DECODERS SHIFT REGISTERS BUFFERS COM SDA GND PERIPHERAL 0 PERIPHERAL 1 PERIPHERAL 2 PERIPHERAL N-1 PERIPHERAL N Figure 18. I2C Simplified Block Diagram www.analog.com Analog Devices | 63 MAX77642/MAX77643 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output Buck-Boost, 1-LDO for Long Battery Life Applications I2C System Configuration The I2C-compatible interface is a multimaster bus. The maximum number of devices that can attach to the bus is only limited by bus capacitance. A device on the I2C bus that sends data to the bus is called a transmitter. A device that receives data from the bus is called a receiver. The device that initiates a data transfer and generates the SCL clock signals to control the data transfer is a master. Any device that is being addressed by the master is considered a slave. The I2C-compatible interface operates as a slave on the I2C bus with transmit and receive capabilities. SDA SCL MASTER TRANSMITTER/ RECEIVER SLAVE RECEIVER SLAVE TRANSMITTER SLAVE TRANSMITTER/ RECEIVER MASTER TRANSMITTER/ RECEIVER Figure 19. I2C System Configuration I2C Interface Power The I2C interface derives its power from VIO. Typically a power input such as VIO would require a local 0.1μF ceramic bypass capacitor to ground. However, in highly integrated power distribution systems, a dedicated capacitor might not be necessary. If the impedance between VIO and the next closest capacitor (≥ 0.1μF) is less than 100mΩ in series with 10nH, then a local capacitor is not needed. Otherwise, bypass VIO to GND with a 0.1µF ceramic capacitor. The VIO accepts voltages from 1.7V to 3.6V (VIO). Cycling VIO does not reset the I2C registers. When VIO is less than VIOUVLO and VSYSA is less than VSYSAUVLO, SDA and SCL are high impedance. I2C Data Transfer One data bit is transferred during each SCL clock cycle. The data on SDA must remain stable during the high period of the SCL clock pulse. Changes in SDA while SCL is high are control signals. See the I2C Start and Stop Conditions section. Each transmit sequence is framed by a START (S) condition and a STOP (P) condition. Each data packet is 9 bits long: 8 bits of data followed by the acknowledge bit. Data is transferred with the MSB first. I2C Start and Stop Conditions When the serial interface is inactive, SDA and SCL idle high. A master device initiates communication by issuing a START condition. A START condition is a high-to-low transition on SDA with SCL high. A STOP condition is a low-to-high transition on SDA, while SCL is high. See Figure 20. A START condition from the master signals the beginning of a transmission to the device. The master terminates transmission by issuing a not-acknowledge followed by a STOP condition (see the I2C Acknowledge Bit section for information on not-acknowledge). The STOP condition frees the bus. To issue a series of commands to the slave, the master can issue repeated start (Sr) commands instead of a STOP command to maintain control of the bus. In general a repeated start command is functionally equivalent to a regular start command. www.analog.com Analog Devices | 64 MAX77642/MAX77643 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output Buck-Boost, 1-LDO for Long Battery Life Applications S Sr P SDA tSU_STA tSU_STO SCL tHD_STA tHD_STA Figure 20. I2C Start and Stop Conditions I2C Acknowledge Bit Both the I2C bus master and slave devices generate acknowledge bits when receiving data. The acknowledge bit is the last bit of each 9-bit data packet. To generate an acknowledge (A), the receiving device must pull SDA low before the rising edge of the acknowledge-related clock pulse (ninth pulse) and keep it low during the high period of the clock pulse. See Figure 21. To generate a not-acknowledge (nA), the receiving device allows SDA to be pulled high before the rising edge of the acknowledge-related clock pulse and leaves it high during the high period of the clock pulse. Monitoring the acknowledge bits allows for detection of unsuccessful data transfers. An unsuccessful data transfer occurs if a receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master should reattempt communication at a later time. This device issues an ACK for all register addresses in the possible address space even if the particular register does not exist. NOT ACKNOWLEDGE (NACK) S ACKNOWLEDGE (ACK) SDA tSU_DAT SCL 1 2 8 tHD_DAT 9 Figure 21. Acknowledge Bit www.analog.com Analog Devices | 65 MAX77642/MAX77643 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output Buck-Boost, 1-LDO for Long Battery Life Applications I2C Slave Address The I2C controller implements 7-bit slave addressing. An I2C bus master initiates communication with the slave by issuing a START condition followed by the slave address. See Figure 22. The OTP address is factory-programmable for one of two options. See Table 14. All slave addresses not mentioned in Table 14 are not acknowledged. Table 14. I2C Slave Address Options ADDRESS 7-BIT SLAVE ADDRESS 8-BIT WRITE ADDRESS 8-BIT READ ADDRESS Main Address (ADDR = 0)* 0x40, 0b 100 0000 0x80, 0b 1000 0000 0x81, 0b 1000 0001 Main Address (ADDR = 1)* 0x48, 0b 100 1000 0x90, 0b 1001 0000 0x91, 0b 1001 0001 Main Address (ADDR = 2)* 0x44, 0b 100 0100 0x88, 0b 1000 1000 0x89, 0b 1000 1001 Main Address (ADDR = 3)* 0x4C, 0b 100 1100 0x98, 0b 1001 1000 0x99, 0b 1001 1001 Test Mode** 0x49, 0b 100 1001 0x92, 0b 1001 0010 0x93, 0b 1001 0011 *Perform all reads and writes on the main address. The ADDR is a factory one-time programmable (OTP) option, allowing for address changes in the event of a bus conflict. **When test mode is unlocked, the additional address is acknowledged. Test mode details are confidential. If possible, leave the test mode address unallocated to allow for the rare event that debugging needs to be performed in cooperation with Maxim. S SDA 1 0 0 1 0 0 0 R/W A ACKNOWLEDGE SCL 1 2 3 4 5 6 7 8 9 Figure 22. Slave Address Example I2C Clock Stretching In general, the clock signal generation for the I2C bus is the responsibility of the master device. The I2C specification allows slow slave devices to alter the clock signal by holding down the clock line. The process in which a slave device holds down the clock line is typically called clock stretching. The IC does not use any form of clock stretching to hold down the clock line. I2C General Call Address This device does not implement the I2C specifications general call address and does not acknowledge the general call address (0b0000_0000). I2C Device ID This device does not support the I2C Device ID feature. www.analog.com Analog Devices | 66 MAX77642/MAX77643 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output Buck-Boost, 1-LDO for Long Battery Life Applications I2C Communication Speed This device is compatible with all four communication speed ranges as defined by the revision 3.0 I2C specification: ● ● ● ● 0Hz to 100kHz (Standard Mode) 0Hz to 400kHz (Fast Mode) 0Hz to 1MHz (Fast-Mode Plus) 0Hz to 3.4MHz (High-Speed Mode) Operating in standard mode, fast mode, and fast-mode plus does not require any special protocols. The main consideration when changing bus speed through this range is the combination of the bus capacitance and pullup resistors. Larger values of bus capacitance and pullup resistance increase the time constant (C x R), slowing bus operation. Therefore, when increasing bus speeds, the pullup resistance must be decreased to maintain a reasonable time constant. Refer to the Pullup Resistor Sizing section of the I2C bus specification and user manual (available for free on the internet) for detailed guidance on the pullup resistor selection. In general for bus capacitances of 200pF, a 100kHz bus needs 5.6kΩ pullup resistors, a 400kHz bus needs about 1.5kΩ pullup resistors, and a 1MHz bus needs 680Ω pullup resistors. Remember that, while the open-drain bus is low, the pullup resistor is dissipating power, and lower value pullup resistors dissipate more power (V2/R). Operating in high-speed mode requires some special considerations. For a full list of considerations, refer to the publicly available I2C bus specification and user manual. Major considerations with respect to this part are: ● The I2C bus master uses current source pullups to shorten the signal rise. ● The I2C slave must use a different set of input filters on its SDA and SCL lines to accommodate for the higher bus. ● The communication protocols need to utilize the high-speed master code. At power-up and after each stop condition, the bus input filters are set for standard mode, fast mode, and fast-mode plus (i.e., 0Hz to 1MHz). To switch the input filters for high-speed mode, use the high-speed master code protocols that are described in the I2C Communication Protocols section. I2C Communication Protocols Both writing to and reading from registers are supported as described in the following subsections. Writing to a Single Register Figure 23 shows the protocol for the I2C master device to write one byte of data to this device. This protocol is the same as the SMBus specification’s write byte protocol. The write byte protocol is as follows: 1. 2. 3. 4. 5. 6. 7. 8. The master sends a start command (S). The master sends the 7-bit slave address followed by a write bit (R/W = 0). The addressed slave asserts an acknowledge (A) by pulling SDA low. The master sends an 8-bit register pointer. The slave acknowledges the register pointer. The master sends a data byte. The slave updates with the new data. The slave asserts an acknowledge or not acknowledge for the data byte. The next rising edge on SDA loads the data byte into its target register and the data becomes active. 9. The master sends a stop condition (P) or a repeated start condition (Sr). Issuing a P ensures that the bus input filters are set for 1MHz or slower operation. Issuing an Sr leaves the bus input filters in their current state. www.analog.com Analog Devices | 67 MAX77642/MAX77643 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output Buck-Boost, 1-LDO for Long Battery Life Applications LEGEND MASTER TO SLAVE 1 S 7 SLAVE TO MASTER 1 1 SLAVE ADDRESS 0 A 8 1 REGISTER POINTER 8 A DATA R/W SDA B1 B0 ACK 1 ACK OR NACK 1 NUMBER OF BITS P OR SR* THE DATA IS LOADED INTO THE TARGET REGISTER AND BECOMES ACTIVE DURING THIS RISING EDGE. ACKNOWLEDGE SCL 7 8 9 *P FORCES THE BUS FILTERS TO SWITCH TO SUB-MEGAHERTZ MODE. SR LEAVES THE BUS FILTERS IN THEIR CURRENT STATE. Figure 23. Writing to a Single Register with the Write Byte Protocol Writing Multiple Bytes to Sequential Registers Figure 24 shows the protocol for writing to sequential registers. This protocol is similar to the write byte protocol in the Writing to a Single Register section, except the master continues to write after it receives the first byte of data. When the master is done writing, it issues a stop or repeated start. The write to sequential registers protocol is as follows: 1. 2. 3. 4. 5. 6. 7. The master sends a start command (S). The master sends the 7-bit slave address followed by a write bit (R/W = 0). The addressed slave asserts an acknowledge (A) by pulling SDA low. The master sends an 8-bit register pointer. The slave acknowledges the register pointer. The master sends a data byte. The slave acknowledges the data byte. The next rising edge on SDA loads the data byte into its target register and the data becomes active. 8. Steps 6 to 7 are repeated as many times as the master requires. 9. During the last acknowledge related clock pulse, the master can issue an acknowledge or a not acknowledge. 10. The master sends a stop condition (P) or a repeated start condition (Sr). Issuing a P ensures that the bus input filters are set for 1MHz or slower operation. Issuing an Sr leaves the bus input filters in their current state. www.analog.com Analog Devices | 68 MAX77642/MAX77643 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output Buck-Boost, 1-LDO for Long Battery Life Applications LEGEND MASTER TO SLAVE SLAVE TO MASTER 1 7 1 1 8 1 8 1 S SLAVE ADDRESS 0 A REGISTER POINTER X A DATA X A NUMBER OF BITS Α R/W 8 1 DATA X+1 A Α REGISTER POINTER = X + 1 8 1 DATA N-1 A REGISTER POINTER = N-1 8 1 DATA X+2 A NUMBER OF BITS Α REGISTER POINTER = X + 2 8 1 ACK OR NACK DATA N Α REGISTER POINTER = N 1 P OR SR* NUMBER OF BITS Β THE DATA IS LOADED INTO THE TARGET REGISTER AND BECOMES ACTIVE DURING THIS RISING EDGE. SDA B1 B0 ACK B9 9 1 ACKNOWLEDGE SCL 7 8 DETAIL: Α THE DATA IS LOADED INTO THE TARGET REGISTER AND BECOMES ACTIVE DURING THIS RISING EDGE. SDA B1 B0 ACK ACKNOWLEDGE SCL 7 8 9 DETAIL: Β *P FORCES THE BUS FILTERS TO SWITCH TO SUB-MEGAHERTZ MODE. SR LEAVES THE BUS FILTERS IN THEIR CURRENT STATE. Figure 24. Writing to Sequential Registers X to N www.analog.com Analog Devices | 69 MAX77642/MAX77643 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output Buck-Boost, 1-LDO for Long Battery Life Applications Reading from a Single Register Figure 25 shows the protocol for the I2C master device to read one byte of data. This protocol is the same as the SMBus specification’s read byte protocol. The read byte protocol is as follows: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. The master sends a start command (S). The master sends the 7-bit slave address followed by a write bit (R/W = 0). The addressed slave asserts an acknowledge (A) by pulling SDA low. The master sends an 8-bit register pointer. The slave acknowledges the register pointer. The master sends a repeated start command (Sr). The master sends the 7-bit slave address followed by a read bit (R/W = 1). The addressed slave asserts an acknowledge by pulling SDA low. The addressed slave places 8-bits of data on the bus from the location specified by the register pointer. The master issues a not acknowledge (nA). The master sends a stop condition (P) or a repeated start condition (Sr). Issuing a P ensures that the bus input filters are set for 1MHz or slower operation. Issuing an Sr leaves the bus input filters in their current state. Note that when this device receives a stop, the register pointer is not modified. Therefore, if the master re-reads the same register, it can immediately send another read command, omitting the command to send a register pointer. *P FORCES THE BUS FILTERS TO SWITCH TO SUB-MEGAHERTZ MODE. SR LEAVES THE BUS FILTERS IN THEIR CURRENT STATE. LEGEND MASTER TO SLAVE SLAVE TO MASTER 1 7 1 1 8 1 1 7 1 1 8 S SLAVE ADDRESS 0 A REGISTER POINTER X A Sr SLAVE ADDRESS 1 A DATA X R/W 1 1 NUMBER OF BITS A P or Sr* R/W Figure 25. Reading from a Single Register with the Read Byte Protocol www.analog.com Analog Devices | 70 MAX77642/MAX77643 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output Buck-Boost, 1-LDO for Long Battery Life Applications Reading from Sequential Registers Figure 26 shows the protocol for reading from sequential registers. This protocol is similar to the read byte protocol except the master issues an acknowledge to signal the slave that it wants more data. When the master has all the data it requires, it issues a not acknowledge (nA) and a stop (P) to end the transmission.The continuous read from sequential registers protocol is as follows: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. The master sends a start command (S). The master sends the 7-bit slave address followed by a write bit (R/W = 0). The addressed slave asserts an acknowledge (A) by pulling SDA low. The master sends an 8-bit register pointer. The slave acknowledges the register pointer. The master sends a repeated start command (Sr). The master sends the 7-bit slave address followed by a read bit (R/W = 1). The addressed slave asserts an acknowledge by pulling SDA low. The addressed slave places 8-bits of data on the bus from the location specified by the register pointer. The master issues an acknowledge (A) signaling the slave that it wishes to receive more data. Steps 9 to 10 are repeated as many times as the master requires. Following the last byte of data, the master must issue a not acknowledge (nA) to signal that it wishes to stop receiving data. 12. The master sends a stop condition (P) or a repeated start condition (Sr). Issuing a stop (P) ensures that the bus input filters are set for 1MHz or slower operation. Issuing an Sr leaves the bus input filters in their current state. Note that when this device receives a stop, it does not modify its register pointer. Therefore, if the master re-reads the same register, it can immediately send another read command, omitting the command to send a register pointer. *P FORCES THE BUS FILTERS TO SWITCH TO SUB-MEGAHERTZ MODE. SR LEAVES THE BUS FILTERS IN THEIR CURRENT STATE. LEGEND MASTER TO SLAVE SLAVE TO MASTER 1 7 1 1 8 1 1 7 1 1 8 1 S SLAVE ADDRESS 0 A REGISTER POINTER X A SR SLAVE ADDRESS 1 A DATA X A 1 8 1 A DATA X+3 A R/NW R/nW 8 1 8 DATA X+1 A DATA X+2 REGISTER POINTER = X + 1 REGISTER POINTER = X + 2 1 8 1 8 1 DATA N-2 A DATA N-1 A DATA N NA REGISTER POINTER = N-1 NUMBER OF BITS REGISTER POINTER = X + 3 8 REGISTER POINTER = N-2 NUMBER OF BITS 1 P OR SR* NUMBER OF BITS REGISTER POINTER = N Figure 26. Reading Continuously from Sequential Registers X to N www.analog.com Analog Devices | 71 MAX77642/MAX77643 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output Buck-Boost, 1-LDO for Long Battery Life Applications Engaging HS-Mode for Operation up to 3.4MHz Figure 27 shows the protocol for engaging HS-mode operation. HS-mode operation allows for a bus operating speed up to 3.4MHz. The engaging HS-mode protocol is as follows: 1. 2. 3. 4. 5. Begin the protocol while operating at a bus speed of 1MHz or lower. The master sends a start command (S). The master sends the 8-bit master code of 0b0000 1XXX where 0bXXX are don’t care bits. The addressed slave issues a not acknowledge (nA). The master can increase its bus speed up to 3.4MHz and issue any read/write operation. The master may continue to issue high-speed read/write operations until a stop (P) is issued. To continue operations in high-speed mode, use repeated start (Sr) LEGEND MASTER TO SLAVE SLAVE TO MASTER 1 8 1 1 S HS-MASTER CODE nA SR FAST-MODE ANY R/W PROTOCOL FOLLOWED BY SR SR ANY R/W PROTOCOL FOLLOWED BY SR HS-MODE SR ANY READ/WRITE PROTOCOL P FAST-MODE Figure 27. Engaging HS Mode www.analog.com Analog Devices | 72 MAX77642/MAX77643 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output Buck-Boost, 1-LDO for Long Battery Life Applications Register Map MAX77643 ADDRESS NAME MSB LSB Global 0x00 INT_GLBL0[7:0] 0x01 INT_GLBL1[7:0] RSVD RSVD 0x02 ERCFLAG[7:0] SBB_FA ULT_F WDT_EX P_F 0x03 STAT_GLBL[7:0] DIDM BOK 0x04 INTM_GLBL0[7:0] RSVD 0x05 INTM_GLBL1[7:0] 0x06 CNFG_GLBL0[7:0] 0x07 CNFG_GLBL1[7:0] 0x08 CNFG_GPIO0[7:0] RSVD[1:0] ALT_GPI O0 DBEN_G PI DO DRV DI DIR 0x09 CNFG_GPIO1[7:0] RSVD[1:0] ALT_GPI O1 DBEN_G PI DO DRV DI DIR 0x10 CID[7:0] WDT_M ODE WDT_CL R WDT_E N WDT_LO CK – – 0x17 CNFG_WDT[7:0] RSVD DOD_R TJAL2_R TJAL1_R nEN_R nEN_F GPI0_R GPI0_F LDO_F SBB2_F SBB1_F SBB0_F GPI1_R GPI1_F SFT_CR ST_F SFT_OF F_F MRST_F INUVLO INOVLO TOVLD RSVD DOD_S TJAL2_S TJAL1_S STAT_E N STAT_IR Q DOD_R M TJAL2_R M TJAL1_R M nEN_RM nEN_FM GPI0_R M GPI0_F M RSVD RSVD LDO_M SBB2_F M SBB1_F M SBB0_F M GPI1_R M GPI1_F M PU_DIS MRST SBIA_LP M nEN_MODE[1:0] RSVD[4:0] – – RSVD[1:0] – DBEN_n EN SFT_CTRL[1:0] SBB_F_ SHUTDN AUTO_WKT[1:0] CID[4:0] WDT_PER[1:0] SBB 0x28 CNFG_SBB_TOP[7:0] 0x29 CNFG_SBB0_A[7:0] 0x2A CNFG_SBB0_B[7:0] 0x2B CNFG_SBB1_A[7:0] 0x2C CNFG_SBB1_B[7:0] 0x2D CNFG_SBB2_A[7:0] 0x2E CNFG_SBB2_B[7:0] 0x2F CNFG_DVS_SBB0_A[7 :0] DIS_LP M – – – DRV_SBB[1:0] TV_SBB0[7:0] OP_MODE[1:0] IP_SBB0[1:0] ADE_SB B0 EN_SBB0[2:0] TV_SBB1[7:0] OP_MODE[1:0] IP_SBB1[1:0] ADE_SB B1 EN_SBB1[2:0] TV_SBB2[7:0] OP_MODE[1:0] IP_SBB2[1:0] ADE_SB B2 EN_SBB2[2:0] TV_SBB0_DVS[7:0] LDO 0x38 CNFG_LDO0_A[7:0] 0x39 CNFG_LDO0_B[7:0] www.analog.com TV_OFS _LDO TV_LDO[6:0] RSVD[2:0] LDO_MD ADE_LD O EN_LDO[2:0] Analog Devices | 73 MAX77642/MAX77643 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output Buck-Boost, 1-LDO for Long Battery Life Applications Register Details INT_GLBL0 (0x00) BIT Field Reset Access Type BITFIELD 7 6 5 4 3 2 1 0 RSVD DOD_R TJAL2_R TJAL1_R nEN_R nEN_F GPI0_R GPI0_F 0b0 0b0 0b0 0b0 0b0 0b0 0b0 0b0 Read Clears All Read Clears All Read Clears All Read Clears All Read Clears All Read Clears All Read Clears All Read Clears All BITS DESCRIPTION DECODE RSVD 7 RSVD DOD_R 6 LDO Dropout Detector Rising Interrupt 0b0 = The LDO has not detected dropout since the last time this bit was read. 0b1 = The LDO has detected dropout since the last time this bit was read. Thermal Alarm 2 Rising Interrupt 0b0 = The junction temperature has not risen above TJAL2 since the last time this bit was read. 0b1 = The junction temperature has risen above TJAL2 since the last time this bit was read. Thermal Alarm 1 Rising Interrupt 0b0 = The junction temperature has not risen above TJAL1 since the last time this bit was read. 0b1 = The junction temperature has risen above TJAL1 since the last time this bit was read. TJAL2_R 5 TJAL1_R 4 nEN_R 3 nEN Rising Interrupt 0b0 = No nEN rising edges have occurred since the last time this bit was read. 0b1 = A nEN rising edge has occurred since the last time this bit was read. nEN_F 2 nEN Falling Interrupt 0b0 = No nEN falling edges have occurred since the last time this bit was read. 0b1 = A nEN falling edge occurred since the last time this bit was read. GPI Rising Interrupt GPI0_R 1 0b0 = No GPI rising edges have occurred since the last time this bit was read. 0b1 = A GPI rising edge has occurred since the last time this bit was read. Note that "GPI" refers to the GPIO programmed to be an input. GPI Falling Interrupt GPI0_F 0 Note that the GPI is the GPIO programmed to be an input. 0b0 = No GPI falling edges have occurred since the last time this bit was read. 0b1 = A GPI falling edge has occurred since the last time this bit was read. INT_GLBL1 (0x01) BIT 7 6 5 4 3 2 1 0 GPI1_F Field RSVD RSVD LDO_F SBB2_F SBB1_F SBB0_F GPI1_R Reset 0b000 0b000 0b0 0b0 0b0 0b0 0b0 0b0 Read Clears All Read Clears All Read Clears All Read Clears All Read Clears All Read Clears All Read Clears All Read Clears All Access Type BITFIELD RSVD www.analog.com BITS 7 DESCRIPTION DECODE Reserved. Unutilized bit. Write to 0. Reads are don't care. Analog Devices | 74 MAX77642/MAX77643 BITFIELD BITS Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output Buck-Boost, 1-LDO for Long Battery Life Applications DESCRIPTION DECODE RSVD 6 Reserved. Unutilized bit. Write to 0. Reads are don't care. LDO_F 5 LDO Fault Interrupt SBB2_F 4 SBB1_F 3 SBB0_F 2 GPI1_R 1 0b0 = No fault has occurred on LDO since the last time this bit was read. 0b1 = LDO has fallen out of regulation since the last time this bit was read. 0b0 = No fault has occurred on SBB2 since the last time this bit was read. 0b1 = SBB2 has fallen out of regulation since the last time this bit was read. SBB2 Fault Indicator 0b0 = No fault has occurred on SBB1 since the last time this bit was read. 0b1 = SBB1 has fallen out of regulation since the last time this bit was read. SBB1 Fault Indicator 0b0 = No fault has occurred on SBB0 since the last time this bit was read. 0b1 = SBB0 has fallen out of regulation since the last time this bit was read. SBB0 Fault Indicator GPI1 Rising Interrupt 0b0 = No GPI1 rising edges have occurred since the last time this bit was read. 0b1 = A GPI1 rising edge has occurred since the last time this bit was read. Note that "GPI" refers to the GPIO programmed to be an input. GPI1 Falling Interrupt GPI1_F 0 Note that the GPI is the GPIO programmed to be an input. 0b0 = No GPI1 falling edges have occurred since the last time this bit was read. 0b1 = A GPI1 falling edge has occurred since the last time this bit was read. ERCFLAG (0x02) BIT Field Reset Access Type BITFIELD SBB_FAULT _F WDT_EXP_F SFT_CRST_ F www.analog.com 7 6 5 4 3 2 1 0 SBB_FAUL T_F WDT_EXP_ F SFT_CRST _F SFT_OFF_ F MRST_F INUVLO INOVLO TOVLD 0b0 0b0 0b0 0b0 0b0 0b0 0b0 0b0 Read Clears All Read Clears All Read Clears All Read Clears All Read Clears All Read Clears All Read Clears All Read Clears All BITS DESCRIPTION DECODE 7 SBBx Fault and Shutdown Flag. This bit sets when a SBBx fault and consequent SBBx shutdown occurs. 0b0 = No SBB shutdown occurred since the last time this bit was read. 0b1 = SBBx fault and SBB shutdown occurred since the last time this bit was read. 6 Watchdog Timer OFF or RESET Flag. This bit sets when the watchdog timer expires and causes a power-off or a reset; based on WDT_MODE bitfield setting. 0b0 = Watchdog timer has not caused a power-off or reset since the last time this bit was read. 0b1 = Watchdog timer has expired and caused a power-off or reset since the last time this bit was read. Software Cold Reset Flag 0b0 = The software cold reset has not occurred since the last read of this register. 0b1 = The software cold reset has occurred since the last read of this register. This indicates that software has set SFT_CTRL[1:0] = 0b01. 5 Analog Devices | 75 MAX77642/MAX77643 BITFIELD SFT_OFF_F MRST_F INUVLO INOVLO TOVLD BITS 4 3 2 1 0 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output Buck-Boost, 1-LDO for Long Battery Life Applications DESCRIPTION DECODE Software OFF Flag 0b0 = The SFT_OFF function has not occurred since the last read of this register. 0b1 = The SFT_OFF function has occurred since the last read of this register. This indicates that software has set SFT_CTRL[1:0] = 0b10. Manual Reset Timer 0b0 = A manual reset has not occurred since the last read of this register. 0b1 = A manual reset has occurred since the last read of this register. IN Domain Undervoltage Lockout 0b0 = The IN domain undervoltage lockout has not occurred since the last read of this register. 0b1 = The IN domain undervoltage lockout has occurred since the last read of this register. This indicates that the IN domain voltage fell below VINUVLO (~2.6V) IN Domain Overvoltage Lockout 0b0 = The IN domain overvoltage lockout has not occurred since the last read of this register. 0b1 = The IN domain overvoltage lockout has occurred since the last read of this register. This indicates that the IN domain voltage rose above VINOVLO (~5.85V) Thermal Overload 0b0 = Thermal overload has not occurred since the last read of this register. 0b1 = Thermal overload has occurred since the last read of this register. This indicates that the junction temperature has exceeded +165ºC. STAT_GLBL (0x03) 7 6 5 4 3 2 1 0 Field BIT DIDM BOK RSVD DOD_S TJAL2_S TJAL1_S STAT_EN STAT_IRQ Reset OTP 0b1 0b0 0b0 0b0 0b0 0b0 0b0 Read Only Read Only Read Clears All Read Only Read Only Read Only Read Only Read Only Access Type BITFIELD BITS DESCRIPTION DECODE DIDM 7 Device Identification Bits for Metal Options 0b0 = MAX77643 0b1 = Reserved BOK 6 BOK Interrupt Status 0b0 = Main bias is not ready. 0b1 = Main bias enabled and ready. RSVD 5 Reserved. Unutilized bit. Write to 0. Reads are don't care. DOD_S 4 LDO Dropout Detector Rising Status 0b0 = LDO is not in dropout. 0b1 = LDO is in dropout. TJAL2_S 3 Thermal Alarm 2 Status 0b0 = The junction temperature is less than TJA2. 0b1 = The junction temperature is greater than TJAL2. TJAL1_S 2 Thermal Alarm 1 Status 0b0 = The junction temperature is less than TJAL1. 0b1 = The junction temperature is greater than TJAL1. STAT_EN 1 Debounced Status for the nEN Input 0b0 = nEN is not active (logic high). 0b1 = nEN is active (logic low). www.analog.com Analog Devices | 76 MAX77642/MAX77643 BITFIELD STAT_IRQ Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output Buck-Boost, 1-LDO for Long Battery Life Applications BITS DESCRIPTION DECODE 0 Software Version of the nIRQ MOSFET Gate Drive 0b0 = Unmasked gate drive is logic low. 0b1 = Unmasked gate drive is logic high. INTM_GLBL0 (0x04) 7 6 5 4 3 2 1 0 Field BIT RSVD DOD_RM TJAL2_RM TJAL1_RM nEN_RM nEN_FM GPI0_RM GPI0_FM Reset 0b0 0b1 0b1 0b1 0b1 0b1 0b1 0b1 Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Access Type BITFIELD RSVD DOD_RM TJAL2_RM TJAL1_RM nEN_RM nEN_FM GPI0_RM GPI0_FM www.analog.com BITS 7 6 5 4 3 2 1 0 DESCRIPTION DECODE Reserved. Unutilized bit. Write to 0. Reads are don't care. LDO Dropout Detector Rising Interrupt Mask 0b0 = Unmasked. If DOD_R goes from 0 to 1, then nIRQ goes low. nIRQ goes high when all interrupt bits are cleared. 0b1 = Masked. nIRQ does not go low due to DOD_R. Thermal Alarm 2 Rising Interrupt Mask 0b0 = Unmasked. If TJAL2_R goes from 0 to 1, then nIRQ goes low. nIRQ goes high when all interrupt bits are cleared. 0b1 = Masked. nIRQ does not go low due to TJAL2_R. Thermal Alarm 1 Rising Interrupt Mask 0b0 = Unmasked. If TJAL1_R goes from 0 to 1, then nIRQ goes low. nIRQ goes high when all interrupt bits are cleared. 0b1 = Masked. nIRQ does not go low due to TJAL1_R. nEN Rising Interrupt Mask 0b0 = Unmasked. If nEN_R goes from 0 to 1, then nIRQ goes low. nIRQ goes high when all interrupt bits are cleared. 0b1 = Masked. nIRQ does not go low due to nEN_R. nEN Falling Interrupt Mask 0b0 = Unmasked. If nEN_F goes from 0 to 1, then nIRQ goes low. nIRQ goes high when all interrupt bits are cleared. 0b1 = Masked. nIRQ does not go low due to nEN_F. GPI0 Rising Interrupt Mask 0b0 = Unmasked. If GPI0_R goes from 0 to 1, then nIRQ goes low. nIRQ goes high when all interrupt bits are cleared. 0b1 = Masked. nIRQ does not go low due to GPI0_R. GPI0 Falling Interrupt Mask 0b0 = Unmasked. If GPI0_F goes from 0 to 1, then nIRQ goes low. nIRQ goes high when all interrupt bits are cleared. 0b1 = Masked. nIRQ does not go low due to GPI0_F. Analog Devices | 77 MAX77642/MAX77643 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output Buck-Boost, 1-LDO for Long Battery Life Applications INTM_GLBL1 (0x05) 7 6 5 4 3 2 1 0 Field BIT RSVD RSVD LDO_M SBB2_FM SBB1_FM SBB0_FM GPI1_RM GPI1_FM Reset 0b0 0b0 0b1 0b0 0b0 0b0 0b1 0b1 Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Access Type BITFIELD BITS DESCRIPTION DECODE RSVD 7 Reserved. Unutilized bit. Write to 0. Reads are don't care. RSVD 6 Reserved. Unutilized bit. Write to 0. Reads are don't care. LDO_M SBB2_FM SBB1_FM SBB0_FM GPI1_RM GPI1_FM 5 4 3 2 1 0 0b0 = Unmasked. If LDO_F goes from 0 to 1, then nIRQ goes low. nIRQ goes high when all interrupt bits are cleared. 0b1 = Masked. nIRQ does not go low due to LDO_F. LDO Fault Interrupt Mask 0b0 = Unmasked. If SBB2_F goes from 0 to 1, then nIRQ goes low. nIRQ goes high when all interrupt bits are cleared. 0b1 = Masked. nIRQ does not go low due to SBB2_F. SBB2 Fault Interrupt Mask 0b0= Unmasked. If SBB1_F goes from 0 to 1, then nIRQ goes low. nIRQ goes high when all interrupt bits are cleared. 0b1 = Masked. nIRQ does not go low due to SBB1_F. SBB1 Fault Interrupt Mask 0b0 = Unmasked. If SBB0_F goes from 0 to 1, then nIRQ goes low. nIRQ goes high when all interrupt bits are cleared. 0b1 = Masked. nIRQ does not go low due to SBB0_F. SBB0 Fault Interrupt Mask GPI1 Rising Interrupt Mask 0b0 = Unmasked. If GPI1_R goes from 0 to 1, then nIRQ goes low. nIRQ goes high when all interrupt bits are cleared. 0b1 = Masked. nIRQ does not go low due to GPI1_R. GPI1 Falling Interrupt Mask 0b0 = Unmasked. If GPI1_F goes from 0 to 1, then nIRQ goes low. nIRQ goes high when all interrupt bits are cleared. 0b1 = Masked. nIRQ does not go low due to GPI1_F. CNFG_GLBL0 (0x06) 7 6 5 Field BIT PU_DIS MRST SBIA_LPM nEN_MODE[1:0] DBEN_nEN SFT_CTRL[1:0] Reset OTP OTP OTP OTP OTP 0b00 Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Access Type www.analog.com 4 3 2 1 0 Analog Devices | 78 MAX77642/MAX77643 BITFIELD BITS Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output Buck-Boost, 1-LDO for Long Battery Life Applications DESCRIPTION DECODE PU_DIS 7 nEN Internal Pullup Resistor 0b0 = Strong internal nEN pullup (200kΩ) 0b1 = Weak internal nEN pullup (10MΩ) MRST 6 Sets the Manual Reset Time (tMRST) 0b0 = 8s 0b1 = 4s SBIA_LPM 5 Main Bias Power Mode 0b0 = Main bias is in normal-power mode by software. 0b1 = Main bias is in low-power mode by software. nEN Input (ON-KEY) Default Configuration Mode 0b00 = Push-button mode 0b01 = Slide-switch mode 0b10 = Logic mode 0b11 = Reserved nEN_MODE 4:3 0b0 = 500μs Debounce 0b1 = 30ms Debounce DBEN_nEN 2 Debounce Timer Enable for the nEN Pin Applies only to push button and slide switch Mmode Software Reset Functions SFT_CTRL 1:0 Note that the SFT_CRST and SFT_OFF commands initiate the power-down sequence flow as described in the data sheet. This power-down sequence flow has delay elements that add up to 205.24ms (60ms delay + 10.24ms nRST assert delay + 4x2.56ms power-down slot delays + 125ms output discharge delay). If issuing the SFT_CRST and/or SFT_OFF functions in software, wait for more than 300ms before trying to issue any additional commands through I2C. 0b00 = No action 0b01 = Software cold reset (SFT_CRST). The device powers down, resets, and then powers up again. 0b10 = Software off (SFT_OFF). The device powers down, resets, and then remains off and waiting for a wake-up event. 0b11 = Auto Wake Up (SFT_AUTO) The device powers down, and then automatically starts power up sequence after time determined in AUTO_WKT. Note that the registers do not get reset with Auto Wake Up. CNFG_GLBL1 (0x07) BIT 7 6 5 4 3 2 1 0 Field RSVD[4:0] SBB_F_SH UTDN AUTO_WKT[1:0] Reset 0b0000 0b0 0x00 Write, Read Write, Read Write, Read Access Type BITFIELD RSVD SBB_F_SHU TDN AUTO_WKT www.analog.com BITS 7:3 2 1:0 DESCRIPTION DECODE Reserved. Unutilized bit. Write to 0. Reads are don't care. SBB Shutdown from SBB Fault 0b0 = The SBB regulators do not shut off when an SBB fault occurs. 0b1 = The SBB regulators powers down sequentially when a SBB fault occurs. Auto Wake-Up Timer 0b00 = 100ms Auto Wake-up Time 0b01 = 200ms Auto Wake-up Time 0b10 = 500ms Auto Wake-up Time 0b11 = 1000ms Auto Wake-up Time Analog Devices | 79 MAX77642/MAX77643 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output Buck-Boost, 1-LDO for Long Battery Life Applications CNFG_GPIO0 (0x08) 5 4 3 2 1 0 Field BIT 7 RSVD[1:0] ALT_GPIO0 DBEN_GPI DO DRV DI DIR Reset 0b0 OTP 0b0 0b0 0b0 0b0 0b1 Write, Read Write, Read Write, Read Write, Read Write, Read Read Only Write, Read Access Type BITFIELD RSVD 6 BITS 7:6 DESCRIPTION DECODE Reserved. Unutilized bit. Write to 0. Reads are don't care. ALT_GPIO0 5 Alternate Mode Enable for GPIO0 0b0 = Standard GPIO 0b1 = GPIO controls whether SBB0 is set by TV_SBB0 or TV_SBB0_DVS DBEN_GPI 4 General Purpose Input Debounce Timer Enable 0b0 = No debounce 0b1 = 30ms debounce This bit is a don't care when DIR = 1 (configured as input). DO 3 When set for GPO (DIR = 0): 0b0 = GPIO is output logic low. 0b1 = GPIO is output logic high when set as pushpull output (DRV = 1). GPIO is high-impedance when set as an open-drain output (DRV = 0). General Purpose Output Data Output This bit is a don't care when DIR = 1 (configured as input). DRV 2 General Purpose Output Driver Type DI 1 GPIO Digital Input Value. Irrespective of whether the GPIO is set for GPI (DIR = 1) or GPO (DIR = 0), DI reflects the state of the GPIO. 0b0 = Input logic low 0b1 = Input logic high DIR 0 GPIO Direction 0b0 = General purpose output (GPO) 0b1 = General purpose input (GPI) When set for GPO (DIR = 0): 0b0 = Open-drain 0b1 = Push-pull CNFG_GPIO1 (0x09) 5 4 3 2 1 0 Field BIT 7 RSVD[1:0] ALT_GPIO1 DBEN_GPI DO DRV DI DIR Reset 0b00 OTP 0b0 0b0 0b0 0b0 0b1 Write, Read Write, Read Write, Read Write, Read Write, Read Read Only Write, Read Access Type BITFIELD RSVD 6 BITS 7:6 DESCRIPTION DECODE Reserved. Unutilized bit. Write to 0. Reads are don't care. ALT_GPIO1 5 Alternate Mode Enable for GPIO1 0b0 = Standard GPIO 0b1 = Flexible power sequencer active-high output for SBB2. DBEN_GPI 4 General Purpose Input Debounce Timer Enable 0b0 = No debounce 0b1 = 30ms debounce www.analog.com Analog Devices | 80 MAX77642/MAX77643 BITFIELD Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output Buck-Boost, 1-LDO for Long Battery Life Applications BITS DESCRIPTION DECODE This bit is a don't care when DIR = 1 (configured as input). DO 3 When set for GPO (DIR = 0): 0b0 = GPIO is output logic low. 0b1 = GPIO is output logic high when set as pushpull output (DRV = 1). GPIO is high-impedance when set as an open-drain output (DRV = 0). General Purpose Output Data Output This bit is a don't care when DIR = 1 (configured as input). DRV 2 General Purpose Output Driver Type DI 1 GPIO Digital Input Value. Irrespective of whether the GPIO is set for GPI (DIR = 1) or GPO (DIR = 0), DI reflects the state of the GPIO. 0b0 = Input logic low 0b1 = Input logic high DIR 0 GPIO Direction 0b0 = General purpose output (GPO) 0b1 = General purpose input (GPI) When set for GPO (DIR = 0): 0b0 = Open-drain 0b1 = Push-pull CID (0x10) 7 6 5 Field BIT – – – CID[4:0] Reset – – – OTP Access Type – – – Read Only BITFIELD CID 4 3 2 1 0 BITS DESCRIPTION 4:0 Chip Identification Code The chip identification code refers to a set of reset values in the register map, or the "OTP configuration." CNFG_WDT (0x17) BIT 7 6 5 4 3 2 1 0 WDT_CLR WDT_EN WDT_LOC K Field RSVD[1:0] WDT_PER[1:0] WDT_MOD E Reset 0b00 0b11 0b0 0b0 OTP OTP Write, Read Write, Read Write, Read Write, Read Write, Read Read Only Access Type BITFIELD RSVD WDT_PER www.analog.com BITS DESCRIPTION 7:6 Reserved. Unutilized bit. Write to 0. Reads are don't care. 5:4 Watchdog Timer Period. Sets tWD. Watchdog timer is reset to the programmed value as soon as this bitfield is changed. DECODE 0b00 = 16 seconds 0b01 = 32 seconds 0b10 = 64 seconds 0b11 = 128 seconds Analog Devices | 81 MAX77642/MAX77643 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output Buck-Boost, 1-LDO for Long Battery Life Applications BITFIELD BITS DESCRIPTION DECODE WDT_MODE 3 Watchdog Timer Expired Action. Determines what the IC does after the watchdog timer expires. 0b0 = Watchdog timer expire causes power-off. 0b1 = Watchdog timer expire causes power reset. WDT_CLR 2 Watchdog Timer Clear Control. Set this bit to feed (reset) the watchdog timer. 0b0 = Watchdog timer period is not reset. 0b1 = Watchdog timer is reset back to tWD. WDT_EN 1 Watchdog Timer Enable. Write protected depending on WDT_LOCK. 0b0 = Watchdog timer is not enabled. 0b1 = Watchdog timer is enabled. The timer expires if not reset by setting WDT_CLR. WDT_LOCK 0 Factory-Set Safety Bit for the Watchdog Timer. Determines if the timer can be disabled through WDT_EN or not. 0b0 = Watchdog timer can be enabled and disabled with WDT_EN. 0b1 = Watchdog timer can not be disabled with WDT_EN. However, WDT_EN can still be used to enable the watchdog timer. CNFG_SBB_TOP (0x28) 7 6 5 4 3 2 1 Field BIT DIS_LPM – – – – – DRV_SBB[1:0] Reset 0b0 – – – – – OTP Write, Read – – – – – Write, Read Access Type BITFIELD DIS_LPM DRV_SBB BITS 7 1:0 DESCRIPTION 0 DECODE Disables the Automatic Low-Power Mode for Each SIMO Channel. 0b0 = Automatic low power mode for each SIMO channel 0b1 = Disable low power mode feature for each SIMO channel SIMO Buck-Boost (All Channels) Drive Strength Trim. See the Drive Strength section for more details. 0b00 = Fastest transition time 0b01 = A little slower than 0b00 0b10 = A little slower than 0b01 0b11 = A little slower than 0b10 CNFG_SBB0_A (0x29) BIT 7 6 5 4 3 Field TV_SBB0[7:0] Reset OTP Access Type www.analog.com 2 1 0 Write, Read Analog Devices | 82 MAX77642/MAX77643 BITFIELD TV_SBB0 BITS Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output Buck-Boost, 1-LDO for Long Battery Life Applications DESCRIPTION DECODE SIMO Buck-Boost Channel 0 Target Output Voltage This 8-bit configuration is a linear transfer function that starts at 0.5V and ends at 5.5V with 25mV increments. 7:0 0x00 = 0.500V 0x01 = 0.525V 0x02 = 0.550V 0x03 = 0.575V 0x04 = 0.600V 0x05 = 0.625V 0x06 = 0.650V 0x07 = 0.675V 0x08 = 0.700V ... 0xC5 = 5.425V 0xC6 = 5.450V 0xC7 = 5.475V 0xC8 to 0xFF = 5.500V CNFG_SBB0_B (0x2A) BIT 7 6 5 4 3 2 1 0 Field OP_MODE[1:0] IP_SBB0[1:0] ADE_SBB0 EN_SBB0[2:0] Reset OTP OTP OTP OTP Write, Read Write, Read Write, Read Write, Read Access Type BITFIELD BITS DESCRIPTION DECODE OP_MODE 7:6 Operation Mode of SBB0 0b00 = Automatic 0b01 = Buck mode 0b10 = Boost mode 0b11 = Buck-boost mode IP_SBB0 5:4 SIMO Buck-Boost Channel 0 Peak Current Limit 0b00 = 1.000A 0b01 = 0.750A 0b10 = 0.500A 0b11 = 0.333A SIMO Buck-Boost Channel 0 ActiveDischarge Enable 0b0 = The active discharge function is disabled. When SBB0 is disabled, its discharge rate is a function of the output capacitance and the external load. 0b1 = The active discharge function is enabled. When SBB0 is disabled, an internal resistor (RAD_SBB0) is activated from SBB0 to PGND to help the output voltage discharge. The output voltage discharge rate is a function of the output capacitance, the external loading, and the internal RAD_SBB0 load. ADE_SBB0 3 Enable Control for SIMO Buck-Boost Channel 0. Select the FPS slot that the channel powers up and powers down in or whether the channel is forced on or off. EN_SBB0 www.analog.com 2:0 Prior to enabling the SIMO, program the bias circuits to normal-power mode (SBIA_LPM = 0). After the SIMO is enabled, the bias circuits may be programmed back to lowpower mode (SBIA_LPM = 1) to decrease quiescent current. 0b000 = FPS slot 0 0b001 = FPS slot 1 0b010 = FPS slot 2 0b011 = FPS slot 3 0b100 = Off irrespective of FPS 0b101 = Same as 0b100 0b110 = On irrespective of FPS 0b111 = Same as 0b110 Analog Devices | 83 MAX77642/MAX77643 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output Buck-Boost, 1-LDO for Long Battery Life Applications CNFG_SBB1_A (0x2B) BIT 7 6 5 4 3 Field TV_SBB1[7:0] Reset OTP Access Type BITFIELD TV_SBB1 2 1 0 Write, Read BITS DESCRIPTION DECODE SIMO Buck-Boost Channel 1 Target Output Voltage This 8-bit configuration is a linear transfer function that starts at 0.5V and ends at 5.5V with 25mV increments. 7:0 0x00 = 0.500V 0x01 = 0.525V 0x02 = 0.550V 0x03 = 0.575V 0x04 = 0.600V 0x05 = 0.625V 0x06 = 0.650V 0x07 = 0.675V 0x08 = 0.700V ... 0xC5 = 5.425V 0xC6 = 5.450V 0xC7 = 5.475V 0xC8 to 0xFF = 5.500V CNFG_SBB1_B (0x2C) BIT 7 6 5 4 3 2 1 0 Field OP_MODE[1:0] IP_SBB1[1:0] ADE_SBB1 EN_SBB1[2:0] Reset OTP OTP OTP OTP Write, Read Write, Read Write, Read Write, Read Access Type BITFIELD OP_MODE IP_SBB1 ADE_SBB1 www.analog.com BITS DESCRIPTION DECODE 7:6 Operation Mode of SBB1 0b00 = Automatic 0b01 = Buck mode 0b10 = Boost mode 0b11 = Buck-boost mode 5:4 SIMO Buck-Boost Channel 1 Peak Current Limit 0b00 = 1.000A 0b01 = 0.750A 0b10 = 0.500A 0b11 = 0.333A SIMO Buck-Boost Channel 1 ActiveDischarge Enable 0b0 = The active discharge function is disabled. When SBB1 is disabled, its discharge rate is a function of the output capacitance and the external load. 0b1 = The active discharge function is enabled. When SBB1 is disabled, an internal resistor (RAD_SBB1) is activated from SBB1 to PGND to help the output voltage discharge. The output voltage discharge rate is a function of the output capacitance, the external loading, and the internal RAD_SBB1 load. 3 Analog Devices | 84 MAX77642/MAX77643 BITFIELD BITS Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output Buck-Boost, 1-LDO for Long Battery Life Applications DESCRIPTION DECODE Enable Control for SIMO Buck-Boost Channel 1. Select the FPS slot that the channel powers up and powers down in or whether the channel is forced on or off. EN_SBB1 2:0 0b000 = FPS slot 0 0b001 = FPS slot 1 0b010 = FPS slot 2 0b011 = FPS slot 3 0b100 = Off irrespective of FPS 0b101 = Same as 0b100 0b110 = On irrespective of FPS 0b111 = Same as 0b110 Prior to enabling the SIMO, program the bias circuits to normal-power mode (SBIA_LPM = 0). After the SIMO is enabled, the bias circuits may be programmed back to lowpower mode (SBIA_LPM = 1) to decrease quiescent current. CNFG_SBB2_A (0x2D) BIT 7 6 5 4 3 Field TV_SBB2[7:0] Reset OTP Access Type BITFIELD TV_SBB2 2 1 0 Write, Read BITS DESCRIPTION DECODE SIMO Buck-Boost Channel 2 Target Output Voltage This 8-bit configuration is a linear transfer function that starts at 0.5V and ends at 5.5V with 25mV increments. 7:0 0x00 = 0.500V 0x01 = 0.525V 0x02 = 0.550V 0x03 = 0.575V 0x04 = 0.600V 0x05 = 0.625V 0x06 = 0.650V 0x07 = 0.675V 0x08 = 0.700V ... 0xC5 = 5.425V 0xC6 = 5.450V 0xC7 = 5.475V 0xC8 to 0xFF = 5.500V CNFG_SBB2_B (0x2E) BIT 7 6 5 4 3 2 1 0 Field OP_MODE[1:0] IP_SBB2[1:0] ADE_SBB2 EN_SBB2[2:0] Reset OTP OTP OTP OTP Write, Read Write, Read Write, Read Write, Read Access Type BITFIELD OP_MODE IP_SBB2 www.analog.com BITS DESCRIPTION DECODE 7:6 Operation Mode of SBB2 0b00 = Automatic 0b01 = Buck mode 0b10 = Boost mode 0b11 = Buck-boost mode 5:4 SIMO Buck-Boost Channel 2 Peak Current Limit 0b00 = 1.000A 0b01 = 0.750A 0b10 = 0.500A 0b11 = 0.333A Analog Devices | 85 MAX77642/MAX77643 BITFIELD ADE_SBB2 BITS 3 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output Buck-Boost, 1-LDO for Long Battery Life Applications DESCRIPTION DECODE 0b0 = The active discharge function is disabled. When SBB2 is disabled, its discharge rate is a function of the output capacitance and the external load. 0b1 = The active discharge function is enabled. When SBB2 is disabled, an internal resistor (RAD_SBB2) is activated from SBB2 to PGND to help the output voltage discharge. The output voltage discharge rate is a function of the output capacitance, the external loading, and the internal RAD_SBB2 load. SIMO Buck-Boost Channel 2 ActiveDischarge Enable Enable Control for SIMO Buck-Boost Channel 2. Select the FPS slot that the channel powers up and powers down in or whether the channel is forced on or off. EN_SBB2 2:0 0b000 = FPS slot 0 0b001 = FPS slot 1 0b010 = FPS slot 2 0b011 = FPS slot 3 0b100 = Off irrespective of FPS 0b101 = Same as 0b100 0b110 = On irrespective of FPS 0b111 = Same as 0b110 Prior to enabling the SIMO, program the bias circuits to normal power mode (SBIA_LPM = 0). After the SIMO is enabled, the bias circuits may be programmed back to low power mode (SBIA_LPM = 1) to decrease quiescent current. CNFG_DVS_SBB0_A (0x2F) BIT 7 6 5 4 3 Field TV_SBB0_DVS[7:0] Reset 0x14 Access Type BITFIELD TV_SBB0_D VS 2 1 0 Write, Read BITS 7:0 DESCRIPTION DECODE SIMO Buck-Boost Channel 0 Target Output Voltage This 7-bit configuration is a linear transfer function that starts at 0.5V and ends at 5.5V with 25mV increments. 0x00 = 0.500V 0x01 = 0.525V 0x02 = 0.550V 0x03 = 0.575V 0x04 = 0.600V 0x05 = 0.625V 0x06 = 0.650V 0x07 = 0.675V 0x08 = 0.700V ... 0xC5 = 5.425V 0xC6 = 5.450V 0xC7 = 5.475V 0xC8 to 0xFF = 5.500V CNFG_LDO0_A (0x38) BIT 7 6 5 4 3 Field TV_OFS_L DO TV_LDO[6:0] Reset 0xOTP OTP Write, Read Write, Read Access Type www.analog.com 2 1 0 Analog Devices | 86 MAX77642/MAX77643 BITFIELD BITS TV_OFS_LD O 7 TV_LDO 6:0 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output Buck-Boost, 1-LDO for Long Battery Life Applications DESCRIPTION DECODE LDO Output Voltage. This bit applies a 1.325V offset to the output voltage of the LDO. LDO Target Output Voltage This 7-bit configuration is a linear transfer function that starts at 0.5V and ends at 3.675V with 25mV increments. 0b0 = No Offset 0b1 = 1.325V Offset 0x00 = 0.500V 0x01 = 0.525V 0x02 = 0.550V 0x03 = 0.575V 0x04 = 0.600V 0x05 = 0.625V 0x06 = 0.650V 0x07 = 0.675V 0x08 = 0.700V ... 0x7E = 3.650V 0x7F = 3.675V When TV_LDO[7] = 0, TV_LDO[6:0] sets the LDO's output voltage range from 0.5V to 3.675V. When TV_LDO[7] = 1, TV_LDO[6:0] sets the LDO's output voltage from 1.825V to 5V. CNFG_LDO0_B (0x39) BIT 7 6 5 4 3 2 1 0 Field RSVD[2:0] LDO_MD ADE_LDO EN_LDO[2:0] Reset 0b0 OTP OTP OTP Write, Read Write, Read Write, Read Write, Read Access Type BITFIELD RSVD LDO_MD ADE_LDO www.analog.com BITS 7:5 4 3 DESCRIPTION DECODE Reserved. Unutilized bit. Write to 0. Reads are don't care. Operation Mode of LDO 0b0 = Low dropout linear regulator (LDO) mode 0b1 = Load switch (LSW) mode LDO Active-Discharge Enable 0b0 = The active discharge function is disabled. When LDO0 is disabled, its discharge rate is a function of the output capacitance and the external load. 0b1 = The active discharge function is enabled. When LDO is disabled, an internal resistor (RAD_LDO) is activated from LDO to GND to help the output voltage discharge. The output voltage discharge rate is a function of the output capacitance, the external loading, and the internal RAD_LDO load. Analog Devices | 87 MAX77642/MAX77643 BITFIELD EN_LDO www.analog.com BITS 2:0 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output Buck-Boost, 1-LDO for Long Battery Life Applications DESCRIPTION Enable Control for LDO. Select the FPS slot that the channel powers up and powers down in or whether the channel is forced on or off. DECODE 0b000 = FPS slot 0 0b001 = FPS slot 1 0b010 = FPS slot 2 0b011 = FPS slot 3 0b100 = Off irrespective of FPS 0b101 = Same as 0b100 0b110 = On irrespective of FPS 0b111 = Same as 0b110 Analog Devices | 88 MAX77642/MAX77643 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output Buck-Boost, 1-LDO for Long Battery Life Applications Typical Application Circuits Typical Applications Circuit CSYS 1µF/6.3V (0402) VSYS CIN_SBB 22µF/10V (0603) L 1.5µH CBST 1000pF/6.3V (0201) SYSA MAX77642 GND IN_SBB SBB0 PGND VSBB0 SBB1 LXA LXB SIMO BUCK-BOOST VSBB1 SBB2 22µF 10V (0603) BST VSBB2 RSET_SBB0 IN_LDO0 RSET_SBB1 RSET_SBB2 RSET_LDO SIMO/LDO CONTROLLER VSBB0 SYSTEM RESOURCES LDO/ LSW LDO0 EN0 RSET_IPK TOP LEVEL EN1 EN2 1µF 6.3V (0402) VLDO0 EN0 EN1 EN2 Figure 28. Typical Applications Circuit - RSEL Version (MAX77642) www.analog.com Analog Devices | 89 MAX77642/MAX77643 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output Buck-Boost, 1-LDO for Long Battery Life Applications Typical Application Circuits (continued) CSYS 1µF/6.3V (0402) VSYS CSYS 22µF/10V (0603) L 1.5µH CBST 1000pF/6.3V (0201) MAX77643 SYSA GND IN_SBB SBB0 PGND VSBB0 SBB1 LXA LXB SIMO BUCK-BOOST VSBB1 SBB2 22µF 10V (0603) BST IN_LDO GPIO1 SYSTEM RESOURCES GPIO0 LDO GPIO0 VSBB2 GPIO0 VSBB0 LDO VIO 1µF 6.3V (0402) VLDO0 VIO/POWER GPIO1 TOP LEVEL/I2C/GPIO SDA SCL SDA SCL nEN nRST nIRQ nRST nIRQ PROCESSOR * * *PULLUP RESISTORS NOT DRAWN Figure 29. Typical Applications Circuit - I2C Version (MAX77643) Ordering Information TEMP RANGE PIN-PACKAGE OPTIONS MAX77642ANA+T PART -40°C to +125°C 25 WLP — MAX77643ANA+T* -40°C to +125°C 25 WLP — MAX77643AANA+T -40°C to +125°C 25 WLP Table 3 MAX77643SANA+T -40°C to +125°C 25 WLP Table 3 MAX77643BANA+T -40°C to +125°C 25 WLP Table 3 MAX77643CANA+T -40°C to +125°C 25 WLP Table 3 MAX77643EANA+T -40°C to +125°C 25 WLP Table 3 MAX77643DANA+T -40°C to +125°C 25 WLP Table 3 +Denotes a lead(Pb)-free/RoHS-compliant package. T = Tape and reel. *Custom samples only. Not for production or stock. Contact factory for more information. www.analog.com Analog Devices | 90 MAX77642/MAX77643 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output Buck-Boost, 1-LDO for Long Battery Life Applications Revision History REVISION NUMBER REVISION DATE 0 8/20 Initial release 1 10/20 Updated the Ordering Information table DESCRIPTION PAGES CHANGED — 88 2 4/21 Updated Table 3, Register Map tables, and Ordering Information table 28, 72, 79, 80, 86, 87 3 5/21 Updated Figure 1, Table 3, Register Details, and Ordering Information table 27–29, 73, 84 4 10/21 Updated Electrical Characteristics—SIMO Buck-Boost table, Table 3, Figure 9, Register Map, and Register Details 13, 28, 29, 42, 73, 75 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks andregistered trademarks are the property of their respective owners. w w w . a n a l o g . c o m Analog Devices | 91 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: MAX77642ANA+ MAX77642ANA+T

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