MAX77658BANX+T

EVALUATION KIT AVAILABLE Click here to ask an associate for production status of specific part numbers. MAX77658 Ultra-Low Power PMIC Featuring SingleInductor, 3-Output Buck-Boost, 2-LDOs, PowerPath Charger, and Fuel Gauge for Small Li+ General Description Benefits and Features The MAX77658 provides highly-integrated battery charging and power supply solutions for low-power applications where size and efficiency are critical. The IC features a SIMO buck-boost regulator that provides three highly-efficient and independently programmable power rails from a single inductor to minimize total solution size. Two 150mA LDOs provide ripple rejection for audio and other noisesensitive applications. The LDOs can also be configured as load switches to manage power consumption by disconnecting external blocks when not required. A highlyconfigurable linear charger supports a wide range of Li+ battery capacities and includes battery temperature monitoring for additional safety (JEITA). The fuel-gauge implements the Maxim ModelGauge™ m5 EZ algorithm with ultra-low power. The IC provides the best performance for batteries with 10mAhr to 1Ahr capacity. ● Highly Integrated • 3x Output, Single-Inductor Multiple-Output (SIMO) Buck-Boost Regulator • Supports Wide Output Voltage Range from 0.5V to 5.5V for all SIMO Channels • Delivers up to 750mA Total Load Current • SBB2 can be Configured to 1.5A Peak Inductor Current Limit to Support a Heavily Loaded Rail • 2x 150mA LDO/LSW • Smart Power Selector™ Li+/Li-Poly Charger • 3x GPIO Resources • Analog MUX Output for Power Monitoring • Lowest Power Mode < 700nA IQ • Watchdog Timer This device includes three GPIOs and an analog multiplexer that selects between several internal voltages and current signals to an external node for monitoring with an external ADC. A bidirectional I2C serial interface allows for configuring and checking the status of the devices. An internal on/off controller provides a controlled startup sequence for the regulators and provides supervisory functionality while they are on. Numerous factory programmable options allow the device to be tailored for many applications, enabling faster time to market. Applications ● ● ● ● ● ● Bluetooth Headphones, Hearables Wireless Speakers Wearables Safety and Security Monitors Sensor Nodes Internet of Things (IoT) ● Low Power • 1μA Shutdown Current • 11.2μA Operating Current (3 SIMO Channels + 2 LDOs + Fuel Gauge) ● Charger Optimized for Small Li-Ion Battery Size • Programmable Fast-Charge Current from 7.5mA to 300mA • Programmable Battery Regulation Voltage from 3.6V to 4.6V • Programmable Termination Current from 0.375mA to 45mA • JEITA Battery Temperature Monitor Adjusts Charge Current and Battery Regulation Voltage for Safe Charging ● Fuel Gauge ModelGauge m5 EZ • No Calibration Required for EZ Performance • Robust Performance Against Battery Variation • Die-Temperature or External Thermistor Measurement Capability • Integrated Internal Current Sensing Using Internal Sense Resistor • Compensates for Age, Current, and Temperature • Does Not Require Empty, Full, or Idle States ● Flexible and Configurable • I2C-Compatible Interface and GPIO ● Small Size • 9.55mm2 Wafer-Level Package (WLP) • 36-Bump, 0.5mm Pitch, 6x6 Array Smart Power Selector and ModelGauge are trademarks of Maxim Integrated Products, Inc. Ordering Information appears at end of data sheet. 19-101207; Rev 2; 9/22 © 2022 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. One Analog Way, Wilmington, MA 01887 U.S.A. | Tel: 781.329.4700 | © 2022 Analog Devices, Inc. All rights reserved. MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ Simplified Block Diagram VBUS Li-Ion + IN_SBB SYS CHGIN BATT VSYS IN_LDO0 IN_LDO1 1.5µH LXA LXB BST SBB0 2.05V SBB1 1.2V SBB2 3.3V SYSTEM RESOURCES PGND BATT CHGR SYS FG GPIO0 GPIO VIO T 1.85V LDO0/LSW0 TH MAX77658 REG VL GND nEN 1.2V LDO1/LSW1 GPIO1 GPIO2 SDA SCL nRST nIRQ ALRT AMUX GPIO GPIO SDA SCL nRST nIRQ ALRT AMUX POWER * * * * * APPLICATION PROCESSOR ADC INPUT *PULLUP RESISTORS NOT DRAWN www.analog.com Analog Devices | 2 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ TABLE OF CONTENTS General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Benefits and Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Simplified Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 WLP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Electrical Characteristics—Global Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Electrical Characteristics—Smart Power Selector Charger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Electrical Characteristics—Adjustable Thermistor Temperature Monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Electrical Characteristics—Analog Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Electrical Characteristics—SIMO Buck-Boost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Electrical Characteristics—Low Dropout Linear Regulator (LDO)/Load Switch (LSW) . . . . . . . . . . . . . . . . . . . . . . . . . 20 Electrical Characteristics—Fuel Gauge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Electrical Characteristics—I2C Serial Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 WLP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Part Number Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Support Material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Top-Level Interconnect Simplified Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Detailed Description—Global Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Features and Benefits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Voltage Monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 SYS POR Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 SYS Undervoltage-Lockout Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 SYS Overvoltage-Lockout Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Thermal Monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Chip Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 nEN Enable Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 nEN Manual Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 nEN Triple-Functionality: Push-Button vs. Slide-Switch vs. Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 nEN Internal Pullup Resistors to VCCINT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Debounced Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Interrupts (nIRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Reset Output (nRST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 www.analog.com Analog Devices | 3 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ TABLE OF CONTENTS (CONTINUED) General-Purpose Input Output (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Alternate Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 On/Off Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Top Level On/Off Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 On/Off Controller Transition Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Internal Wake-Up Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Reset and Off Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Power-Up/Down Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Flexible Power Sequencer (FPS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Startup Timing Diagram Due to nEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Startup Timing Diagram Due to Charge Source Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Force Enabled/Disabled Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Debounced Inputs (nEN, GPI, CHGIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Watchdog Timer (WDT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Detailed Description—Smart Power Selector Charger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Charger Symbol Reference Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Smart Power Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 CHGIN Voltage Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Minimum Input Voltage Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Input Current Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Minimum System Voltage Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Die Temperature Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Charger State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Charger-Off State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Prequalification State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Fast-Charge States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Top-Off State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Done State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Prequalification Timer Fault State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Fast-Charge Timer Fault State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Battery Temperature Fault State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 JEITA-Modified States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Typical Charge Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Charger Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Configuring a Valid System Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 CHGIN/SYS/BATT Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Detailed Description—Adjustable Thermistor Temperature Monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Detailed Description—Analog Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 www.analog.com Analog Devices | 4 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ TABLE OF CONTENTS (CONTINUED) Measuring Battery Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Method for Measuring Discharge Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Method for Measuring Charge Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Detailed Description—SIMO Buck-Boost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 SIMO Features and Benefits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 SIMO Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 SIMO Control Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Drive Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 SIMO Fault Indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 SIMO Output Voltage Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Peak Current Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 SIMO Soft-Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 SIMO Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 SIMO Active Discharge Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 SIMO Buck-Only and Boost-Only Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 SIMO Available Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Inductor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Input Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Boost Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Output Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Example Component Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Inductor, Peak Current Limit, and Input Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Output Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 SIMO Switching Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Unused Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 PCB Layout Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Input Capacitor at IN_SBB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Inductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Ground Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Detailed Description—Low Dropout Linear Regulator (LDO)/Load Switch (LSW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Features and Benefits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 LDO Fault Indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 LDO/LSW Simplified Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 LDO/LSW Active-Discharge Resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 LDO/LSW Soft-Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Load Switch Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 www.analog.com Analog Devices | 5 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ TABLE OF CONTENTS (CONTINUED) Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Input Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Output Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Detailed Description—Fuel Gauge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 ModelGauge m5 EZ Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Standard Register Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 ModelGauge m5 Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Analog Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Voltage Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 VCell Register (0x09) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 AvgVCell Register (0x19) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 MaxMinVolt Register (0x1B). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Current Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Current Register (0x0A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 AvgCurrent Register (0x0B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 MaxMinCurr Register (0x1C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Temperature Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Temp Register (0x08). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 MaxMinTemp Register (0x1A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 DieTemp Register (0x34) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Power Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Power Register (0xB1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 AvgPower Register (0xB3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Alert Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Serial Number Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 ModelGauge m5 Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Detailed Description—I2C Serial Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 I2C Simplified Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 I2C System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 I2C Interface Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 I2C Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 I2C Start and Stop Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 I2C Acknowledge Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 I2C Slave Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 I2C Clock Stretching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 I2C General Call Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 www.analog.com Analog Devices | 6 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ TABLE OF CONTENTS (CONTINUED) I2C Device ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 I2C Communication Speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 I2C Communication Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Writing to a Single 8-Bit Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Writing Multiple Bytes to Sequential Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Writing to 16-Bit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Reading from a Single Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Reading from Sequential Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Reading From 16-Bit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 MAX77658 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Register Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Fuel Gauge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Register Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Typical Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 www.analog.com Analog Devices | 7 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ LIST OF FIGURES Figure 1. Part Number Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Figure 2. Top-Level Interconnect Simplified Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 3. nEN Usage Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Figure 4. nEN Pullup Resistor Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Figure 5. Debounced Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Figure 6. GPIOx Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Figure 7. Top Level On/Off Controller State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Figure 8. On/Off Controller Reset and Off-Action Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Figure 9. Power-Up/Down Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Figure 10. Flexible Power Sequencer Basic Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Figure 11. Startup Timing Diagram Due to nEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Figure 12. Startup Timing Diagram Due to Charge Source Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Figure 13. Debounced Inputs (nEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Figure 14. Watchdog Timer State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Figure 15. Charger Simplified Control Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Figure 16. Charger State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Figure 17. Example Battery Charge Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Figure 18. Safe-Charging Profile Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Figure 19. SIMO Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Figure 20. ULPM and Normal Mode Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Figure 21. Component Selection—High Utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Figure 22. Component Selection—Final Current Peak Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Figure 23. Component Selection—Expected Ripple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Figure 24. PCB Top-Layer and Component Placement Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Figure 25. LDO Simplified Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Figure 26. LDO to LSW Transition Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Figure 27. ModelGauge m5 EZ Configuration Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Figure 28. ModelGauge m5 Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Figure 29. I2C Simplified Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Figure 30. I2C System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Figure 31. I2C Start and Stop Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Figure 32. Acknowledge Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Figure 33. Slave Address Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Figure 34. Writing to a Single 8-Bit Register with the Write-Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Figure 35. Writing to Sequential Registers X to N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Figure 36. Example I2C Write 16-Bit Data Communication Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Figure 37. Reading from a Single Register with the Read Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Figure 38. Reading Continuously from Sequential Registers X to N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Figure 39. Example I2C Read 16-Bit Data Communication Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 www.analog.com Analog Devices | 8 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ LIST OF TABLES Table 1. Regulator Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 2. OTP Options Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 3. GPIO Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 4. CHGIN Suspend State Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 5. Enabling/Disabling DISQBAT while GPIO2 is in Alternate Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 6. On/Off Controller Transition/State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 7. Watchdog Timer Factory-Programmed Safety Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Table 8. Charger Quick Symbol Reference Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Table 9. Input Current Limit Factory Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Table 10. AMUX Signal Transfer Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Table 11. Battery Current Direction Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Table 12. SIMO Available Output Current for Common Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Table 13. Design Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Table 14. Summary of Design for Component Selection Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Table 15. Summary of Design with Lower Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Table 16. Switching Frequency Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Table 17. ModelGauge m5 EZ Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Table 18. ModelGauge m5 Register Standard Resolutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Table 19. Serial Number Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Table 20. ModelGauge m5 Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Table 21. I2C Slave Address Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 www.analog.com Analog Devices | 9 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ Absolute Maximum Ratings nEN, nIRQ, nRST to GND ...........................-0.3V to VSYS + 0.3V SCL, SDA, GPIO to GND ...............................-0.3V to VIO + 0.3V CHGIN to GND .................................................... -0.3V to +30.0V SYS, BATT CHGR, SYS FG to GND .................... -0.3V to +6.0V SYS to IN_SBB ..................................................... -0.3V to +0.3V VL to GND ............................................................. -0.3V to +6.0V AMUX to GND ....................................................... -0.3V to +6.0V nIRQ, nRST, SDA, AMUX, GPIO, ALRT Continous Current .............................................................................. ±20mA CHGIN Continuous Current ............................................ 1.2ARMS SYS Continuous Current ................................................ 1.2ARMS BATT CHGR Continuous Current (Note 1) .................... 1.2ARMS IN_LDO0, IN_LDO1 to GND ................................... -0.3V to 6.0V LDO0, LDO1 to GND ............................. -0.3V to VIN_LDO + 0.3V VIO to GND ..................................................-0.3V to VSYS + 0.3V IN_SBB to PGND .................................................. -0.3V to +6.0V LXA Continuous Current (Note 2) .................................. 1.2ARMS LXB Continuous Current (Note 2) .................................. 1.2ARMS SBB0, SBB1, SBB2 to PGND ............................... -0.3V to +6.0V BST to IN_SBB ...................................................... -0.3V to +6.0V BST to LXB ............................................................ -0.3V to +6.0V SBB0, SBB1, SBB2 Short-Circuit Duration .................Continuous PGND to GND........................................................ -0.3V to +0.3V Operating Temperature Range ...........................-40°C to +125°C Junction Temperature ....................................................... +150°C Storage Temperature Range ..............................-65°C to +150°C Soldering Temperature (reflow) ........................................ +260°C Continuous Power Dissipation (Multilayer Board, TA = +70°C, derate 20.4mW/°C above +70°C) ...................................1632mW ALRT to GND .......................................................... -0.3V to +17V REG to GND .......................................................... -0.3V to +2.2V TH to GND .............................................. -0.3 V to VBATT + 0.3 V Continuous Source Current for TH ........................................1mA Lead Temperature (soldering 10s).................................... +300ºC Current Limit of Sense Resistor (Continuous current at 100% utilization (Note 3)) .................................................................0.8A Current Limit of Sense Resistor (Continuous current at 10% utilization (Note 3)) .................................................................1.2A Note 1: Do not repeatedly hot-plug a source to the BATT CHGR terminal at a rate greater than 10Hz. Hot plugging low impedance sources results in an ~8A momentary (~2μs) current spike. Note 2: Do not externally bias LXA or LXB. LXA has internal clamping diodes to PGND and IN_SBB. LXB has an internal low-side clamping diode to PGND and an internal high-side clamping diode that dynamically connects to a selected SIMO output. It is normal for these diodes to briefly conduct during switching events. When the SIMO regulator is disabled, the LXB to PGND absolute maximum voltage is -0.3V to VSBB0 + 0.3V. Note 3: Guaranteed by design and not production tested. Total available utilization is 100,000 hours. Utilization is proportionately cumulative. See the Current Measurement section for a detailed explanation of the current limit under different utilization patterns. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Package Information WLP Package Code N362A3+1 Outline Number 21-100490 Land Pattern Number Refer to Application Note 1891 Thermal Resistance, Four-Layer Board: Junction to Ambient (θJA) www.analog.com 49ºC/W (2s2p board) Analog Devices | 10 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ Pin 1 Ind ic a tor Ma rking E 1 see Note 7 COMMON DIMENSIONS A A1 0.50 MAX 0.19 0.03 A2 0.28 REF A3 0.04 BASIC 0.29 0.03 A AAAA D b 2.958 3.228 D E A3 TOP VIEW A1 A S A2 2.50 BASIC 2.50 BASIC e 0.50 BASIC SD 0.25 BASIC 0.25 BASIC DEPOPULATED BUMPS: NONE SE 0.05 S FRONT VIEW E1 D1 SIDE VIEW 0.025 0.025 E1 SE e F B E SD D D1 C NOTES: 1. Term ina l p itc h is d efined b y term ina l c enter to c enter va lue. 2. Outer d im ension is d efined b y c enter lines b etw een sc rib e lines. 3. All d im ensions in m illim eter. 4. Ma rking show n is for p a c ka g e orienta tion referenc e only. 5. Tolera nc e is ± 0.02 unless sp ec ified otherw ise. 6. All d im ensions a p p ly to Pb Free (+) p a c ka g e c od es only. 7. Front - sid e finish c a n b e either Bla c k or Clea r. B A 1 2 A 3 4 5 BOTTOM VIEW - DRAWING NOT TO SCALE - 6 b 0.05 M S AB maxim integrated TITLE TM PACKAGE OUTLINE 36 BUMPS THIN WLP PKG. 0.5 m m PITCH, N362A3+1 APPROVAL DOCUMENT CONTROL NO. 21-100490 REV. A 1 1 For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial. www.analog.com Analog Devices | 11 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ Electrical Characteristics (VCHGIN = 0V, VSYS = VBATT = VIN_SBB = VIN_LDOx = 3.7V, VIO = 1.8V, limits are 100% production tested at TA = +25°C. Limits over the operating temperature range (TA = -40°C to +125°C) are guaranteed by design and characterization, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 5.5 V TOP-LEVEL Operating Voltage Range Shutdown Supply Current VSYS ISHDN Main Bias Quiescent Current Quiescent Supply Current 2.7 Current measured into BATT and SYS and IN_SBB and IN_LDOx, all resources are off (LDO0, LDO1, SBB0, SBB1, SBB2), TA = +25°C Fuel gauge is in shutdown mode 1.0 1.5 Fuel gauge is in hibernate mode 5.6 8.0 Fuel gauge is in active mode 16.5 23 IQ Main bias is in normal-power mode (CNFG_GLBL.SBIA_LPM = 0) IQ Main bias is in low-power mode, current measured into BATT and SYS and IN_SBB and IN_LDOx; LDO0, LDO1, SBB0, SBB1, SBB2 are enabled with no load watchdog timer disabled, fuel gauge is in hibernate mode, TA = -40°C to +85°C 28 11.2 μA μA 25 μA Electrical Characteristics—Global Resources (VSYS = 3.7V, limits are 100% production tested at TA = +25°C, limits over the operating temperature range (TA = -40°C to +125°C) are guaranteed by design and characterization, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS GENERAL CHARACTERISTICS Main Bias Enable Time tSBIAS_EN 0.5 ms 1.55 V 150 mV VOLTAGE MONITORS / POWER-ON RESET (POR) POR Threshold VPOR VSYS falling POR Threshold Hysteresis VOLTAGE MONITORS / UNDERVOLTAGE LOCKOUT (UVLO) UVLO Threshold VSYSUVLO UVLO Threshold Hysteresis VSYSUVLO_HY VSYS falling 2.45 2.6 2.73 200 S V mV VOLTAGE MONITORS / OVERVOLTAGE LOCKOUT (OVLO) OVLO Threshold VSYSOVLO VSYS rising 5.70 5.85 6.00 V THERMAL MONITORS OvertemperatureLockout Threshold TOTLO TJ rising 145 °C Thermal Alarm Temperature 1 TJAL1 TJ rising 80 °C Thermal Alarm Temperature 2 TJAL2 TJ rising 100 °C www.analog.com Analog Devices | 12 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ Electrical Characteristics—Global Resources (continued) (VSYS = 3.7V, limits are 100% production tested at TA = +25°C, limits over the operating temperature range (TA = -40°C to +125°C) are guaranteed by design and characterization, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN Thermal Alarm Temperature Hysteresis TYP MAX 15 UNITS °C ENABLE INPUT (nEN) nEN Input Leakage Current InEN_LKG VnEN = VCCINT = 5.5V nEN Input Falling Threshold VTH_nEN_F nEN Falling nEN Input Rising Threshold VTH_nEN_R nEN Rising TA = +25°C -1 TA = +125°C Debounce Time VCCINT tDBNC_nEN Manual Reset Time tMRST nEN Internal Pullup RnEN-PU (Note 4) +1 ±0.01 VCCINT 1.4 VCCINT 1.0 VCCINT 0.9 VCHGIN = 0V, battery is present (VBATT is valid) VCC Internal ±0.001 μA V VCCINT 0.6 V VBATT V VCHGIN = 5V, not suspended (CNFG_CHG_G.U SBS = 0) VL CNFG_GLBL.DBEN_nEN = 0 500 μs CNFG_GLBL.DBEN_nEN = 1 30 ms CNFG_GLBL.T_MRT = 1 3 4 5 CNFG_GLBL.T_MRT = 0 7 8 10.5 Pullup to VCCINT PU_DIS = 0 200 PU_DIS = 1 10000 s kΩ OPEN-DRAIN INTERRUPT OUTPUT (nIRQ) Output Voltage Low VOL ISINK = 2mA Output Falling Edge Time tf_nIRQ CIRQ = 25pF Leakage Current InIRQ_LKG VSYS = VIO = 5.5V nIRQ is high impedance (no interrupts) VnIRQ = 0V and 5.5V 0.4 2 TA = +25°C TA = +125°C -1 ±0.001 V ns +1 μA ±0.01 OPEN-DRAIN RESET OUTPUT (nRST) Output Voltage Low VOL ISINK = 2mA Output Falling Edge Time tf_nRST CRST = 25pF nRST Deassert Delay Time tRSTODD nRST Assert Delay Time tRSTOAD www.analog.com See Figure 11 and Figure 12 for more information 0.4 V 2 ns 5.12 ms 10.24 ms Analog Devices | 13 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ Electrical Characteristics—Global Resources (continued) (VSYS = 3.7V, limits are 100% production tested at TA = +25°C, limits over the operating temperature range (TA = -40°C to +125°C) are guaranteed by design and characterization, unless otherwise noted.) PARAMETER Leakage Current SYMBOL InRST_LKG CONDITIONS VSYS = VIO = 5.5V nRST is high impedance (no reset) VnRST = 0V and 5.5V TA = +25°C MIN TYP MAX -1 ±0.001 +1 TA = +125°C UNITS μA ±0.01 GENERAL PURPOSE INPUT/OUTPUT (GPIO) Input Voltage Low VIL VIO = 1.8V Input Voltage High VIH VIO = 1.8V Input Leakage Current IGPI_LKG 0.3 x VIO 0.7 x VIO CNFG_GPIOx.DIR =1 VIO = 5.5V VGPIO = 0V and 5.5V Output Voltage Low VOL ISINK = 2mA Output Voltage High VOH ISOURCE = 1mA Input Debounce Time tDBNC_GPI Output Falling Edge Time Output Rising Edge Time TA = +25°C -1 TA = +125°C V V ±0.001 +1 μA ±0.01 0.4 0.8 x VIO V V CNFG_GPIOx.DBEN_GPI = 1 30 ms tf_GPIO CGPIO = 25pF 3 ns tr_GPIO CGPIO = 25pF 3 ns 1.43 ms FLEXIBLE POWER SEQUENCER FPS Startup Delay tFPS_DLY Power-Up Event Periods tEN See Figure 10 1.28 ms Power-Down Event Periods tDIS See Figure 10 2.56 ms Note 4: See the nEN Internal Pullup Resistors to VCCINT section for more details Electrical Characteristics—Smart Power Selector Charger (VCHGIN = 5.0V, VSYS = 4.5V, VBATT = 4.2V, limits are 100% production tested at TA = +25°C, limits over the operating temperature range (TA = -40°C to +125°C) are guaranteed by design and characterization, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 7.25 V DC INPUT CHGIN Valid Voltage Range VCHGIN Initial CHGIN voltage before enabling charging CHGIN Standoff Voltage Range VSTANDOFF DC rising CHGIN Overvoltage Threshold VCHGIN_OVP DC rising CHGIN Overvoltage Hysteresis www.analog.com 4.1 28 7.25 7.50 100 V 7.75 V mV Analog Devices | 14 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ Electrical Characteristics—Smart Power Selector Charger (continued) (VCHGIN = 5.0V, VSYS = 4.5V, VBATT = 4.2V, limits are 100% production tested at TA = +25°C, limits over the operating temperature range (TA = -40°C to +125°C) are guaranteed by design and characterization, unless otherwise noted.) PARAMETER CHGIN Undervoltage Lockout SYMBOL VCHGIN_UVLO CHGIN UndervoltageLockout Hysteresis Input Current-Limit Range ICHGIN-LIM Input Current-Limit Accuracy Minimum Input Voltage Regulation Range DC rising HYST_CHGINUVL O_100 = 0 MIN TYP MAX UNITS 4.0 4.1 4.2 V HYST_CHGINUVL O_100 = 1 3.6 HYST_CHGINUVLO_100 = 0 600 HYST_CHGINUVLO_100 = 1 100 VSYS = VSYS-REG - 100mV, programmable in 95mA steps 95 ICHGIN-LIM = 95mA, VSYS = VSYS-REG 100mV 90 VCHGIN-MIN mV 475 95 100 475 500 mA mA ICHGIN-LIM = 475mA, VSYS = VSYS-REG - 100mV VCHGIN falling due to loading conditions and/or high-impedance charge source, programmable in 100mV increments with CNFG_CHG_B.VCHGIN_MIN[2:0] 4.0 VCHGIN-MIN = 4.5V (CNFG_CHG_B.VCHGIN_MIN[2:0] = 0b101), ICHGIN reduced by 10% 4.32 VCHGIN = 5V, time before CHGIN is allowed to deliver current to SYS or BATT 100 4.7 V 4.50 4.68 V 120 140 ms 1.0 1.8 mA VCHGIN = 0V to 1V, VBATT = 3.3V, ISYS = 0mA 50 μA ICHGIN-SUS VCHGIN = 5V, charger in USB suspend (CNFG_CHG_G.USBS = 1) 50 μA IBATT-BIAS VCHGIN = 5V, charger is not in USB suspend (CNFG_CHG_G.USBS = 0), charging is finished (STAT_CHG_B.CHG_DTLS[3:0] indicates done), ISYS = 0mA Minimum Input Voltage Regulation Accuracy Charger Input Debounce Timer CONDITIONS tCHGIN-DB SUPPLY AND QUIESCENT CURRENTS CHGIN Supply Current CHGIN Suspend Supply Current BATT Bias Current ICHGIN VCHGIN = 5V, charger is not in USB suspend (CNFG_CHG_G.USBS = 0), charging is finished (STAT_CHG_B.CHG_DTLS[3:0] indicates done), ISYS = 0mA 5 μA PREQUALIFICATION Prequalification Voltage Threshold Range Programmable in 100mV steps with CNFG_CHG_C.CHG_PQ[2:0] 2.3 3.0 V Prequalification Voltage Threshold Accuracy VPQ = 3.0V -3 +3 % Prequalification Mode Charge Current VBATT = 2.5V VPQ = 3.0V Expressed as a percentage of IFAST-CHG www.analog.com VPQ IPQ CNFG_CHG_B.I_P Q=0 10 CNFG_CHG_B.I_P Q=1 20 % Analog Devices | 15 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ Electrical Characteristics—Smart Power Selector Charger (continued) (VCHGIN = 5.0V, VSYS = 4.5V, VBATT = 4.2V, limits are 100% production tested at TA = +25°C, limits over the operating temperature range (TA = -40°C to +125°C) are guaranteed by design and characterization, unless otherwise noted.) PARAMETER Prequalification Safety Timer SYMBOL tPQ CONDITIONS MIN TYP MAX UNITS VBATT < VPQ = 3.0V 27 30 33 minutes IBATT = 0mA, programmable in 25mV steps with CNFG_CHG_G.CHG_CV[5:0] 3.6 4.6 V -0.5 +0.5 FAST-CHARGE Fast-Charge Voltage Range VFAST-CHG Fast-Charge Voltage Accuracy Fast-Charge Current Range IBATT = 0mA IFAST-CHG VFAST-CHG = 4.3V, VSYS = 4.5V, TA = +25°C Programmable in 7.5mA steps with CNFG_CHG_E.CHG_CC[5:0] 300 IFAST-CHG = 15mA -1.5 +1.5 IFAST-CHG = 300mA -2.0 +2.0 -10 +10 % 3 7 hours -10 +10 % TA = +25°C, VBATT = VFAST-CHG 300mV Fast-Charge Current Accuracy over Temperature Across all current settings, VBATT = VFAST-CHG - 300mV, TA = -40°C to +125°C Fast-Charge Safety Timer Range Programmable in 2 hour increments or disabled with CNFG_CHG_E.T_FAST_CHG[1:0], time measured from prequal. done to timer fault Fast-Charge Safety Timer Accuracy tFC = 3 hours Fast-Charge Safety Timer Suspend Threshold Fast-charge CC mode, fast-charge safety timer paused when charge current drops below this threshold, expressed as a percentage of IFAST-CHG Junction Temperature Regulation Setting Range Junction Temperature Regulation Loop Gain Charge Current SoftStart Slew Time www.analog.com TJ-REG GTJ-REG Programmable in 10°C steps with CNFG_CHG_D.TJ_REG[2:0] Rate at which IFAST-CHG/IPQ is reduced to maintain TJ-REG, expressed a percentage of IFAST-CHG/IPQ per degree centigrade rise Zero to full-scale 1.0 7.5 Fast-Charge Current Accuracy tFC % VFAST-CHG = 3.6V to 4.6V, VSYS = 4.8V 20 60 mA % % 100 °C -5.4 %/°C 1 ms Analog Devices | 16 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ Electrical Characteristics—Smart Power Selector Charger (continued) (VCHGIN = 5.0V, VSYS = 4.5V, VBATT = 4.2V, limits are 100% production tested at TA = +25°C, limits over the operating temperature range (TA = -40°C to +125°C) are guaranteed by design and characterization, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS TERMINATION AND TOP-OFF End-of-Charge Termination Current ITERM CNFG_CHG_C.I_TERM[1:0] = 0b00 expressed as a percentage of IFAST-CHG 5 CNFG_CHG_C.I_TERM[1:0] = 0b01 expressed as a percentage of IFAST-CHG 7.5 CNFG_CHG_C.I_TERM[1:0] = 0b10 expressed as a percentage of IFAST-CHG % 8.5 CNFG_CHG_C.I_TERM[1:0] = 0b11 expressed as a percentage of IFAST-CHG Top-Off Timer Range tTO IBATT < ITERM, programmable in 5 minute steps with CNFG_CHG_C.T_TOPOFF[2:0] 10 11.5 15 0 35 minutes +10 % Top-Off Timer Accuracy tTO = 10 minutes -10 Charge Restart Threshold Charging is finished (STAT_CHG_B.CHG_DTLS[3:0] indicates done and CNFG_CHG_H.CHR_TH_EN = 1) Charging resumes when VBATT < VFASTCHG - VRESTART 65 150 IFAST-CHG = 15mA, ITERM = 1.5mA (10% of IFAST-CHG), TA = +25°C 1.35 1.5 1.65 27 30 33 VRESTART End-of-Charge Termination Current Accuracy IFAST-CHG = 300mA, ITERM = 30mA (10% of IFAST-CHG), TA = +25°C mV mA End-of-Charge Termination Current Glitch Filter 60 μs DEVICE ON-RESISTANCE AND LEAKAGE BATT CHGR to SYS On-Resistance VBATT = 3.7V, IBATT = 300mA, VCHGIN = 0V, battery is discharging to SYS Charger FET Leakage Current VSYS = 4.5V, VBATT = 0V, charger disabled 100 150 TA = +25°C 0.1 1.0 TA = +125°C 1 CHGIN to SYS OnResistance μA 600 VCHGIN = 0V, VSYS = 4.2V, bodyswitched diode reverse biased Input FET Leakage Current TA = +25°C 0.1 TA = +125°C 1 mΩ mΩ 1.0 μA SYSTEM NODE System Voltage Regulation Range System Voltage Regulation Accuracy www.analog.com VSYS-REG VSYS Programmable in 50mV steps with CNFG_CHG_D.VSYS_REG[4:0] 3.4 TA = +25°C 4.41 4.50 4.59 TA = -40°C to +125°C 4.365 4.5 4.635 VSYS-REG = 4.5V, ISYS = 1mA 4.8 V V Analog Devices | 17 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ Electrical Characteristics—Smart Power Selector Charger (continued) (VCHGIN = 5.0V, VSYS = 4.5V, VBATT = 4.2V, limits are 100% production tested at TA = +25°C, limits over the operating temperature range (TA = -40°C to +125°C) are guaranteed by design and characterization, unless otherwise noted.) PARAMETER Minimum System Voltage Regulation Loop Setpoint SYMBOL CONDITIONS MIN TYP MAX UNITS VSYS-MIN VCHGIN = 5V, VSYS-REG = 4.5V, VSYS < VSYS-REG due to ICHGIN = ICHGIN-LIM (input in current limit), battery charging, IBATT reduced to 50% of IFAST-CHG (minimum system voltage regulation active) 4.34 4.4 4.45 V Supplement Mode System Voltage Regulation Active Discharge Resistance VBATT 0.15V ISYS = 150mA RAD_SYS When CNFG_GLBL.SFT_CTRL[1:0] = 0b11 and CHGIN is disconnected 80 V 140 260 Ω Electrical Characteristics—Adjustable Thermistor Temperature Monitors (VCHGIN = 5.0V, VSYS = 4.5V, VBATT = 4.2V, limits are 100% production tested at TA = +25°C, limits over the operating temperature range (TA = -40°C to +125°C) are guaranteed by design and characterization, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS JEITA TEMPERATURE MONITORS Temperature Threshold Hysteresis Temperature hysteresis set on each JEITA threshold 3 °C JEITA Modified FastCharge Voltage Range VFASTCHG_JEITA IBATT = 0mA, programmable in 25mV steps, battery is either cool or warm 3.6 4.6 V JEITA Modified FastCharge Current Range IFASTCHG_JEITA Programmable in 7.5mA steps, battery is either cool or warm 7.5 300 mA Electrical Characteristics—Analog Multiplexer (VCHGIN = 5.0V, VSYS = 4.5V, VBATT = 4.2V, limits are 100% production tested at TA = +25°C, limits over the operating temperature range (TA = -40°C to +125°C) are guaranteed by design and characterization, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS ANALOG MULTIPLEXER Full-Scale Voltage VFS Channel Switching Time VAMUX = 0V, AMUX is high impedance Off Leakage Current 1.25 V 0.3 μs TA = +25°C 1 500 nA TA = +125°C 1 μA CHGIN POWER MEASUREMENT CHGIN Current Monitor Gain GICHGIN VFS corresponds to maximum ICHGIN-LIM setting 2.632 V/A CHGIN Voltage Monitor Gain GVCHGIN VFS corresponds to VCHGIN_OVP 0.167 V/V 12.5 mV/% BATT AND SYS POWER MEASUREMENT Battery Charge Current Monitor Gain www.analog.com GIBATT-CHG VFS corresponds to 100% of IFAST-CHG setting (CNFG_CHG_E.CHG_CC[5:0]) Analog Devices | 18 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ Electrical Characteristics—Analog Multiplexer (continued) (VCHGIN = 5.0V, VSYS = 4.5V, VBATT = 4.2V, limits are 100% production tested at TA = +25°C, limits over the operating temperature range (TA = -40°C to +125°C) are guaranteed by design and characterization, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS IFAST-CHG = 15mA, TA = +25°C, VBATT = VFAST-CHG - 300mV -3.5 +3.5 IFAST-CHG = 300mA, TA = +25°C, VBATT = VFAST-CHG - 300mV -3.5 +3.5 Across all current settings, VBATT = VFAST-CHG - 300mV -10 +10 % Programmable with CNFG_CHG_I.IMON_DISCHG_ SCALE[3:0] 8.2 300 mA Battery Discharge Current Monitor Accuracy 15mA to 300mA battery discharge current, IDISCHG-SCALE = 300mA -15 +15 % Battery Discharge Current Monitor Offset IBATT = 0mA -0.5 +0.8 mA Charge Current Monitor Accuracy Charge Current Monitor Accuracy over Temperature Battery Discharge Monitor Full-Scale Current Range IDISCHGSCALE % Battery-Voltage Monitor Gain GVBATT VFS corresponds to maximum VFASTCHG setting 0.272 V/V SYS Voltage Monitor Gain GVSYS VFS corresponds to maximum VSYS-REG setting 0.26 V/V Electrical Characteristics—SIMO Buck-Boost (VIN = 3.7V, CSBBx = 10μF, L = 1.5μH, limits are 100% production tested at TA = +25°C, limits over the operating temperature range (TA = -40°C to +125°C) are guaranteed by design and characterization, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 5.5 V GENERAL CHARACTERISTICS / OUTPUT VOLTAGE RANGE (SBB0/1/2) Programmable Output Voltage Range VSBBx 0.5 Output DAC Bits Output DAC LSB Size 0.5V to 5.5V 8 bits 25 mV OUTPUT VOLTAGE ACCURACY VSBBx falling, threshold where LXA switches high; specified as a percentage of target output voltage Output Voltage Accuracy OUT Over-Regulation Threshold VOV TA = -40°C to +125°C -2.0 +2.0 % 3 % TA = +25°C 1.7 Delay time from the SIMO receiving its first enable signal to when it begins to switch in order to service that output 10 μs IPK = 1A, COUT = 10μF 5.0 mV/μs TIMING CHARACTERISTICS Enable Delay Soft-Start Slew Rate www.analog.com dV/dtSS Analog Devices | 19 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ Electrical Characteristics—SIMO Buck-Boost (continued) (VIN = 3.7V, CSBBx = 10μF, L = 1.5μH, limits are 100% production tested at TA = +25°C, limits over the operating temperature range (TA = -40°C to +125°C) are guaranteed by design and characterization, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX -1.0 ±0.1 +1.0 UNITS POWER STAGE CHARACTERISTICS TA = +25°C LXA Leakage Current SBB0, SBB1, SBB2 are disabled, VIN_SBB = 5.5V, VLXA = 0V, or 5.5V TA = +25°C LXB Leakage Current SBB0, SBB1, SBB2 are disabled, VIN_SBB = 5.5V, VLXA = 0V or 5.5V, all VSBBx = 5.5V TA = +125°C ±1.0 VIN_SBB = 5.5V, VLXB = 5.5V, VBST = 11V TA = +25°C +0.01 BST Leakage Current TA = +125°C +0.1 TA = +25°C +0.1 Disabled Output Leakage Current SBB0, SBB1, SBB2 are disabled, active-discharge disabled (ADE_SBBx = 0), VSBBx = 5.5V, VLXB = 0V, VSYS = VIN_SBB = VBST = 5.5V TA = +125°C +0.2 Active-Discharge Resistance RAD_SBBx TA = +125°C SBB0, SBB1, SBB2 are disabled, activedischarge enabled (CNFG_SBBx_B.ADE_SBBx = 1) μA ±1.0 -1.0 ±0.1 +1.0 μA +1.0 μA +1.0 μA 60 120 180 CNFG_SBBx_B.IP_SBBx[1:0] = 0b11 -18% 0.335 +18% CNFG_SBBx_B.IP_SBBx[1:0] = 0b10 -14% 0.500 +14% CNFG_SBBx_B.IP_SBBx[1:0] = 0b01 -8% 0.750 +8% CNFG_SBBx_B.IP_SBBx[1:0] = 0b00 -7% 1.000 +7% Ω CONTROL SCHEME Peak Current Limit SIMO Output Fault Threshold IP_SBB (Note 5) VSBBx_F INT_GLBL1.SBBx_ F = 1, expressed as a percentage of VSBBx Falling 80.0 A % Note 5: Typical values align with bench observations using the stated conditions with an inductor. Minimum and maximum values are tested in production with DC currents without an inductor. See the Typical Operating Characteristics SIMO switching waveforms to gain more insight on this specification. Electrical Characteristics—Low Dropout Linear Regulator (LDO)/Load Switch (LSW) (VSYS = VIN_LDO = 3.7V, limits are 100% production tested at TA = +25°C, limits over the operating temperature range (TA = -40°C to +125°C) are guaranteed by design and characterization, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS LDO0/1 Input Voltage Range www.analog.com VIN_LDOx LDO mode 1.71 5.5 Switch mode 1.2 5.5 V Analog Devices | 20 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ Electrical Characteristics—Low Dropout Linear Regulator (LDO)/Load Switch (LSW) (continued) (VSYS = VIN_LDO = 3.7V, limits are 100% production tested at TA = +25°C, limits over the operating temperature range (TA = -40°C to +125°C) are guaranteed by design and characterization, unless otherwise noted.) PARAMETER SYMBOL Quiescent Supply Current IIN_LDOx Quiescent Supply Current in Dropout IIN_DRP_LDOx Maximum Output Current IOUT_LDOx Output Voltage VOUT_LDOx CONDITIONS MAX 1.4 2.4 IOUT_LDOx = 0, switch mode 0.5 1.2 IOUT_LDOx = 0, VIN_LDOx = 2.9V, VLDOx = 3V 2.1 4.6 VDRP_LDOx MIN VIN_LDOx > 1.8V 150 VIN_LDOx = 1.8V or lower 100 VIN_LDOx = (VOUT_LDOx + 0.5V) or higher, IOUT_LDOx = 1mA Output Accuracy Dropout Voltage TYP IOUT_LDOx = 0 5.0 V -3.1 +3.1 % 100 mV +0.5 %/V 0.005 %/mA VIN_LDOx = 3V, LDOx programmed to 3V, IOUT_LDOx = 100mA Load Regulation VIN_LDOx = 1.8V or higher, IOUT_LDOx = 100μA to 100mA Line Transient VIN_LDOx = 4V to 5V, 5µs rise time ± 35 IOUT_LDOx = 100μA to 10mA, 200ns rise time 100 IOUT_LDOx = 100μA to 100mA, 200ns rise time 200 Switch Mode OnResistance Slew Rate Short-Circuit Current Limit Output Noise RAD_LDOX RON_LDOx µA 0.5 VIN_LDOx = (VOUT_LDOx + 0.5 V) to 5.5V Active-Discharge Resistance µA mA Line Regulation Load Transient UNITS -0.5 0.001 mV mV 42 80 200 VIN_LDOx = 2.7V, IOUT_LDOx = 100mA 0.5 VIN_LDOx = 1.8V, IOUT_LDOx = 50mA 0.8 VIN_LDOx = 1.2V, IOUT_LDOx = 5mA 1.2 IOUT_LDOx = 0mA, time from 10% to 90% of final register value 2.2 IOUT_LDOx = 0mA, time from 10% to 90% of final register value, switch mode 2.2 Ω Ω V/ms VIN_LDOx = 2.7V, VOUT_LDOx = GND 230 550 VIN_LDOx = 2.7V, VOUT_LDOx = 2.55V, switch mode 230 550 10Hz to 100kHz, VIN_LDOx = 5V, VOUT_LDOx = 3.3V 150 10Hz to 100kHz, VIN_LDOx = 5V, VOUT_LDOx = 2.5V 125 10Hz to 100kHz, VIN_LDOx = 5V, VOUT_LDOx = 1.2V 90 10Hz to 100kHz, VIN_LDOx = 5V, VOUT_LDOx = 0.9V 80 880 mA µVRMS Output DAC Bits 8 bits Output DAC LSB Size 25 mV www.analog.com Analog Devices | 21 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ Electrical Characteristics—Low Dropout Linear Regulator (LDO)/Load Switch (LSW) (continued) (VSYS = VIN_LDO = 3.7V, limits are 100% production tested at TA = +25°C, limits over the operating temperature range (TA = -40°C to +125°C) are guaranteed by design and characterization, unless otherwise noted.) PARAMETER LDO Output Fault Threshold SYMBOL VLDOx_F CONDITIONS INT_GLBL1.LDOx_ F = 1, expressed as a percentage of VLDOx MIN Falling TYP MAX 87.5 UNITS % Electrical Characteristics—Fuel Gauge (VBATT = 2.3V to 4.9V, TA = -40ºC to +125ºC, typical value for TA is +25ºC. Limits are 100% tested at TA = +25°C. The operating temperature range and relevant supply voltage range are guaranteed by design and characterization. Specifications marked "GBD" are guaranteed by design and not production tested.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 4.9 V POWER SUPPLY Supply Voltage VBATT 2.3 Hibernate Supply Current IDD1 TA ≤ +50ºC, average current 5.2 12 μA Active Supply Current IDD2 TA ≤ +50ºC, average current not including thermistor measurement current 16 30 μA Regulation Voltage VREG 1.8 V ANALOG-TO-DIGITAL CONVERSION BATT Measurement Error VGERR BATT Measurement Resolution VLSB BATT Measurement Range VFS TA = +25ºC -7.5 +7.5 -40ºC ≤ TA ≤ +125ºC -20 +20 78.125 2.3 mV μV 4.9 V Sense Resistance RSNS TA = +25°C 35 mΩ Current Measurement Offset Error IOERR Zero current, long term average ±1 mA Current Measurement Resolution ILSB 0.03125 mA Current Measurement Gain Error IGERR ±2.5 % of Reading Current Measurement Error IERR Internal Temperature Measurement Error TIGERR Internal Temperature Measurement Resolution TILSB (Note 6) TA ≤ +50ºC, 0.15A and 0.3A (Note 6) -3 ±0.5 +3 TA ≤ +50ºC, 0.5A (Note 6) ±1 % of Reading -40ºC ≤ TA ≤ +125ºC ±1 ºC 0.00391 ºC INPUT/OUTPUT External Thermistance Resistance www.analog.com REXT10 Config.R100 = 0 10 REXT100 Config.R100 = 1 100 kΩ Analog Devices | 22 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ Electrical Characteristics—Fuel Gauge (continued) (VBATT = 2.3V to 4.9V, TA = -40ºC to +125ºC, typical value for TA is +25ºC. Limits are 100% tested at TA = +25°C. The operating temperature range and relevant supply voltage range are guaranteed by design and characterization. Specifications marked "GBD" are guaranteed by design and not production tested.) PARAMETER SYMBOL Output Drive Low, ALRT VOL Input Logic High, ALRT, SCL, SDA VIH Input Logic Low, ALRT, SCL, SDA VIL CONDITIONS TYP MAX UNITS 0.4 V 1.5 Battery-Detach Detection Threshold VDET Measured as a fraction of VBATT on TH rising Battery-Detach Detection Threshold Hysteresis VDET-HYS Measured as a fraction of VBATT on TH falling Battery-Detach Comparator Delay MIN IOL = 4mA, VBATT = 2.3V tTOFF TH step from 70% to 100% of VBATT (Alrtp = 0, EnAIN = 1, FTHRM = 1) Leakage Current, CSN, ALRT ILEAK VALRT < 15V Input Pulldown Current IPD 91 V 96.2 0.5 V 99 % 1 % 100 μs +1 μA 0.4 μA +1 % LEAKAGE -1 VSDA = 0.4V, VSCL = 0.4V 0.05 0.2 TIMING Time-Base Accuracy tERR TH Precharge Time tPRE TA = +25°C -1 8.48 ms Electrical Characteristics—I2C Serial Communication (VIN = 3.7V, VIO = 1.8V, limits are 100% production tested at TA = +25°C, limits over the operating temperature range (TA = -40°C to +125°C) are guaranteed by design and characterization, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS V POWER SUPPLY VIO Voltage Range VIO VIO Bias Current 1.7 1.8 3.6 VIO = 3.6V, VSDA = VSCL = 0V or 3.6V, TA = +25°C -1 0 +1 VIO = 1.7V, VSDA = VSCL= 0V or 1.7V -1 0 +1 μA SDA AND SCL I/O STAGE SCL, SDA Input High Voltage VIH VIO = 1.7V to 3.6V SCL, SDA Input Low Voltage VIL VIO = 1.7V to 3.6V SCL, SDA Input Hysteresis VHYS SCL, SDA Input Leakage Current II SDA Output Low Voltage VOL SCL, SDA Pin Capacitance www.analog.com CI 0.7 x VIO V 0.3 x VIO 0.05 x VIO VIO = 3.6V, VSCL = VSDA = 0V and 3.6V -10 Sinking 20mA 10 V V +10 μA 0.4 V pF Analog Devices | 23 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ Electrical Characteristics—I2C Serial Communication (continued) (VIN = 3.7V, VIO = 1.8V, limits are 100% production tested at TA = +25°C, limits over the operating temperature range (TA = -40°C to +125°C) are guaranteed by design and characterization, unless otherwise noted.) PARAMETER Output Fall Time from VIH to VIL SYMBOL CONDITIONS MIN TYP tOF (Note 6) MAX UNITS 120 ns 400 kHz I2C-COMPATIBLE INTERFACE TIMING (STANDARD, FAST AND FAST-MODE PLUS) (Note 6) Clock Frequency fSCL 0 tHD_STA 0.6 μs SCL Low Period tLOW 1.3 μs SCL High Period Hold Time (REPEATED) START Condition tHIGH 0.6 μs Setup Time REPEATED START Condition tSU_STA 0.6 μs Data Hold Time tHD_DAT 0 μs Data Setup Time tSU_DAT 100 ns Setup Time for STOP Condition tSU_STO 0.6 μs Bus Free Time between STOP and START Condition tBUF 1.3 μs Pulse Width of Suppressed Spikes tSP Maximum pulse width of spikes that must be suppressed by the input filter 50 ns I2C-COMPATIBLE INTERFACE TIMING (HIGH-SPEED MODE, CB = 400pF) (Note 6) SCL Fall Time tFCL TA = +25°C 20 80 ns Note 6: Design guidance only. Not production tested. www.analog.com Analog Devices | 24 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ Typical Operating Characteristics (Typical Applications Circuit. VCHGIN = 0V, VSYS = VIN_SBB = VBATT = 3.7V, VIO = 3.3V, TA = +25°C, SIMO in automatic operation mode, VSBB0 = 1.8V, IP_SBB0 = 0.5A, VSBB1 = 1.1V, IP_SBB1 = 0.5A, VSBB2 = 3.3V, IP_SBB2 = 1.0A, unless otherwise noted. Inductor = DFE201610E-1R5M, 1.5μH, 91mΩ.) www.analog.com Analog Devices | 25 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ Typical Operating Characteristics (continued) (Typical Applications Circuit. VCHGIN = 0V, VSYS = VIN_SBB = VBATT = 3.7V, VIO = 3.3V, TA = +25°C, SIMO in automatic operation mode, VSBB0 = 1.8V, IP_SBB0 = 0.5A, VSBB1 = 1.1V, IP_SBB1 = 0.5A, VSBB2 = 3.3V, IP_SBB2 = 1.0A, unless otherwise noted. Inductor = DFE201610E-1R5M, 1.5μH, 91mΩ.) www.analog.com Analog Devices | 26 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ Typical Operating Characteristics (continued) (Typical Applications Circuit. VCHGIN = 0V, VSYS = VIN_SBB = VBATT = 3.7V, VIO = 3.3V, TA = +25°C, SIMO in automatic operation mode, VSBB0 = 1.8V, IP_SBB0 = 0.5A, VSBB1 = 1.1V, IP_SBB1 = 0.5A, VSBB2 = 3.3V, IP_SBB2 = 1.0A, unless otherwise noted. Inductor = DFE201610E-1R5M, 1.5μH, 91mΩ.) www.analog.com Analog Devices | 27 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ Typical Operating Characteristics (continued) (Typical Applications Circuit. VCHGIN = 0V, VSYS = VIN_SBB = VBATT = 3.7V, VIO = 3.3V, TA = +25°C, SIMO in automatic operation mode, VSBB0 = 1.8V, IP_SBB0 = 0.5A, VSBB1 = 1.1V, IP_SBB1 = 0.5A, VSBB2 = 3.3V, IP_SBB2 = 1.0A, unless otherwise noted. Inductor = DFE201610E-1R5M, 1.5μH, 91mΩ.) www.analog.com Analog Devices | 28 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ Typical Operating Characteristics (continued) (Typical Applications Circuit. VCHGIN = 0V, VSYS = VIN_SBB = VBATT = 3.7V, VIO = 3.3V, TA = +25°C, SIMO in automatic operation mode, VSBB0 = 1.8V, IP_SBB0 = 0.5A, VSBB1 = 1.1V, IP_SBB1 = 0.5A, VSBB2 = 3.3V, IP_SBB2 = 1.0A, unless otherwise noted. Inductor = DFE201610E-1R5M, 1.5μH, 91mΩ.) www.analog.com Analog Devices | 29 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ Typical Operating Characteristics (continued) (Typical Applications Circuit. VCHGIN = 0V, VSYS = VIN_SBB = VBATT = 3.7V, VIO = 3.3V, TA = +25°C, SIMO in automatic operation mode, VSBB0 = 1.8V, IP_SBB0 = 0.5A, VSBB1 = 1.1V, IP_SBB1 = 0.5A, VSBB2 = 3.3V, IP_SBB2 = 1.0A, unless otherwise noted. Inductor = DFE201610E-1R5M, 1.5μH, 91mΩ.) www.analog.com Analog Devices | 30 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ Typical Operating Characteristics (continued) (Typical Applications Circuit. VCHGIN = 0V, VSYS = VIN_SBB = VBATT = 3.7V, VIO = 3.3V, TA = +25°C, SIMO in automatic operation mode, VSBB0 = 1.8V, IP_SBB0 = 0.5A, VSBB1 = 1.1V, IP_SBB1 = 0.5A, VSBB2 = 3.3V, IP_SBB2 = 1.0A, unless otherwise noted. Inductor = DFE201610E-1R5M, 1.5μH, 91mΩ.) www.analog.com Analog Devices | 31 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ Typical Operating Characteristics (continued) (Typical Applications Circuit. VCHGIN = 0V, VSYS = VIN_SBB = VBATT = 3.7V, VIO = 3.3V, TA = +25°C, SIMO in automatic operation mode, VSBB0 = 1.8V, IP_SBB0 = 0.5A, VSBB1 = 1.1V, IP_SBB1 = 0.5A, VSBB2 = 3.3V, IP_SBB2 = 1.0A, unless otherwise noted. Inductor = DFE201610E-1R5M, 1.5μH, 91mΩ.) www.analog.com Analog Devices | 32 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ Pin Configuration WLP TOP VIEW (BUMP SIDE DOWN) MAX77658 1 2 3 4 5 6 CHGIN SYS BATT CHGR TH SYS FG NC VL GPIO2 VIO SCL ALRT BATT AMUX GPIO1 GND SDA REG GND nEN GPIO0 GND SBB1 SBB2 IN_SBB LDO1 IN_LDO1 nIRQ LXB LXB LXA LDO0 IN_LDO0 nRST SBB0 BST PGND + A B C D E F WLP (3.228mm x 2.958mm x 0.5mm, 0.5mm PITCH) Pin Description PIN NAME FUNCTION TYPE A6 NC Not connected. VIO I2C Interface and GPIO Driver Power Power Input D1 nEN Active-Low Enable Input. EN supports push-button, slide-switch, or logic mode configurations. If not used, connect EN to SYS and use the CNFG_SBBx_B.EN_SBBx[2:0] and CNFG_LDOx_B.EN_LDOx[2:0] bitfields to enable channels. Digital Input E3 nIRQ Active-Low, Open-Drain Interrupt Output. Connect a 100kΩ pullup resistor between IRQ and a voltage equal to or less than VSYS. Digital Output F3 nRST Active-Low, Open-Drain Reset Output. Connect a 100kΩ pullup resistor between RST and a voltage equal to or less than VSYS. Digital Output B2 GPIO2 General Purpose Input/Output. The GPIO I/O stage is internally biased with VIO. Digital I/O TOP LEVEL B3 www.analog.com Analog Devices | 33 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ Pin Description (continued) PIN NAME C2 GPIO1 General Purpose Input/Output. The GPIO I/O stage is internally biased with VIO. FUNCTION TYPE D2 GPIO0 General Purpose Input/Output. The GPIO I/O stage is internally biased with VIO. B4 SCL I2C Clock Digital Input C4 SDA I2C Data Digital I/O Digital I/O Digital I/O Analog Multiplexer Output. Connect to system ADC to perform conversions on charger power signals. Analog Output C1 AMUX C3, C6, D3 GND Quiet Ground. Connect GND to PGND, and the low-impedance ground plane of the PCB. Ground A1 CHGIN Charger Input. Connect to a DC charging source. Bypass to PGND with a 4.7μF ceramic capacitor. Power Input A2 SYS System Power Output. SYS provides power to the system resources as well as the control logic of the device. Connect to IN_SBB and bypass to GND with a 22μF ceramic capacitor. Power Output A3 BATT CHGR Battery Connection to the Charger. Connect to SYS FG pin if fuel gauge is intended to be used. Otherwise, connect to positive battery terminal. Bypass to GND with a 4.7μF ceramic capacitor. Power I/O B1 VL Internal charger 3V logic supply powered from CHGIN. Bypass to GND with a 1μF ceramic capacitor. Do not load VL externally. A4 TH Thermistor Input. Connect a thermistor from TH to GND. TH also provides battery insertion/removal detection. Connect to BATT if not used. CHARGER Power Output SIMO BUCK-BOOST SIMO Power Input. Connect IN_SBB to SYS and bypass to PGND with a minimum of 10μF ceramic capacitor as close as possible to the IN_SBB pin. D6 IN_SBB Power Input F4 SBB0 SIMO Buck-Boost Output 0. SBB0 is the power output for channel 0 of the SIMO buck-boost. Bypass SBB0 to PGND with a 22μF ceramic capacitor. If not used, see the Unused Outputs section. Power Output D4 SBB1 SIMO Buck-Boost Output 1. SBB1 is the power output for channel 1 of the SIMO buck-boost. Bypass SBB1 to PGND with a 22μF ceramic capacitor. If not used, see the Unused Outputs section. Power Output D5 SBB2 SIMO Buck-Boost Output 2. SBB2 is the power output for channel 2 of the SIMO buck-boost. Bypass SBB2 to PGND with a 22μF ceramic capacitor. If not used, see the Unused Outputs section. Power Output F5 BST SIMO Power Input for the High-Side Output NMOS Drivers. Connect a 10nF ceramic capacitor between BST and LXB. Power Input E4, E5 LXB Switching Node B. LXB is driven between PGND and SBBx when SBBx is enabled. LXB is driven to PGND when all SIMO channels are disabled. Connect a 1.5μH inductor between LXA and LXB. Power Input E6 LXA Switching Node A. LXA is driven between PGND and IN_SBB when any SIMO channel is enabled. LXA is driven to PGND when all SIMO channels are disabled. Connect a 1.5μH inductor between LXA and LXB. Power I/O F6 PGND Power ground for the SIMO low-side FETs. Connect PGND to GND, and the lowimpedance ground plane of the PCB. Ground F2 IN_LDO0 Linear Regulator Input. If connected to a SIMO output with a short trace, IN_LDO0 can share the output's capacitor. Otherwise, bypass with a 2.2μF ceramic capacitor to ground. If not used, connect to ground or leave unconnected. Power Input LDO www.analog.com Analog Devices | 34 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ Pin Description (continued) PIN NAME FUNCTION TYPE E2 IN_LDO1 Linear Regulator Input. If connected to a SIMO output with a short trace, IN_LDO1 can share the output's capacitor. Otherwise, bypass with a 2.2μF ceramic capacitor to ground. If not used, connect to ground or leave unconnected. Power Input F1 LDO0 Linear Regulator Output 0. Bypass with a 1.0μF ceramic capacitor to GND. If not used, disable LDO0 and connect this pin to ground or leave unconnected. Power Output E1 LDO1 Linear Regulator Output 1. Bypass with a 1.0μF ceramic capacitor to GND. If not used, disable LDO1 and connect this pin to ground or leave unconnected. Power Output B5 ALRT Alert Output. The ALRT pin is an open-drain active-low output which indicates fuel-gauge alerts. Connect to GND if not used. C5 REG Internal 1.8V Regulator Output. Bypass with an external 0.47μF capacitor to GND. Do not load externally. A5 SYS FG System Power of Fuel Gauge. Connect to BATT CHGR or connect to system load. B6 BATT FUEL GAUGE www.analog.com IC Power Supply and Battery Voltage Sense Input. Connect to the positive terminal of a battery cell. Bypass with a 4.7μF capacitor to GND. Analog Devices | 35 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ Detailed Description The MAX77658 provides a highly-integrated battery charging and power management solution for low-power applications. The linear charger can charge various Li+ batteries with a wide range of charge current and charger termination voltage options. Temperature monitoring and JEITA compliance settings add additional functionality and safety to the charger. Five regulators are integrated within this device (see Table 1). A single-inductor, multiple output (SIMO) buck-boost regulator provides three highly-efficient and independently programmable power rails. Two 150mA low-dropout linear regulators (LDOs) provide ripple rejection for audio and other noise sensitive applications. An ultra-low power fuel gauge which implements the Maxim ModelGauge m5 EZ algorithm is also packed into the MAX77658. The ModelGauge m5 algorithm combines the short-term accuracy and linearity of a coulomb-counter with the long-term stability of a voltage-based fuel gauge, along with temperature compensation to provide industry-leading fuel gauge accuracy. The additional robustness from the ModelGauge m5 EZ algorithm enables simpler implementation for most applications and batteries by avoiding time-consuming battery characterization. This device includes other features such as an analog multiplexer that switches several internal voltage and current signals to an external node for monitoring with an external ADC. A bidirectional I2C serial interface allows for configuring and checking the status of the device. An internal on/off controller provides regulator sequencing and supervisory functionality for the device. Table 1. Regulator Summary REGULATOR NAME REGULATOR TOPOLOGY MAXIMUM IOUT (mA) VIN RANGE MAX77658 VOUT RANGE/ RESOLUTION SBB0 SIMO Up to 500* 2.7 to 5.5V 0.5V to 5.5V in 25mV steps SBB1 SIMO Up to 500* 2.7 to 5.5V 0.5V to 5.5V in 25mV steps SBB2 SIMO Up to 750* 2.7 to 5.5V 0.5V to 5.5V in 25mV steps LDO0/1 PMOS LDOs 150 1.7 to 5.5V 0.5V to 5V in 25mV steps *Shared capacity with other SBBx channels. See the SIMO Available Output Current section for more information. Part Number Decoding The MAX77658 has different one-time programmable (OTP) options to support a variety of applications. OTP options set default settings such as output voltage or CHGIN current limit. See Figure 1 for how to identify these. Table 2 list all available OTP options. Refer to the Maxim Integrated naming convention for more details. www.analog.com Analog Devices | 36 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ MAX77658 x A N X + T BASE PART NUMBER TAPE-AND-REEL LEAD-FREE (RoHS) OTP OPTION OPERATING TEMP. RANGE NUMBER OF PINS PACKAGE TYPE Figure 1. Part Number Decode Table 2. OTP Options Table OTP LETTER AND SETTINGS BLOCK Global Watchdog SIMO BIT FIELD NAME SETTING NAME A B S NPM NPM NPM SBIA_LPM Bias Low-Power Mode DBEN_nEN nEN Debounce Time nEN_MODE nEN Mode T_MRST Manual Reset Time 8s 8s 8s ALT_GPIO0 GPIO0 Mode GPIO GPIO GPIO ALT_GPIO1 GPIO1 Mode GPIO Alt. GPIO ALT_GPIO2 GPIO2 Mode GPIO GPIO GPIO ADDR I2C Address (7-Bit) 0x48 0x48 0x40 DIDM Device ID for Metal Options 0b0 0b0 0b0 CID[4:0] Chip ID 0x01 0x0B 0x10 WDT_LOCK Watchdog Timer Disable Control Unlocked Unlocked Unlocked WDT_EN Watchdog Timer Enable Disabled Disabled Disabled SBB_F_SHUTDN SBB Shutdown from SBB Faults Disabled Disabled Disabled TV_SBB0[7:0] SBB0 VOUT 3.300V 1.100V 1.825V IP_SBB0[1:0] SBB0 Inductor Current Peak Limit 1.000A 0.500A 0.333A OP_MODE[1:0] (SBB0) SBB0 Operating Mode Automatic Automatic Buck ADE_SBB0 Active-Discharge Resistor Enable EN_SBB0[2:0] SBB0 Enable Control TV_SBB1[7:0] IP_SBB1[1:0] OP_MODE[1:0] (SBB1) SBB1 Operating Mode ADE_SBB1 Active-Discharge Resistor Enable EN_SBB1[2:0] SBB1 Enable Control TV_SBB2[7:0] SBB2 VOUT www.analog.com 500μs 500μs 500μs Push-Button Push-Button Push-Button Enabled Enabled Enabled FPS Slot 0 Off FPS Slot 0 SBB1 VOUT 1.500V 1.800V 2.000V SBB1 Inductor Current Peak Limit 1.000A 0.500A 0.333A Automatic Automatic Buck Enabled Enabled Enabled FPS Slot 0 On Off 0.900V 3.300V 3.300V Analog Devices | 37 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ Table 2. OTP Options Table (continued) OTP LETTER AND SETTINGS LDO Charger IP_SBB2[1:0] SBB2 Inductor Current Peak Limit OP_MODE[1:0] (SBB2) SBB2 Operating Mode ADE_SBB2 Active-Discharge Resistor Enable EN_SBB2[2:0] SBB2 Enable Control TV_OFS_LDO0 and TV_LDO0[6:0] LDO0 VOUT LDO0_MD LDO or LSW Mode ADE_LDO0 Active-Discharge Resistor Enable EN_LDO0[2:0] LDO0 Enable Control TV_OFS_LDO1 and TV_LDO1[6:0] LDO1 VOUT LDO1_MD LDO or LSW Mode ADE_LDO1 Active-Discharge Resistor Enable EN_LDO1[2:0] LDO1 Enable Control CHG_EN Charger Enable ICHGIN_LIM_DEF Default Charger Input Current Limit 1.000A 1.000A 0.500A Automatic Automatic Automatic Enabled Enabled Enabled FPS Slot 0 Off Off 1.800V 1.800V 1.825V LDO LSW LDO Enabled Enabled Enabled FPS Slot 0 Off Off 1.800V 1.800V 2.800V LDO LDO LDO Enabled Enabled Enabled FPS Slot 0 Off Off Disabled Enabled Enabled 475mA 475mA 475mA *Future OTP option. Contact Maxim Integrated for availability. Support Material The following support materials are available for this device: ● MAX77658 Programmer's Guide: Basic software implementation advice. Contact Maxim for document availability. ● MAX77658 SIMO Calculator: Tool to estimate supported maximum current and ripple for specified conditions. ● ModelGauge m5 EZ User Guide • Documents full fuel gauge register set • More details about ModelGauge m5 algorithm • Discusses additional applications ● ModelGauge m5 EZ Software Implementation Guide • Guidelines for software drivers for ModelGauge m5 EZ including example code Top-Level Interconnect Simplified Diagram Figure 2 shows the same major blocks as the Typical Applications Circuit with an increased emphasis on the routing between each block. This diagram is intended to familiarize the user with the landscape of the device. Many of the details associated with these signals are discussed throughout the data sheet. At this stage of the data sheet, note the addition of the main bias and clock block that are not shown in the Typical Applications Circuit section. The main bias and clock block provides voltage, current, and clock references for other blocks as well as many resources for the top-level digital control. www.analog.com Analog Devices | 38 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ MAX77658 SYS CLK VREF VIREF MAIN BIAS AND CLOCK SYS_RST FPS SYSUVLO SYSOVLO OTLO POR BOK BIAS_EN SBIA_LPM 500µs/30ms DEBOUNCE TIMER tDBNC_nEN IRQ_CHG CHGINPOK CHARGER AND MUX AMUX IRQ_CHG IRQ_CHG SYS nEN VREF VIREF SYS_RST nEN COMM DBEN_nEN DBNEN VREF VIREF SYS_RST FPS COMM SIMO VREF VIREF SYS_RST FPS COMM LDO0 VREF VIREF SYS_RST FPS COMM LDO1 VIO GPIO0 10ns/30ms DEBOUNCE TIMER tDBNC_nEN DBEN_GPI DI TOP-LEVEL DIGITAL CONTROL DO ALRT COMM FUEL GAUGE ALRT VIO nRST DBEN_GPI GPIO1 GPO AND GPI BUFFERS AND DEBOUNCE TIMER RST DI DO VIO nIRQ IRQ_TOP DBEN_GPI GPIO2 GPO AND GPI BUFFERS AND DEBOUNCE TIMER DI DO SDA COMM I 2C SCL Figure 2. Top-Level Interconnect Simplified Diagram www.analog.com Analog Devices | 39 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ Detailed Description—Global Resources The global resources encompass a set of circuits that serve the entire device and ensure safe, consistent, and reliable operation. Features and Benefits ● Voltage Monitors • SYS POR (power-on-reset) comparator generates a reset signal upon power-up. • SYS undervoltage ensures repeatable behavior when power is applied to and removed from the device. • SYS overvoltage monitor inhibits operation with overvoltage power sources to ensure reliability in faulty environments. ● Thermal Monitors • +145°C junction temperature shutdown ● Manual Reset • 4s or 8s period ● Wake-Up Events • Charger insertion (with 120ms debounce) • nEN input assertion ● Interrupt Handler • Digital interrupt output (nIRQ) • All interrupts are maskable ● Push-Button/Slide-Switch/Logic Mode On-key (nEN) • Configurable push-button/slide-switch/logic mode functionality • 500μs or 30ms debounce timer interfaces directly with mechanical switches ● On/Off Controller • Startup/shut-down sequencing • Programmable sequencing delay ● GPIO, RST Digital I/Os Voltage Monitors The device monitors the system voltage (VSYS) to ensure proper operation using three comparators (POR, UVLO, and OVLO). These comparators include hysteresis to prevent their outputs from toggling between states during noisy system transitions. SYS POR Comparator The SYS POR comparator monitors VSYS and generates a power-on reset signal (POR). When VSYS is below VPOR, the device is held in reset (SYSRST = 1). When VSYS rises above VPOR, internal signals and on-chip memory stabilize and the device is released from reset (SYSRST = 0). SYS Undervoltage-Lockout Comparator The SYS undervoltage-lockout (UVLO) comparator monitors VSYS and generates a SYSUVLO signal when the VSYS falls below UVLO threshold. The SYSUVLO signal is provided to the top-level digital controller. See Figure 7 and Table 6 for additional information regarding the UVLO comparator: ● When the device is in the shutdown state, the UVLO comparator is disabled. ● When transitioning out of the shutdown state, the UVLO comparator is enabled allowing the device to check for sufficient input voltage. If the device has sufficient input voltage, it can transition to the resource on state; if there is insufficient input voltage, the device transitions back to the shutdown state. SYS Overvoltage-Lockout Comparator The device is rated for 5.5V maximum operating voltage (VSYS) with an absolute maximum input voltage of 6.0V. An www.analog.com Analog Devices | 40 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ overvoltage-lockout monitor increases the robustness of the device by inhibiting operation when the supply voltage is greater than VSYSOVLO. See Figure 7 and Table 6 for additional information regarding the OVLO comparator: ● When the device is in the shutdown state, the OVLO comparator is disabled. Thermal Monitors MAX77658 has three global on-chip thermal sensors: ● Junction Temperature Alarm 1 → 80°C ● Junction Temperature Alarm 2 → 100°C ● Junction Temperature Shutdown → 145°C The junction temperature alarms have maskable rising interrupts as well as status bits (see the Register Map section for more information). Unmasking these thermal alarms is recommended for all systems. If the first alarm is triggered, the system software should attempt to lower system power dissipation. If the second alarm is triggered, then attempts to lower the power dissipation were unsuccessful and the system software should turn the device off. Finally, if the junction temperature rises to junction temperature shutdown, then the MAX77658 sets the ERCFLAG.TOVLD bit and automatically turns itself off. After a junction temperature shutdown event, the system can be enabled again. The system software can read the ERCFLAG register during initialization to see ERCFLAG.TOVLD = 1 and log that an extreme thermal event has occurred. Chip Identification The MAX77658 offers different one-time-programmable (OTP) options to, for example, set the default output voltages. These options are identified by the chip identification number, which can be read in the CID register. nEN Enable Input nEN is an active-low internally debounced digital input that typically comes from the system’s on-key. The debounce time is programmable with CNFG_GLBL0.DBEN_nEN[1:0]. The primary purpose of this input is to generate a wake-up signal for the PMIC that turns on the regulators. Maskable rising/falling interrupts are available for nEN (INT_GLBL0.nEN_R and INT_GLBL0.nEN_F) for alternate functionality. The nEN input can be configured to work either with a push-button (CNFG_GLBL.nEN_MODE[1:0] = 0b00), a slideswitch (CNFG_GLBL.nEN_MODE[1:0] = 0b01), or Logic Mode (CNFG_GLBL0.nEN_MODE[1:0] = 0b10). See Figure 3 for more information. In both push-button mode and slide-switch mode, the on/off controller looks for a falling edge on the nEN input to initiate a power-up sequence. nEN Manual Reset nEN works as a manual reset input when the on/off controller is in the "Resource-On" state. The manual reset function is useful for forcing a power-down in case communication with the processor fails. When nEN is configured for push-button mode and the input is asserted (nEN = LOW) for an extended period (tMRST), the on/off controller initiates a power-down sequence and goes to Shutdown mode. When nEN is configured for slideswitch mode and the input is deasserted (nEN = HIGH) for an extended period (tMRST), the on/off controller initiates a power-down sequence and goes to Shutdown mode. When nEN is configured as a logic mode, the on/off controller initiates a power-up sequence and goes into Resource ON mode when the input is asserted (nEN = LOW). When the input is deasserted (nEN = HIGH), the on/off controller initiates a power-down sequence and goes into Shutdown mode. nEN Triple-Functionality: Push-Button vs. Slide-Switch vs. Logic The nEN digital input can be configured to work with a push-button, a slide-switch, or a logic input. The following timing diagram shows nEN's triple functionality for power-on sequencing and manual reset. The default push-button mode is OTP programmable. www.analog.com Analog Devices | 41 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ NOT DRAWN TO SCALE STATE SHUTDOWN POWER-ON SEQUENCE RESOURCE ON POWER-DOWN SEQUENCE INPUT VOLTAGE APPLIED VCCINT IN tDBNC_nEN nEN tDBNC_nEN tDBNC_nEN tMRST PUSH-BUTTON MODE IN tDBNC_nEN nEN tMRST tDBNC_nEN SLIDE-SWITCH MODE DRIVEN BY LOGIC SIGNAL nEN LOGIC MODE Figure 3. nEN Usage Timing Diagram nEN Internal Pullup Resistors to VCCINT The nEN logic thresholds are referenced to VCCINT. There are internal pullup resistors between nEN and VCCINT (RnEN_PU), which can be configured with the CNFG_GLBL.PU_DIS bit. See Figure 4. While CNFG_GLBL.PU_DIS = 0, the pullup value is approximately 200kΩ. While CNFG_GLBL.PU_DIS = 1, the pullup value is 10MΩ. Applications using a slide-switch on-key or logic mode can reduce quiescent current consumption by changing pullup strength to 10MΩ. Applications using normally-open, momentary, and push-button on-keys (as shown in Figure 4) do not create this leakage path and should use the stronger 200kΩ pullup option. VCCINT 10MΩ 200kΩ ON-KEY SWITCH CONTROL PU_DIS SWITCH 0b0 CLOSED 0b1 OPEN RnEN_PU ~200kΩ 10MΩ nEN Figure 4. nEN Pullup Resistor Configuration www.analog.com Analog Devices | 42 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ Debounced Input The nEN is debounced on both rising and falling edges to reject undesired transitions. The input must be at a stable logic level for the entire debounce period for the output to change its logic state. Figure 5 shows an example timing diagram for the nEN debounce. NOT DRAWN TO SCALE BOUNCING IS REJECTED STABLE SIGNAL IS ACCEPTED BOUNCING IS REJECTED STABLE SIGNAL IS ACCEPTED nEN tDBUF DBEN tDBNC_nEN tDBUF tDBNC_nEN (INTERNAL) Figure 5. Debounced Input Interrupts (nIRQ) nIRQ is an active-low, open-drain output that is typically routed to the host processor's interrupt input to signal an important change in device status. See the Register Map section for a comprehensive list of all interrupt bits and status registers. A pullup resistor to a voltage less than or equal to VSYS is required for this node. nIRQ is the logical NOR of all unmasked interrupt bits in the register map. All interrupts are masked by default. Masked interrupt bits do not cause the nIRQ pin to change. Unmask the interrupt bits to allow nIRQ to assert. Reset Output (nRST) nRST is an open-drain, active-low output that is typically used to hold the processor in a reset state when the device is powered down. During a power-up sequence, the nRST deasserts after the last regulator in the power-up chain is enabled (tRSTODD). During a power-down sequence, the nRST output asserts before any regulator is powered down (tRSTOAD). See Figure 11 for nRST timing. A pullup resistor to a voltage less than or equal to VSYS is required for this node. www.analog.com Analog Devices | 43 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ General-Purpose Input Output (GPIO) The MAX77658 provides general-purpose input/output (GPIO) pins to increase system flexibility. See Figure 6 for more details. Clear CNFG_GPIOx.DIR to configure GPIO as a general-purpose output (GPO). The GPO can either be in push-pull mode (CNFG_GPIOx.DRV = 1) or open-drain mode (CNFG_GPIOx.DRV = 0). ● The push-pull output mode is ideal for applications that need fast (~2ns) edges and low power consumption. ● The open-drain mode requires an external pullup resistor (typically 10kΩ to 100kΩ). Connect the external pullup resistor to a bias voltage that is less than or equal to VIO. • The open-drain mode can be used to communicate to different logic domains. For example, to send a signal from the GPO on a 1.8V logic domain (VIO = 1.8V) to a device on a 1.2V logic domain, connect the external pullup resistor to 1.2V. • The open-drain mode can be used to connect several open-drain (or open-collector) devices together on the same bus to create wired logic (wired AND logic is positive-true; wired OR logic is negative-true). ● The general-purpose input (GPI) functions are still available while the pin is configured as a GPO. In other words, the CNFG_GPIOx.DI (input status) bit still functions and does not collide with the state of the CNFG_GPIOx.DIR bit. Set CNFG_GPIOx.DIR to have the GPIO function as a GPI. The GPI features a 30ms debounce timer (tDBNC_GPI) that can be enabled or disabled with DBEN_GPI. ● Enable the debounce timer (CNFG_GPIOx.DBEN_GPI = 1) if the GPI is connected to a device that can bounce or chatter, like a mechanical switch. ● If the GPI is connected to a circuit with clean logic transitions and no risk of bounce, disable the debounce timer (CNFG_GPIOx.DBEN_GPI = 0) to eliminate logic delays. With no debounce timer, the GPI input logic propagates to nIRQ in 10ns. A dedicated internal oscillator is used to create the 30ms (tDBNC_GPI) debounce timer. To obtain low VIO supply current, ensure the GPIO voltage is either logic high or logic low. If the GPIO pin is unconnected (either as a GPI or an open-drain GPO) and VIO is powered, the GPIO voltage trends towards the logic level gray area (0.3 x VIO < VGPIO < 0.7 x VIO). If VGPIO is in the gray area, VIO current can be more than 10μA. The GPI features edge detectors that feed into the the top-level interrupt system of the chip. This allows software to use interrupts to service events associated with a GPI change instead of polling for these changes. ● If the application wants nIRQ to go low only on a GPI rising edge, then it should clear the GPI rising edge interrupt mask bit (INTM_GLBL1.GPI_RM = 0) and set the GPI falling edge interrupt mask bit (INTM_GLBL1.GPI_FM = 1). ● If the application wants nIRQ to go low only on a GPI falling edge, then it should set the GPI rising edge interrupt mask bit (INTM_GLBL1.GPI_RM = 1) and clear the GPI falling edge interrupt mask bit (INTM_GLBL1.GPI_FM = 0). ● If the application wants nIRQ to go low on both GPI falling and rising edges, then it should clear the GPI rising edge interrupt mask bit (INTM_GLBL1.GPI_RM = 0) and clear the GPI falling edge interrupt mask bit (INTM_GLBL1.GPI_FM = 0). www.analog.com Analog Devices | 44 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ SYS COMM CNFG_GPIOx DRVx DIRx DOx GPIx_RM GPIx_FM DBNC_EN DIx GPIx_R GPIx_F GPIx_R GPIx_RM nIRQ Q VIO DBNC_EN R IRQ OTHER nIRQ ASSERTION SOURCES NOT SHOWN GPIx_FM GPIx_F DRVx D 1 Q READ (GPIx_R) DIx 0 1 DIRx DOx D 1 R GPIOx 30ms DEBOUNCE (tDBNC_GPI) LOGIC READ (GPIx_F) GND Figure 6. GPIOx Block Diagram Alternate Mode Each GPIO in the MAX77658 can be configured to have a different function. Whether a particular GPIO is in GPIO mode or an alternate mode can be checked by reading the CNFG_GPIOx.ALT_GPIOx bit. Table 3 summarizes the alternate functions for each GPIO. Table 3. GPIO Mode CNFG_GPIOx REGISTER GPIOx ALT_GPIOx = 0 ALT_GPIOx = 1 GPIO0 Standard GPIO Active-high input, enables force USB suspend (FUS). FUS is only active if the FUS_M bit is set to 0. GPIO1 Standard GPIO Active-high input, controls the DVS feature for SBB0. GPIO2 Standard GPIO Active-high input, enables DISQBAT. Table 4. CHGIN Suspend State Truth Table CNFG_CHG_G.USBS CNFG_CHG_G.FUS_M GPIO0 CHGIN TO SYS FET 0 0 0 ON 0 0 1 OFF 0 1 X ON 1 X X OFF Table 5. Enabling/Disabling DISQBAT while GPIO2 is in Alternate Mode GPIO2 CHARGING PATH FROM SYS TO BATT CHGR 0 ON 1 OFF www.analog.com Analog Devices | 45 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ On/Off Controller The on/off controller monitors multiple power-up (wake-up) and power-down (shutdown) conditions to enable or disable resources that are necessary for the system and its processor to move between its operating modes. Please note the on/off controller described in this section does not control the behavior of the on-chip fuel gauge. Many systems have one power management controller and one processor. These systems rely on the on/off controller to be the master controller. In this case, the on/off controller receives wake-up events and enables some or all of the regulators to power-up a processor. That processor then manages the system. To conceptualize this master operation, see Figure 7 and Table 6. A typical path through the on/off controller is: 1. Apply a battery and start in the Shutdown state. 2. Press the system's on-key (nEN = LOW) and follow transition 1 to the Resource-On state. If any resources are on the FPS, transitions 3A and 3B are followed. 3. The device performs its desired functions in the Resource-On state. when it is ready to turn off, a manual reset first drives the transition through transitions 4A and 4B to power down the device. Afterwards, the device automatically follows transition 2 to the Shutdown state. Some systems have several power management blocks, a main processor, and sub-processors. These systems can use this device as a sub-power management block for a peripheral portion of circuitry as long as there is an I2C port available from a higher level processor. To conceptualize this operation, see Figure 7 and Table 6. A typical path through the on/ off controller used in this way is: 1. Apply a battery to the system and start in the Shutdown state. 2. The higher level processor can now control this device's resources with I2C commands, e.g., turn on/off regulators. 3. When the higher level processor is ready to turn this device off, it turns off everything through I2C to transition along path 2 to the Shutdown state. Note that in this style of operation, the CNFG_GLBL_SFT_CTRL[1:0] bits should not be used to turn the device off. The CNFG_GLBL_SFT_CTRL[1:0] bits establish directives to the on/off controller itself that does not make sense in this sub-power management block operation. If the processor uses I2C commands to enable the device's resources, the processor should also use I2C commands to disable them. www.analog.com Analog Devices | 46 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ Top Level On/Off Controller STATE ACTION SEQUENCE X ANY STATE2 ANY STATE2 TRANSITION NUMBER. SEE ON/OFF CONTROLLER TRANSITION/STATE TABLE 5A 5B SHUTDOWN ((BIAS OFF) SPS1 CONTROL ALL RESOURCES OFF 0A RESET ACTIONS 0B 4B FPS POWER-DOWN 2 1 0D RESOURCE ON SPS1 CONTROL BIAS AND AT LEAST ONE RESOURCE IS ON 4A 3B 0C OFF ACTIONS 3A FPS POWER-UP Figure 7. Top Level On/Off Controller State Diagram On/Off Controller Transition Table Table 6. On/Off Controller Transition/State TRANSITION CONDITION (TRANSITION HAPPENS WHEN...) 0A Software cold reset (CNFG_GLBL.SFT_CTRL[1:0] = 0b01) OR Watchdog timer expired and caused reset (ERCFLAG.WDT_RST = 1, CNFG_WDT.WDT_MODE = 1) 0B Reset actions completed 0C Software power-off (CNFG_GLBL.SFT_CTRL[1:0] = 0b10) OR Watchdog expired and caused power-off (ERCFLAG.WDT_OFF = 1, CNFG_WDT.WDT_MODE = 0) OR Chip over-temperature lockout (TJ > TOTLO) OR SYS undervoltage lockout (VSYS < VSYSUVLO + VSYSUVLO_HYS) OR SYS overvoltage lockout (VSYS > VSYSOVLO) OR Manual reset occurred (ERCFLAG.MRST = 1) 0D Off actions completed 1 www.analog.com AMUX is being used (CNFG_CHG_I.MUX_SEL[3:0] ≠ 0b0000) OR CHGIN inserted and debounced (STAT_CHG_B.CHGIN_DTLS[1:0] = 0b11) OR Any resources force enabled OR Internal wake-up flags are set (see the Internal Wake-Up Flags section) Analog Devices | 47 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ Table 6. On/Off Controller Transition/State (continued) TRANSITION 2 CONDITION (TRANSITION HAPPENS WHEN...) NOT (Transition 3) Software cold reset (CNFG_GLBL.SFT_CTRL[1:0] = 0b01) OR Software power-off (CNFG_GLBL.SFT_CTRL[1:0] = 0b10) OR Watchdog timer expired OR Manual reset occurred (ERCFLAG.MRT = 1) 3A FPS power-up sequence has not happened yet AND Resources are not forced off AND Internal wake-up flags are set (see the Internal Wake-Up Flags section) 3B FPS power-up sequence done 4A FPS power-up sequence completed AND All resources are force disabled OR Software cold reset (CNFG_GLBL.SFT_CTRL[1:0] = 0b01) OR Software power-off (CNFG_GLBL.SFT_CTRL[1:0] = 0b10) OR Watchdog timer expired OR Manual reset occurred (ERCFLAG.MRT = 1) 4B FPS power-down sequence finished 5A Chip over-temperature lockout (TJ > TOTLO) OR SYS undervoltage lockout (VSYS < VSYSUVLO) OR SYS overvoltage lockout (VSYS > VSYSOVLO) 5B System voltage is below POR threshold (VSYS < VPOR) Internal Wake-Up Flags After transitioning to the shutdown state because of a reset, to allow the device to power-up again, internal wake-up flags are set to remember the wake-up request. In Figure 7 and Table 6, these internal wake-up flags trigger transitions 1 and 3A. The internal wake-up flags are set when any of the following happen: ● nEN is debounced (see the nEN Enable Input section) • For example, after a push-button is pressed or a slide-switch switched to HIGH. ● CHGIN is debounced and valid (STAT_CHG_B.CHGIN_DTLS[1:0] = 0b11) ● Software cold reset command sent (CNFG_GLBL.SFT_CTRL[1:0] = 0b01) ● Watchdog timer expired and caused reset (ERCFLAG.WDT_RST = 1, CNFG_WDT.WDT_MODE = 1) www.analog.com Analog Devices | 48 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ Reset and Off Sequences RESET ACTIONS OFF ACTIONS 0A 0C EVENT RECORDER (ERCFLAG) LOGS RESET CAUSE EVENT RECORDER (ERCFLAG) LOGS POWER-OFF CAUSE RESET FLAGS CLEARED: WDT_EXP = 0 OFF FLAGS CLEARED: WDT_EXP = 0 WAIT 60ms WAIT 60ms RESET CONFIG REGISTERS RESET CONFIG REGISTERS INTERNAL WAKE-UP FLAGS SET INTERNAL WAKE-UP FLAGS CLEARED 0B 0D Figure 8. On/Off Controller Reset and Off-Action Sequences www.analog.com Analog Devices | 49 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ Power-Up/Down Sequence FPS POWER-UP ACTIONS FPS POWER-DOWN ACTIONS 3A 4A FPS ENABLE SLOT 0 ASSERT nRST WAIT tEN WAIT tRSTOAD FPS ENABLE SLOT 1 FPS DISABLE SLOT 3 WAIT tEN WAIT tDIS FPS ENABLE SLOT 2 FPS DISABLE SLOT 2 WAIT tEN WAIT tDIS FPS ENABLE SLOT 3 FPS DISABLE SLOT 1 WAIT tRSTODD WAIT tDIS DEASSERT nRST FPS DISABLE SLOT 0 3B 4B Figure 9. Power-Up/Down Sequence www.analog.com Analog Devices | 50 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ Flexible Power Sequencer (FPS) The FPS allows resources to power up under hardware or software control. Additionally, each resource can power up independently or among a group of other regulators with adjustable power-up/down delays (sequencing). Figure 10 shows four resources powering up under the control of the flexible power sequencer. The flexible sequencing structure consists of one master sequencing timer and four slave resources (SBB0, SBB1, SBB2, LDO0). When the FPS is enabled, a master timer generates four sequencing events for device power-up/down. NOT DRAWN TO SCALE ENFPS tDIS SAME FOR ALL FPS DISABLE PULSES tDIS = 2x tEN tEN SAME FOR ALL FPS ENABLE PULSES PLSFPS 0 1 2 3 3 2 1 0 FPS RESOURCES SBB0 LDO0 SBB1 SBB2 Figure 10. Flexible Power Sequencer Basic Timing Diagram www.analog.com Analog Devices | 51 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ Startup Timing Diagram Due to nEN NOT DRAWN TO SCALE STATE NO POWER POR STANDBY POWER-UP SEQUENCE RESOURCE ON BATTERY INSERTION VSYS VPOR~1.9V tPOR~100µs tDBNC_nEN nEN NOTE 1 tDBNC_nEN NOTE 2 STAT_EN nEN_F nEN_R tSBIA_EN tFPS_DLY BIAS EN (INTERNAL) INTERNAL WAKE-UP SIGNAL NOTE 3 FPS0 FPS1 tEN FPS2 tEN FPS3 tEN REGULATORS nIRQ NOTE 4 tRSTODD nRST NOTES: 1 – nEN LOGIC INPUT IS CONFIGURED TO PUSH-BUTTON MODE AND HAS AN INTERNAL PULLUP TO VCCINT. 2 – nEN ASSERTION RESULTS IN A WAKE-UP EVENT AFTER A DEBOUNCE TIME (tDBNC_nEN). NOTE 5 3 – INTERNAL WAKE-UP SIGNAL CAN ALSO BE GENERATED BY CHARGER PLUG-IN EVENT. 4 – nIRQ HAS AN EXTERNAL PULLUP TO VIO WHICH IS ENABLED IN FLEXIBLE POWER SEQUENCER SLOT #1. 5 – AS PART OF ITS INITIALIZATION ROUTINE, SOFTWARE READS THE INTERRUPT REGISTERS (CLEAR ON READ) AND PROGRAMS THE INTERRUPT MASKS AS DESIRED. Figure 11. Startup Timing Diagram Due to nEN www.analog.com Analog Devices | 52 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ Startup Timing Diagram Due to Charge Source Insertion NOT DRAWN TO SCALE CHARGER INSERTION CHGIN DEBOUNCE POWER-UP SEQUENCE ON THROUGH ON/OFF CONTROLLER PRE-QUAL FAST CHARGE (CC) TOP-OFF (CV) DONE CHGINOK = 1 CHARGER VOLTAGE STATE 5V VCHGIN SYSTEM VOLTAGE 0V VSYS-REG VFAST-CHG VSYSUVLO~2.9V tCHGIN-DB (~120ms) VPOR~2.0V 0V VFAST-CHG INTERNAL CHARGER GENERATED WAKE SIGNAL NOTE 2 VBATT BATTERY VOLTAGE VSYS VPQ 0V NOTE 3 CHARGE CURRENT VFAST-CHG IBATT ITOPOFF IPQ 0mA NOTE 4 CHG_EN = 1 CHARGER ENABLED NOTE 1 nEN FPS0 tSBIA_EN FPS1 tEN FPS2 tEN FPS3 NOTES: tEN 1 – nEN LOGIC INPUT IS CONFIGURED TO PUSH-BUTTON MODE AND HAS AN INTERNAL PULLUP TO VCCINT. REGULATORS 2 - IF CHG_EN = 1 (BY OTP) THEN THE “CHARGER ENABLED” EVENT COINCIDES WITH THE “WAKE” EVENT (CHARGING STARTS ALONG WITH POWER-UP SEQUENCE). tFPS_DLY tRSTODD nRST 3 – THIS INFLECTION POINT IS SYMBOLIC OF BATTERY PROTECTION FET CLOSING. 4 – SOFTWARE SETS CHG_EN = 1 TO ENABLE CHARGING. IF CHG_EN = 1 BY OTP, SEE NOTE 2. - - - - BLUE DOTTED LINES ARE USER INITIATED EVENTS Figure 12. Startup Timing Diagram Due to Charge Source Insertion Force Enabled/Disabled Channels Force enable SIMO and LDO output channels by setting CNFG_SBBx_B.EN_SBBx[2:0] (SIMO) or CNFG_LDOx_B.EN_LDOx[2:0] (LDO) = 0x6 or 0x7. Depending on the OTP, output channels may already be force enabled by default. Output channels configured this way are independent of the flexible power sequence and start up as soon as SYS > UVLO rising. The main bias also automatically turns on. Likewise, output channels can be force disabled by setting EN_SBBx[2:0] or EN_LDOx[2:0] = 0x4 or 0x5. www.analog.com Analog Devices | 53 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ Debounced Inputs (nEN, GPI, CHGIN) nEN, CHGIN, and GPIO (when operating as an input and CNFG_GPIOx.DBEN_GPI = 1), are debounced on both rising and falling edges to reject undesired transitions. The input must be at a stable logic level for the entire debounce period for the output to change its logic state. Figure 13 shows an example timing diagram for the nEN debounce. NOT DRAWN TO SCALE BOUNCING IS REJECTED STABLE SIGNAL IS ACCEPTED BOUNCING IS REJECTED STABLE SIGNAL IS ACCEPTED nEN tDBUF tDBUF tDBNC_nEN tDBNC_nEN EN (INTERNAL) DBEN (INTERNAL) Figure 13. Debounced Inputs (nEN) www.analog.com Analog Devices | 54 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ Watchdog Timer (WDT) The IC features a watchdog timer function for operational safety. If this timer expires without being cleared, the on/off controller causes the IC to enter the shutdown state and resets configuration registers. See the On/Off Controller and On/Off Controller Transition Table sections (transitions 0A and 0C) for more details. Write CNFG_WDT.WDT_EN = 1 through I2C to enable the timer. The watchdog timer period (tWD) is configurable from 16 to 128 seconds in 4 steps with CNFG_WDT.WDT_PER[1:0]. The default timer period is 128 seconds. While the watchdog timer is enabled, the CNFG_WDT.WDT_CLR bit must be set through I2C periodically (within tWD) to reset the timer and prevent shutdown. See the Register Map and Figure 14 for additional details. WATCHDOG TIMER RESET INTERNAL COUNT = tWD WDT_CLR = 0 CLEAR CONTROL SET (WDT_CLR = 1) OR TIMER DISABLED (WDT_EN = 0) OR SHUTDOWN (BIAS OFF) STATE* OR tWD CHANGED (NEW BITS IN WDT_PER[1:0]) TIME ELAPSED < tWD SHUTDOWN (BIAS OFF) STATE** (THE ON/OFF CONTROLLER FORCES THIS TRANSITION WHEN THE TIMER EXPIRES) CLEAR CONTROL NOT SET (WDT_CLR = 0) AND TIMER ENABLED (WDT_EN = 1) AND NOT IN SHUTDOWN (BIAS OFF) STATE* WATCHDOG TIMER ENABLED AND OK TIMER COUNTING DOWN INTENAL COUNT < tWD TIME ELAPSED = tWD WATCHDOG TIMER EXPIRED INTERNAL COUNT = 0 *WATCHDOG TIMER DOES NOT RUN WHILE IN SHUTDOWN STATE. WDT_MODE BIT CAN CAUSE THE ON/OFF CONTROLLER TO EXIT SHUTDOWN AUTOMATICALLY. SEE REGISTER MAP. **SEE ON/OFF CONTROLLER STATE MACHINE Figure 14. Watchdog Timer State Machine The timer can be factory-programmed to be enabled by default, disabled by default, or locked from accidental disable. The CNFG_WDT.WDT_LOCK bit is read-only and must be configured at the factory. See Table 7 for a full description. Table 7. Watchdog Timer Factory-Programmed Safety Options WDT_LOCK WDT_EN 0 0 Watchdog timer is disabled by default. Timer can be enabled or disabled by I2C writes. 0 1 Watchdog timer is enabled by default. Timer can be enabled or disabled by I2C writes. 1 0 Watchdog timer is disabled by default. Timer can be enabled by an I2C write, but only a SYSRST can reset the CNFG_WDT.WDT_EN value back to 0. Timer can not be disabled by direct I2C writes to CNFG_WDT.WDT_EN (write from 1 → 0 is ignored, write from 0 → 1 is accepted). 1 1 Watchdog timer is enabled by default. Nothing can disable the timer. www.analog.com FUNCTION Analog Devices | 55 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ Detailed Description—Smart Power Selector Charger Overview The linear Li+ charger implements a power path with Maxim's Smart Power Selector. This allows separate input current limit and battery charge current settings. Batteries are charged faster under the supervision of the Smart Power Selector because charge current is independently regulated and not shared with variable system loads. See the Smart Power Selector section for more information. The programmable constant-current charge rate (7.5mA to 300mA) supports a wide range of battery capacities. The programmable input current limit (95mA to 475mA) supports a range of charge sources, including USB. The charger's programmable battery regulation voltage range (3.6V to 4.6V) supports a wide variety of cell chemistry. The charger accurately terminates charging by detecting battery currents as low as 0.375mA. Additionally, the robust charger input withstands overvoltage up to 28V. To enhance charger safety, properly configured fuel gauge registers and an externally connected NTC thermistor provide temperature monitoring in accordance with the JEITA recommendations. See the Temperature Measurement section for more information. Charger Symbol Reference Guide Table 8 lists the names and functions of charger-specific signals and if they can be programmed through I2C serial communication. See the Electrical Characteristics and Register Map for more information. Table 8. Charger Quick Symbol Reference Guide I2C PROGRAMMABLE? SYMBOL NAME VCHGIN_OVP CHGIN overvoltage threshold No VCHGIN_UVLO CHGIN undervoltage-lockout threshold No VCHGIN-MIN Minimum CHGIN voltage regulation setpoint Yes, through CNFG_CHG_B.VCHGIN_MIN[2:0] ICHGIN-LIM CHGIN input current limit Yes, through CNFG_CHG_B.ICHGIN_LIM[2:0] VSYS-REG SYS voltage regulation target Yes, through CNFG_CHG_D.VSYS_REG[4:0] VSYS-MIN Minimum SYS voltage regulation setpoint No, tracks VSYS-REG VFAST-CHG Fast-charge constant-voltage level Yes, through CNFG_CHG_G.CHG_CV[5:0] IFAST-CHG Fast-charge constant-current level Yes, through CNFG_CHG_G_E.CHG_CC[5:0] IPQ Prequalification current level Yes, through CNFG_CHG_B.I_PQ VPQ Prequalification voltage threshold Yes, through CNFG_CHG_C.CHG_PQ[2:0] ITERM Termination current level Yes, through CNFG_CHG_C.I_TERM[1:0] TJ-REG Die temperature regulation setpoint Yes, through CNFG_CHG_D.TJ_REG[2:0] tPQ Prequalification safety timer No tFC Fast-charge safety timer Yes, through CNFG_CHG_E.T_FAST_CHG[1:0] tTO Top-off timer Yes, through CNFG_CHG_C.T_TOPOFF[2:0] Figure 15 indicates the high-level functions of each control circuit within the linear charger. www.analog.com Analog Devices | 56 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ BODYSWITCH CHGIN SYS VSYS-MIN INPUT CONTROLLER VSYS-REG BODYSWITCH ICHGIN-LIM CHARGE CONTROLLER VCHGIN-MIN VCHGIN_OVP VCHGIN_UVLO DIE TEMP MONITOR VFAST-CHG TJ-REG TIMER tPQ VPQ IFAST-CHG IPQ ITERM BATT CHGR tFC tTO Figure 15. Charger Simplified Control Loops Smart Power Selector The Smart Power Selector seamlessly distributes power from the input (CHGIN) to the battery (BATT) and the system (SYS). The Smart Power Selector basic functions are: ● When the system load current is less than the input current limit, the battery is charged with residual power from the input. ● When a valid input source is connected to CHGIN, the system regulates to VSYS-REG to power system loads regardless of the battery's voltage (instant on). ● When the system load current exceeds the input current limit, the battery provides additional current to the system (supplement mode). ● When the battery is finished charging and an input source is present to power the system, the battery remains disconnected from the system. ● When the battery is connected and there is no input power from CHGIN, the system is powered from the battery. www.analog.com Analog Devices | 57 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ CHGIN Voltage Monitoring CHGIN is capable of withstanding a maximum of 28V with respect to ground. CHGIN suspends power delivery to the system and battery when VCHGIN exceeds VCHGIN_OVP (7.5V, typ). The input circuit also suspends when VCHGIN falls below VCHGIN_UVLO minus CHGIN UVLO hysteresis (3.5V, typ). While in OVP or UVLO, the charger remains off and the battery provides power to the system. Power transfer to SYS is delayed by a 120ms debounce timer (tCHGIN-DB) after a valid DC source is connected to CHGIN. SYS does not begin regulating to VSYS-REG until after the timer expires. The STAT_CHG_B.CHGIN_DTLS[1:0] bitfield continuously indicates the state of CHGIN's voltage quality. A maskable interrupt (INT_CHG.CHGIN_I) asserts when STAT_CHG_B.CHGIN_DTLS[1:0] changes. Minimum Input Voltage Regulation In the event of a poor-quality charge source, the minimum input voltage regulation loop works to reduce input current if VCHGIN falls below VCHGIN-MIN (programmed by CNFG_CHG_B.VCHGIN_MIN[2:0]). This is important because many commonly used charge adapters feature foldback protection mechanisms where the adapter completely shuts off if its output drops too low. The minimum input voltage regulation loop also prevents VCHGIN from dropping below VCHGIN_UVLO if the cable between the charge source and the charger's input is long or highly resistive. The input voltage regulation loop improves performance with current limited adapters. If the charger’s input current limit is programmed above the current limit of the given adapter, the input voltage loop allows the input to regulate at the current limit of the adapter. The input voltage regulation loop also allows the charger to perform well with adapters that have poor transient load response times. A maskable interrupt (INT_CHG.CHGIN_CTRL_I) signals when the minimum input voltage regulation loop engages. The state of this loop is reflected by STAT_CHG_A.VCHGIN_MIN_STAT. www.analog.com Analog Devices | 58 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ Input Current Limiter The input current limiter limits CHGIN current to not exceed ICHGIN-LIM (programmed by CNFG_CHG_B.ICHGIN_LIM[2:0]). A maskable interrupt (INT_CHG.CHGIN_CTRL_I) signals when the input current limit engages. The STAT_CHG_A.ICHGIN_LIM_STAT bit reflects the state of the current limiter loop. The default value of ICHGIN-LIM is 475mA. Table 9. Input Current Limit Factory Options ICHGIN_LIM[2:0] 475mA FACTORY-DEFAULT 95mA FACTORY-DEFAULT 0b000 475mA 95mA 0b001 380mA 190mA 0b010 285mA 285mA 0b011 190mA 380mA 0b100 to 0b111 95mA 475mA Minimum System Voltage Regulation The minimum system voltage regulation loop ensures that the system rail remains close to the programmed SYS regulation voltage (VSYS-REG) regardless of system loading. The loop engages when the combined battery charge current and system load current causes the CHGIN input to current limit at ICHGIN-LIM. When this happens, the minimum system voltage loop reduces charge current in an attempt to keep the input out of current limit, thereby keeping the system voltage above VSYS-MIN (VSYS-REG - 100mV, typ). If this loop reduces battery current to 0 and the system is in need of more current than the input can provide, then the Smart Power Selector overrides the minimum system voltage regulation loop and allows SYS to collapse to BATT for the battery to provide supplement current to the system. The Smart Power Selector automatically reenables the minimum system voltage loop when the supplement event has ended. A maskable interrupt (INT_CHG.SYS_CTRL_I) asserts to signal a change in STAT_CHG_A.VSYS_MIN_STAT. This status bit asserts when the minimum system voltage regulation loop is active. Die Temperature Regulation If the die temperature exceeds TJ-REG (programmed by CNFG_CHG_D.TJ_REG[2:0]) the charger attempts to limit the temperature increase by reducing the battery charge current. The STAT_CHG_A.TJ_REG_STAT bit asserts whenever charge current is reduced due to this loop. The charger's current sourcing capability to SYS remains unaffected when STAT_CHG_A.TJ_REG_STAT is high. A maskable interrupt (INT_CHG.TJ_REG_I) asserts to signal a change in STAT_CHG_A.TJ_REG_STAT. Use the INT_CHG.TJ_REG_I interrupt to signal the system processor to reduce loads on SYS to reduce total system temperature. Charger State Machine The battery charger follows a strict state-to-state progression to ensure that a battery is charged safely. The status bitfield STAT_CHG_B.CHG_DTLS[3:0] reflects the charger's current operational state. A maskable interrupt (INT_CHG.CHG_I) is available to signal a change in STAT_CHG_B.CHG_DTLS[3:0]. www.analog.com Analog Devices | 59 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ CHGIN INVALID (CHGIN_DTLS[1:0] = 0b00 or 0b01) OR CHARGER DISABLED (CHG_EN = 0) ANY STATE ETHRM = 1 AND CHG_EN = 1 AND (TBATT > THOT OR TBATT < TCOLD) CHGIN INSERTED (CHGIN_DTLS[1:0] = 0b10) CHARGER OFF CHG_DTLS[3:0] = 0b0000 CHG = 0 RETURNS TO SAME STATE WHEN: ETHRM = 0 OR (TBATT < THOT AND TBATT > TCOLD) DEBOUNCE CHG_DTLS[3:0] = 0b0000 CHG = 0 CHGIN DEBOUNCED TIME ELAPSED ≥ tCHGIN-DB (CHGIN_DTLS[1:0] = 0b11) TIME ELAPSED < tCHGIN-DB CHARGER ENABLED (CHG_EN = 1) AND CHGIN DEBOUNCED AND VALID (CHGIN_DTLS[1:0] = 0b11) AND BATTERY TEMPERATURE FAULT CHG_DTLS[3:0] = 0b1100 CHG = 0 ( VBATT < VFAST-CHG – VRESTART OR (CHR_TH_EN = 0b1) PREQUALIFICATION CHG_DTLS[3:0] = 0b0001 CHG = 1 IBATT = IPQ TIME ELAPSED > tPQ Don’t care if VBATT < VFAST-CHG – VRESTART (CHR_TH_EN = 0b0) ) PREQUALIFICATION TIMER FAULT CHG_DTLS[3:0] = 0b1010 CHG = 0 VBATT < VPQ – 100mV VBATT < VPQ – 100mV JEITA-MODIFIED FAST FAST-CHARGE -CHARGE (CC) CHG_DTLS[3:0] = 0b0011 CHG = 1 IBATT = IFAST-CHG_JEITA** VBATT < VBATT = VFAST-CHG_JEITA JEITA-MODIFIED FAST FAST-CHARGE -CHARGE (CV) CHG_DTLS[3:0] = 0b0101 CHG = 1 VBATT = VFAST-CHG_JEITA IBATT > ITERM ETHRM = 0 OR (TBATT < TWARM AND TBATT > TCOOL) ETHRM = 0 OR (TBATT < TWARM AND TBATT > TCOOL) IBATT < ITERM JEITA-MODIFIED TOP TOP-OFF -OFF CHG_DTLS[3:0] = 0b0111 CHG = 1 VBATT = VFAST-CHG_JEITA ETHRM = 0 OR (TBATT < TWARM AND TBATT > TCOOL) TIME ELAPSED > tTO JEITA-MODIFIED DONE CHG_DTLS[3:0] = 0b1001 CHG = 0 ETHRM = 0 OR (TBATT < TWARM AND TBATT > TCOOL) TIME ELAPSED* > tFC VBATT = VFAST-CHG FAST-CHARGE (CV) CHG_DTLS[3:0] = 0b0100 CHG = 1 VBATT = VFAST-CHG IBATT > ITERM ETHRM = 1 AND (TBATT > TWARM OR TBATT < TCOOL) ANY FAST-CHARGE OR JEITA JEITA-MODIFIED -MODIFIED FAST-CHARGE STATE CHG_DTLS[3:0] = 0b0010-0b0101 CHG = 1 FAST-CHARGE (CC) CHG_DTLS[3:0] = 0b0010 CHG = 1 IBATT = IFAST-CHG** VBATT < VFAST-CHG ETHRM = 1 AND (TBATT > TWARM OR TBATT < TCOOL) VBATT > VPQ IBATT < ITERM TOP-OFF CHG_DTLS[3:0] = 0b0110 CHG = 1 VBATT = VFAST-CHG TIME ELAPSED > tTO DONE CHG_DTLS[3:0] = 0b1000 CHG = 0 VBATT < VFAST-CHG – 150mV VBATT < VFAST-CHG_JEITA – 150mV VFAST-CHG_JEITA ETHRM = 1 AND (TBATT > TWARM OR TBATT < TCOOL) FAST-CHARGE TIMER FAULT CHG_DTLS[3:0] = 0b1011 CHG = 0 *TIME ELAPSED IS AGGREGATED THROUGHOUT THE FAST-CHARGE AND JEITA-MODIFIED FASTCHARGE STATES. ALL FASTCHARGE STATES (REGARDLESS OF JEITA STATUS) SHARE THE SAME SAFETY TIMER. **IFAST-CHG CAN BE REDUCED BY THE MINIMUM INPUT VOLTAGE REGULATION LOOP, THE MINIMUM SYSTEM VOLTAGE REGULATION LOOP, OR THE DIE TEMPERATURE REGULATION LOOP. Figure 16. Charger State Machine Charger-Off State The charger is off when CHGIN is invalid, the charger is disabled, or the battery is fresh. CHGIN is invalid when the CHGIN input is invalid (VCHGIN < VCHGIN_UVLO or VCHGIN > VCHGIN_OVP). While CHGIN is invalid, the battery is connected to the system. CHGIN voltage quality can be separately monitored by the STAT_CHG_B.CHGIN_DTLS[1:0] status bitfield. See the Register Map section for details. The charger is disabled when the charger enable bit is 0 (CNFG_CHG_B.CHG_EN = 0). The battery is connected or disconnected to the system depending on the validity of VCHGIN while CNFG_CHG_B.CHG_EN = 0. See the Smart Power Selector section. www.analog.com Analog Devices | 60 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ When the charger restart threshold is enabled (CNFG_CHG_H.CHR_TH_EN = 1, by default), the battery is fresh when the battery is not lower than VFAST-CHG by VRESTART (VBATT > VFAST-CHG - VRESTART). The battery is disconnected from the system and not charged while the battery is fresh. The charger state machine exits this state and begins charging when the battery becomes lower than VFAST-CHG - VRESTART (VRESTART = 150mV, typ). This condition is functionally similar to done state. See the Done State section. The charger restart threshold can be disabled with I2C command by writing CNFG_CHG_H.CHR_TH_EN to 0. When the charger restart threshold is disabled, the battery voltage should be closely monitored by the a micro-controller to avoid unwanted restarted charging event. Note that the charger restart threshold can only be disabled for the transition from charger-off state to prequalification state. Prequalification State The prequalification state is intended to assess a low-voltage battery's health by charging at a reduced rate. If the battery voltage is less than the VPQ threshold, the charger is automatically in prequalification. If the cell voltage does not exceed VPQ in 30 minutes (tPQ), the charger faults. The prequalification charge rate is a percentage of IFAST-CHG and is programmable with CNFG_CHG_B.I_PQ. The prequalification voltage threshold (VPQ) is programmable through CNFG_CHG_C.CHG_PQ[2:0]. Fast-Charge States When the battery voltage is above VPQ, the charger transitions to the fast-charge (CC) state. In this state, the charger delivers a constant current (IFAST-CHG) to the cell. The constant current level is programmable from 7.5mA to 300mA by CNFG_CHG_E.CHG_CC[5:0]. When the cell voltage reaches VFAST-CHG, the charger state machine transitions to fast-charge (CV). VFAST-CHG is programmable with CNFG_CHG_G.CHG_CV[5:0] from 3.6V to 4.6V. The charger holds the battery's voltage constant at VFAST-CHG while in the fast-charge (CV) state. As the battery approaches full, the current accepted by the battery reduces. When the charger detects that the battery charge current has fallen below ITERM, the charger state machine enters the top-off state. A fast-charge safety timer starts when the state machine enters fast-charge (CC) or JEITA-modified fast-charge (CC) from a non-fast-charge state. The timer continues to run through all fast-charge states regardless of JEITA status. The timer length (tFC) is programmable from 3 hours to 7 hours in 2 hour increments with CNFG_CHG_E.T_FAST_CHG[1:0]. If it is desired to charge without a safety timer, program CNFG_CHG_E.T_FAST_CHG[1:0] with 0b00 to disable the feature. If the timer expires before the fast-charge states are exited, the charger faults. See the Fast-Charge Timer Fault State section for more information. If the charge current falls below 20% of the programmed value during fast-charge (CC), the safety timer pauses. The timer also pauses for the duration of supplement mode and battery temperature fault events. The STAT_CHG_B.TIME_SUS bit indicates the status of the fast-charge safety timer. See the Register Map section for more details. Top-Off State Top-off state is entered when the battery charge current falls below ITERM during the fast-charge (CV) state. ITERM is a percentage of IFAST-CHG and is programmable through CNFG_CHG_C.I_TERM[1:0]. While in the top-off state, the battery charger continues to hold the battery's voltage at VFAST-CHG. A programmable top-off timer starts when the charger state machine enters the top-off state. When the timer expires, the charger enters the done state. The top-off timer value (tTO) is programmable from 0 minutes to 35 minutes with CNFG_CHG_C.T_TOPOFF[2:0]. If it is desired to stop charging as soon as battery current falls below ITERM, program tTO to 0 minutes. Done State The charger enters the done state when the top-off timer expires. The battery remains disconnected from the system during done. The charger restarts if the battery voltage falls more than VRESTART (150mV, typ) below the programmed VFAST-CHG value. Status of CNFG_CHG_H.CHR_TH_EN does not affect the threshold to transition from done state to fast-charge CC state. www.analog.com Analog Devices | 61 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ Prequalification Timer Fault State The prequalification timer fault state is entered when the battery's voltage fails to rise above VPQ in tTO (30 minutes, typ) from when the prequalification state was first entered. If a battery is too deeply discharged, damaged, or internally shorted, the prequalification timer fault state can occur. During the timer fault state, the charger stops delivering current to the battery and the battery remains disconnected from the system. To exit the prequalification timer fault state, toggle the charger enable (CNFG_CHG_B.CHG_EN) bit or unplug and replug the external voltage source connected to CHGIN. Fast-Charge Timer Fault State The charger enters the fast-charge timer fault state if the fast-charge safety timer expires. While in this state, the charger stops delivering current to the battery and the battery remains disconnected from the system. To exit the fast-charge timer fault state, toggle the charger enable bit (CNFG_CHG_B.CHG_EN) or unplug and replug the external voltage source connected to CHGIN. Battery Temperature Fault State If the thermistor monitoring circuit of the fuel gauge reports that the battery is either too hot or too cold to charge (as programmed by CNFG_CHG_A.THM_HOT[1:0] and CNFG_CHG_A.THM_COLD[1:0]), the state machine enters the battery temperature fault state. While in this state, the charger stops delivering current to the battery and the battery remains disconnected from the system. This state can only be entered if the thermistor is enabled (Config.ETHRM = 1). Battery temperature fault state has priority over any other fault state, and can be exited when the thermistor is disabled (Config.ETHRM = 0) or when the battery returns to an acceptable temperature. When this fault state is exited, the state machine returns to the last state it was in before battery temperature fault state was entered. All active charger timers (fast-charge safety timer, prequalification timer, or top-off timer) are paused in this state. When the charger exits this state, the prequalification timer resumes while the fast-charge safety and top-off timers reset. The STAT_CHG_A.THM_DTLS[2:0] bitfield reports battery temperature status. See the Adjustable Thermistor Temperature Monitors and the Register Map sections for more information. JEITA-Modified States If the thermistor is enabled (Config.ETHRM = 1), then the charger state machine is allowed to enter the JEITA-modified states. These states are entered if the charger's temperature monitors indicate that the battery temperature is either warm (greater than TWARM) or cool (less than TCOOL). See the Adjustable Thermistor Temperature Monitors section for more information about setting the temperature thresholds. The charger's current and voltage parameters change from IFAST-CHG and VFAST-CHG to IFAST-CHG_JEITA and VFASTCHG_JEITA while in the JEITA-modified states. The JEITA modified parameters can be independently set to lower voltage and current values so that the battery can charge safely over a wide range of ambient temperatures. If the battery temperature returns to normal, or the thermistor is disabled (Config.ETHRM = 0), the charger exits the JEITA-modified states. www.analog.com Analog Devices | 62 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ Typical Charge Profile A typical battery charge profile (and state progression) is illustrated in Figure 17. (V) 5 (mA) CHGIN 500 SYS VSYS-REG = 4.5V 4 VFAST-CHG = 4.25V 400 BATT IFAST-CHG = 300mA 3 300 VPQ = 2.3V IBATT 2 200 1 100 IPQ = 30mA FAST-CHARGE (CC) ITERM = 30mA FAST-CHARGE (CV) tTO TOP-OFF DONE CHGIN INVALID (TIME) PREQUALIFICATION Figure 17. Example Battery Charge Profile Charger Applications Information Configuring a Valid System Voltage The Smart Power Selector begins to regulate SYS to VSYS-REG when CHGIN is connected to a valid source and debounced. To ensure the charger's accuracy specified in the Electrical Characteristics table, the system voltage must always be programmed at least 200mV above the charger's constant-voltage level (VFAST-CHG). If this condition is not met, then the charger's internal configuration logic forces VFAST-CHG to reduce to satisfy the 200mV requirement by default (CNFG_CHG_H.SYS_BAT_PRT = 1). If this happens, the charger asserts the INT_CHG.SYS_CNFG_I interrupt to alert the user that a configuration error has been made and that the bits in CNFG_CHG_G.CHG_CV[5:0] have changed to reduce VFAST-CHG. The 200mV clamp between VSYS-REG and VFAST-CHG can be disabled by clearing the CNFG_CHG_H.SYS_BAT_PRT bit. If this bit is cleared, the software has to provide the protection to guarantee the overall performance of the charger. CHGIN/SYS/BATT Capacitor Selection Bypass CHGIN to GND with a 4.7μF ceramic capacitor to minimize inductive kick caused by long cables between the DC charge source and the product/IC. Larger values increase decoupling for the linear charger but increase inrush current from the DC charge source when the product/IC is first connected to a source through a cable/plug. If the DC charging source is an upstream USB device, limit the maximum CHGIN input capacitance based on the appropriate USB specification (typically no more than 10μF). www.analog.com Analog Devices | 63 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ Bypass SYS to GND with a 22μF ceramic capacitor. This capacitor ensures the stability of SYS while it is regulated from CHGIN. Larger values of SYS capacitance increase decoupling for all SYS loads. The effective value of the SYS capacitor must be greater than 4μF and no more than 100μF. Bypass BATT to GND with a 4.7μF ceramic capacitor. This capacitor stabilizes the BATT voltage regulation loop. The effective value of the BATT capacitor must be greater than 1μF. Ceramic capacitors with X5R or X7R dielectric are highly recommended due to their small size, low ESR, and small temperature coefficients. All ceramic capacitors derate with DC bias voltage (effective capacitance goes down as DC bias goes up). Generally, small case size capacitors derate heavily compared to larger case sizes (0603 case size performs better than 0402). Consider the effective capacitance value carefully by consulting the manufacturer's data sheet. Detailed Description—Adjustable Thermistor Temperature Monitors The optional use of a negative temperature coefficient (NTC) thermistor (thermally coupled to the battery) enables the charger to operate safely over the JEITA temperature range. When the thermistor is enabled (Config.ETHRM = 1), the charger continuously monitors the reading at the Temp register in order to sense the temperature of the battery being charged. See Figure 18 for a visual example of the following: ● If the battery temperature is higher than TCOOL and lower than TWARM, the battery charges normally with the normal values for VFAST-CHG and IFAST-CHG. The charger state machine does not enter JEITA-modified states while the battery temperature is normal. ● If the battery temperature is either above TWARM but below THOT, or, below TCOOL but above TCOLD, the battery charges with the JEITA-modified voltage and current values. These modified values, VFAST-CHG_JEITA and IFAST-CHG_JEITA, are programmable through CNFG_CHG_H.CHG_CV_JEITA[5:0] and CNFG_CHG_F.CHG_CC_JEITA[5:0], respectively. These values are independently programmable from the unmodified VFAST-CHG and IFAST-CHG values and can even be programmed to the same values if an automatic response to a warm or cool battery is not desired. The charger state machine enters JEITA-modified states while the battery temperature is outside of normal. ● If the battery temperature is either above THOT or below TCOLD, the charger follows the JEITA recommendation and pauses charging. The charger state machine enters battery temperature fault state while charging is paused due to unacceptably high or low temperatures. The battery's temperature status is reflected by the STAT_CHG_A.THM_DTLS[2:0] status bitfield. A maskable interrupt (INT_CHG.THM_I) signals a change in status. See the Register Map for more information. To completely disable the charger's automatic response to battery temperature, disable the feature by programming Config.ETHRM = 0. www.analog.com Analog Devices | 64 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ EXAMPLE TEMPERATURES FOR NTC β = 3380K THM_COLD[1:0] = 0b10 (0°C) THM_COOL[1:0] = 0b11 (15°C) THM_WARM[1:0] = 0b10 (45°C) THM_HOT[1:0] = 0b11 (60°C) BATT REGULATION VOLTAGE (V) 4.4V 4.3V VFAST-CHG = 4.2V (CHG_CV[5:0] = 0b011000) 4.2V VFAST-CHG_JEITA = 4.075V (CHG_CV_JEITA[5:0] = 0b010011) 4.1V COLD COOL NORMAL WARM HOT 4.0V -40°C -25°C 0° C 15°C TCOLD TCOOL 25°C 45°C 60°C TWARM THOT 75°C 85°C FAST-CHARGE CURRENT (A) BATTERY TEMPERATURE IFAST-CHG = 150mA (CHG_CC[5:0] = 0b010011) 0.15 IFAST-CHG_JEITA = 75mA (CHG_CC_JEITA[5:0] = 0b001001) 0.10 0.05 COLD COOL NORMAL WARM HOT 0 -40°C -25°C 0° C 15°C TCOLD TCOOL 25°C 45°C 60°C TWARM THOT 75°C 85°C BATTERY TEMPERATURE Figure 18. Safe-Charging Profile Example The JEITA temperature thresholds are independently programmable through CNFG_CHG_A.THM_HOT[1:0], CNFG_CHG_A.THM_WARM[1:0], CNFG_CHG_A.THM_COOL[1:0], and CNFG_CHG_A.THM_COLD[1:0]. Each threshold can be programmed to one of four voltage options spanning 15°C. See the Register Map for more information. Detailed Description—Analog Multiplexer An external ADC can be used to measure the chip's various signals for general functionality or on-the-fly power monitoring. The CNFG_CHG_I.MUX_SEL[3:0] bitfield controls the internal analog multiplexer responsible for connecting the proper channel to the AMUX pin. Each measurable signal is listed in Table 10 with its appropriate multiplexer channel. The voltage on the AMUX pin is a buffered output that ranges from 0V to VFS (1.25V, typ). The buffer has 50μA of quiescent current consumption and is only active when a channel is selected (CNFG_CHG_I.MUX_SEL[3:0] ≠ 0b0000). Disable the buffer by programming CNFG_CHG_I.MUX_SEL[3:0] to 0b0000 when not actively converting the voltage on AMUX. The AMUX output is high-impedance while CNFG_CHG_I.MUX_SEL[3:0] is 0b0000. Table 10 shows how to translate the voltage signal on the AMUX pin to the value of the parameter being measured. See the Electrical Characteristics table and the Register Map for more details. www.analog.com Analog Devices | 65 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ Table 10. AMUX Signal Transfer Functions TRANSFER FUNCTION FULL-SCALE SIGNAL MEANING (VAMUX = 1.25V) ZEROSCALE SIGNAL MEANING (VAMUX = 0V) 7.5V 0V 0.475A 0A 4.6V 0V 100% of IFAST-CHG 0% of IFAST-CHG SIGNAL MUX_SEL[3:0] CHGIN Pin Voltage 0b0001 VCHGIN = CHGIN Pin Current 0b0010 ICHGIN = BATT Pin Voltage 0b0011 VBATT = BATT Pin Charging Current 0b0100 IBATT(CHG) = BATT Pin Discharge Current 0b0101 BATT Pin Discharge Current NULL 0b0110 VNULL = VAMUX 1.25V 0V AGND Pin Voltage* 0b1001 VAGND = VAMUX 1.25V 0V SYS Pin Voltage 0b1010 4.8V 0V IBATT(DISCHG) = VAMUX GVCHGIN VAMUX GICHGIN VAMUX GVBATT VAMUX VFS × IFAST − CHG (VAMUX − VNULL) × I DISCHG − SCALE (VFS − VNULL) VSYS = VAMUX GVSYS (CHG_CC[5:0]) 100% of IDISCHG-SCALE (IMON_DISCHG_SCALE[3:0]) 0% of IDISCHGSCALE *AGND pin voltage is accessed through a 100Ω (typ) pulldown resistor. www.analog.com Analog Devices | 66 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ Measuring Battery Current Sampling current in the BATT pin is possible at any time or in any mode with an external ADC. For improved accuracy, the analog circuitry used for monitoring battery discharge current is different from the circuitry monitoring battery charge current. Table 11 outlines how to determine the direction of battery current. Table 11. Battery Current Direction Decode MEASUREMENT CHARGING OR DISCHARGING INDICATORS STAT_CHG_B.CHG STAT_CHG_B.CHG_DTLS[3:0] Don't care Don't care Discharging Battery Current (Positive Battery Terminal STAT_CHG_B.CHGIN_DTLS[1:0] 0b00 Sourcing Current) 0b01 0b10 Charging Battery Current (Positive Battery Terminal 1 0b0001 to 0b0111 0b11 Sinking Current) Method for Measuring Discharge Current 1. Program the multiplexer to switch to the discharge NULL measurement by changing CNFG_CHG_I.MUX_SEL[3:0] to 0b0110. A NULL conversion must always be performed first to cancel offsets. 2. Wait the appropriate channel switching time (0.3μs, typ). 3. Convert the voltage on the AMUX pin and store as VNULL. 4. Program the multiplexer to switch to the battery discharge current measurement by changing CNFG_CHG_I.MUX_SEL[3:0] to 0b0101. A nonnulling conversion should be done immediately after a NULL conversion. 5. Wait the appropriate channel switching time (0.3μs, typ). 6. Convert the voltage on the AMUX pin and use the following transfer function to determine the discharge current: IBATT(DISCHG) = (VAMUX − VNULL) × I DISCHG − SCALE (VFS − VNULL) VFS is 1.25V typical. IDISCHG-SCALE is programmable through CNFG_CHG_I.IMON_DISCHG_SCALE[3:0]. The default value is 300mA. If smaller currents are anticipated, then IDISCHG-SCALE can be reduced for improved measurement accuracy. www.analog.com Analog Devices | 67 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ Method for Measuring Charge Current 1. Program the multiplexer to switch to the charge current measurement by changing CNFG_CHG_I.MUX_SEL[3:0] to 0b0100. 2. Wait the appropriate channel switching time (0.3μs, typ). 3. Convert the voltage on the AMUX pin and use the following transfer function to determine charging current. IBATT(CHG) = VAMUX VFS × IFAST − CHG VFS is 1.25V typical. IFAST-CHG is the charger's fast-charge constant-current setting and is programmable through CNFG_CHG_E.CHG_CC[5:0]. Detailed Description—SIMO Buck-Boost The device has a micropower single-inductor, multiple-output (SIMO) buck-boost DC-to-DC converter designed for applications that emphasize low supply current and small solution size. A single inductor is used to regulate three separate outputs, saving board space while delivering better total system efficiency than equivalent power solutions using one buck and linear regulators. The buck-boost architecture utilizes the entire battery voltage range due to its ability to create output voltages that are above, below, or equal to the input voltage. Peak inductor current for each output is independently programmable to optimize the balance between efficiency, output ripple, EMI, PCB design, and load capability. To further boost efficiency, when the output voltage is always lower than the input, the individual channel of the SIMO buck-boost converter can be configured to be in buck-only mode. Similarly, each SIMO channel can be individually configured to be in boost-only mode if the output voltage is constantly higher than the input. The buck only and boostonly mode reduce switching losses with less switching operations compared to buck-boost mode, and thus, improves conversion efficiency. MAX77658 also allows each SIMO channel to be configured in automatic mode, which provides an automatic decision between buck/boost/buck-boost mode to optimize regulator efficiency based on the VIN/VOUT condition. SIMO Features and Benefits ● Three Output Channels ● Ideal for Low-Power Designs • SBB0/1 Delivers up to 500mA at 1.8V from a 3.7V Input • SBB2 Delivers up to 750mA at 1.8V from a 3.7V Input ● Small Solution Size • Multiple Outputs from a Single 1.5μH Inductor • Small 10μF (0402) Output Capacitors ● Flexible and Easy to Use • Glitchless Transitions Between Buck, Boost, and Buck-Boost Modes • Programmable Peak Inductor Current • Programmable On-Chip Active Discharge • Programmable Operating Modes (Buck Only, Boost Only, Buck-Boost Only, Automatic Mode) • Automatic Low Power Mode to Normal-Power Mode Transition ● Long Battery Life • > 91% Peak Efficiency at 1.8V Output in Buck-Only Mode • > 93% Peak Efficiency at 5.0V Output in Boost-Only Mode • Better Total System Efficient than one switching regulator + LDOs • Low Quiescent Current, 1μA per Output • Low Input Operating Voltage, 2.7V (MIN) • Wide Output Voltage Range (0.5V - 5.5V) www.analog.com Analog Devices | 68 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ SIMO Detailed Block Diagram 10nF (0201) 1.5µH (0806) LXA LXB BST IN_SBB 10µF (0402) SYNCHRONOUS RECTIFIER MAIN POWER STAGE IN_SBB SYS REVERSE BLOCKING ILIM PGND SBB0 M1 BST DRV_SBB M3_0 IZX DRV_SBB CHG DIS M2 ERROR COMPARATOR ACTIVE-DISCHARGE SIMO CONTROLLER CHG DIS DIS_SBB[2:0] REG1 AD_SBB1 RAD_SSB0 (140Ω) SYNCHRONOUS RECTIFIER (M3_1) AND ERROR COMPARATOR AND ACTIVE-DISCHARGE SBB1 BST DRV_SBB DIS_SBB1 22µF (0603) / VREF VIREF DIS_SBB1 REG0 M4 AD_SBB0 I.LIM I.ZX REG[2:0] 22µF (0603) COMM FPS SYS_RST DIGITAL AND REGISTERS CNFG_SBB_TOP, CNFG_SBBX_A, CNFG_SBBX_B DRV_SBB AD_SBB[2:0] REG2 AD_SBB2 SYNCHRONOUS RECTIFIER (M3_2) AND ERROR COMPARATOR AND ACTIVE-DISCHARGE SBB2 BST DRV_SBB DIS_SBB2 22µF (0603) Figure 19. SIMO Detailed Block Diagram SIMO Control Scheme The SIMO buck-boost is designed to service multiple outputs simultaneously. A proprietary controller ensures that all outputs get serviced in a timely manner, even while multiple outputs are contending for the energy stored in the inductor. When no regulator needs service, the state machine rests in a low-power rest state. In buck-boost mode, when the controller determines that a regulator requires service, it charges the inductor (M1 + M4) until the peak current limit is reached (ILIM = CNFG_SBBx_B.IP_SBB[1:0]). The inductor energy then discharges (M2 + M3_x) into the output until the current reaches zero (IZX). In the event that multiple output channels need servicing at the same time, the controller ensures that no output utilizes all of the switching cycles. Instead, cycles interleave between all the outputs that are demanding service, while outputs that do not need service are skipped. When the load current for any output is very light, that output automatically switches to an ultra-low-power mode (ULPM) to reduce the quiescent current consumption. Figure 20 shows a typical waveform during the ULPM and normal mode. While operating in ULPM, the output voltage is biased 1.7% higher than normal mode by design so that future large load transients can be handled without excessive undershoot. www.analog.com Analog Devices | 69 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ VOUT NOT DRAWN TO SCALE SIMO AUTOMATIC LOW-POWER MODE; LIGHT LOADS VOUT TARGET + 1.7% MEDIUM, HEAVY LOADS 24µs 7.5µs VOUT TARGET LOAD DEPENDENT TIME Figure 20. ULPM and Normal Mode Waveforms Drive Strength The SIMO regulator's drive strength for its internal power MOSFETs is adjustable using the CNFG_SBB_TOP.DRV_SBB[1:0] bit field. The ideal value is determined experimentally for each application. Faster settings such as DRV_SBB[1:0] = 0b00 result in higher efficiency but generally require stricter PCB layout rules (comparable to the MAX77658 EV kit) or shielding to avoid additional EMI. Slower settings limit EMI in non-ideal settings (e.g., contained layout, antennae adjacent to the device, etc.). Change the drive strength only once during system initialization. SIMO Fault Indicator The IC has an SBBx fault shutdown option to protect itself when an SBBx fault is detected. If this option is enabled then the regulators power down sequentially after an SBBx fault. An SBBx fault occurs when the output voltage falls below 80% of regulation target. The corresponding SBBx_F bit remains high until the output voltage rises above 85% of regulation target. SIMO Output Voltage Configuration Each of the SIMO outputs are independently configurable. To set the output voltages at SBB0/1/2 for the MAX77658, use the I2C interface to load the configuration registers TV_SBBx[7:0]. This 8-bit configuration is a linear transfer function that starts at 0.5V, ends at 5.5V, with 25mV increments and sets the output voltage as: VSBBx = 0.5V + 25mV x TV_SBBx[7:0] (decimal) Peak Current Configuration The peak inductor current limit corresponding to each SIMO output are independently configurable. To set the inductor peak current for the MAX77658, use the I2C interface to load the configuration registers IP_SBBx[1:0]. SIMO Soft-Start The soft-start feature of the SIMO limits inrush current during startup. The soft-start feature is achieved by limiting the slew rate of the output voltage during startup (dV/dtSS). More output capacitance results in higher input current surges during startup. The following set of equations and example describes the input current surge phenomenon during startup. www.analog.com Analog Devices | 70 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ In buck-boost mode, the current into the output capacitor (ICSBB) during soft-start is: dV ICSBB = CSBB dt SS ( Equation1 ) where: ● CSBB is the capacitance on the output of the regulator ● dV/dtSS is the voltage change rate of the output The input current (IIN) during soft-start is: IIN = (ICSBB + ILOAD) ξ VSBBx VIN ( ) Equation2 where: ● ● ● ● ● ICSBB is from the calculation above ILOAD is current consumed from the external load VSBBx is the output voltage VIN is the input voltage ξ is the efficiency of the regulator For example, given the following conditions, the peak input current (IIN) during soft-start is ~71mA: Given: ● ● ● ● ● ● ● VIN is 3.5V SBB0 and SBB1 are disabled VSBB2 is 3.3V CSBB2 = 10µF dV/dtSS = 5mV/µs Load2 = 10mA ξ is 80% Calculation: ● ICSBB = 10µF x 5mV/µs (from Equation 1) ● ICSBB = 50mA 3.3V ● IIN = (50mA + 10mA) 3.5V 0.80 (from Equation1) ● IIN ~ 71mA SIMO Registers Each SIMO buck-boost channel has registers to program its target output voltage (CNFG_SBBx_A.TV_SBBx[7:0]) and its peak current limit (CNFG_SBBx_B.IP_SBBx[1:0]). Additional controls are available for enabling/disabling the active-discharge resistors (CNFG_SBBx_B.ADE_SBBx), operatation mode (CNFG_SBBx_B.OP_MODE[1:0]), as well as enabling/disabling the SIMO buck-boost channels (CNFG_SBBx_B.EN_SBBx[2:0]). For a full description of bits, registers, default values, and reset conditions, see the Register Map. SIMO Active Discharge Resistance Each SIMO buck-boost channel has an active-discharge resistor (RAD_SBBx) that is automatically enabled/disabled based on a CNFG_SBBx_B.ADE_SBBx bit and the status of the SIMO regulator. The active discharge feature may be enabled (CNFG_SBBx_B.ADE_SBBx = 1) or disabled (CNFG_SBBx_B.ADE_SBBx = 0) independently for each SIMO channel. Enabling the active discharge feature helps ensure a complete and timely power down of all system peripherals. If the active-discharge resistor is enabled by default, then the active-discharge resistor is on whenever VSYS is below VSYSUVLO and above VPOR. www.analog.com Analog Devices | 71 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ These resistors discharge the output when CNFG_SBBx_B.ADE_SBBx = 1, and their respective SIMO channel is off. If the regulator is forced on through CNFG_SBBx_B.EN_SBBx[2:0] = 0b110 or 0b111, then the resistors do not discharge the output even if the regulator is disabled by the main-bias. Note that when VSYS is less than 1.0V, the NMOS transistors that control the active-discharge resistors lose their gate drive and become open. SIMO Buck-Only and Boost-Only Mode If the input voltage at IN_SBB never falls below the target output voltage of one or more SIMO converter channels, the individual channels can be configured to be in buck mode with the bitfield CNFG_SBBx_B.OP_MODE[1:0]. In buck mode, when the buck-mode channel needs service, switch M3_x remains closed and M4 remains open (see Figure 19) when SBBx is being serviced. Only M1 and M2 are toggled as in a traditional buck converter for the switching cycle. Similarly, if the input voltage at IN_SBB never rises above the target output voltage of one or more SIMO converter channels, individual channels can be configured to be in boost mode with CNFG_SBBx_B.OP_MODE[1:0]. In boost mode, when the boost-mode channel needs service, switch M1 remains closed and M2 remains open (see Figure 19). Only M3x and M4 are toggled as in a traditional boost converter. Efficiency is boosted in these two modes compared to buck-boost mode due to three major factors: ● Reduced switching loss for each switching cycle: buck mode and boost mode toggles only two switches versus the four in buck-boost mode. Therefore, there are less switching events in a switching cycle. ● Lower inductor core losses for each switching cycle: Inductor current changes from 0A to peak current during a switching cycle. The larger the change in current the inductor experiences, the more energy is lost in the inductor core in the form of heat. In buck mode and boost mode, the peak current can be reduced since less average inductor current is needed to support a load. Less inductor current is needed because of direct energy transfer. Direct energy transfer occurs the input (IN_SBB) is connected directly to the output (SBBx) through the inductor. Therefore, the input not only provides energy to charge the inductor, energy is also supplied to the output capacitor and load devices. Thus, less current is needed to charge the inductor to provide sufficient load to the output. ● Less frequent switching cycles with the same peak current limit setting: With the same peak current limit, because of direct energy transfer during the converter operation, more energy gets delivered in each switching cycle with buckonly and boost-only mode than that with buck-boost mode. Maintain a minimum headroom of 0.7V between IN_SBB and SBBx in buck mode because inductor charge time (dt = L x IP_SBBx/(VIN_SBB - VSBBx)) increases as the difference between the IN_SBB and SBBx voltages shrink. As the inductor current takes longer to reach the peak current limit, the MAX77658 can trigger a fault flag. Likewise, it is recommended to keep SBBx at least 0.7V higher than IN_SBB to force the rail into boost-only mode so that the inductor current does not take too long to reach zero. Applications Information SIMO Available Output Current The available output current on a given SIMO channel is a function of the input voltage, output voltage, the peak current limit setting, and the output current of the other SIMO channels. Maxim offers the SIMO Calculator that outlines the available capacity for specific conditions. Table 12 is an extraction from the calculator. Table 12. SIMO Available Output Current for Common Applications PARAMETERS EXAMPLE 1 EXAMPLE 2 EXAMPLE 3 EXAMPLE 4 VIN_SBB 3.7V 3.7V 3.2V 3.4V RL_DCR 90mΩ 90mΩ 90mΩ 120mΩ SBB0 1.0V at 100mA 1.0V at 80mA 1.2V at 50mA 1.2V at 20mA SBB1 1.2V at 75mA 1.2V at 50mA 1.8V at 100mA 1.8V at 80mA SBB2 1.8V at 50mA 1.8V at 40mA 3.3V at 30mA 3.3V at 10mA Operating Mode Automatic Automatic Automatic Automatic IP_SBB0 0.50A 0.50A 0.50A 0.50A www.analog.com Analog Devices | 72 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ Table 12. SIMO Available Output Current for Common Applications (continued) IP_SBB1 0.75A 0.50A 0.50A 0.50A IP_SBB2 0.50A 0.50A 0.75A 0.50A Utilized Capacity 81% 69% 75% 49% *ESRC_IN = ESRC_OUT = 5mΩ, L = 1.5μH Inductor Selection Choose an inductance from 1.0μH to 2.2μH; 1.5μH inductors work best for most designs. Larger inductance transfers more energy to the output for each cycle and typically results in lower switching frequency, thus, better efficiency but larger output voltage ripple. See the Output Capacitor Selection section for more information on how to size your output capacitor to control ripple. Choose the inductor saturation current to be greater than or equal to the maximum peak current limit setting that is used for all of the SIMO buck-boost channels (IP_SBBx). For example, if SBB0 is set for 0.5A, SBB1 is set for 0.75A, and SBB2 is set for 1.0A, then choose the saturation current to be greater than or equal to 1.0A. Choose the RMS current rating of the inductor (typically the current at which the temperature rises appreciably) based on the expected load requirement of the system. For systems where the expected load conditions are not well known, be conservative and choose the RMS current to be greater than or equal to half the higher maximum peak current limit setting [IRMS ≥ MAX(IP_SBB0, IP_SBB1, IP_SBB2)/2]. This is a conservative choice because the SIMO buck-boost regulator implements a discontinuous conduction mode (DCM) control scheme, which returns the inductor current to zero at the end of each cycle. Consider the DC-resistance (DCR), AC-resistance (ACR), and package size of the inductor. Typically, smaller-sized inductors have larger DC-resistance and larger AC-resistance that reduces efficiency and the total output power. Note that many inductor manufacturers have inductor families which contain different versions of core material to balance trade-offs between DCR, ACR (i.e., core losses), and component cost. For this SIMO regulator, inductors with the lowest ACR in the 1.0MHz to 2.0MHz region tend to provide the best efficiency. Input Capacitor Selection Choose the input bypass capacitance (CIN_SBB) to be 22µF. Larger values of CIN_SBB improve the decoupling for the SIMO regulator. CIN_SBB reduces the current peaks drawn from the battery or input power source during SIMO regulator operation and reduces switching noise in the system. The ESR/ESL of the input capacitor should be very low (i.e., ESR ≤ 5mΩ and ESL ≤ 500pH) for frequencies up to 2MHz. Ceramic capacitors with X5R or X7R dielectric are highly recommended due to their small size, low ESR, and small temperature coefficients. To fully utilize the available input voltage range of the SIMO (5.5V, max), use a capacitor with a voltage rating of 6.3V at minimum. Boost Capacitor Selection Choose the boost capacitance (CBST) to be 10nF. Smaller values of CBST result in insufficient gate drive for M3. Larger values of CBST have the potential to degrade the startup performance. Ceramic capacitors with 0201 or 0402 case sizes are recommended. www.analog.com Analog Devices | 73 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ Output Capacitor Selection Choose each output bypass capacitance (CSBBx) based on the target output voltage ripple (∆VSBBx): typical values are 22μF. Larger values of CSBBx improve the output voltage ripple but increase the input surge currents during soft-start and output voltage changes. The output voltage ripple is a function of the inductance (L), the output voltage (VSBBx), and the peak current limit setting (IP_SBBx). See Equation 3 to estimate required effective capacitance. 2×L I CSBBx = P_SBBx 2 × VSBBx × ∆ VSBBx(Equation3) The SIMO Calculator can be used to aid in the selection of the output capacitance. Note that most designs concern themselves with having enough capacitance on the output but there is also a maximum capacitance limitation that is calculated within the SIMO calculator; take care not to exceed the maximum capacitance. CSBBx is required to keep the output voltage ripple small. The impedance of the output capacitors (ESR, ESL) should be very low (i.e., ESR ≤ 5mΩ and ESL ≤ 500pH) for frequencies up to 2MHz. Ceramic capacitors with X5R or X7R dielectric are highly recommended due to their small size, low ESR, and small temperature coefficients. A capacitor's effective capacitance decreases with increased DC bias voltage. This effect is more pronounced as capacitor case sizes decrease. Due to this characteristic, it is possible for an 0603 case size capacitor to perform well, while an 0402 case size capacitor of the same value performs poorly. The SIMO regulator is stable with low output capacitance (1μF) but the output voltage ripple would be large; consider the effective output capacitance value after initial tolerance, bias voltage, aging, and temperature derating. Example Component Selection Pick input/output capacitors and the inductor for the given requirements: ● VIN_SBB, typical = 3.7V Table 13. Design Requirements SBB0 SBB1 SBB2 Output Voltage 3.3V 1.8V 1.2V Maximum Load Current 50mA 60mA 80mA Maximum Voltage Ripple 50mV 30mV 30mV Inductor, Peak Current Limit, and Input Capacitor For the best efficiency, a 1.5μH inductor is chosen. For this example, assume the DFE201610E-1R5M inductor from Murata is used. This particular inductor has 91mΩ of DCR. Since the load current is low, first choose the inductor current peak to be 0.333A for all outputs. Next, enter these values into Maxim's SIMO calculator as mentioned previously. www.analog.com Analog Devices | 74 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ Figure 21. Component Selection—High Utilization As shown in Figure 21, the utilization is over 100%, which leads to high output voltage ripple. To lower utilization, increase the inductor peak current limits. For this example, 1A is used for SBB0 and 0.5A for SBB1 and SBB2. Figure 22 shows the utilization of less than 80%. Using 0.5A for the inductor peak current limit has the added benefit of increased efficiency. www.analog.com Analog Devices | 75 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ Figure 22. Component Selection—Final Current Peak Limits To support the selected peak currents, choose 22μF for the input capacitor. Output Capacitors Using Equation 3 and the selected inductor current peak limits, the minimum output capacitances required are: IP_SBB02xL 12x2.2x10 − 6 A2xH = 6.67μF V2 IP_SBB12xL 0.52x2.2x10 − 6 A2xH = 5.09μF 2x1.8x0.03 V2 IP_SBB22xL 0.52x2.2x10 − 6 A2xH = 7.64μF 2x1.2x0.03 V2 CSBB0_min = 2xV = 2x3.3x0.05 SBB0x ∆ VSBB0 CSBB1_min = 2xV = SBB1x ∆ VSBB1 CSBB2_min = 2xV = SBB2x ∆ VSBB2 For this example, the 22μF GRM188R61A226ME15 is chosen for all three outputs. The effective capacitance after derating is the following: CSBB0 = 8.113μF CSBB1 = 13.828μF CSBB2 = 16.793μF Go back to the calculator and enter the capacitance for each channel. Figure 23 shows the expected ripples, which fit the requirements. www.analog.com Analog Devices | 76 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ Figure 23. Component Selection—Expected Ripple Summary ● L = 2.2μH ● CIN_SBB = 22μF ● Total Switching Utilization = 79% Table 14. Summary of Design for Component Selection Example IP_SBBx CSBBx (nominal) ∆VSBBx SBB0 SBB1 SBB2 1A 0.5A 0.5A 22μF 22μF 22μF 35.2mV 17.9mV 14.7mV Real applications should also consider the minimum input voltage since the battery discharges. The following is a www.analog.com Analog Devices | 77 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ summary using the same components but an input voltage of 3.0V instead. The switching utilization increased to 82.4%, above the recommended 80% but still acceptable. ● L = 2.2μH ● CIN_SBB = 22μF ● Total Switching Utilization = 82.4% Table 15. Summary of Design with Lower Input Voltage IP_SBBx CSBBx (nominal) ∆VSBBx SBB0 SBB1 SBB2 1A 0.5A 0.5A 22μF 22μF 22μF 13.0mV 14.9mV 13.0mV SIMO Switching Frequency The SIMO buck-boost regulator uses a pulse frequency modulation (PFM) control scheme. The switching frequency for each output is a function of the operating mode, inductor peak current limit, input voltage, output voltage, load current, and inductance. Output capacitance is a minor factor in SIMO switching frequency. The SIMO Calculator can be used to estimate expected switching frequency. At no load, switching frequencies can be as low as 10Hz. For the 3.7V input to 1.2V output channel from the Example Component Selection section, the switching frequency is about 327kHz. Table 16 lists how different factors increase or decrease switching frequency. Table 16. Switching Frequency Control FACTOR INCREASING FREQUENCY DECREASING FREQUENCY Inductor Current Peak Limit Lower Peak Limit Higher Peak Limit Operating Mode Buck-Boost Mode Buck Mode/Boost Mode Inductor Decrease Inductance Increase Inductance Input Voltage Higher Voltage Lower Voltage Output Voltage Higher Voltage Lower Voltage Load Current Higher Current Lower Current Unused Outputs Do not leave unused outputs unconnected. If an output left unconnected is accidentally enabled, the charged inductor experiences an open circuit, and the output voltage soars above the absolute maximum rating, damaging the device. If an output is not used, do one of the following: 1. Disable the output (CNFG_SBBx_B.EN_SBBx[2:0] = 0x4 or 0x5) and connect the output to ground. If an unused output is default enabled or can be accidentally enabled, do one of the following recommendations instead. 2. Bypass the unused output with a 1μF capacitor to ground. 3. Connect the unused output to IN_SBB or a different output channel if the unused output is programmed to a lower voltage. Since the output voltage is higher than the unused output, the regulator does not service the unused output even if it is unintentionally enabled. • Note that some OTP options have the active-discharge resistors enabled by default. Connecting an unused output to IN_SBB is not recommended if the active discharge is enabled by default. If connecting the unused output to a different channel, disable the active-discharge resistor (CNFG_SBBx_B.ADE_SBBx = 0) of the unused channel. www.analog.com Analog Devices | 78 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ PCB Layout Guide Figure 24 shows an example layout of the top layer. TH CREG CBATT CCHGIN CSYS GPIO2 GPIO1 GPIO0 VIO SDA SCL CVL CIN_SBB CLDO1 CLDO0 CBST CSBB0 CIN_LDO CSBB1 CSBB2 nIRQ LSBB nRST AMUX nEN Figure 24. PCB Top-Layer and Component Placement Example Capacitors Place decoupling capacitors as close as possible to the IC such that connections from capacitor pads to pin and from capacitor pads to ground pins are short. Keeping the connections short lowers parasitic inductance and resistance, improving performance and shrinking the physical size of hot loops. If connections to the capacitors are through vias, use multiple vias to minimize parasitics. Also, connect loads to the capacitor pads rather than the device pins. Most critical are the capacitors for the switching regulator: input capacitor at IN_SBB and output capacitors at SBBx. Input Capacitor at IN_SBB Minimize the parasitic inductance from PGND to input capacitor to IN_SBB to reduce ringing on the LXA voltage. Inductor Keep the inductor close to the IC to reduce trace resistance; however, prioritize any regulator input/output capacitors over the inductor. Use the appropriate trace width from LXA to inductor to LXB to support the peak inductor current. Likewise, if there are vias in the path, use an appropriate amount of vias to support the peak current. www.analog.com Analog Devices | 79 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ Ground Connections As the switching regulator charges and discharges the inductor, current flows from PGND to the input capacitor ground, from output capacitor ground to PGND, or from output capacitor ground to input capacitor ground. Therefore, use a wide, continuous copper plane to connect PGND to the capacitor grounds. When connecting the GND and PGND pins together, ensure noise from the power ground does not enter the analog ground (where GND is connected). For example, assuming the ground pins are connected through a solid ground plane on an internal layer, one via connecting GND to the internal ground plane can be sufficient to protect GND from most of the noise in the power-ground plane. Likewise, if there are other higher current or noisy circuitry near this device, avoid connecting the GND pin directly to their grounds. For more guidelines on proper grounding, visit: https://www.maximintegrated.com/en/design/partners-and-technology/ design-technology/ground-layout-board-designers.html. Detailed Description—Low Dropout Linear Regulator (LDO)/Load Switch (LSW) The device includes two on-chip low-dropout linear regulators (LDO0/1) that can also be configured as load switches. These LDOs are optimized to have low-quiescent current. The input voltage range (VIN_LDOx) allows it to be powered directly from the main energy source such as a Li-Poly battery or from an intermediate regulator. Each linear regulator delivers up to 150mA. Features and Benefits ● ● ● ● ● ● 2x 150mA LDO LDO Input Voltage Range: 1.71V to 5.5V LSW Input Voltage Range: 1.2V to 5.5V Adjustable Output Voltage 100mV Maximum Dropout Voltage at ECT Conditions Programmable On-Chip Active Discharge LDO Fault Indicator The IC has an LDOx fault shutdown option to protect itself when an LDOx fault is detected. If this option is enabled then the regulators power down sequentially after an LDOx fault. An LDOx fault occurs when the output voltage falls below 80% of regulation target. The corresponding LDOx_F bit remains high until the output voltage rises above 85% of regulation target. LDO/LSW Simplified Block Diagram Each LDO/LSW block has one input (IN_LDOx) and one output (LDOx) and several ports that exchange information with the rest of the device (VREF, EN_LDOx, ADE_LDOx). VREF comes from the main bias circuits. CNFG_LDOx_B.EN_LDOx and CNFG_LDOx_B.ADE_LDOx are register bits for controlling the enable and activedischarge feature, respectively. See the Register Map for more information. www.analog.com Analog Devices | 80 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ IN_LDOx VREF EN_LDOx ADE_LDOx 150mA LDOx LDOx_F DOD_x_R SBB0 10µF* (0402) *THE FLOOR PLAN IS SUCH THAT THE SBB0 OUTPUT CAPACITOR IS ALSO THE IN_LDOx INPUT CAPACITOR. LDOx RADE_LDOx 1.0µF (0402) LDOx Figure 25. LDO Simplified Block Diagram www.analog.com Analog Devices | 81 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ LDO/LSW Active-Discharge Resistor Each LDO/LSW block has an active-discharge resistor (RAD_LDOx) that is enabled if CNFG_LDO_B.ADE_LDOx = 1 and LDOx is disabled. Enabling the active discharge feature helps ensure a complete and timely power down of the resource. During power up, if VSYS > VPOR and CNFG_LDO_B.ADE_LDOx = 1, the active-discharge resistor is enabled. LDO/LSW Soft-Start The soft-start feature limits inrush current during startup, and is achieved by limiting the slew rate of the output voltage during startup (dVOUT_LDOx/dtSS). More output capacitance results in higher input current surges during startup. The equation and example describes the input current surge phenomenon during startup. The input current (IIN_LDOx) during soft-start is: IIN_LDOx = CLDOx dVOUT_LDOx dtSS + IOUT_LDOx where: ● CLDOx is the capacitance on the output of the regulator ● dVOUT_LDOx/dtSS is the voltage change rate of the output For example, given the following conditions, the input current (IIN_LDOx) during soft-start is 13.08mA: Given: ● ● ● ● CLDOx = 2.2µF dVOUT_LDOx/dtSS = 1.4mV/µs LDOx programmed to 1.85V RLDOx = 185Ω (IOUT_LDOx = 1.85V/185Ω = 10mA) Calculation: ● IIN = 2.2µF x 1.4mV/µs + 10mA ● IIN = 13.08mA Load Switch Configuration Both LDO0 and LDO1 can be configured as load switches with the CNFG_LDOx_B.LDOx_MD bit. As shown in Figure 26, the transition from LDO to LSW mode is controlled by a defined slew rate until dropout is detected. Once dropout is detected, the load switch is fully closed and the dropout interrupt flag (INT_GLBL.DODx_R) is set. NOT DRAWN TO SCALE DOD DETECTED LSW TO LDOx SLEW DEPENDS ON LOAD LDOx STARTS IN LDO MODE LDOx CONFIGURED TO BE IN LSW MODE LDOx CONFIGURED TO BE IN LDO MODE Figure 26. LDO to LSW Transition Waveform www.analog.com Analog Devices | 82 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ Applications Information Input Capacitor Selection Make sure the input bypass capacitance (CIN_LDOx) is at least 2.2µF. Larger values of CIN_LDOx improve the decoupling for LDOx. The floor plan of the device is such that SBB0 is adjacent to IN_LDOx and if the SIMO channel 0 output powers the input of LDOx, then its output capacitor (CSBB0) can also serve as CIN_LDOx such that only one capacitor is required. CIN_LDOx reduces the current peaks drawn from the battery or input power source during operation. The impedance of the input capacitor (ESR, ESL) should be very low (i.e., ESR ≤ 50mΩ and ESL ≤ 5nH) for frequencies up to 0.5MHz. Ceramic capacitors with X5R or X7R dielectric are highly recommended due to their small size, low ESR, and small temperature coefficients. Output Capacitor Selection For both LDO and LSW modes, choose the output bypass capacitance (CLDOx) to be 1μF. In LDO mode, larger values of CLDOx improve output PSRR but increase input surge currents during soft-start and output voltage changes. The effective output capacitance should not exceed 2.8μF to maintain stability. While in LDO mode, CLDOx is required to keep stability. The series inductance of the output capacitor and its series resistance should be low (i.e., ESR ≤ 10mΩ and ESL ≤ 1nH) for frequencies up to 0.5MHz. Ceramic capacitors with X5R or X7R dielectric are highly recommended due to their small size, low ESR, and small temperature coefficients. A capacitor's effective capacitance decreases with increased DC bias voltage. This effect is more pronounced with smaller capacitor case sizes. Due to this characteristic, 0603 case size capacitors tend to perform well while 0402 case size capacitors of the same value perform poorly. www.analog.com Analog Devices | 83 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ Detailed Description—Fuel Gauge The MAX77658 is an ultra-low power fuel gauge which implements the Maxim ModelGauge m5 EZ algorithm. The IC measures voltage, current, and temperature accurately to produce fuel gauge results. The ModelGauge m5 EZ robust algorithm provides tolerance against battery diversity. This additional robustness enables simpler implementation for most applications and batteries by avoiding time-consuming battery characterization. The ModelGauge m5 algorithm combines the short-term accuracy and linearity of a coulomb-counter with the long-term stability of a voltage-based fuel gauge, along with temperature compensation to provide industry-leading fuel gauge accuracy. The IC automatically compensates for aging, temperature, and discharge rate and provides an accurate stateof-charge (SOC) in percentage (%) and remaining capacity in milliampere-hours (mAhr) over a wide range of operating conditions. Fuel gauge error always converges to 0% as the cell approaches empty. The IC has a register set that is compatible with Intel's DBPT v2 dynamic power standard. This allows the system designer to safely estimate the maximum allowed CPU turbo-boost power level in complex power conditions. The IC provides accurate estimation of time-to-empty and time-to-full and provides three methods for reporting the age of the battery: reduction in capacity, increase in battery resistance, and cycle odometer. The IC contains a unique serial number. It can be used for cloud-based authentication. See the Serial Number Feature section for more information. Communication to the host occurs over the standard I2C interface. ModelGauge m5 EZ Performance ModelGauge m5 EZ performance provides plug-and-play operation when the IC is connected to most lithium batteries. While the IC can be custom-tuned to the application's specific battery through a characterization process for ideal performance, the IC can provide good performance for most applications with no custom characterization required. Table 17 and Figure 27 show the performance of the ModelGauge m5 algorithm in applications using ModelGauge m5 EZ configuration. The ModelGauge m5 EZ provides good performance for most cell types. For some chemistries, such as lithium-ironphosphate (LiFePO4) and Panasonic NCR/NCA series cells, it is suggested that the customer request a custom model from Maxim for best performance. For even better fuel-gauging accuracy than ModelGauge m5 EZ, contact Maxim for information regarding cell characterization. Table 17. ModelGauge m5 EZ Performance AFTER FIRST CYCLE* (%) AFTER SECOND CYCLE* (%) Tests with less than 3% error DESCRIPTION 95 97 Tests with less than 5% error 98.7 99 Tests with less than 10% error 100 100 *Test conditions: +20°C and +40°C, run time of > 3 hours. www.analog.com Analog Devices | 84 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ ModelGauge m5 EZ CONFIGURATION PERFORMANCE 60% PERCENTILE OF TESTS (%) 50% TEST CONDITIONS: · 300+ DIFFERENT BATTERIES · 3000+ DISCHARGES · BETWEEN +20ºC TO +40ºC · RUN TIME OF > 3 HOURS · AFTER FIRST CYCLE 40% 30% 20% 10% 0% 1 2 3 4 5 6 7 8 9 10 WORST CASE ERROR DURING DISCHARGE (%) Figure 27. ModelGauge m5 EZ Configuration Performance Application Notes This data sheet describes the basic feature sets and the minimal register set needed to support the plug-and-play ModelGauge™ m5 EZ performance. Refer to the following application notes for additional reference material for the fuel gauge of MAX77658: ● ModelGauge m5 EZ User Guide • Documents full register set • More details about ModelGauge m5 algorithm • Discusses additional applications ● Software Implementation Guide • Guidelines for software drivers including example code Standard Register Formats Unless otherwise stated during a given register's description, all fuel gauge registers of the MAX77658 follow the same format depending on the type of register. See Table 18 for the resolution and range of any register described hereafter. Table 18. ModelGauge m5 Register Standard Resolutions REGISTER TYPE LSb SIZE MINIMUM VALUE MAXIMUM VALUE Capacity 0.107mAh 0.0mAh 7021.106mAh Percentage 1/256% 0.0% 255.9961% Voltage 1.25mV/ 16 0.0V 5.11992V www.analog.com NOTES 1% LSb when reading only the upper byte. Analog Devices | 85 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ Table 18. ModelGauge m5 Register Standard Resolutions (continued) REGISTER TYPE LSb SIZE MINIMUM VALUE MAXIMUM VALUE Current 33.487μA -1.097A 1.097A Temperature 1/256°C -128.0°C 127.996°C Resistance 1/4096Ω 0.0Ω 15.99976Ω Time 5.625s 0.0s 102.3984h Special — — — NOTES Signed two's-complement format. Signed two's-complement format. 1°C LSb when reading only the upper byte. Format details are included with the register description. ModelGauge m5 Algorithm Classical coulomb-counter-based fuel gauges have excellent linearity and short-term performance. However, they suffer from drift due to the accumulation of the offset error in the current-sense measurement. Although the offset error is often very small, it cannot be eliminated. It causes the reported capacity error to increase over time and requires periodic corrections. Corrections are traditionally performed at full or empty. Some other systems also use the relaxed battery voltage to perform corrections. These systems determine the true state-of-charge (SOC) based on the battery voltage after a long time of no current flow. Both have the same limitation: if the correction condition is not observed over time in the actual application, the error in the system is boundless. The performance of classic coulomb counters is dominated by the accuracy of such corrections. Voltage measurement-based SOC estimation has accuracy limitations due to imperfect cell modeling but does not accumulate offset error over time. The MAX77658 includes an advanced voltage fuel gauge (VFG) that estimates open-circuit voltage (OCV), even during current flow, and simulates the nonlinear internal dynamics of a Li+ battery to determine the SOC with improved accuracy. The model considers the time effects of a battery caused by the chemical reactions and impedance in the battery to determine SOC. This SOC estimation does not accumulate offset error over time. The IC performs a smart empty compensation algorithm that automatically compensates for the effect of temperature condition and load condition to provide accurate state-of-charge information. The converge-to-empty function eliminates error toward an empty state. The IC learns battery capacity over time automatically to improve long-term performance. The age information of the battery is available in the output registers. The ModelGauge m5 algorithm combines a high-accuracy coulomb counter with a VFG. See Figure 28. The complementary combined result eliminates the weaknesses of both the coulomb counter and the VFG while providing the strengths of both. A mixing algorithm combines the VFG capacity with the coulomb counter and weighs each result so that both are used optimally to determine the battery state. In this way, the VFG capacity result is used to continuously make small adjustments to the battery state, canceling the coulomb-counter drift. www.analog.com Analog Devices | 86 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ RSENSE CURRENT INTEGRATOR ModelGauge ALGORITHM COULOMB COUNTER Q CHANGE %SOC CHANGE CAPACITY MICROCORRECTIONS FULL, EMPTY, AND STANDBY-STATE DETECTION UNNECESSARY Figure 28. ModelGauge m5 Algorithm The ModelGauge m5 algorithm uses this battery state information and accounts for temperature, battery current, age, and application parameters to determine the remaining capacity available to the system. As the battery approaches the critical region near empty, the ModelGauge m5 algorithm invokes a special error correction mechanism that eliminates any error. The ModelGauge m5 algorithm continually adapts to the cell and application through independent learning routines. As the cell ages, its change in capacity is monitored and updated and the voltage-fuel-gauge dynamics adapt based on cellvoltage behavior in the application. Analog Measurements The IC monitors voltage, current, and temperature. This information is provided to the fuel-gauge algorithm to predict cell capacity and also made available to the user. Voltage Measurement VCell Register (0x09) Register Type: Voltage VCell reports the voltage measured between BATT and GND AvgVCell Register (0x19) Register Type: Voltage The AvgVCell register reports an average of the VCell register readings. MaxMinVolt Register (0x1B) Register Type: Special Initial Value: 0x00FF The MaxMinVolt register maintains the maximum and minimum of VCell register values since the device reset. At power-up, the maximum voltage value is set to 0x00 (the minimum) and the minimum voltage value is set to 0xFF (the maximum). Therefore, both values are changed to the voltage register reading after the first update. Host software can reset this register by writing it to its power-up value of 0x00FF. The maximum and minimum voltages are each stored as 8-bit values with a 20mV resolution. See the Register Map for register format. www.analog.com Analog Devices | 87 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ Current Measurement The MAX77658 monitors the current flow through the battery by measuring the voltage across the internal current sensing element. The IC is precalibrated for current-measurement accuracy in Maxim's factory. Additionally, the IC maintains a record of the minimum, maximum, and average current measured by the IC. The maximum current constraints listed in the Absolute Maximum Ratings section should be followed to ensure the 100,000 hours lifetime of the sensing element. In general, the root mean square of current over whole lifetime should be below 0.8A, with additional limitation on peak value based on utilization. If the device utilization is 100% (charges or discharges at the highest allowable current level without stopping), then the maximum DC current rating is 0.8A. If the device utilization is 10%, then the maximum DC current allowed is 1.2A. For example, it spends 10% of its time charging, and the remaining 90% resting or discharging, then it can be allowed 1.2A charge current, but discharge currents should be below 0.74A. Current Register (0x0A) Register Type: Current The MAX77658 uses internal current sensing to monitor the current through the SYS FG pin. The measurement value is stored in two's-complement format. Measurement that exceeds maximum and minimum current range is stored as maximum and minimum value. The current register has a LSb value of 33.487μA, a register scale range of ±1.097A, and an allowable measurement range as described in the Absolute Maximum Ratings. AvgCurrent Register (0x0B) Register Type: Current The AvgCurrent register reports an average of the Current register readings. MaxMinCurr Register (0x1C) Register Type: Special Initial Value: 0x807F The MaxMinCurr register maintains the maximum and minimum Current register values since the last IC reset or until cleared by host software. At power-up, the maximum current value is set to 0x80 (most negative) and the minimum current value is set to 0x7F (most positive). Therefore, both values are changed to the Current register reading after the first update. Host software can reset this register by writing it to its power-up value of 0x807F. The maximum and minimum currents are each stored as two's complement 8-bit values with 160mA resolution. See the Register Map for register format. Temperature Measurement The IC can be configured to measure its own internal die temperature or an external NTC thermistor. Set Config.TSEL = 0 (default) to enable die temperature measurement. Set Config.TSEL = 1 to enable thermistor measurement. Thermistor conversions are initiated by periodically connecting the TH and BATT pins internally. Measurement results of the TH pin are compared to the voltage of the BATT pin and converted to a ratiometric value from 0% to 100%. The active pullup is disabled when temperature measurements are complete. This reduces the current consumption. The ratiometric results are converted to temperature using the temperature gain (TGain), temperature offset (TOff), and temperature curve (Curve) register values. Internal die temperature measurements are factory calibrated and are not affected by TGain, TOff, and Curve register settings. Refer to the ModelGauge m5 EZ User Guide for more details. Additionally, the IC maintains a record of the minimum, maximum, and average temperature measured by the IC. Temp Register (0x08) Register Type: Temperature The Temp register provides the temperature measured by the thermistor or die temperature based on the Conifg register setting. www.analog.com Analog Devices | 88 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ MaxMinTemp Register (0x1A) Register Type: Special Initial Value: 0x807F The MaxMinTemp register maintains the maximum and minimum Temp register (0x08) values since the last fuel-gauge reset or until cleared by host software. At power-up, the maximum value is set to 0x80 (most negative) and the minimum value is set to 0x7F (most positive). Therefore, both values are changed to the Temp register reading after the first update. Host software can reset this register by writing it to its power-up value of 0x807F. The maximum and minimum temperatures are each stored as two's complement 8-bit values with 1°C resolution. See the Register Map for format of the register. DieTemp Register (0x34) Register Type: Temperature The DieTemp register provides the internal die temperature measurement. If Config.TSel = 0, DieTemp and Temp registers have the value of the die temperature. Power Measurement Power Register (0xB1) Instant power calculation from immeidate current and voltage. The LSb is 0.171mW. AvgPower Register (0xB3) Filtered average power from the Power register. LSb is 0.171mW. Alert Function The Alert Threshold registers allow interrupts to be generated by detecting a high or low voltage, current, temperature, or state-of-charge. Interrupts are generated on the ALRT pin open-drain output driver. An external pullup is required to generate a logic-high signal. Alerts can be triggered by any of the following conditions: • Battery removal: (VTH > VBATT Χ VDET) and battery removal detection enabled (Ber = 1). • Battery insertion: (VTH < VBATT Χ (VDET - VDET-HYS)) and battery insertion detection enabled (Bei = 1). • Over/undervoltage: VAlrtTh register threshold violation (upper or lower) and alerts enabled (Aen = 1). • Over/undertemperature: TAlrtTh register threshold violation (upper or lower) and alerts enabled (Aen = 1). • Over/undercurrent: IAlrtTh register threshold violation (upper or lower) and alerts enabled (Aen = 1). • Over/under SOC: SAlrtTh register threshold violation (upper or lower) and alerts enabled (Aen = 1). • 1% SOC change: RepSOC register bit d8 (1% bit) changed (dSOCen = 1). To prevent false interrupts, the threshold registers should be initialized before setting the Aen bit. Alerts generated by battery insertion or removal can only be reset by clearing the corresponding bit in the Status (0x00) register. Alerts generated by a threshold-level violation can be configured to be cleared only by software, or cleared automatically when the threshold level is no longer violated. See the Config (1Dh) and Config2 (BBh) register descriptions for details of the alert function configuration. Serial Number Feature Each IC provides a unique serial number ID. To read this serial number, clear the AtRateEn and the DPEn bit in the Config2 register. The 128-bit serial information overwrites the Dynamic Power and AtRate output registers. To continue Dynamic Power and AtRate operations after reading the serial number, the host should set Config2.AtRateEn and Config2.DPEn to 1. Table 19. Serial Number Format ADDRESS Config2.AtRateEn = 1 || Config2.DPEn = 1 Config2.AtRateEn = 0 && Config2.DPEn = 0 0xD4 MaxPeakPower Serial Number Word0 www.analog.com Analog Devices | 89 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ Table 19. Serial Number Format (continued) 0xD5 SusPeakPower Serial Number Word1 0xD9 MPPCurrent Serial Number Word2 0xDA SPPCurrent Serial Number Word3 0xDC AtQResidual Serial Number Word4 0xDD AtTTE Serial Number Word5 0xDE AtAvSoc Serial Number Word6 0xDF AtAvCap Serial Number Word7 ModelGauge m5 Memory Space Registers that relate to functionality of the ModelGauge m5 fuel gauge are located on pages 0h-4h and are continued on pages Bh and Dh. See the ModelGauge m5 EZ Algorithm section for details of specific register operation. Register locations marked reserved should not be written to. Table 20. ModelGauge m5 Register Memory Map PAGE/WORD 00h 10h 20h 30h 40h B0h D0h 0h Status FullCapRep TTF Reserved Reserved Status2 RSense / UserMem3 1h VAlrtTh TTE DevName Reserved Reserved Power ScOcvLim 2h TAlrtTh QRTable00 QRTable10 QRTable20 QRTable30 ID / UserMem2 VGain 3h SAlrtTh FullSocThr FullCapNom Reserved RGain AvgPower SOCHold 4h AtRate RCell Reserved DieTemp Reserved IAlrtTh MaxPeakPower 5h RepCap Reserved Reserved FullCap dQAcc TTFCfg SusPeakPower 6h RepSOC AvgTA Reserved Reserved dPAcc CVMixCap PackResistance 7h Age Cycles AIN Reserved Reserved CVHalfTime SysResistance 8h Temp DesignCap LearnCfg RComp0 Reserved CGTempCo MinSysVoltage 9h VCell AvgVCell FilterCfg TempCo ConvgCfg Curve MPPCurrent Ah Current MaxMinTemp RelaxCfg VEmpty VFRemCap HibCfg SPPCurrent Bh AvgCurrent MaxMinVolt MiscCfg Reserved Reserved Config2 ModelCfg Ch QResidual MaxMinCurr TGain Reserved Reserved VRipple AtQResidual Dh MixSOC Config TOff FStat QH RippleCfg AtTTE Eh AvSOC IChgTerm CGain Timer Reserved TimerH AtAvSOC Fh MixCap AvCap COff ShdnTimer Reserved Reserved AtAvCap Detailed Description—I2C Serial Communication General Description The IC features a revision 3.0 I2C-compatible, 2-wire serial interface consisting of a bidirectional serial data line (SDA) and a serial clock line (SCL). This device acts as a slave-only device, relying on the master to generate a clock signal. SCL clock rates from 0Hz to 500kHz are supported. I2C is an open-drain bus, and therefore, SDA and SCL require pullups. Optional resistors (24Ω) in series with SDA and SCL protect the device inputs from high-voltage spikes on the bus lines. Series resistors also minimize crosstalk and undershoot on bus signals. Figure 29 shows the functional diagram for the I2C based communications controller. For additional information on I2C, refer to the I2C Bus Specification and User Manual which is available for free through the internet. www.analog.com Analog Devices | 90 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ Features ● I2C Revision 3.0 Compatible Serial Communications Channel ● Compatible with Any Bus Timing up to 400kHz ● Does not Utilize I2C Clock Stretching I2C Simplified Block Diagram There are three pins (aside from GND) for the I2C-compatible interface. VIO determines the logic level, SCL is the clock line, and SDA is the data line. Note that the interface does not have the ability to drive the SCL line. COMMUNICATIONS CONTROLLER VIO SCL INTERFACE DECODERS SHIFT REGISTERS BUFFERS COM SDA GND PERIPHERAL 0 PERIPHERAL 1 PERIPHERAL 2 PERIPHERAL N-1 PERIPHERAL N Figure 29. I2C Simplified Block Diagram I2C System Configuration The I2C-compatible interface is a multimaster bus. The maximum number of devices that can attach to the bus is only limited by bus capacitance. A device on the I2C bus that sends data to the bus is called a transmitter. A device that receives data from the bus is called a receiver. The device that initiates a data transfer and generates the SCL clock signals to control the data transfer is a master. Any device that is being addressed by the master is considered a slave. The I2C-compatible interface operates as a slave on the I2C bus with transmit and receive capabilities. www.analog.com Analog Devices | 91 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ SDA SCL MASTER TRANSMITTER/ RECEIVER SLAVE RECEIVER SLAVE TRANSMITTER/ RECEIVER SLAVE TRANSMITTER MASTER TRANSMITTER/ RECEIVER Figure 30. I2C System Configuration I2C Interface Power The I2C interface derives its power from VIO. Typically a power input such as VIO would require a local 0.1μF ceramic bypass capacitor to ground. However, in highly integrated power distribution systems, a dedicated capacitor might not be necessary. If the impedance between VIO and the next closest capacitor (≥ 0.1μF) is less than 100mΩ in series with 10nH, then a local capacitor is not needed. Otherwise, bypass VIO to GND with a 0.1µF ceramic capacitor. VIO accepts voltages from 1.7V to 3.6V (VIO). Cycling VIO does not reset the I2C registers. When VIO is less than VIOUVLO and VSYS is less than VSYSUVLO, SDA and SCL are high-impedance I2C Data Transfer One data bit is transferred during each SCL clock cycle. The data on SDA must remain stable during the high period of the SCL clock pulse. Changes in SDA while SCL is high are control signals. See the I2C Start and Stop Conditions section. Each transmit sequence is framed by a START (S) condition and a STOP (P) condition. Each data packet is nine bits long: eight bits of data followed by the acknowledge bit. Data is transferred with the MSB first. I2C Start and Stop Conditions When the serial interface is inactive, SDA and SCL idle high. A master device initiates communication by issuing a START condition. A START condition is a high-to-low transition on SDA with SCL high. A STOP condition is a low-to-high transition on SDA, while SCL is high. See Figure 31. A START condition from the master signals the beginning of a transmission to the device. The master terminates transmission by issuing a not-acknowledge followed by a STOP condition (see the I2C Acknowledge Bit section for information on not-acknowledge). The STOP condition frees the bus. To issue a series of commands to the slave, the master can issue repeated start (Sr) commands instead of a STOP command to maintain control of the bus. In general a repeated start command is functionally equivalent to a regular start command. S Sr P SDA tSU_STA tSU_STO SCL tHD_STA tHD_STA Figure 31. I2C Start and Stop Conditions www.analog.com Analog Devices | 92 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ I2C Acknowledge Bit Both the I2C bus master and slave devices generate acknowledge bits when receiving data. The acknowledge bit is the last bit of each nine bit data packet. To generate an acknowledge (A), the receiving device must pull SDA low before the rising edge of the acknowledge-related clock pulse (ninth pulse) and keep it low during the high period of the clock pulse. See Figure 32. To generate a not-acknowledge (nA), the receiving device allows SDA to be pulled high before the rising edge of the acknowledge-related clock pulse and leaves it high during the high period of the clock pulse. Monitoring the acknowledge bits allows for detection of unsuccessful data transfers. An unsuccessful data transfer occurs if a receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master should reattempt communication at a later time. This device issues an ACK for all register addresses in the possible address space even if the particular register does not exist. NOT ACKNOWLEDGE (NACK) S ACKNOWLEDGE (ACK) SDA tSU_DAT SCL 1 2 8 tHD_DAT 9 Figure 32. Acknowledge Bit I2C Slave Address The I2C controller implements 7-bit slave addressing. An I2C bus master initiates communication with the slave by issuing a START condition followed by the slave address. See Figure 33. The OTP address is factory-programmable for one of two options. See Table 21. All slave addresses not mentioned in Table 21 are not acknowledged. Table 21. I2C Slave Address Options ADDRESS 7-BIT SLAVE ADDRESS 8-BIT WRITE ADDRESS 8-BIT READ ADDRESS Main Address (ADDR = 1)* 0x48, 0b 100 1000 0x90, 0b 1001 0000 0x91, 0b 1001 0001 Main Address (ADDR = 0)* 0x40, 0b 100 0000 0x80, 0b 1000 0000 0x81, 0b 1000 0001 Fuel Gauge Address 0x36, 0b 011 0110 0x6C, 0b 0110 1100 0x6D, 0b 0110 1101 Test Mode** 0x49, 0b 100 1001 0x92, 0b 1001 0010 0x93, 0b 1001 0011 *Perform all reads and writes on the main address. ADDR is a factory one-time programmable (OTP) option, allowing for address changes in the event of a bus conflict. Contact Maxim for more information. **When test mode is unlocked, the additional address is acknowledged. Test mode details are confidential. If possible, leave the test mode address unallocated to allow for the rare event that debugging needs to be performed in cooperation with Maxim. www.analog.com Analog Devices | 93 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ S SDA 1 0 0 0 1 0 SCL 1 2 3 4 5 6 0 R/W A ACKNOWLEDGE 7 8 9 Figure 33. Slave Address Example I2C Clock Stretching In general, the clock signal generation for the I2C bus is the responsibility of the master device. The I2C specification allows slow slave devices to alter the clock signal by holding down the clock line. The process in which a slave device holds down the clock line is typically called clock stretching. The IC does not use any form of clock stretching to hold down the clock line. I2C General Call Address This device does not implement the I2C specifications general call address and does not acknowledge the general call address (0b0000_0000). I2C Device ID This device does not support the I2C Device ID feature. I2C Communication Speed This device is compatible with any bus timing up to 400kHz. The main consideration when changing bus speed through this range is the combination of the bus capacitance and pullup resistors. Larger values of bus capacitance and pullup resistance increase the time constant (C x R), slowing bus operation. Therefore, when increasing bus speeds, the pullup resistance must be decreased to maintain a reasonable time constant. Refer to the Pullup Resistor Sizing section of the I2C bus specification and user manual (available for free on the internet) for detailed guidance on the pullup resistor selection. In general, for bus capacitances of 200pF, a 100kHz bus needs 5.6kΩ pullup resistors, and a 400kHz bus needs about 1.5kΩ pullup resistors. Remember that, while the open-drain bus is low, the pullup resistor is dissipating power, and lower value pullup resistors dissipate more power (V2/R). Operating in high-speed mode requires some special considerations. For a full list of considerations, refer to the publicly available I2C bus specification and user manual. Major considerations concerning this part are: ● The I2C bus master uses current source pullups to shorten the signal rise. ● The I2C slave must use a different set of input filters on its SDA and SCL lines to accommodate for the higher bus. ● The communication protocols need to utilize the high-speed master code. At power-up and after each stop condition, the bus input filters are set for standard mode, fast mode, and fast-mode plus (i.e., 0Hz to 1MHz). To switch the input filters for high-speed mode, use the high-speed master code protocols that are described in the I2C Communication Protocols section. I2C Communication Protocols Both writing to and reading from registers are supported as described in the following subsections. Writing to a Single 8-Bit Register Figure 34 shows the protocol for the I2C master device to write one byte of data to this device. This protocol is the same as the SMBus specification’s write byte protocol. The write byte protocol is as follows: 1. 2. 3. 4. 5. The master sends a start command (S). The master sends the 7-bit slave address followed by a write bit (R/W = 0). The addressed slave asserts an acknowledge (A) by pulling SDA low. The master sends an 8-bit register pointer. The slave acknowledges the register pointer. www.analog.com Analog Devices | 94 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ 6. The master sends a data byte. 7. The slave updates with the new data. 8. The slave acknowledges or not acknowledges the data byte. The next rising edge on SDA loads the data byte into its target register and the data becomes active. 9. The master sends a stop condition (P) or a repeated start condition (Sr). Issuing a P ensures that the bus input filters are set for 1MHz or slower operation. Issuing an Sr leaves the bus input filters in their current state. LEGEND MASTER TO SLAVE SLAVE TO MASTER 1 7 1 1 8 1 8 S SLAVE ADDRESS 0 A REGISTER POINTER A DATA R/W SDA B1 B0 ACK 1 ACK OR NACK 1 NUMBER OF BITS P OR Sr* THE DATA IS LOADED INTO THE TARGET REGISTER AND BECOMES ACTIVE DURING THIS RISING EDGE. ACKNOWLEDGE SCL 7 8 9 *P FORCES THE BUS FILTERS TO SWITCH TO SUB-MEGAHERTZ MODE. Sr LEAVES THE BUS FILTERS IN THEIR CURRENT STATE. Figure 34. Writing to a Single 8-Bit Register with the Write-Byte Protocol Writing Multiple Bytes to Sequential Registers Figure 35 shows the protocol for writing to sequential registers. This protocol is similar to the write byte protocol above, except the master continues to write after it receives the first byte of data. When the master is done writing, it issues a stop or repeated start. The writing to sequential registers protocol is as follows: 1. 2. 3. 4. 5. 6. 7. The master sends a start command (S). The master sends the 7-bit slave address followed by a write bit (R/W = 0). The addressed slave asserts an acknowledge (A) by pulling SDA low. The master sends an 8-bit register pointer. The slave acknowledges the register pointer. The master sends a data byte. The slave acknowledges the data byte. The next rising edge on SDA loads the data byte into its target register and the data becomes active. 8. Steps 6 to 7 are repeated as many times as the master requires. 9. During the last acknowledge-related clock pulse, the master can issue an acknowledge or a not acknowledge. 10. The master sends a stop condition (P) or a repeated start condition (Sr). Issuing a P ensures that the bus input filters are set for 1MHz or slower operation. Issuing an Sr leaves the bus input filters in their current state. www.analog.com Analog Devices | 95 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ LEGEND MASTER TO SLAVE SLAVE TO MASTER 1 7 1 1 S SLAVE ADDRESS 8 0 A REGISTER POINTER X 1 8 1 8 1 A DATA X LSB A DATA X MSB A NUMBER OF BITS Α R/W 8 1 8 1 DATA X+1 LSB A DATA X+1 MSB A Α REGISTER POINTER = X+1 8 1 DATA N LSB A Α 8 1 DATA N MSB Α REGISTER POINTER = N NUMBER OF BITS ACK OR NACK NUMBER OF BITS 1 P OR Sr* Β THE DATA IS LOADED INTO THE TARGET REGISTER AND BECOMES ACTIVE DURING THIS RISING EDGE. SDA B1 B0 ACK B9 9 1 ACKNOWLEDGE SCL 7 8 DETAIL: Α THE DATA IS LOADED INTO THE TARGET REGISTER AND BECOMES ACTIVE DURING THIS RISING EDGE. SDA B1 B0 ACK ACKNOWLEDGE SCL 7 8 9 DETAIL: Β *P FORCES THE BUS FILTERS TO SWITCH TO SUBMEGAHERTZ MODE. Sr LEAVES THE BUS FILTERS IN THEIR CURRENT STATE. Figure 35. Writing to Sequential Registers X to N Writing to 16-Bit Registers The write data protocol is used to transmit data to the registers of the fuel gauge at memory addresses from 00h to FFh. Addresses 00h to FFh can be written as a block. The memory address is sent by the bus master as a single byte value immediately after the slave address. The LSB of the data to be stored is written immediately after the memory address byte is acknowledged. Because the address is automatically incremented after the last bit of each 16-bit word received by the IC, the LSB of the data at the next memory address can be written immediately after the acknowledgment of the MSB of data at the previous address. The master indicates the end of a write transaction by sending a STOP or Repeated START after receiving the last acknowledge bit. If the bus master continues an auto-incremented write transaction beyond address FFh, the IC ignores the data. Data is also ignored on writes to read-only addresses but not reserved addresses. Do not write to reserved address locations. See Figure 36 for an example write data communication sequence. www.analog.com Analog Devices | 96 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ LEGEND MASTER TO SLAVE SLAVE TO MASTER 1 7 1 1 S SLAVE ADDRESS 8 0 A REGISTER POINTER X 1 8 1 8 1 A DATA X LSB A DATA X MSB A NUMBER OF BITS Α R/W 8 1 DATA X+1 LSB A 8 1 DATA X+1 MSB A Α REGISTER POINTER = X+1 8 Α 1 DATA N LSB 8 A 1 ACK OR NACK DATA N MSB Α REGISTER POINTER = N NUMBER OF BITS NUMBER OF BITS 1 P OR Sr* Β Figure 36. Example I2C Write 16-Bit Data Communication Sequence Reading from a Single Register Figure 37 shows the protocol for the I2C master device to read one byte of data. This protocol is the same as the SMBus specification’s read byte protocol. The read byte protocol is as follows: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. The master sends a start command (S). The master sends the 7-bit slave address followed by a write bit (R/W = 0). The addressed slave asserts an acknowledge (A) by pulling SDA low. The master sends an 8-bit register pointer. The slave acknowledges the register pointer. The master sends a repeated start command (Sr). The master sends the 7-bit slave address followed by a read bit (R/W = 1). The addressed slave asserts an acknowledge by pulling SDA low. The addressed slave places 8-bits of data on the bus from the location specified by the register pointer. The master issues a not acknowledge (nA). The master sends a stop condition (P) or a repeated start condition (Sr). Issuing a P ensures that the bus input filters are set for 1MHz or slower operation. Issuing an Sr leaves the bus input filters in their current state. Note that when this device receives a stop, the register pointer is not modified. Therefore, if the master re-reads the same register, it can immediately send another read command, omitting the command to send a register pointer. *P FORCES THE BUS FILTERS TO SWITCH TO THEIR ≤ 1MHz MODE. Sr LEAVES THE BUS FILTERS IN THEIR CURRENT STATE. LEGEND MASTER TO SLAVE 1 7 S SLAVE ADDRESS SLAVE TO MASTER 1 1 R/W 8 0 A REGISTER POINTER X 1 1 7 1 1 8 1 1 A Sr SLAVE ADDRESS 1 A DATA X A P or Sr* NUMBER OF BITS R/W Figure 37. Reading from a Single Register with the Read Byte Protocol www.analog.com Analog Devices | 97 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ Reading from Sequential Registers Figure 38 shows the protocol for reading from sequential registers. This protocol is similar to the read byte protocol except the master issues an acknowledge to signal the slave that it wants more data: when the master has all the data it requires it issues a not acknowledge (nA) and a stop (P) to end the transmission. The continuous read from sequential registers protocol is as follows: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. The master sends a start command (S). The master sends the 7-bit slave address followed by a write bit (R/W = 0). The addressed slave asserts an acknowledge (A) by pulling SDA low. The master sends an 8-bit register pointer. The slave acknowledges the register pointer. The master sends a repeated start command (Sr). The master sends the 7-bit slave address followed by a read bit (R/W = 1). The addressed slave asserts an acknowledge by pulling SDA low. The addressed slave places 8-bits of data on the bus from the location specified by the register pointer. The master issues an acknowledge (A) signaling the slave that it wishes to receive more data. Steps 9 to 10 are repeated as many times as the master requires. Following the last byte of data, the master must issue a not acknowledge (nA) to signal that it wishes to stop receiving data. 12. The master sends a stop condition (P) or a repeated start condition (Sr). Issuing a stop (P) ensures that the bus input filters are set for 1MHz or slower operation. Issuing an Sr leaves the bus input filters in their current state. Note that when this device receives a stop it does not modify its register pointer. Therefore, if the master re-reads the same register, it can immediately send another read command, omitting the command to send a register pointer. *P FORCES THE BUS FILTERS TO SWITCH TO THEIR ≤ 1MHz MODE. Sr LEAVES THE BUS FILTERS IN THEIR CURRENT STATE. LEGEND MASTER TO SLAVE 1 7 S SLAVE ADDRESS SLAVE TO MASTER 1 1 R/W 8 0 A REGISTER POINTER X 1 1 7 1 1 8 1 A Sr SLAVE ADDRESS 1 A DATA X A 1 8 1 A DATA X+3 A R/W 8 1 8 DATA X+1 A DATA X+2 NUMBER OF BITS NUMBER OF BITS REGISTER POINTER = X + 1 REGISTER POINTER = X + 2 REGISTER POINTER = X + 3 8 1 8 1 8 1 1 DATA N-2 A DATA N-1 A DATA N NA P OR Sr* REGISTER POINTER = N-2 REGISTER POINTER = N-1 NUMBER OF BITS REGISTER POINTER = N Figure 38. Reading Continuously from Sequential Registers X to N www.analog.com Analog Devices | 98 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ Reading From 16-Bit Registers The Read Data protocol is used to transmit data from memory locations of the fuel gauge registers 00h to FFh. The memory address is sent by the bus master as a single byte value immediately after the slave address. Immediately following the memory address, the bus master issues a REPEATED START followed by the slave address. The MAX77658 ACKs the address and begins transmitting data. A word of data is read as two separate bytes that the master must ACK. Because the address is automatically incremented after the final bit of each 16-bit word received by the IC, the LSB of the data at the next memory address can be read immediately after the acknowledgment of the MSB of data at the previous address. The master indicates the end of a read transaction by sending a NACK followed by a STOP. If the bus master continues an auto-incremented read transaction beyond memory address FFh, the IC transmits all 1s until a NACK or STOP is received. Data from reserved address locations is undefined. See Figure 39 for an example Read Data communication sequence. *P FORCES THE BUS FILTERS TO SWITCH TO THEIR ≤ 1MHz MODE. Sr LEAVES THE BUS FILTERS IN THEIR CURRENT STATE. LEGEND MASTER TO SLAVE 1 7 S SLAVE ADDRESS SLAVE TO MASTER 1 1 R/W 8 0 A REGISTER POINTER X 1 1 7 1 1 A Sr SLAVE ADDRESS 1 A R/W NUMBER OF BITS NUMBER OF BITS 8 1 8 1 DATA X LSB A DATA X MSB A 8 1 8 1 DATA X+1 LSB A DATA X+1 MSB A 8 1 8 1 1 DATA N LSB A DATA N MSB NA P OR Sr* REGISTER POINTER = X NUMBER OF BITS REGISTER POINTER = X+1 NUMBER OF BITS REGISTER POINTER = N Figure 39. Example I2C Read 16-Bit Data Communication Sequence www.analog.com Analog Devices | 99 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ Register Map MAX77658 ADDRESS NAME MSB LSB Global 0x00 INT_GLBL0[7:0] DOD0_R DOD1_R TJAL2_R TJAL1_R nEN_R nEN_F GPI0_R GPI0_F 0x04 INT_GLBL1[7:0] RSVD LDO1_F LDO0_F SBB2_F SBB1_F SBB0_F GPI1_R GPI1_F SBB_FA ULT EVT_WD T_SFT_2 3OR SFT_CR ST_F SFT_OF F_F MRST_F SYSUVL O SYSOVL O TOVLD 0x05 ERCFLAG[7:0] 0x06 STAT_GLBL[7:0] DIDM BOK DOD0_S DOD1_S TJAL2_S TJAL1_S STAT_E N STAT_IR Q 0x08 INTM_GLBL0[7:0] DOD0_R M DOD1_R M TJAL2_R M TJAL1_R M nEN_RM nEN_FM GPI0_R M GPI0_F M 0x09 INTM_GLBL1[7:0] RSVD LDO1_M LDO0_M SBB2_F M SBB1_F M SBB0_F M GPI1_R M GPI1_F M 0x10 CNFG_GLBL[7:0] PU_DIS T_MRST SBIA_LP M 0x11 CNFG_GPIO0[7:0] SBB_F_ SHUTDN – ALT_GPI O0 DBEN_G PI DO DRV DI DIR 0x12 CNFG_GPIO1[7:0] RSVD[1:0] ALT_GPI O1 DBEN_G PI DO DRV DI DIR 0x13 CNFG_GPIO2[7:0] RSVD[1:0] ALT_GPI O2 DBEN_G PI DO DRV DI DIR 0x14 CID[7:0] 0x17 CNFG_WDT[7:0] – – DBEN_n EN nEN_MODE[1:0] – RSVD[1:0] SFT_CTRL[1:0] CID[4:0] WDT_PER[1:0] WDT_M ODE WDT_CL R WDT_E N WDT_LO CK CHGIN_I CHG_I THM_I OVERLAP Charger 0x01 INT_CHG[7:0] RSVD SYS_CN FG_I SYS_CT RL_I CHGIN_ CTRL_I TJ_REG _I 0x02 STAT_CHG_A[7:0] RSVD VCHGIN _MIN_S TAT ICHGIN_ LIM_STA T VSYS_M IN_STAT TJ_REG _STAT 0x03 STAT_CHG_B[7:0] 0x07 INT_M_CHG[7:0] 0x20 CNFG_CHG_A[7:0] 0x21 CNFG_CHG_B[7:0] VCHGIN_MIN[2:0] 0x22 CNFG_CHG_C[7:0] CHG_PQ[2:0] 0x23 CNFG_CHG_D[7:0] TJ_REG[2:0] 0x24 CNFG_CHG_E[7:0] CHG_CC[5:0] 0x25 CNFG_CHG_F[7:0] CHG_CC_JEITA[5:0] RSVD – 0x26 CNFG_CHG_G[7:0] CHG_CV[5:0] USBS FUS_M 0x27 CNFG_CHG_H[7:0] CHG_CV_JEITA[5:0] SYS_BA T_PRT CHR_TH _EN www.analog.com CHG_DTLS[3:0] DIS_AIC L SYS_CN FG_M SYS_CT RL_M THM_HOT[1:0] THM_DTLS[2:0] CHG TIME_S US CHG_M THM_M CHGIN_DTLS[1:0] CHGIN_ CTRL_M THM_WARM[1:0] TJ_REG _M CHGIN_ M THM_COOL[1:0] THM_COLD[1:0] ICHGIN_LIM[2:0] I_TERM[1:0] I_PQ CHG_EN T_TOPOFF[2:0] VSYS_REG[4:0] T_FAST_CHG[1:0] Analog Devices | 100 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ ADDRESS 0x28 NAME MSB CNFG_CHG_I[7:0] LSB IMON_DISCHG_SCALE[3:0] MUX_SEL[3:0] SBB DIS_LP M 0x38 CNFG_SBB_TOP[7:0] 0x39 CNFG_SBB0_A[7:0] 0x3A CNFG_SBB0_B[7:0] 0x3B CNFG_SBB1_A[7:0] 0x3C CNFG_SBB1_B[7:0] 0x3D CNFG_SBB2_A[7:0] 0x3E CNFG_SBB2_B[7:0] 0x3F CNFG_DVS_SBB0_A[7 :0] IPK_1P5 A – – – – DRV_SBB[1:0] TV_SBB0[7:0] OP_MODE[1:0] ADE_SB B0 IP_SBB0[1:0] EN_SBB0[2:0] TV_SBB1[7:0] OP_MODE[1:0] ADE_SB B1 IP_SBB1[1:0] EN_SBB1[2:0] TV_SBB2[7:0] OP_MODE[1:0] ADE_SB B2 IP_SBB2[1:0] EN_SBB2[2:0] TV_SBB0_DVS[7:0] LDO 0x48 CNFG_LDO0_A[7:0] TV_OFS _LDO0 0x49 CNFG_LDO0_B[7:0] – 0x4A CNFG_LDO1_A[7:0] TV_OFS _LDO1 0x4B CNFG_LDO1_B[7:0] – TV_LDO0[6:0] – – LDO0_M D ADE_LD O0 EN_LDO0[2:0] TV_LDO1[6:0] – – LDO1_M D ADE_LD O1 EN_LDO1[2:0] Register Details INT_GLBL0 (0x00) BIT 7 6 5 4 3 2 1 0 Field DOD0_R DOD1_R TJAL2_R TJAL1_R nEN_R nEN_F GPI0_R GPI0_F Reset 0b0 0b0 0b0 0b0 0b0 0b0 0b0 0b0 Read Clears All Read Clears All Read Clears All Read Clears All Read Clears All Read Clears All Read Clears All Read Clears All Access Type BITFIELD BITS DESCRIPTION DECODE DOD0_R 7 LDO Dropout Detector Rising Interrupt 0b0 = The LDO has not detected dropout since the last time this bit was read. 0b1 = The LDO has detected dropout since the last time this bit was read. DOD1_R 6 LDO Dropout Detector Rising Interrupt 0b0 = The LDO has not detected dropout since the last time this bit was read. 0b1 = The LDO has detected dropout since the last time this bit was read. Thermal Alarm 2 Rising Interrupt 0b0 = The junction temperature has not risen above TJAL2 since the last time this bit was read. 0b1 = The junction temperature has risen above TJAL2 since the last time this bit was read. TJAL2_R www.analog.com 5 Analog Devices | 101 MAX77658 BITFIELD Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ BITS DESCRIPTION DECODE TJAL1_R 4 Thermal Alarm 1 Rising Interrupt 0b0 = The junction temperature has not risen above TJAL1 since the last time this bit was read. 0b1 = The junction temperature has risen above TJAL1 since the last time this bit was read. nEN_R 3 nEN Rising Interrupt 0b0 = No nEN rising edges have occurred since the last time this bit was read. 0b1 = A nEN rising edge has occurred since the last time this bit was read. nEN Falling Interrupt 0b0 = No nEN falling edges have occurred since the last time this bit was read. 0b1 = A nEN falling edge occurred since the last time this bit was read. nEN_F 2 GPI Rising Interrupt GPI0_R 1 GPI0_F 0 0b0 = No GPI rising edges have occurred since the last time this bit was read. 0b1 = A GPI rising edge has occurred since the last time this bit was read. Note that "GPI" refers to the GPIO programmed to be an input. GPI Falling Interrupt Note that the GPI is the GPIO programmed to be an input. 0b0 = No GPI falling edges have occurred since the last time this bit was read. 0b1 = A GPI falling edge has occurred since the last time this bit was read. INT_GLBL1 (0x04) BIT Field Reset Access Type BITFIELD RSVD LDO1_F 7 6 5 4 3 2 1 0 RSVD LDO1_F LDO0_F SBB2_F SBB1_F SBB0_F GPI1_R GPI1_F 0b0 0b0 0b0 0b0 0b0 0b0 0b0 0b0 Read Clears All Read Clears All Read Clears All Read Clears All Read Clears All Read Clears All Read Clears All Read Clears All BITS 7 6 DESCRIPTION DECODE Reserved. Unutilized bit. Write to 0. Reads are don't care. LDO1 Fault Interrupt 0b0 = No fault has occurred on LDO1 since the last time this bit was read. 0b1 = LDO1 has fallen out of regulation since the last time this bit was read. LDO0_F 5 LDO0 Fault Interrupt 0b0 = No fault has occurred on LDO0 since the last time this bit was read. 0b1 = LDO0 has fallen out of regulation since the last time this bit was read. SBB2_F 4 SBB2 Fault Indicator 0b0 = No fault has occurred on SBB2 since the last time this bit was read. 0b1 = SBB2 has fallen out of regulation since the last time this bit was read. SBB1 Fault Indicator 0b0 = No fault has occurred on SBB1 since the last time this bit was read. 0b1 = SBB1 has fallen out of regulation since the last time this bit was read. SBB0 Fault Indicator 0b0 = No fault has occurred on SBB0 since the last time this bit was read. 0b1 = SBB0 has fallen out of regulation since the last time this bit was read. SBB1_F SBB0_F www.analog.com 3 2 Analog Devices | 102 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ BITFIELD BITS DESCRIPTION DECODE GPI Rising Interrupt GPI1_R 1 GPI1_F 0 0b0 = No GPI rising edges have occurred since the last time this bit was read. 0b1 = A GPI rising edge has occurred since the last time this bit was read. Note that "GPI" refers to the GPIO programmed to be an input. GPI Falling Interrupt Note that the GPI is the GPIO programmed to be an input. 0b0 = No GPI falling edges have occurred since the last time this bit was read. 0b1 = A GPI falling edge has occurred since the last time this bit was read. ERCFLAG (0x05) BIT Field Reset Access Type 7 6 5 4 3 2 1 0 SBB_FAUL T EVT_WDT_ SFT_23OR SFT_CRST _F SFT_OFF_ F MRST_F SYSUVLO SYSOVLO TOVLD 0b0 0b0 0b0 0b0 0b0 0b0 0b0 0b0 Read Clears All Read Clears All Read Clears All Read Clears All Read Clears All Read Clears All Read Clears All Read Clears All BITFIELD BITS SBB_FAULT 7 SBB Fault Shutdown Flag 0b0 = No shutdown event has occurred from SBB fault since the last time this bit was read. 0b1 = A shutdown event has occurred from SBB fault since the last time this bit was read. 6 Watchdog Timer Expired Flag. This bit sets when the watchdog timer expires and causes a power-off (WDT_MODE = 0) or a powerreset (WDT_MODE = 1). 0b0 = Watchdog timer has not expired since the last time this bit was read. 0b1 = Watchdog timer has expired since the last time this bit was read. Software Cold Reset Flag 0b0 = The software cold reset has not occurred since the last read of this register. 0b1 = The software cold reset has occurred since the last read of this register. This indicates that software has set SFT_CTRL[1:0] = 0b01. Software OFF Flag 0b0 = The SFT_OFF function has not occurred since the last read of this register. 0b1 = The SFT_OFF function has occurred since the last read of this register. This indicates that software has set SFT_CTRL[1:0] = 0b10. Manual Reset Timer 0b0 = A manual reset has not occurred since the last read of this register. 0b1 = A manual reset has occurred since the last read of this register. SYS Domain Undervoltage Lockout 0b0 = The SYS domain undervoltage lockout has not occurred since the last read of this register. 0b1 = The SYS domain undervoltage lockout has occurred since the last read of this register. This indicates that the SYS domain voltage fell below VSYSUVLO (~2.6V) SYS Domain Overvoltage Lockout 0b0 = The SYS domain overvoltage lockout has not occurred since the last read of this register. 0b1 = The SYS domain overvoltage lockout has occurred since the last read of this register. This indicates that the SYS domain voltage rose below VSYSOVLO (~5.85V) EVT_WDT_S FT_23OR SFT_CRST_ F SFT_OFF_F MRST_F SYSUVLO SYSOVLO www.analog.com 5 4 3 2 1 DESCRIPTION DECODE Analog Devices | 103 MAX77658 BITFIELD TOVLD Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ BITS 0 DESCRIPTION DECODE 0b0 = Thermal overload has not occurred since the last read of this register. 0b1 = Thermal overload has occurred since the last read of this register. This indicates that the junction temperature has exceeded 145ºC. Thermal Overload STAT_GLBL (0x06) BIT 7 6 5 4 3 2 1 0 Field DIDM BOK DOD0_S DOD1_S TJAL2_S TJAL1_S STAT_EN STAT_IRQ Reset OTP 0b1 0b0 0b0 0b0 0b0 0b0 0b0 Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Access Type BITFIELD BITS DESCRIPTION DECODE DIDM 7 Device Identification Bits for Metal Options 0b0 = MAX77658 0b1 = Reserved BOK 6 BOK Interrupt Status 0b0 = Main bias is not ready. 0b1 = Main bias enabled and ready. DOD0_S 5 LDO0 Dropout Detector Rising Status 0b0 = LDO0 is not in dropout. 0b1 = LDO0 is in dropout. DOD1_S 4 LDO1 Dropout Detector Rising Status 0b0 = LDO1 is not in dropout. 0b1 = LDO1 is in dropout. TJAL2_S 3 Thermal Alarm 2 Status 0b0 = The junction temperature is less than TJA2. 0b1 = The junction temperature is greater than TJAL2. TJAL1_S 2 Thermal Alarm 1 Status 0b0 = The junction temperature is less than TJAL1. 0b1 = The junction temperature is greater than TJAL1. STAT_EN 1 Debounced Status for the nEN Input 0b0 = nEN is not active (logic-high). 0b1 = nEN is active (logic-low). STAT_IRQ 0 Software Version of the nIRQ MOSFET Gate Drive 0b0 = Unmasked gate drive is logic-low. 0b1 = Unmasked gate drive is logic-high. INTM_GLBL0 (0x08) 7 6 5 4 3 2 1 0 Field BIT DOD0_RM DOD1_RM TJAL2_RM TJAL1_RM nEN_RM nEN_FM GPI0_RM GPI0_FM Reset 0b1 0b1 0b1 0b1 0b1 0b1 0b1 0b1 Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Access Type BITFIELD DOD0_RM www.analog.com BITS 7 DESCRIPTION LDO Dropout Detector Rising Interrupt Mask DECODE 0b0 = Unmasked. If DOD0_R goes from 0 to 1, then nIRQ goes low. nIRQ goes high when all interrupt bits are cleared. 0b1 = Masked. nIRQ does not go low due to DOD0_R. Analog Devices | 104 MAX77658 BITFIELD DOD1_RM TJAL2_RM TJAL1_RM nEN_RM nEN_FM GPI0_RM GPI0_FM Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ BITS 6 5 4 3 2 1 0 DESCRIPTION DECODE LDO Dropout Detector Rising Interrupt Mask 0b0 = Unmasked. If DOD1_R goes from 0 to 1, then nIRQ goes low. nIRQ goes high when all interrupt bits are cleared. 0b1 = Masked. nIRQ does not go low due to DOD1_R. Thermal Alarm 2 Rising Interrupt Mask 0b0 = Unmasked. If TJAL2_R goes from 0 to 1, then nIRQ goes low. nIRQ goes high when all interrupt bits are cleared. 0b1 = Masked. nIRQ does not go low due to TJAL2_R. Thermal Alarm 1 Rising Interrupt Mask 0b0 = Unmasked. If TJAL1_R goes from 0 to 1, then nIRQ goes low. nIRQ goes high when all interrupt bits are cleared. 0b1 = Masked. nIRQ does not go low due to TJAL1_R. nEN Rising Interrupt Mask 0b0 = Unmasked. If nEN_R goes from 0 to 1, then nIRQ goes low. nIRQ goes high when all interrupt bits are cleared. 0b1 = Masked. nIRQ does not go low due to nEN_R. nEN Falling Interrupt Mask 0b0 = Unmasked. If nEN_F goes from 0 to 1, then nIRQ goes low. nIRQ goes high when all interrupt bits are cleared. 0b1 = Masked. nIRQ does not go low due to nEN_F. GPI Rising Interrupt Mask 0b0 = Unmasked. If GPI_R goes from 0 to 1, then nIRQ goes low. nIRQ goes high when all interrupt bits are cleared. 0b1 = Masked. nIRQ does not go low due to GPI_R. GPI Falling Interrupt Mask 0b0 = Unmasked. If GPI_F goes from 0 to 1, then nIRQ goes low. nIRQ goes high when all interrupt bits are cleared. 0b1 = Masked. nIRQ does not go low due to GPI_F. INTM_GLBL1 (0x09) BIT 7 6 5 4 3 2 1 0 Field RSVD LDO1_M LDO0_M SBB2_FM SBB1_FM SBB0_FM GPI1_RM GPI1_FM Reset 0b0 0b1 0b1 0b1 0b1 0b1 0b1 0b1 Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Access Type BITFIELD RSVD LDO1_M www.analog.com BITS 7 6 DESCRIPTION DECODE Reserved. Unutilized bit. Write to 0. Reads are don't care. LDO1 Fault Interrupt Mask 0b0 = Unmasked. If LDO1_F goes from 0 to 1, then nIRQ goes low. nIRQ goes high when all interrupt bits are cleared. 0b1 = Masked. nIRQ does not go low due to LDO1_F. Analog Devices | 105 MAX77658 BITFIELD LDO0_M SBB2_FM SBB1_FM SBB0_FM GPI1_RM GPI1_FM Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ BITS 5 4 3 2 1 0 DESCRIPTION DECODE LDO0 Fault Interrupt Mask 0b0 = Unmasked. If LDO0_F goes from 0 to 1, then nIRQ goes low. nIRQ goes high when all interrupt bits are cleared. 0b1 = Masked. nIRQ does not go low due to LDO0_F. SBB2 Fault Interrupt Mask 0b0 = Unmasked. If SBB2_F goes from 0 to 1, then nIRQ goes low. nIRQ goes high when all interrupt bits are cleared. 0b1 = Masked. nIRQ does not go low due to SBB2_F. SBB1 Fault Interrupt Mask 0b0= Unmasked. If SBB1_F goes from 0 to 1, then nIRQ goes low. nIRQ goes high when all interrupt bits are cleared. 0b1 = Masked. nIRQ does not go low due to SBB1_F. SBB0 Fault Interrupt Mask 0b0 = Unmasked. If SBB0_F goes from 0 to 1, then nIRQ goes low. nIRQ goes high when all interrupt bits are cleared. 0b1 = Masked. nIRQ does not go low due to SBB0_F. GPI Rising Interrupt Mask 0b0 = Unmasked. If GPI_R goes from 0 to 1, then nIRQ goes low. nIRQ goes high when all interrupt bits are cleared. 0b1 = Masked. nIRQ does not go low due to GPI_R. GPI Falling Interrupt Mask 0b0 = Unmasked. If GPI_F goes from 0 to 1, then nIRQ goes low. nIRQ goes high when all interrupt bits are cleared. 0b1 = Masked. nIRQ does not go low due to GPI_F. CNFG_GLBL (0x10) BIT 7 6 5 Field PU_DIS T_MRST SBIA_LPM nEN_MODE[1:0] DBEN_nEN SFT_CTRL[1:0] Reset 0b0 OTP OTP OTP OTP 0b00 Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Access Type BITFIELD BITS 4 3 DESCRIPTION 2 1 0 DECODE PU_DIS 7 nEN Internal Pullup Resistor 0b0 = Strong internal nEN pullup (200kΩ) 0b1 = Weak internal nEN pullup (10MΩ) T_MRST 6 Sets the Manual Reset Time (tMRST) 0b0 = 8s 0b1 = 4s SBIA_LPM 5 Main Bias Low-Power Mode Software Request 0b0 = Main bias requested to be in normal-power mode by software. 0b1 = Main bias requested to be in low-power mode by software. nEN Input (ON-KEY) Default Configuration Mode 0b00 = Push-button mode 0b01 = Slide-switch mode 0b10 = Logic mode 0b11 = Reserved nEN_MODE www.analog.com 4:3 Analog Devices | 106 MAX77658 BITFIELD DBEN_nEN Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ BITS 2 DESCRIPTION DECODE 0b0 = 500μs Debounce 0b1 = 30ms Debounce Debounce Timer Enable for the nEN Pin Software Reset Functions SFT_CTRL 1:0 Note that the SFT_CRST and SFT_OFF commands initiate the power-down sequence flow as described in the data sheet. This power-down sequence flow has delay elements that add up to 205.24ms (60ms delay + 10.24ms nRST assert delay + 4x2.56ms power-down slot delays + 125ms output discharge delay). If issuing the SFT_CRST and/or SFT_OFF functions in software, wait for more than 300ms before trying to issue any additional commands through I2C. 0b00 = No action 0b01 = Software cold reset (SFT_CRST). The device powers down, resets, and then powers up again. 0b10 = Software off (SFT_OFF). The device powers down, resets, and then remains off and waiting for a wake-up event. 0b11 = Reserved CNFG_GPIO0 (0x11) BIT 7 6 5 4 3 2 1 0 Field SBB_F_SH UTDN – ALT_GPIO0 DBEN_GPI DO DRV DI DIR Reset OTP – OTP 0b0 0b0 0b0 0b0 0b1 Write, Read – Write, Read Write, Read Write, Read Write, Read Read Only Write, Read Access Type BITFIELD SBB_F_SHU TDN BITS 7 DESCRIPTION DECODE SBB Shutdown from SBB Fault 0b0 = The SBB regulator does not shut off when an SBB fault occurs 0b1 = The SBB regulator powers down sequentially when an SBB fault occurs ALT_GPIO0 5 Alternate Mode Enable for GPIO0 0b0 = Standard GPIO 0b1 = Active-high input, Force USB Suspend (FUS). FUS is only active if the FUS_M bit is set to 0 DBEN_GPI 4 General Purpose Input Debounce Timer Enable for GPI0 0b0 = No debounce 0b1 = 30ms Debounce This bit is a don't care when DIR = 1 (configured as input). DO 3 General Purpose Output Data Output for GPO0 When set for GPO (DIR = 0): 0b0 = GPIO is output logic-low. 0b1 = GPIO is output logic-high when set as pushpull output (DRV = 1). GPIO is high-impedance when set as an open-drain output (DRV = 0). This bit is a don't care when DIR = 1 (configured as input). DRV 2 General Purpose Output Driver Type for GPO0 DI 1 GPIO Digital Input Value for GPI0. Irrespective of whether the GPIO is set for GPI (DIR = 1) or GPO (DIR = 0), DI reflects the state of the GPIO. www.analog.com When set for GPO (DIR = 0): 0b0 = Open-drain 0b1 = Push-pull 0 = Input logic-low 1 = Input logic-high Analog Devices | 107 MAX77658 BITFIELD DIR Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ BITS 0 DESCRIPTION DECODE 0b0 = General purpose output (GPO) 0b1 = General purpose input (GPI) GPIO Direction for GPIO0 CNFG_GPIO1 (0x12) 5 4 3 2 1 0 Field BIT 7 RSVD[1:0] ALT_GPIO1 DBEN_GPI DO DRV DI DIR Reset 0b00 OTP 0b0 0b0 0b0 0b0 0b1 Write, Read Write, Read Write, Read Write, Read Write, Read Read Only Write, Read Access Type BITFIELD RSVD 6 BITS 7:6 DESCRIPTION DECODE Reserved. Unutilized bit. Write to 0. Reads are don't care. ALT_GPIO1 5 Alternate Mode Enable for GPIO1 0b0 = Standard GPIO 0b1 = Active-high input, enable DVS control for SBB0: If GPIO1 = 0, SBB0 is set by TV_SBB0; If GPIO1 = 1, SBB0 is set by TV_SBB0_DVS DBEN_GPI 4 General Purpose Input Debounce Timer Enable for GPI1 0b0 = No debounce 0b1 = 30ms Debounce This bit is a don't care when DIR = 1 (configured as input). DO General Purpose Output Data Output for GPO1 3 When set for GPO (DIR = 0): 0b0 = GPIO is output logic-low. 0b1 = GPIO is output logic-high when set as pushpull output (DRV = 1). GPIO is high-impedance when set as an open-drain output (DRV = 0). This bit is a don't care when DIR = 1 (configured as input). 2 General Purpose Output Driver Type for GPO1 DI 1 GPIO Digital Input Value for GPI1. Irrespective of whether the GPIO is set for GPI (DIR = 1) or GPO (DIR = 0), DI reflects the state of the GPIO. 0 = Input logic-low 1 = Input logic-high DIR 0 GPIO Direction for GPIO1 0b0 = General purpose output (GPO) 0b1 = General purpose input (GPI) DRV When set for GPO (DIR = 0): 0b0 = Open-drain 0b1 = Push-pull CNFG_GPIO2 (0x13) 5 4 3 2 1 0 Field BIT RSVD[1:0] ALT_GPIO2 DBEN_GPI DO DRV DI DIR Reset 0b00 OTP 0b0 0b0 0b0 0b0 0b1 Write, Read Write, Read Write, Read Write, Read Write, Read Read Only Write, Read Access Type BITFIELD RSVD www.analog.com 7 6 BITS 7:6 DESCRIPTION DECODE Reserved. Unutilized bit. Write to 0. Reads are don't care. Analog Devices | 108 MAX77658 BITFIELD Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ BITS DESCRIPTION DECODE ALT_GPIO2 5 Alternate Mode Enable for GPIO2. 0b0 = Standard GPIO 0b1 = Active-high input, enable DISQBAT control: If GPIO2 = 0, DISQBAT is disabled; If GPIO2 = 1, DISQBAT is enabled DBEN_GPI 4 General Purpose Input Debounce Timer Enable for GPI2 0b0 = No debounce 0b1 = 30ms debounce This bit is a don't care when DIR = 1 (configured as input). DO General Purpose Output Data Output for GPO2 3 When set for GPO (DIR = 0): 0b0 = GPIO is output logic low. 0b1 = GPIO is output logic high when set as pushpull output (DRV = 1). GPIO is high-impedance when set as an open-drain output (DRV = 0). This bit is a don't care when DIR = 1 (configured as input). DRV 2 General Purpose Output Driver Type for GPO2 DI 1 GPIO Digital Input Value for GPI2. Irrespective of whether the GPIO is set for GPI (DIR = 1) or GPO (DIR = 0), DI reflects the state of the GPIO. 0 = Input logic-low 1 = Input logic-high DIR 0 GPIO Direction for GPIO2 0b0 = General purpose output (GPO) 0b1 = General purpose input (GPI) When set for GPO (DIR = 0): 0b0 = Open-drain 0b1 = Push-pull CID (0x14) 7 6 5 Field BIT – – – CID[4:0] Reset – – – OTP Access Type – – – Read Only BITFIELD CID 4 3 2 1 0 BITS DESCRIPTION 4:0 Chip Identification Code The chip identification code refers to a set of reset values in the register map, or the "OTP configuration." CNFG_WDT (0x17) BIT 7 6 5 4 3 2 1 0 WDT_CLR WDT_EN WDT_LOC K Field RSVD[1:0] WDT_PER[1:0] WDT_MOD E Reset 0b00 0b11 0b0 0b0 OTP OTP Write, Read Write, Read Write, Read Write, Read Write, Read Read Only Access Type BITFIELD RSVD www.analog.com BITS 7:6 DESCRIPTION DECODE Reserved. Unutilized bit. Write to 0. Reads are don't care. Analog Devices | 109 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ BITFIELD WDT_PER BITS DESCRIPTION DECODE 5:4 Watchdog Timer Period. Sets tWD. Watchdog timer is reset to the programmed value as soon as this bitfield is changed. 0b00 = 16 seconds 0b01 = 32 seconds 0b10 = 64 seconds 0b11 = 128 seconds WDT_MODE 3 Watchdog Timer Expired Action. Determines what the IC does after the watchdog timer expires. 0b0 = Watchdog timer expire causes power-off. 0b1 = Watchdog timer expire causes power-reset. WDT_CLR 2 Watchdog Timer Clear Control. Set this bit to feed (reset) the watchdog timer. 0b0 = Watchdog timer period is not reset. 0b1 = Watchdog timer is reset back to tWD. WDT_EN 1 Watchdog Timer Enable. Write protected depending on WDT_LOCK. 0b0 = Watchdog timer is not enabled. 0b1 = Watchdog timer is enabled. The timer expires if not reset by setting WDT_CLR. 0 Factory-Set Safety Bit for the Watchdog Timer. Determines if the timer can be disabled through WDT_EN or not. 0b0 = Watchdog timer can be enabled and disabled with WDT_EN. 0b1 = Watchdog timer can not be disabled with WDT_EN. However, WDT_EN can still be used to enable the watchdog timer. WDT_LOCK INT_CHG (0x01) BIT 7 6 5 4 3 2 1 0 Field RSVD SYS_CNFG _I SYS_CTRL _I CHGIN_CT RL_I TJ_REG_I CHGIN_I CHG_I THM_I Reset 0b0 0b0 0b0 0b0 0b0 0b0 0b0 0b0 Read Clears All Read Clears All Read Clears All Read Clears All Read Clears All Read Clears All Read Clears All Read Clears All Access Type BITFIELD RSVD SYS_CNFG_ I SYS_CTRL_I CHGIN_CTR L_I TJ_REG_I www.analog.com BITS 7 DESCRIPTION DECODE Reserved. Unutilized bit. Write to 0. Reads are don't care. 6 System Voltage Configuration Error Interrupt 0b0 = The bit combination in CHG_CV has not been forced to change since the last time this bit was read. 0b1 = The bit combination in CHG_CV has been forced to change to ensure VSYS-REG = VFASTCHG + 200mV since the last time this bit was read. 5 Minimum System Voltage Regulation-Loop Related Interrupt. This interrupt signals a change in the status bit VSYS_MIN_STAT. 0b0 = The minimum system voltage regulation loop has not engaged since the last time this bit was read. 0b1 = The minimum system voltage regulation loop has engaged since the last time this bit was read. 4 CHGIN Control-Loop Related Interrupt. This bit asserts when the input reaches current limit (ICHGIN-LIM) or VCHGIN falls below VCHGIN_MIN. 0b0 = Neither the VCHGIN_MIN_STAT nor the ICHGIN_LIM_STAT bits have changed since the last time this bit was read. 0b1 = The VCHGIN_MIN_STAT or ICHGIN_LIM_STAT bits have changed since the last time this bit was read. 3 Die Junction Temperature Regulation Interrupt. This bit asserts when the die temperature (TJ) exceeds TJ-REG. This interrupt signals a change in the status bit TJ_REG_STAT. 0b0 = The die temperature has not exceeded TJREG since the last time this bit was read. 0b1 = The die temperature has exceeded TJ-REG since the last time this bit was read. Analog Devices | 110 MAX77658 BITFIELD Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ BITS DESCRIPTION DECODE CHGIN_I 2 CHGIN Related Interrupt 0b0 = The bits in CHGIN_DTLS[1:0] have not changed since the last time this bit was read. 0b1 = The bits in CHGIN_DTLS[1:0] have changed since the last time this bit was read. CHG_I 1 Charger Related Interrupt 0b0 = The bits in CHG_DTLS[3:0] have not changed since the last time this bit was read. 0b1 = The bits in CHG_DTLS[3:0] have changed since the last time this bit was read. Thermistor Related Interrupt 0b0 = The bits in THM_DTLS[2:0] have not changed since the last time this bit was read. 0b1 = The bits in THM_DTLS[2:0] have changed since the last time this bit was read. THM_I 0 STAT_CHG_A (0x02) BIT 7 6 5 4 3 Field RSVD VCHGIN_M IN_STAT ICHGIN_LI M_STAT VSYS_MIN _STAT TJ_REG_S TAT THM_DTLS[2:0] Reset 0b0 0b0 0b0 0b0 0b0 0b000 Read Only Read Only Read Only Read Only Read Only Read Only Access Type BITFIELD RSVD VCHGIN_MI N_STAT ICHGIN_LIM _STAT VSYS_MIN_ STAT TJ_REG_ST AT www.analog.com BITS 7 DESCRIPTION 2 1 0 DECODE Reserved. Unutilized bit. Write to 0. Reads are don't care. Minimum Input Voltage Regulation Loop Status 0b0 = The minimum CHGIN voltage regulation loop is not engaged. 0b1 = The minimum CHGIN voltage regulation loop has engaged to regulate VCHGIN ≥ VCHGINMIN. 5 Input Current Limit Loop Status 0b0 = The CHGIN current limit loop is not engaged. 0b1 = The CHGIN current limit loop has engaged to regulate ICHGIN ≤ ICHGIN-LIM. 4 Minimum System Voltage Regulation Loop Status 0b0 = The minimum system voltage regulation loop is not enganged. 0b1 = The minimum system voltage regulation loop is engaged to regulate VSYS ≥ VSYS-MIN. Maximum Junction Temperature Regulation Loop Status 0b0 = The maximum junction temperature regulation loop is not engaged. 0b1 = The maximum junction temperature regulation loop has engaged to regulate the junction temperature to less than TJ-REG. 6 3 Analog Devices | 111 MAX77658 BITFIELD THM_DTLS Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ BITS 2:0 DESCRIPTION DECODE Battery Temperature Details. Valid only when CHGIN_DTLS[1:0] = 0b11. 0b000 = Thermistor is disabled (Config.TSel = 0). 0b001 = Battery is cold as programmed by THM_COLD[1:0]. If thermistor and charger are enabled while the battery is cold, a battery temperature fault occurs. 0b010 = Battery is cool as programmed by THM_COOL[1:0]. 0b011 = Battery is warm as programmed by THM_WARM[1:0]. 0b100 = Battery is hot as programmed by THM_HOT[1:0]. If thermistor and charger are enabled while the battery is hot, a battery temperature fault occurs. 0b101 = Battery is in the normal temperature region. 0b110 to 0b111 = Reserved. STAT_CHG_B (0x03) BIT 7 6 5 4 3 2 1 0 Field CHG_DTLS[3:0] CHGIN_DTLS[1:0] CHG TIME_SUS Reset 0x0 0b00 0b0 0b0 Read Only Read Only Read Only Read Only Access Type BITFIELD CHG_DTLS CHGIN_DTL S CHG www.analog.com BITS DESCRIPTION DECODE Charger Details 0b0000 = Off 0b0001 = Prequalification mode. 0b0010 = Fast-charge constant-current (CC) mode. 0b0011 = JEITA modified fast-charge constantcurrent mode. 0b0100 = Fast-charge constant-voltage (CV) mode. 0b0101 = JEITA modified fast-charge constantvoltage mode. 0b0110 = Top-off mode. 0b0111 = JEITA modified top-off mode. 0b1000 = Done 0b1001 = JEITA modified done (done was entered through the JEITA-modified fast-charge states). 0b1010 = Prequalification timer fault. 0b1011 = Fast-charge timer fault. 0b1100 = Battery temperature fault. 0b1101 to 0b1111 = Reserved. 3:2 CHGIN Status Detail 0b00 = The CHGIN input voltage is below the UVLO threshold (VCHGIN < VUVLO). 0b01 = The CHGIN input voltage is above the OVP threshold (VCHGIN > VOVP). 0b10 = The CHGIN input is being debounced (no power accepted from CHGIN during debounce). 0b11 = The CHGIN input is okay and debounced. 1 Quick Charger Status 0b0 = Charging is not happening. 0b1 = Charging is happening. 7:4 Analog Devices | 112 MAX77658 BITFIELD TIME_SUS Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ BITS DESCRIPTION 0 DECODE 0b0 = The charger's timers are either not active, or not suspended. 0b1 = The charger's active timer is suspended due to one of three reasons: charge current dropped below 20% of IFAST-CHG while the charger state machine is in FAST CHARGE CC mode, the charger is in SUPPLEMENT mode, or the charger state machine is in BATTERY TEMPERATURE FAULT mode. Time Suspend Indicator INT_M_CHG (0x07) BIT 7 6 5 4 3 2 1 0 Field DIS_AICL SYS_CNFG _M SYS_CTRL _M CHGIN_CT RL_M TJ_REG_M CHGIN_M CHG_M THM_M Reset 0b0 0b1 0b1 0b1 0b1 0b1 0b1 0b1 Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Access Type BITFIELD BITS DESCRIPTION DECODE DIS_AICL 7 Active Input Current Loop Disable 0b0 = Active input current loop active 0b1 = Active input current loop disabled SYS_CNFG_ M 6 Setting this bit prevents the SYS_CNFG_I bit from causing hardware IRQs. 0b0 = SYS_CNFG_I is not masked. 0b1 = SYS_CNFG_I is masked. SYS_CTRL_ M 5 Setting this bit prevents the SYS_CTRL_I bit from causing hardware IRQs. 0b0 = SYS_CTRL_I is not masked. 0b1 = SYS_CTRL_I is masked. CHGIN_CTR L_M 4 Setting this bit prevents the CHGIN_CTRL_I bit from causing hardware IRQs. 0b0 = CHGIN_CTRL_I is not masked. 0b1 = CHGIN_CTRL_I is masked. TJ_REG_M 3 Setting this bit prevents the TJREG_I bit from causing hardware IRQs. 0b0 = TJREG_I is not masked. 0b1 = TJREG_I is masked. CHGIN_M 2 Setting this bit prevents the CHGIN_I bit from causing hardware IRQs. 0b0 = CHGIN_I is not masked. 0b1 = CHGIN_I is masked. CHG_M 1 Setting this bit prevents the CHG_I bit from causing hardware IRQs. 0b0 = CHG_I is not masked. 0b1 = CHG_I is masked. THM_M 0 Setting this bit prevents the THM_I bit from causing hardware IRQs. 0b0 = THM_I is not masked. 0b1 = THM_I is masked. CNFG_CHG_A (0x20) BIT 7 6 5 4 3 2 1 0 Field THM_HOT[1:0] THM_WARM[1:0] THM_COOL[1:0] THM_COLD[1:0] Reset 0b00 0b00 0b11 0b11 Write, Read Write, Read Write, Read Write, Read Access Type BITFIELD THM_HOT www.analog.com BITS DESCRIPTION 7:6 Sets the THOT JEITA Temperature Threshold DECODE 0b00 = THOT = 45ºC 0b01 = THOT = 50ºC 0b10 = THOT = 55ºC 0b11 = THOT = 60ºC Analog Devices | 113 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ BITFIELD BITS THM_WARM 5:4 Sets the TWARM JEITA Temperature Threshold 0b00 = TWARM = 35ºC 0b01 = TWARM = 40ºC 0b10 = TWARM = 45ºC 0b11 = TWARM = 50ºC THM_COOL 3:2 Sets the TCOOL JEITA Temperature Threshold 0b00 = TCOOL = 0ºC 0b01 = TCOOL = 5ºC 0b10 = TCOOL = 10ºC 0b11 = TCOOL = 15ºC 1:0 Sets the TCOLD JEITA Temperature Threshold 0b00 = TCOLD = -10ºC 0b01 = TCOLD = -5ºC 0b10 = TCOLD = 0ºC 0b11 = TCOLD = 5ºC THM_COLD DESCRIPTION DECODE CNFG_CHG_B (0x21) BIT 7 6 5 4 3 2 1 0 Field VCHGIN_MIN[2:0] ICHGIN_LIM[2:0] I_PQ CHG_EN Reset 0b000 0b000 0b0 OTP Write, Read Write, Read Write, Read Write, Read Access Type BITFIELD VCHGIN_MI N ICHGIN_LIM BITS 7:5 4:2 DESCRIPTION DECODE Minimum CHGIN Regulation Voltage (VCHGIN-MIN) 0b000 = 4.0V 0b001 = 4.1V 0b010 = 4.2V 0b011 = 4.3V 0b100 = 4.4V 0b101 = 4.5V 0b110 = 4.6V 0b111 = 4.7V CHGIN Input Current Limit (ICHGIN-LIM) 0b000 = 475mA 0b001 = 380mA 0b010 = 285mA 0b011 = 190mA 0b100 = 95mA 0b101 to 0b111 = Reserved. Defaults to 0b100. I_PQ 1 Sets the prequalification charge current (IPQ) as a percentage of IFAST-CHG. 0b0 = 10% 0b1 = 20% CHG_EN 0 Charger Enable Default value defined by OTP bit CHG_EN_DFT: 0b0 = The battery charger is disabled. 0b1 = The battery charger is enabled. CNFG_CHG_C (0x22) BIT 7 6 5 4 3 2 1 0 Field CHG_PQ[2:0] I_TERM[1:0] T_TOPOFF[2:0] Reset 0b111 0b11 0b000 Write, Read Write, Read Write, Read Access Type www.analog.com Analog Devices | 114 MAX77658 BITFIELD CHG_PQ I_TERM T_TOPOFF Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ BITS DESCRIPTION DECODE 7:5 Battery Prequalification Voltage Threshold (VPQ) 0b000 = 2.3V 0b001 = 2.4V 0b010 = 2.5V 0b011 = 2.6V 0b100 = 2.7V 0b101 = 2.8V 0b110 = 2.9V 0b111 = 3.0V 4:3 Charger Termination Current (ITERM). I_TERM[1:0] sets the charger termination current as a percentage of the fast-charge current IFAST-CHG. 0b00 = 5% 0b01 = 7.5% 0b10 = 10% 0b11 = 15% Top-Off Timer Value (tTO) 0b000 = 0 minutes 0b001 = 5 minutes 0b010 = 10 minutes 0b011 = 15 minutes 0b100 = 20 minutes 0b101 = 25 minutes 0b110 = 30 minutes 0b111 = 35 minutes 2:0 CNFG_CHG_D (0x23) BIT 7 6 5 4 3 2 1 Field TJ_REG[2:0] VSYS_REG[4:0] Reset 0b000 0b10110 Write, Read Write, Read Access Type BITFIELD TJ_REG BITS 7:5 DESCRIPTION DECODE Sets the die junction temperature regulation point, TJ-REG. System Voltage Regulation (VSYS-REG) VSYS_REG 4:0 0 This 5-bit configuration is a linear transfer function that starts at 3.4V and ends at 4.8V, with 50mV increments. Program VSYS_REG to at least 200mV above the higher of VFAST-CHG and VFAST-CHGJEITA. 0b000 = 60ºC 0b001 = 70ºC 0b010 = 80ºC 0b011 = 90ºC 0b100 to 0b111 = 100ºC 0x0 = 3.400V 0x1 = 3.450V 0x2 = 3.500V ... 0x1B = 4.750V 0x1C - 0x1F = 4.800V CNFG_CHG_E (0x24) BIT 7 6 5 4 3 2 1 0 Field CHG_CC[5:0] T_FAST_CHG[1:0] Reset 0b000001 0b01 Write, Read Write, Read Access Type www.analog.com Analog Devices | 115 MAX77658 BITFIELD Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ BITS DESCRIPTION DECODE Sets the fast-charge constant current value, IFAST-CHG. CHG_CC T_FAST_CH G 7:2 1:0 This 6-bit configuration is a transfer function with 7.5mA increments starts at 7.5mA and ends at 300mA, with 7.5mA increments. Sets the fast-charge safety timer, tFC. 0x0 = 7.5mA 0x1 = 15.0mA 0x2 = 22.5mA ... 0x26 = 292.5mA 0x27 to 0x3F = 300.0mA 0b00 = Timer disabled 0b01 = 3 hours 0b10 = 5 hours 0b11 = 7 hours CNFG_CHG_F (0x25) BIT 7 6 5 4 Field CHG_CC_JEITA[5:0] Reset 0b000001 Access Type BITFIELD CHG_CC_JE ITA 2 Write, Read BITS 7:2 1 1 0 RSVD – – Write, Read DESCRIPTION – DECODE Sets the modified IFAST-CHG-JEITA for when the battery is either cool or warm as defined by the THM_HOT, THM_WARM, THM_COOL, and THM_COLD temperature thresholds. This register is a don't care if the battery temperature is normal. This 6-bit configuration is a transfer function with 7.5mA increments starts at 7.5mA and ends at 300mA, with 7.5mA increments. RSVD 3 0x0 = 7.5mA 0x1 = 15.0mA 0x2 = 22.5mA ... 0x26 = 292.5mA 0x27 to 0x3F = 300mA Reserved. Unutilized bit. Write to 0. Reads are don't care. CNFG_CHG_G (0x26) 1 0 Field BIT 7 CHG_CV[5:0] USBS FUS_M Reset 0b000000 0b0 0b1 Write, Read Write, Read Write, Read Access Type BITFIELD BITS 6 5 4 DESCRIPTION Sets fast-charge battery regulation voltage, VFAST-CHG. CHG_CV 7:2 This 6-bit configuration is a linear transfer function that starts at 3.6V and ends at 4.6V, with 25mV increments. Program VSYS_REG to at least 200mV above the higher of VFAST-CHG and VFAST-CHGJEITA if CNFG_CHG_H.SYS_BAT_PRT = 1. www.analog.com 3 2 DECODE 0x0 = 3.600V 0x1 = 3.625V 0x2 = 3.650V ... 0x27 = 4.575V 0x28 to 0x3F = 4.600V Analog Devices | 116 MAX77658 BITFIELD USBS Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ BITS 1 DESCRIPTION DECODE Setting this bit places CHGIN in USB suspend mode. 0b0 = CHGIN is not suspended and can draw current from an adapter source. 0b1 = CHGIN is suspended and can not draw current from an adapter source. Note: USBS = 1 results in CHGIN_I interrupt AND CHGIN_DTLS[1:0] = 0b00. FUS_M 0 FUS (ALT mode of GPIO0) is only active if the FUS_M bit is set to 0. See the GPIO Alternate Mode section for more details. Forced USB Suspend Mask CNFG_CHG_H (0x27) BIT 7 6 5 4 3 2 1 0 CHR_TH_E N Field CHG_CV_JEITA[5:0] SYS_BAT_ PRT Reset 0b000000 0b1 0b1 Write, Read Write, Read Write, Read Access Type BITFIELD BITS DESCRIPTION Sets the modified VFAST-CHG-JEITA for when the battery is either cool or warm as defined by the THM_HOT, THM_WARM, THM_COOL, and THM_COLD temperature thresholds. This register is a don't care if the battery temperature is normal. CHG_CV_JE ITA 7:2 This 6-bit configuration is a linear transfer function that starts at 3.6V and ends at 4.6V, with 25mV increments. DECODE 0x0 = 3.600V 0x1 = 3.625V 0x2 = 3.650V ... 0x27 = 4.575V 0x28 to 0x3F = 4.600V Program VSYS_REG to at least 200mV above the higher of VFAST-CHG and VFAST-CHGJEITA if CNFG_CHG_H.SYS_BAT_PRT = 1. SYS_BAT_P RT 1 VSYS_REG - CHG_CV Clamp By default, the VSYS_REG has to be at least 200mV higher than the programmed CHG_CV. If this bit is cleared (hardware protection is turned off), the software has to provide the protection (the SYS voltage has to be 200mV higher than the BATT voltage). If the VSYS_REG is lower than CHG_CV+200mV, the charger reduces CHG_CV to satisfy the 200mV requirement. CHR_TH_EN 0 Charger Restart Threshold Enable www.analog.com 0b0 = VSYS_REG-CHG_CV, 200mV clamp disabled 0b1 = VSYS_REG-CHG_CV, 200mV clamp enabled 0b0 = Restart threshold disabled 0b1 = Restart threshold enabled Analog Devices | 117 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ CNFG_CHG_I (0x28) BIT 7 6 5 4 3 2 1 Field IMON_DISCHG_SCALE[3:0] MUX_SEL[3:0] Reset 0xF 0x0 Write, Read Write, Read Access Type BITFIELD IMON_DISC HG_SCALE BITS 7:4 DESCRIPTION DECODE Selects the battery discharge current fullscale current value. Selects the analog channel to connect to AMUX: MUX_SEL 3:0 0 Note that the multiplexer consumes current unless it is in the 0b0000 state. When measurements are not needed, make sure to configure MUX_SEL[3:0] = 0b0000. Also note that for AMUX to operate, the on/off controller must be in the "Resource On" state. 0x0 = 8.2mA 0x1 = 40.5mA 0x2 = 72.3mA 0x3 = 103.4mA 0x4 = 134.1mA 0x5 = 164.1mA 0x6 = 193.7mA 0x7 = 222.7mA 0x8 = 251.2mA 0x9 = 279.3mA 0xA to 0xF = 300.0mA 0b0000 = Multiplexer is disabled and AMUX is high-impedance. 0b0001 = CHGIN voltage monitor. 0b0010 = CHGIN current monitor. 0b0011 = BATT voltage monitor. 0b0100 = BATT charge current monitor. Valid only while battery charging is happening (CHG = 1). 0b0101 = BATT discharge current monitor normal measurement. 0b0110 = BATT discharge current monitor nulling measurement. 0b0111 = Reserved. 0b1000 = Reserved. 0b1001 = AGND voltage monitor (through 100Ω pulldown resistor). 0b1010 to 0b1111 = SYS voltage monitor. CNFG_SBB_TOP (0x38) 7 6 5 4 3 2 1 Field BIT DIS_LPM IPK_1P5A – – – – DRV_SBB[1:0] Reset 0b0 0b0 – – – – 0b00 Write, Read Write, Read – – – – Write, Read Access Type BITFIELD DIS_LPM IPK_1P5A www.analog.com BITS 7 6 DESCRIPTION 0 DECODE Disables the automatic low-power mode for each SIMO channel. 0b0 = Automatic low-power mode for each SIMO channel. 0b1 = Disable LPM feature for each SIMO channel. SBB2 Inductor Current Limit Offset 0b0 = SBB2 inductor current limit is 1.0A if CNFG_SBB_B.IP_SBB2[1:0] = 0b00. 0b1 = SBB2 inductor current limit is 1.5A if CNFG_SBB_B.IP_SBB2[1:0] = 0b00. Analog Devices | 118 MAX77658 BITFIELD DRV_SBB Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ BITS DESCRIPTION DECODE SIMO Buck-Boost (all channels) Drive Strength Trim See the Drive Strength section for more details. 1:0 0b00 = Fastest transition time. 0b01 = A little slower than 0b00. 0b10 = A little slower than 0b01. 0b11 = A little slower than 0b10. CNFG_SBB0_A (0x39) BIT 7 6 5 4 3 Field TV_SBB0[7:0] Reset OTP Access Type BITFIELD TV_SBB0 2 1 0 Write, Read BITS DESCRIPTION DECODE SIMO Buck-Boost Channel 0 Target Output Voltage This 8-bit configuration is a linear transfer function that starts at 0.5V, ends at 5.5V, with 25mV increments. 7:0 0x00 = 0.500V 0x01 = 0.525V 0x02 = 0.550V 0x03 = 0.575V 0x04 = 0.600V 0x05 = 0.625V 0x06 = 0.650V 0x07 = 0.675V 0x08 = 0.700V ... 0xC5 = 5.425V 0xC6 = 5.450V 0xC7 = 5.475V 0xC8 to 0xFF = 5.500V CNFG_SBB0_B (0x3A) BIT 7 6 5 4 3 2 1 0 Field OP_MODE[1:0] IP_SBB0[1:0] ADE_SBB0 EN_SBB0[2:0] Reset OTP OTP OTP OTP Write, Read Write, Read Write, Read Write, Read Access Type BITFIELD OP_MODE IP_SBB0 www.analog.com BITS DESCRIPTION DECODE 7:6 Operation Mode of SBB0 0b00 = Automatic 0b01 = Buck mode 0b10 = Boost mode 0b11 = Buck-boost mode 5:4 SIMO Buck-Boost Channel 0 Peak Current Limit 0b00 = 1.000A 0b01 = 0.750A 0b10 = 0.500A 0b11 = 0.333A Analog Devices | 119 MAX77658 BITFIELD ADE_SBB0 EN_SBB0 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ BITS DESCRIPTION 3 2:0 DECODE SIMO Buck-Boost Channel 0 ActiveDischarge Enable 0b0 = The active discharge function is disabled. When SBB0 is disabled, its discharge rate is a function of the output capacitance and the external load. 0b1 = The active discharge function is enabled. When SBB0 is disabled, an internal resistor (RAD_SBB0) is activated from SBB0 to PGND to help the output voltage discharge. The output voltage discharge rate is a function of the output capacitance, the external loading, and the internal RAD_SBB0 load. Enable Control for SIMO Buck-Boost Channel 0, selecting either an FPS slot the channel powers-up and powers-down in or whether the channel is forced on or off. 0b000 = FPS slot 0 0b001 = FPS slot 1 0b010 = FPS slot 2 0b011 = FPS slot 3 0b100 = Off irrespective of FPS 0b101 = Same as 0b100 0b110 = On irrespective of FPS 0b111 = Same as 0b110 CNFG_SBB1_A (0x3B) BIT 7 6 5 4 3 Field TV_SBB1[7:0] Reset OTP Access Type BITFIELD TV_SBB1 2 1 0 Write, Read BITS DESCRIPTION DECODE SIMO Buck-Boost Channel 1 Target Output Voltage This 8-bit configuration is a linear transfer function that starts at 0.5V, ends at 5.5V, with 25mV increments. 7:0 0x00 = 0.500V 0x01 = 0.525V 0x02 = 0.550V 0x03 = 0.575V 0x04 = 0.600V 0x05 = 0.625V 0x06 = 0.650V 0x07 = 0.675V 0x08 = 0.700V ... 0xC5 = 5.425V 0xC6 = 5.450V 0xC7 = 5.475V 0xC8 to 0xFF = 5.500V CNFG_SBB1_B (0x3C) BIT 7 6 5 4 3 2 1 0 Field OP_MODE[1:0] IP_SBB1[1:0] ADE_SBB1 EN_SBB1[2:0] Reset OTP OTP OTP OTP Write, Read Write, Read Write, Read Write, Read Access Type www.analog.com Analog Devices | 120 MAX77658 BITFIELD Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ BITS DESCRIPTION DECODE OP_MODE 7:6 Operation Mode of SBB1 0b00 = Automatic 0b01 = Buck mode 0b10 = Boost mode 0b11 = Buck-boost mode IP_SBB1 5:4 SIMO Buck-Boost Channel 1 Peak Current Limit 0b00 = 1.000A 0b01 = 0.750A 0b10 = 0.500A 0b11 = 0.333A SIMO Buck-Boost Channel 1 ActiveDischarge Enable 0b0 = The active discharge function is disabled. When SBB1 is disabled, its discharge rate is a function of the output capacitance and the external load. 0b1 = The active discharge function is enabled. When SBB1 is disabled, an internal resistor (RAD_SBB1) is activated from SBB1 to PGND to help the output voltage discharge. The output voltage discharge rate is a function of the output capacitance, the external loading, and the internal RAD_SBB1 load. Enable control for SIMO buck-boost channel 1, selecting either an FPS slot the channel powers-up and powers-down in or whether the channel is forced on or off. 0b000 = FPS slot 0 0b001 = FPS slot 1 0b010 = FPS slot 2 0b011 = FPS slot 3 0b100 = Off irrespective of FPS 0b101 = Same as 0b100 0b110 = On irrespective of FPS 0b111 = Same as 0b110 ADE_SBB1 EN_SBB1 3 2:0 CNFG_SBB2_A (0x3D) BIT 7 6 5 4 3 Field TV_SBB2[7:0] Reset OTP Access Type BITFIELD TV_SBB2 www.analog.com 2 1 0 Write, Read BITS 7:0 DESCRIPTION SIMO Buck-Boost Channel 2 Target Output Voltage This 8-bit configuration is a linear transfer function that starts at 0.5V, ends at 5.5V, with 25mV increments. DECODE 0x00 = 0.500V 0x01 = 0.525V 0x02 = 0.550V 0x03 = 0.575V 0x04 = 0.600V 0x05 = 0.625V 0x06 = 0.650V 0x07 = 0.675V 0x08 = 0.700V ... 0xC5 = 5.425V 0xC6 = 5.450V 0xC7 = 5.475V 0xC8 to 0xFF = 5.500V Analog Devices | 121 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ CNFG_SBB2_B (0x3E) BIT 7 6 5 4 3 2 1 0 Field OP_MODE[1:0] IP_SBB2[1:0] ADE_SBB2 EN_SBB2[2:0] Reset OTP OTP OTP OTP Write, Read Write, Read Write, Read Write, Read Access Type BITFIELD OP_MODE IP_SBB2 ADE_SBB2 EN_SBB2 BITS 7:6 5:4 3 2:0 DESCRIPTION DECODE Operation Mode of SBB2 0b00 = Automatic 0b01 = Buck mode 0b10 = Boost mode 0b11 = Buck-boost mode SIMO Buck-Boost Channel 2 Peak Current Limit 0b00 = 1.000A if CNFG_SBB_TOP.IPK_1P5A = 0; 1.500A if CNFG_SBB_TOP.IPK_1P5A = 1 0b01 = 0.750A 0b10 = 0.500A 0b11 = 0.333A SIMO Buck-Boost Channel 2 ActiveDischarge Enable 0b0 = The active discharge function is disabled. When SBB2 is disabled, its discharge rate is a function of the output capacitance and the external load. 0b1 = The active discharge function is enabled. When SBB2 is disabled, an internal resistor (RAD_SBB2) is activated from SBB2 to PGND to help the output voltage discharge. The output voltage discharge rate is a function of the output capacitance, the external loading, and the internal RAD_SBB2 load. Enable control for SIMO buck-boost channel 2, selecting either an FPS slot the channel powers-up and powers-down in or whether the channel is forced on or off. 0b000 = FPS slot 0 0b001 = FPS slot 1 0b010 = FPS slot 2 0b011 = FPS slot 3 0b100 = Off irrespective of FPS 0b101 = Same as 0b100 0b110 = On irrespective of FPS 0b111 = Same as 0b110 CNFG_DVS_SBB0_A (0x3F) BIT 7 6 5 4 3 Field TV_SBB0_DVS[7:0] Reset 0x00 Access Type www.analog.com 2 1 0 Write, Read Analog Devices | 122 MAX77658 BITFIELD TV_SBB0_D VS Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ BITS 7:0 DESCRIPTION DECODE SIMO Buck-Boost Channel 0 Target Output Voltage This 7-bit configuration is a linear transfer function that starts at 0.5V, ends at 5.5V, with 25mV increments. 0x00 = 0.500V 0x01 = 0.525V 0x02 = 0.550V 0x03 = 0.575V 0x04 = 0.600V 0x05 = 0.625V 0x06 = 0.650V 0x07 = 0.675V 0x08 = 0.700V ... 0xC5 = 5.425V 0xC6 = 5.450V 0xC7 = 5.475V 0xC8 to 0xFF = 5.500V CNFG_LDO0_A (0x48) BIT 7 6 5 4 3 Field TV_OFS_L DO0 TV_LDO0[6:0] Reset OTP OTP Write, Read Write, Read Access Type BITFIELD TV_OFS_LD O0 TV_LDO0 BITS DESCRIPTION 7 LDO0 Output Voltage Offset. This bit applies a 1.325V offset to the output voltage of the LDO0. 6:0 2 1 0 DECODE LDO0 Target Output Voltage The tareget output voltage of the LDO would be TV_OFS_LDO0 + TV_LDO0. This 7-bit configuration is a linear transfer function that starts at 0.5V, ends at 3.675V, with 25mV increments. 0b0 = No Offset 0b1 = 1.325V Offset 0x00 = 0.500V 0x01 = 0.525V 0x02 = 0.550V 0x03 = 0.575V 0x04 = 0.600V 0x05 = 0.625V 0x06 = 0.650V 0x07 = 0.675V 0x08 = 0.700V ... 0x7E = 3.650V 0x7F = 3.675V When TV_LDO[7] = 0, TV_LDO[6:0] sets the LDO's output voltage range from 0.5V to 3.675V. When TV_LDO[7] = 1, TV_LDO[6:0] sets the LDO's output voltage from 1.825V to 5V. CNFG_LDO0_B (0x49) 7 6 5 4 3 Field BIT – – – LDO0_MD ADE_LDO0 EN_LDO0[2:0] Reset – – – OTP OTP OTP Access Type – – – Write, Read Write, Read Write, Read www.analog.com 2 1 0 Analog Devices | 123 MAX77658 BITFIELD LDO0_MD ADE_LDO0 EN_LDO0 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ BITS 4 3 2:0 DESCRIPTION DECODE Operation Mode of LDO0 0b0 = Low dropout linear regulator (LDO) mode 0b1 = Load switch (LSW) mode LDO0 Active-Discharge Enable 0b0 = The active discharge function is disabled. When LDO0 is disabled, its discharge rate is a function of the output capacitance and the external load. 0b1 = The active discharge function is enabled. When LDO is disabled, an internal resistor (RAD_LDO) is activated from LDO to GND to help the output voltage discharge. The output voltage discharge rate is a function of the output capacitance, the external loading, and the internal RAD_LDO load. Enable Control for LDO0, selecting either an FPS slot the channel powers-up and powersdown in or whether the channel is forced on or off. 0b000 = FPS slot 0 0b001 = FPS slot 1 0b010 = FPS slot 2 0b011 = FPS slot 3 0b100 = Off irrespective of FPS 0b101 = Same as 0b100 0b110 = On irrespective of FPS 0b111 = Same as 0b110 CNFG_LDO1_A (0x4A) BIT 7 6 5 4 3 Field TV_OFS_L DO1 TV_LDO1[6:0] Reset OTP OTP Write, Read Write, Read Access Type BITFIELD TV_OFS_LD O1 TV_LDO1 BITS DESCRIPTION 7 LDO1 Output Voltage Offset. This bit applies a 1.325V offset to the output voltage of the LDO1. 6:0 LDO1 Target Output Voltage The target output voltage of the LDO would be TV_OFS_LDO1 + TV_LDO1. This 7-bit configuration is a linear transfer function that starts at 0.5V, ends at 3.675V, with 25mV increments. 2 1 0 DECODE 0b0 = No offset 0b1 = 1.325V offset 0x00 = 0.500V 0x01 = 0.525V 0x02 = 0.550V 0x03 = 0.575V 0x04 = 0.600V 0x05 = 0.625V 0x06 = 0.650V 0x07 = 0.675V 0x08 = 0.700V ... 0x7E = 3.650V 0x7F = 3.675V When TV_LDO[7] = 0, TV_LDO[6:0] sets the LDO's output voltage range from 0.5V to 3.675V. When TV_LDO[7] = 1, TV_LDO[6:0] sets the LDO's output voltage from 1.825V to 5V. www.analog.com Analog Devices | 124 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ CNFG_LDO1_B (0x4B) 7 6 5 4 3 Field BIT – – – LDO1_MD ADE_LDO1 EN_LDO1[2:0] Reset – – – OTP OTP OTP Access Type – – – Write, Read Write, Read Write, Read BITFIELD BITS LDO1_MD 4 ADE_LDO1 3 EN_LDO1 2:0 2 DESCRIPTION 1 0 DECODE Operation Mode of LDO 0b0 = Low dropout linear regulator (LDO) mode 0b1 = Load switch (LSW) mode LDO1 Active-Discharge Enable 0b0 = The active discharge function is disabled. When LDO0 is disabled, its discharge rate is a function of the output capacitance and the external load. 0b1 = The active discharge function is enabled. When LDO is disabled, an internal resistor (RAD_LDO) is activated from LDO to GND to help the output voltage discharge. The output voltage discharge rate is a function of the output capacitance, the external loading, and the internal RAD_LDO load. Enable control for LDO1, selecting either an FPS slot the channel powers-up and powersdown in or whether the channel is forced on or off. 0b000 = FPS slot 0 0b001 = FPS slot 1 0b010 = FPS slot 2 0b011 = FPS slot 3 0b100 = Off irrespective of FPS 0b101 = Same as 0b100 0b110 = On irrespective of FPS 0b111 = Same as 0b110 Fuel Gauge ADDRESS NAME MSB LSB Status and Configuration Registers 0x00 0x01 0x02 0x03 0x13 0x18 Status[15:8] Br Smx Tmx Vmx Bi Smn Tmn Vmn Status[7:0] dSOCi Imx X X Bst Imn POR X VAlrtTh[15:8] VMAX[7:0] VAlrtTh[7:0] VMIN[7:0] TAlrtTh[15:8] TMAX[7:0] TAlrtTh[7:0] TMIN[7:0] SAlrtTh[15:8] SMAX[7:0] SAlrtTh[7:0] 0x1E FullSOCThr[15:8] FullSOCThr[7:0] FullSOCThr[7:0] DesignCap[15:8] DesignCap[15:8] DesignCap[7:0] Config[15:8] 0x1D SMIN[7:0] FullSOCThr[15:8] Config[7:0] IChgTerm[15:8] www.analog.com DesignCap[7:0] TSel SS TS VS IS THSH Ten Tex SHDN COMMS H 0 ETHRM FTHRM Aen Bei Ber ICHGTerm[15:8] Analog Devices | 125 MAX77658 ADDRESS Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ NAME MSB LSB IChgTerm[7:0] 0x21 0x28 0x29 0x3A 0xB1 0xB3 0xB4 0xBB ICHGTerm[7:0] DevName[15:8] – – – – – – – – DevName[7:0] – – – – – – – – LearnCfg[15:8] 0 1 0 0 0 1 0 0 LearnCfg[7:0] 1 0 1 1 0 FilterCfg[15:8] 1 FilterCfg[7:0] MIX[0] LS[2:0] 1 – – – VOLT[2:0] MIX[3:1] NCURR[3:0] VEmpty[15:8] VE[8:1] VEmpty[7:0] VE[0] VR[6:0] Power[15:8] – – – – – – – – Power[7:0] – – – – – – – – AvgPower[15:8] AvgPower[15:8] AvgPower[7:0] AvgPower[7:0] IAlrtTh[15:8] IMAX[7:0] IAlrtTh[7:0] IMIN[7:0] Config2[15:8] 0 0 Config2[7:0] dSOCen TAlrtEn AtRateE N DPEN LDMdl – POWR[3:0] DRCfg[1:0] CPMode – OVERLAP Measurement Registers 0x08 0x09 0x0A 0x0B 0x16 0x19 0x1A 0x1B 0x1C 0x27 0x3E 0xBE Temp[15:8] TEMP[15:8] Temp[7:0] TEMP[7:0] Vcell[15:8] VCELL[15:8] Vcell[7:0] VCELL[7:0] Current[15:8] Current[15:8] Current[7:0] Current[7:0] AvgCurrent[15:8] AvgCurrent[15:8] AvgCurrent[7:0] AvgCurrent[7:0] AvgTA[15:8] AvgTA[7:0] AvgVCell[15:8] AvgVCell[7:0] AvgTA[15:8] AvgTA[7:0] AvgVCELL[15:8] AvgVCELL[7:0] MaxMinTemp[15:8] MaxTemperature[7:0] MaxMinTemp[7:0] MinTemperature[7:0] MaxMinVolt[15:8] MaxVoltage[7:0] MaxMinVolt[7:0] MinVoltage[7:0] MaxMinCurr[15:8] MaxCurrent[7:0] MaxMinCurr[7:0] MinCurrent[7:0] AIN0[15:8] AIN0[15:8] AIN0[7:0] AIN0[7:0] Timer[15:8] Timer[7:0] TimerH[15:8] www.analog.com TIMER[15:8] TIMER[7:0] TIMERH[15:8] Analog Devices | 126 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ ADDRESS NAME MSB LSB TimerH[7:0] TIMERH[7:0] OVERLAP ModelGauge m5 Output Registers 0x05 0x06 0x0E 0x10 0x11 0x14 0x17 0x1F 0x20 RepCap[15:8] RepCap[15:8] RepCap[7:0] RepCap[7:0] RepSOC[15:8] RepSOC[15:8] RepSOC[7:0] RepSOC[7:0] AvSOC[15:8] AvSOC[15:8] AvSOC[7:0] AvSOC[7:0] FullCapRep[15:8] FullCapRep[15:8] FullCapRep[7:0] FullCapRep[7:0] TTE[15:8] TTE[15:8] TTE[7:0] TTE[7:0] RCell[15:8] RCell[15:8] RCell[7:0] RCell[7:0] Cycles[15:8] Cycles[15:8] Cycles[7:0] Cycles[7:0] AvCap[15:8] AvCap[15:8] AvCap[7:0] AvCap[7:0] TTF[15:8] TTF[15:8] TTF[7:0] TTF[7:0] Register Details Status (0x00) Interrupt status register for the FG block. 15 14 13 12 11 10 9 8 Field BIT Br Smx Tmx Vmx Bi Smn Tmn Vmn Reset 0b1 0b0 0b0 0b0 0b0 0b0 0b0 0b0 Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Access Type 7 6 5 4 3 2 1 0 Field BIT dSOCi Imx X X Bst Imn POR X Reset 0b1 0b0 0b0 0b0 0b0 0b0 0b1 0b0 Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Access Type BITFIELD Br www.analog.com BITS 15 DESCRIPTION Battery Removal DECODE This bit is set to 1 when the device detects that a battery has been removed from the system. This bit must be cleared by system software to detect the next removal event. Br is set to 1 at power-up. Analog Devices | 127 MAX77658 BITFIELD Smx Tmx Vmx Bi Smn Tmn Vmn dSOCi Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ BITS 14 13 12 11 10 9 8 7 DESCRIPTION DECODE Maximum SOCALRT Threshold Exceeded This bit is set to 1 whenever SOC rises above the maximum SAlrtTh value. This bit may or may not need to be cleared by system software to detect the next event. See the Config.SS description. The bit is cleared to 0 at power-up. Maximum TALRT Threshold Exceeded This bit is set to 1 whenever the reading at the Temperature register rises above the maximum TAlrtTh value. This bit may or may not need to be cleared by system software to detect the next event. See the Config.TS description. The bit is cleared to 0 at power-up. Maximum VALRT Threshold Exceeded This bit is set to 1 whenever a VCell register reading is above the maximum VAlrtTh value. This bit may or may not need to be cleared by system software to detect the next event. See the Config.VS description. This bit is set to 0 at powerup. Battery Insertion This bit is set to 1 when the device detects that a battery has been inserted into the system by monitoring the AIN pin. This bit must be cleared by system software to detect the next insertion event. Bi is set to 0 at power-up. Minimum SOCALRT Threshold Exceeded This bit is set to 1 whenever SOC rises above the minimum SAlrtTh value. This bit may or may not need to be cleared by system software to detect the next event. See the Config.SS description. The bit is cleared to 0 at power-up. Minimum TALRT Threshold Exceeded This bit is set to 1 whenever the reading at the Temperature register rises above the minimum TAlrtTh value. This bit may or may not need to be cleared by system software to detect the next event. See the Config.TS description. The bit is cleared to 0 at power-up. Minimum VALRT Threshold Exceeded This bit is set to 1 whenever a VCell register reading is above the minimum VAlrtTh value. This bit may or may not need to be cleared by system software to detect the next event. See the Config.VS description. This bit is set to 0 at powerup. 1% SOC Change Alert This bit is set to 1 whenever the RepSOC register crosses an interger percentage boundary such as 50.0%, 51.0%, etc. Must be cleared by host software. dSOCi is set to 1 at power-up. Imx 6 Maximum Current-Alert Threhold Exceeded This bit is set to 1 whenever a Current register reading is above the IAlrtTh.IMAX threhold. This bit may or may not need to be cleared by system software to detect the next event. See the Config.IS description. The bit is cleared to 0 at power-up. X 5 Don't Care This bit is undefined and can be logic 0 or 1 X 4 Don't Care This bit is undefined and can be logic 0 or 1 Battery Status Useful when the IC is used in a host-side application. This bit is set to 0 when a battery is present in the system, and set to 1 when the battery is absent. Bst is set to 0 at power-up. Bst www.analog.com 3 Analog Devices | 128 MAX77658 BITFIELD Imn Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ BITS 2 DESCRIPTION DECODE Minimum Current-Alert Threshold Exceeded This bit is set to 1 whenever a Current register reading is below the IAlrtTH.IMIN threshold. This bit may or may not need to be cleared by system software to detect the next event. See the Config.IS description. The bit is cleared to 0 at power-up. POR 1 Power-On Reset This bit is set to 1 when the device detects that a software or hardware POR event has occurred. This bit must be cleared by system software to detect the next POR event. POR is set to 1 at power-up. X 0 Don't Care This bit is undefined and can be logic 0 or 1. VAlrtTh (0x01) The VAlrtTh register sets upper and lower limits that generate an alert if exceeded by the VCell register value. BIT 15 14 13 12 Field VMAX[7:0] Reset 0xFF Access Type BIT 7 6 5 4 VMIN[7:0] Reset 0x00 Access Type VMAX VMIN 10 9 8 3 2 1 0 Write, Read Field BITFIELD 11 Write, Read BITS DESCRIPTION DECODE 15:8 Maximum Voltage Reading. An alert is generated if the VCell register reading exceeds this value. Register type: special Set Max = 0xFF to disable. Selectable with 20mV resolution over the full operating range of the VCell register. 7:0 Minimum Voltage Reading. An alert is generated if the VCell register reading falls below this value. Register type: special Set Min = 0x00 to disable. Selectable with 20mV resolution over the full operating range of the VCell register. TAlrtTh (0x02) The TAlrtTh register sets upper and lower limits that generate an alert if exceeded by the Temp register value. BIT 15 14 13 12 Field TMAX[7:0] Reset 0x7F Access Type BIT 7 6 5 4 TMIN[7:0] Reset 0x80 www.analog.com 10 9 8 3 2 1 0 Write, Read Field Access Type 11 Write, Read Analog Devices | 129 MAX77658 BITFIELD Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ BITS DESCRIPTION DECODE TMAX 15:8 Sets an alert threshold for maximum temperature. Register type: special Set Max = 0x7F to disable. Stored in two's complement format with 1˚C resolution over the full operating range of the Temp register. TMIN 7:0 Sets an alert threshold for minimum temperature. Register type: special Set Min = 0x80 to disable. Stored in two's complement format with 1˚C resolution over the full operating range of the Temp register. SAlrtTh (0x03) The SAlrtTh register sets upper and lower limits that generate an alert if exceeded by RepSOC. BIT 15 14 13 12 Field SMAX[7:0] Reset 0xFF Access Type BIT 7 6 5 4 SMIN[7:0] Reset 0x00 Access Type SMAX SMIN 10 9 8 3 2 1 0 Write, Read Field BITFIELD 11 Write, Read BITS 15:8 7:0 DESCRIPTION DECODE Sets an alert for maximum SOC. Register type: special This may be used for charge termination, or for power-management near full. Set to 0xFF to disable. The threshold is configurable with 1% resolution over the full operating range of the RepSOC register. Sets an alert for minimum SOC. Register type: special This may be used for discharge termination, or for power-management near empty. Set to 0x00 to disable. The threshold is configurable with 1% resolution over the full operating range of the RepSOC register. FullSOCThr (0x13) The FullSOCThr register gates detection of end-of-charge. VFSOC must be larger than the FullSOCThr value before IChgTerm is compared to the AvgCurrent register value. The recommended FullSOCThr register setting for most custom characterized applications is 95% (default, 0x5F05). For EZ Performance applications, the recommendation is 80% (0x5005). See the IChgTerm register description and refer to the ModelGauge m5 EZ User Guide for details. BIT 15 14 13 12 11 Field FullSOCThr[15:8] Reset 0x5000 Access Type www.analog.com 10 9 8 Write, Read Analog Devices | 130 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ BIT 7 6 5 4 3 Field FullSOCThr[7:0] Reset 0x5000 Access Type 2 1 0 Write, Read BITFIELD BITS FullSOCThr 15:0 DESCRIPTION DECODE Default value: 95%. Register type: percentage DesignCap (0x18) The DesignCap register holds the nominal capacity of the cell. This value is used to determine the age of the cell by comparing against the measured present cell capacity. BIT 15 14 13 12 11 Field DesignCap[15:8] Reset 0x0BB8 Access Type BIT 7 6 5 4 3 DesignCap[7:0] Reset 0x0BB8 Access Type DesignCap 9 8 2 1 0 Write, Read Field BITFIELD 10 Write, Read BITS 15:0 DESCRIPTION DECODE Expected cell capacity. Register type: capacity Config (0x1D) The Config registers (Config and Config2) hold all shutdown enable, alert enable, and temperature enable control bits of the fuel gauge. Writing a bit location enables the corresponding function within one task period. Please note that the shutdown mode of the other components of the IC is controlled by the on/off controller. 15 14 13 12 11 10 9 8 Field BIT TSel SS TS VS IS THSH Ten Tex Reset 0b0 0b0 0b1 0b0 0b0 0b0 0b1 0b0 Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Access Type 7 6 5 4 3 2 1 0 Field BIT SHDN COMMSH 0 ETHRM FTHRM Aen Bei Ber Reset 0b0 0b0 0b0 0b1 0b0 0b0 0b0 0b0 Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Access Type BITFIELD TSel www.analog.com BITS 15 DESCRIPTION Temperature Sensor Select DECODE Temperature Sensor Select. Set to 0 to use internal die temperature. Set to 1 to use temperature information from thermistor. ETHRM bit must be set to 1 when TSel is 1. Analog Devices | 131 MAX77658 BITFIELD Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ BITS DESCRIPTION DECODE SS 14 SOC ALRT Sticky SOC ALRT Sticky. When SS = 1, SOC alerts can only be cleared through software. When SS = 0, SOC alerts are cleared automatically when the threshold is no longer exceeded. TS 13 Temperature ALRT Sticky When TS = 1, temperature alerts can only be cleared through software. When TS = 0, temperature alerts are cleared automatically when the threshold is no longer exceeded. Voltage ALRT Sticky When VS = 1, voltage alerts can only be cleared through software. When VS = 0, voltage alerts are cleared automatically when the threshold is no longer exceeded. VS is set to 0 at power-up. Current ALRT Sticky When IS = 1, current alerts can only be cleared through software. When IS = 0, current alerts are cleared automatically when the threshold is no longer exceeded. VS IS 12 11 THSH 10 TH Pin Shutdown Set to 1 to enable fuel gauge shutdown when the battery is removed. The fuel gauge of the IC enters shutdown if the AIN pin remains high (AIN reading > VTHRM - VDETR) for longer than the timeout of the SHDNTIMER register. This also configures the fuel gauge to wake up when AIN is pulled low on cell insertion. AINSH is set to 0 at power-up. Note that if I2CSH and AINSH are both set to 0, the fuel gauge wakes up an edge of any of the SDA, SCL, or INTB pins. Ten 9 Enable Temperature Channel Set to 1 and set ETHRM or FTHRM to 1 to enable temperature measurements. Temperature External When set to 1, the fuel gauge requires external temperature measurements to be written from the host. When set to 0, the IC's own measurements are used instead. Shutdown Write this bit to logic 1 to force a shutdown of the fuel gauge after timeout of the SHDNTIMER register (default 45s delay). SHDN is reset to 0 at power-up and upon exiting shutdown mode. In order to command fuel gauge shutdown within 45 seconds, first write HibCFG = 0x0000 to enter active mode. Tex SHDN 8 7 COMMSH 6 Communication Shutdown Set to logic 1 to force the fuel gauge to enter shutdown mode if both SDA and SCL are held low for more than timeout of the ShdnTimer register. This also configures the fuel gauge to wake up on a rising edge of any communication. Note that if COMMSH and THSH are both set to 0, the device wakes up on any edge of SDA. Refer to the User Guide for details. 0 5 Bit must be written 0. Do not write 1. ETHRM 4 Enable Thermistor Enable Thermistor. Set to logic 1 to enable the TH pin measurement. www.analog.com Analog Devices | 132 MAX77658 BITFIELD FTHRM Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ BITS 3 DESCRIPTION DECODE Force Thermistor Bias Switch Force Thermistor Bias Switch. This allows the host to control the bias of the thermistor switch or enable fast detection of battery removal. Set FTHRM = 1 to always enable the thermistor bias switch. With a standard 10kΩ thermistor, this adds an additional ~200μA to the current drain of the circuit. Aen 2 Enable alert on fuel-gauge outputs. Enable Alert on Fuel-Gauge Outputs. When Aen = 1, any violation of the alert threshold register values by temperature, voltage, current, or SOC triggers an alert. This bit affects the ALRT pin operation only. The Smx, Smn, Tmx, Tmn, Vmx, Vmn, Imx, and Imn bits of the Status register (0x000) are not disabled. Bei 1 Enable alert on battery insertion. When Bei = 1, a battery-insertion condition, as detected by the TH pin voltage, triggers an alert. Ber 0 Enable alert on battery removal. When Ber = 1, a battery-removal condition, as detected by the TH pin voltage, triggers an alert. IChgTerm (0x1E) The IChgTerm register allows the fuel gauge to detect when charge termination has occurred. BIT 15 14 13 12 11 Field ICHGTerm[15:8] Reset 0x0640 Access Type BIT 7 6 5 4 3 ICHGTerm[7:0] Reset 0x0640 Access Type ICHGTerm 9 8 2 1 0 Write, Read Field BITFIELD 10 Write, Read BITS 15:0 DESCRIPTION Program IChgTerm to the exact charge termination current used in the application. DECODE Register type: current DevName (0x21) The DevName register holds revision information. This allows host software to easily identify the type of IC being communicated to. LearnCfg (0x28) The LearnCFG register controls all functions relating to adaptation during operation. The LearnCFG register default values should not be changed unless specifically required by the application. www.analog.com Analog Devices | 133 MAX77658 BIT Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ 15 14 13 12 11 10 9 8 Field 0 1 0 0 0 1 0 0 Reset 0b0 0b1 0b0 0b0 0x0 0b001 0x0 0b0 Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read 7 6 5 4 3 2 1 0 Access Type BIT Field 1 LS[2:0] 0 1 1 0 Reset 0b1 0b000 0b0 0b1 0b1 0b0 Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Access Type BITFIELD BITS DESCRIPTION DECODE 0 15 Bit must be written 0. Do not write 1. 1 14 Bit must be written 1. Do not write 0. 0 13 Bit must be written 0. Do not write 1. 0 12 Bit must be written 0. Do not write 1. 0 11 Bit must be written 0. Do not write 1. 1 10 Bit must be written 1. Do not write 0. 0 9 Bit must be written 0. Do not write 1. 0 8 Bit must be written 0. Do not write 1. 1 7 Bit must be written 1. Do not write 0. Learn Stage. The Learn Stage value controls the influence of the voltage fuel gauge on the mixing algorithm. Learn Stage defaults 0x0, making the voltage fuel gauge dominate. Learn Stage then advances to 0x7 over the course of two full cell cycles to make the coulomb counter dominate. Host software can write the Learn Stage value to 0x7 to advance to the final stage at any time. Values between 0x1 and 0x6 are ignored. LS 6:4 0 3 Bit must be written 0. Do not write 1. 1 2 Bit must be written 1. Do not write 0. 1 1 Bit must be written 1. Do not write 0. 0 0 Bit must be written 0. Do not write 1. FilterCfg (0x29) The FilterCfg register sets the average time period for all A/D readings, for mixing OCV results and coulomb-count results. It is recommended that these values are not changed unless absolutely required by the application. BIT Field 15 1 BIT 13 12 11 10 9 1 – – – MIX[3:1] – – – 0xD Write, Read Write, Read – – – Write, Read 7 6 5 4 3 2 1 Field MIX[0] VOLT[2:0] NCURR[3:0] Reset 0xD 0b010 0x4 Write, Read Write, Read Write, Read Access Type www.analog.com 8 0b11 Reset Access Type 14 0 Analog Devices | 134 MAX77658 BITFIELD Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ BITS DESCRIPTION DECODE 1 15 Bit must be written 1. Do not write 0. 1 14 Bit must be written 1. Do not write 0. MIX 10:7 Sets the time constant for the mixing algorithm. The default POR value of 0xD gives a time constant of 12.8 hours. The equation setting the period is: Mixing Period = 45s x 2(MIX-3) VOLT 6:4 Sets the time constant for the AvgVCell register. The default POR value of 0x4 gives a time constant of 45s. The equation setting the period is: AvgVCell time constant = 45s x 2(VOLT-2) 3:0 Sets the time constant for the AverageCurrent register. The default POR value of 4h gives a time constant of 11.25 seconds. The equation setting the period is: AverageCurrent time constant = 175.8ms × 2^(2+NCURR) NCURR VEmpty (0x3A) The VEmpty register sets the thresholds related to empty detection during operation. BIT 15 14 13 12 11 Field VE[8:1] Reset 0b101001010 Access Type 9 8 2 1 0 Write, Read BIT 7 6 5 4 3 Field VE[0] VR[6:0] Reset 0b1010010 10 0b1100001 Access Type Write, Read Write, Read BITFIELD 10 BITS VE VR DESCRIPTION DECODE 15:7 Empty voltage target during load. The fuel gauge provides capacity and percentage relative to the empty voltage target, eventually declaring 0% at VE. A 10mV resolution gives a 0V to 5.11V range. This value defaults to 3.3V after reset. 6:0 Recovery Voltage. Sets the voltage level for clearing empty detection. Once the cell voltage rises above this point, empty voltage detection is reenabled. A 40mV resolution gives a 0V to 5.08V range. This value defaults to 3.88V, which is recommended for most applications. AvgPower (0xB3) BIT 15 14 13 12 11 Field AvgPower[15:8] Reset 0x0000 Access Type www.analog.com 10 9 8 Write, Read Analog Devices | 135 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ BIT 7 6 5 4 3 Field AvgPower[7:0] Reset 0x0000 Access Type 2 1 0 Write, Read BITFIELD BITS AvgPower 15:0 DESCRIPTION DECODE Filtered average power from the Power register LSB is 0.171mW. IAlrtTh (0xB4) The IAlrtTh register sets upper and lower limits that generate an alert if exceeded by the Current register value. Interrupt threshold limits are selectable with 8.567mA resolution over the full operating range of the Current register. BIT 15 14 13 12 Field IMAX[7:0] Reset 0x7F Access Type 11 10 9 8 3 2 1 0 Write, Read BIT 7 6 5 4 Field IMIN[7:0] Reset 0x80 Access Type Write, Read BITFIELD BITS DESCRIPTION DECODE IMAX 15:8 The upper 8 bits set the maximum value. Register type: special An alert is generated if the current register reading exceeds this value. IMIN 7:0 The lower 8 bits set the minimum value. An alert is generated if the current register reading falls below this value. Config2 (0xBB) The Config registers (Config and Config2) hold all shutdown enable, alert enable, and temperature enable control bits of the fuel gauge. Writing a bit location enables the corresponding function within one task period. Please note that the shutdown mode of the other components of the IC is controlled by the on/off controller. BIT Field 15 14 13 12 0 0 AtRateEN DPEN POWR[3:0] 0b1 0b1 0b0100 Write, Read Write, Read Write, Read Reset Access Type BIT Write, Read Write, Read 11 10 7 6 5 4 Field dSOCen TAlrtEn LDMdl – DRCfg[1:0] Reset 0b0 0b1 0b0 – 0b10 Write, Read Write, Read Write, Read – Write, Read Access Type BITFIELD 0 www.analog.com BITS 15 3 2 DESCRIPTION Bit must be written 0. 9 8 1 0 CPMode – – Write, Read – DECODE Do not write 1. Analog Devices | 136 MAX77658 BITFIELD 0 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ BITS 14 AtRateEN DPEN POWR 13 12 11:8 DESCRIPTION DECODE Bit must be written 0. Do not write 1. AtRate Enable When this bit is set to 0, AtRate calculations are disabled and registers AtQResidual/AtTTE/ AtAvSOC/AtAvCap can be used as general purpose memory. Dynamic Power Enable When this bit is set to 0, Dynamic Power calculations are disabled and registers MaxPeakPower/SusPeakPower/MPPCurrent/ SPPCurrent can be used as general purpose memory. Sets the time constant for the AvgPower register. The default POR value of 0100b gives a time constant of 11.25s. The equation setting the period is: AvgPower time constant = 45s x 2(POWR-6) dSOCen 7 SOC Change Alert Enable Set this bit to 1 to enable alert output with the Status.dSOCi bit function. Write this bit to 0 to disable alert output with the Status.dSOCi bit. This bit is set to 0 at power-up. TAlrtEn 6 Temperature Alert Enable Set this bit to 1 to enable temperature based alerts. Write this bit to 0 to disable temperature alerts. This bit is set to 1 at power-up. Load New Model Host sets this bit to 1 in order to initiate firmware to finish processing a newly loaded model. Firmware clears this bit to zero to indicate that model loading is finished. Deep Relax Time Configuration 00 for 0.8 to 1.6 hours, 01 for 1.6 to 3.2 hours, 10 for 3.2 to 6.4 hours, and 11 for 6.4 to 12.8 hours. Constant-Power Mode Set to 1 to enable constant-power mode. If it is set to 0, AtRate/AvgCurrent is used for (At)TTE/(At)QResidual/(At)AvSOC/(At)AvCap. If it is set to 1, AtRate/AvgCurrent x AvgVCell / (AvgVCell + VEmpty) / 2 is used for those calculations. LDMdl 5 DRCfg 3:2 CPMode 1 Temp (0x8) The Temp register provides the temperature measured by the thermistor or die temperature. BIT 15 14 13 12 Field TEMP[15:8] Reset 0x1600 Access Type BIT 7 6 5 4 TEMP[7:0] Reset 0x1600 www.analog.com 10 9 8 3 2 1 0 Write, Read Field Access Type 11 Write, Read Analog Devices | 137 MAX77658 BITFIELD TEMP Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ BITS 15:0 DESCRIPTION DECODE Register type: temperature When using AIN for temperature (Tex = 0), configure TGain and TOff to adjust the AIN measurement to provide units degrees in the highbyte of Temp. When TGain and TOff are configured properly for the selected thermistor, the LSB is 0.0039˚C and the upper Byte has units 1°C. Temp is a signed register. To configure the BT07 to receive temperature information from the I2C, set Tex = 1 and periodically write the Temp register with the appropriate temperature. This is the most recent trimmed temperature measurement. Temperature is measured every 1.4 seconds. Vcell (0x9) VCell reports the voltage measured between BATT and CSP. BIT 15 14 13 12 11 Field VCELL[15:8] Reset 0xB400 Access Type BIT 7 6 5 4 3 VCELL[7:0] Reset 0xB400 Access Type VCELL 9 8 2 1 0 Write, Read Field BITFIELD 10 Write, Read BITS DESCRIPTION 15:0 This is the most recent trimmed cell voltage result. It represents an FIR average of raw results. The VOLT_Raw is sampled every 175.8ms and gain and offset trim are applied to calculate VCELL. DECODE Register type: voltage Current (0xA) The MAX77658 uses internal current sensing to monitor the current through the SYS FG pin. The measurement value is stored in two's-complement format. Measurement that exceeds maximum and minimum current range is stored as maximum and minimum value. The Current register has a LSB value of 33.487μA, a register scale of 1.097A, and an allowable measurement range as described in the Absolute Maximum Ratings. BIT 15 14 13 12 11 Field Current[15:8] Reset 0x0000 Access Type BIT 7 6 5 4 3 Current[7:0] Reset 0x0000 www.analog.com 9 8 2 1 0 Write, Read Field Access Type 10 Write, Read Analog Devices | 138 MAX77658 BITFIELD Current Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ BITS DESCRIPTION DECODE 15:0 Register type: current AvgCurrent (0x0B) The AvgCurrent register reports an average of Current register readings. BIT 15 14 13 12 11 Field AvgCurrent[15:8] Reset 0x0000 Access Type BIT 7 6 5 4 3 AvgCurrent[7:0] Reset 0x0000 Access Type AvgCurrent 9 8 2 1 0 Write, Read Field BITFIELD 10 Write, Read BITS DESCRIPTION DECODE 15:0 This is the 0.7s to 6.4hr (configurable) IIR average of the current. This register represents the upper 16 bits of the 32-bit shift register that filters current. The average should be set equal to Current upon startup. Register type: current AvgTA (0x16) The AvgTA register reports an average of the readings from the Temp register. BIT 15 14 13 12 11 Field AvgTA[15:8] Reset 0x1600 Access Type BIT 7 6 5 4 3 AvgTA[7:0] Reset 0x1600 Access Type AvgTA 9 8 2 1 0 Write, Read Field BITFIELD 10 Write, Read BITS 15:0 DESCRIPTION This is the 6min to 12hr (configurable) IIR average of the Temperature. The average is set equal to Temp upon startup. DECODE Register type: temperature AvgVCell (0x19) The AvgVCell register reports an average of the VCell register readings. www.analog.com Analog Devices | 139 MAX77658 BIT Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ 15 14 13 12 11 Field AvgVCELL[15:8] Reset 0xB400 Access Type BIT 7 6 5 4 3 AvgVCELL[7:0] Reset 0xB400 Access Type AvgVCELL 9 8 2 1 0 Write, Read Field BITFIELD 10 Write, Read BITS 15:0 DESCRIPTION DECODE This reports the 12s to 24min (configurable) IIR average of VCELL. The average is set equal to VCELL at startup. Register type: voltage MaxMinTemp (0x1A) The MaxMinTemp register maintains the maximum and minimum Temp register values since the last fuel gauge reset or until cleared by host software. At power-up, the maximum value is set to 0x80 (most negative) and the minimum value is set to 0x7F (most positive). Therefore, both values are changed to the Temp register reading after the first update. Host software can rest this register by writing it to its power-up value of 0x807F. The maximum and minimum temperatures are each stored as two's complement 8-bit values with 1°C resolution. BIT 15 14 13 12 11 Field MaxTemperature[7:0] Reset 0x80 Access Type BIT 10 9 8 2 1 0 Write, Read 7 6 5 4 3 Field MinTemperature[7:0] Reset 0x7F Access Type Write, Read BITFIELD BITS DESCRIPTION DECODE MaxTempera ture 15:8 Records the maximum Temperature. Register type: special Two's complement 8-bit value with 1°C resolution. MinTemperat ure 7:0 Records the minimum Temperature. Register type: special Two's complement 8-bit value with 1°C resolution. MaxMinVolt (0x1B) The MAXMINVolt register maintains the maximum and minimum of VCell register values since fuel gauge reset. At power-up, the maximum vaoltage is set to 00h (the minimum) and the minimum voltage value is set to FFh (the maximum). Therefore, both values are changed to the voltage register reading after the first update. Host software can reset this register by writing it to its power-up value of 0x00FF. The maximum and minimum voltages are each stored as 8-bit values with a 20mV resolution. www.analog.com Analog Devices | 140 MAX77658 BIT Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ 15 14 13 12 11 Field MaxVoltage[7:0] Reset 0x00 Access Type BIT 9 8 2 1 0 Write, Read 7 6 5 4 3 Field MinVoltage[7:0] Reset 0xFF Access Type BITFIELD 10 Write, Read BITS DESCRIPTION DECODE MaxVoltage 15:8 Records the VCELL maximum voltage. Register type: special The maximum and minimum voltages are each stored as 8-bit values with a 20mV resolution. MinVoltage 7:0 Records the VCELL minimum voltage. Register type: special The maximum and minimum voltages are each stored as 8-bit values with a 20mV resolution. MaxMinCurr (0x1C) The MaxMinCurr register maintains the maximum and minimum Current register values since the last fuel gauge reset or until cleared by host software. At power-up, the maximum current value is set to 80h (most negative) and the minimum current value is set to 7Fh (most positive). Therefore, both values are changed to the Current register reading after the first update. Host software can reset this register by writing it to its power-up value of 0x807F. The maximum and minimum currents are each stored as two's complement 8-bit values with 8.567mA resolution. BIT 15 14 13 12 11 Field MaxCurrent[7:0] Reset 0x80 Access Type BIT 9 8 2 1 0 Write, Read 7 6 5 4 3 Field MinCurrent[7:0] Reset 0x7F Access Type BITFIELD 10 Write, Read BITS DESCRIPTION DECODE MaxCurrent 15:8 Records the maximum current reading. Register type: special Two's complement 8-bit values with 8.57mA resolution. MinCurrent 7:0 Records the minimum current reading. Register type: special Two's complement 8-bit values with 8.57mA resolution. AIN0 (0x27) The external temperature measurement on the TH pin is compared to the BATT pin voltage. www.analog.com Analog Devices | 141 MAX77658 BIT Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ 15 14 13 12 Field AIN0[15:8] Reset 0x88D0 Access Type BIT 7 6 5 9 8 3 2 1 0 4 AIN0[7:0] Reset 0x88D0 Access Type AIN0 10 Write, Read Field BITFIELD 11 Write, Read BITS 15:0 DESCRIPTION DECODE Register type: special The MAX77658 stores the result as a ratio-metric value from 0% to 100% in the AIN register with an LSB of 0.0122%. The TGain, TOff, and Curve register values are then applied to this ratio-metric reading to convert the result to temperature. Timer (0x3E) TimerH and Timer provide a long-duration time count since last POR. BIT 15 14 13 12 11 Field TIMER[15:8] Reset 0x0000 Access Type BIT 7 6 5 4 3 TIMER[7:0] Reset 0x0000 Access Type TIMER 9 8 2 1 0 Write, Read Field BITFIELD 10 Write, Read BITS DESCRIPTION 15:0 Timer increments once every task period. With default TaskPeriod, timer has units 0.1758 seconds.The timer manages the following tasks: 1) Thermistor measurements occur once every 8 tasks. 2) Debouncing repeats for 8 TIMER ticks. 3) dV is measured based on dTthr TIMER ticks. DECODE Register type: special The Timer register LSb is 175.8ms, giving a fullscale range of 0 to 3.2 hours. TimerH (0xBE) TimerH and Timer provide a long-duration time count since last POR. BIT 15 14 13 12 11 Field TIMERH[15:8] Reset 0x0000 Access Type www.analog.com 10 9 8 Write, Read Analog Devices | 142 MAX77658 BIT Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ 7 6 5 4 3 Field TIMERH[7:0] Reset 0x0000 Access Type BITFIELD TIMERH 2 1 0 Write, Read BITS 15:0 DESCRIPTION DECODE TIMERH is a 16-bit high-word extension to the TIMER register. This extension allows time counting up to 24 years. This register can be enabled in the save and restore registers. Register type: special A 3.2 hour LSb gives a full-scale range for the register of up to 23.94 years. RepCap (0x05) RepCap is the reported remaining capacity in mAh. BIT 15 14 13 12 11 Field RepCap[15:8] Reset 0x05DC Access Type BIT 7 6 5 4 3 RepCap[7:0] Reset 0x05DC Access Type RepCap 9 8 2 1 0 Write, Read Field BITFIELD 10 Write, Read BITS 15:0 DESCRIPTION DECODE RepCap or reported capacity is a filtered version of the AvCap register that prevents large jumps in the reported value caused by changes in the application such as abrupt changes in tempreature or load current. Register type: capacity RepSOC (0x06) RepSOC is the reported state-of-charge percentage output for use by the application GUI BIT 15 14 13 12 11 Field RepSOC[15:8] Reset 0x3200 Access Type BIT 7 6 5 4 3 RepSOC[7:0] Reset 0x3200 www.analog.com 9 8 2 1 0 Write, Read Field Access Type 10 Write, Read Analog Devices | 143 MAX77658 BITFIELD RepSOC Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ BITS DESCRIPTION DECODE 15:0 RepSOC is the complete calculation for stateof-charge. This includes all processing, including: ModelGauge Mixing, Empty Compensation Register type: percentage AvSOC (0xE) The AvSOC registers hold the calculated available percentage of the battery based on all inputs from the ModelGauge m5 algorithm, including empty compensation. This register provides unfiltered results. Jumps in the reported values can be caused by abrupt changes in load current or temperature. Refer to the ModelGauge m5 EZ User Guide for details. BIT 15 14 13 12 11 Field AvSOC[15:8] Reset 0x3200 Access Type BIT 7 6 5 4 3 AvSOC[7:0] Reset 0x3200 Access Type AvSOC 9 8 2 1 0 Write, Read Field BITFIELD 10 Write, Read BITS DESCRIPTION DECODE 15:0 This register provides unfiltered results. Jumps in the reported values can be caused by abrupt changes in load current or temperature. Refer to the ModelGauge m5 EZ User Guide for more details. This includes all processing, including: ModelGauge mixing and empty compensation. Register type: percentage FullCapRep (0x10) This register reports the full capacity that goes with RepCap, generally used for reporting to the GUI. BIT 15 14 13 12 11 Field FullCapRep[15:8] Reset 0x0BB8 Access Type BIT 7 6 5 4 3 FullCapRep[7:0] Reset 0x0BB8 Access Type FullCapRep www.analog.com 9 8 2 1 0 Write, Read Field BITFIELD 10 Write, Read BITS DESCRIPTION 15:0 Most applications should only monitor FullCapRep, instead of FullCap or FullCapNom. A new full-capacity value is calculated at the end of every charge cycle in the application. DECODE Register type: capacity Analog Devices | 144 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ TTE (0x11) The TTE register holds the estimated time-to-empty for the application under present temperature and load conditions. BIT 15 14 13 12 Field 11 10 9 8 3 2 1 0 TTE[15:8] Reset Access Type BIT Write, Read 7 6 5 4 Field TTE[7:0] Reset Access Type BITFIELD TTE Write, Read BITS DESCRIPTION 15:0 The TTE value is determined by relating AvCap with AvgCurrent. The corresponding AvgCurrent filtering gives a delay in TTE but provides more stable results. DECODE Register type: time RCell (0x14) BIT 15 14 13 12 Field RCell[15:8] Reset 0x0290 Access Type BIT 7 6 5 9 8 3 2 1 0 4 RCell[7:0] Reset 0x0290 Access Type RCell 10 Write, Read Field BITFIELD 11 Write, Read BITS DESCRIPTION 15:0 This register provides the calculated internal resistance of the cell. RCell is determined by comparing open-circuit voltage (VFOCV) against measured voltage (VCell) over a long time period while under load or charge current. DECODE Register type: resistance Cycles (0x17) BIT 15 14 13 12 11 Field Cycles[15:8] Reset 0x0000 Access Type www.analog.com 10 9 8 Write, Read Analog Devices | 145 MAX77658 BIT Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ 7 6 5 4 3 Field Cycles[7:0] Reset 0x0000 Access Type BITFIELD Cycles 2 1 0 Write, Read BITS 15:0 DESCRIPTION DECODE Register type: special The LSB indicates 1% of a battery cycle (1% charge + 1% discharge). One cycle (Cycles = 100%) indicates 100% charge and discharge. Odometer style accumulation of battery cycles. AvCap (0x1F) The AvCAP registers hold the calculated available capacity of the battery based on all inputs from the ModelGauge m5 algorithm, including empty compensation. This register provides unfiltered results. Jumps in the reported values can be caused by abrupt changes in load current or temperature. Refer to the ModelGauge m5 EZ User Guide for details. BIT 15 14 13 12 11 Field AvCap[15:8] Reset 0x05DC Access Type BIT 7 6 5 4 3 AvCap[7:0] Reset 0x05DC Access Type AvCap 9 8 2 1 0 Write, Read Field BITFIELD 10 Write, Read BITS 15:0 DESCRIPTION DECODE This is the remaining capacity with coulombcounter + Voltage-Fuel-Gauge mixing, after accounting for capacity that is unavailable due to the discharge rate. Register type: capacity TTF (0x20) The TTF register holds the estimated time-to-full for the application under present conditions. BIT 15 14 13 12 Field 11 10 9 8 3 2 1 0 TTF[15:8] Reset Access Type BIT Field Write, Read 7 6 5 4 TTF[7:0] Reset Access Type www.analog.com Write, Read Analog Devices | 146 MAX77658 BITFIELD TTF www.analog.com Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ BITS DESCRIPTION 15:0 The TTF value is determined by learning the constant current and constant voltage portions of the charge cycle based on experience of prior charge cycles. Time-to-full is then estimated by comparing the present charge current to the charge termination current. Operation of the TTF register assumes all charge profiles are consistent in the application. The TTF register is only valid when the current register is positive. DECODE Register type: time Analog Devices | 147 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ Typical Application Circuits Typical Application Circuit MAX77658 DC CHARGING SOURCE SYS CHGIN 4.7µF 25V (0603) 1µF 10V (0402) GND VL LINEAR CHARGER WITH POWER PATH SELECTOR REG 0.47µF 25V (0402) VSYS L 1.5µH CBST 10nF/6.3V (0201) BATT CHGR SYS FG TH 10k 100kΩ NTC VSYS CSYS 22µF/10V (0603) ModelGauge m5 EZ WITH CURRENT SENSING ALRT ALRT 4.7µF 6.3V (0603) IN_SBB SBB0 SIMO BUCK/BUCK-BOOST BST VSBB0 VSBB1 SBB2 PGND VSBB2 22µF 10V (0603) IN_LDO0 VSBB0 IN_LDO1 LDO/LSW VSBB1 LDO0 VLDO0 LDO1 GPIO0 GPIO1 GPIO2 GPIO0 VIO GPIO1 SDA SCL GPIO2 GPIO/I2C/AMUX AMUX nEN TOP LEVEL nRST nIRQ SYSTEM RESOURCES + LITHIUM ION BATTERY SBB1 LXA LXB * BATT 1µF 6.3V (0402) VLDO1 VIO/POWER SDA SCL * * AMUX nRST nIRQ PROCESSOR ADC INPUT * * *PULLUP RESISTORS NOT DRAWN www.analog.com Analog Devices | 148 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ Ordering Information PART TEMP RANGE PIN-PACKAGE OPTIONS MAX77658ANX+* -40°C to +125°C 36 WLP — MAX77658AANX+T -40°C to +125°C 36 WLP Table 2 MAX77658BANX+T -40°C to +125°C 36 WLP Table 2 MAX77658SANX+T -40°C to +125°C 36 WLP Table 2 +Denotes a lead(Pb)-free/RoHS-compliant package. T = Tape and reel. *Custom samples only. Not for production or stock. Contact factory for more information. www.analog.com Analog Devices | 149 MAX77658 Ultra-Low Power PMIC Featuring Single-Inductor, 3-Output Buck-Boost, 2-LDOs, Power-Path Charger, and Fuel Gauge for Small Li+ Revision History REVISION NUMBER REVISION DATE 0 10/21 Initial release 1 8/22 Updated Benefits and Features, Electrical Characteristics, Typical Operating Characteristics, Table 2, Table 3, On/Off Controller section, Table 6, Current Measurement section, Register Details, added SIMO Fault Indicator section, and LDO Fault Indicator section 1, 12, 20, 22, 25–32, 37, 38, 45–48, 70, 80, 88, 97, 101–118, 122, 126, 131–133, 136, 140, 141 2 9/22 Updated On/Off Controller section, Internal Wake-Up Flags section, Table 18, Power Register (0xB1), AvgPower Register (0xB3), and Register Details 46, 48, 85, 89, 141 DESCRIPTION PAGES CHANGED — Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. w w w . a n a l o g . c o m Analog Devices | 150