EVALUATION KIT AVAILABLE
MAX8550/MAX8551
Integrated DDR Power-Supply Solutions for
Desktops, Notebooks, and Graphic Cards
General Description
Features
The MAX8550/MAX8551 integrate a synchronous-buck
PWM controller to generate VDDQ, a sourcing and sinking
LDO linear regulator to generate VTT, and a 10mA reference output buffer to generate VTTR. The buck controller
drives two external N-channel MOSFETs to generate output voltages down to 0.7V from a 2V to 28V input with output currents up to 15A. The LDO can sink or source up to
1.5A continuous and 3A peak current. Both the LDO output and the 10mA reference buffer output can be made
to track the REFIN voltage. These features make the
MAX8550/MAX8551 ideally suited for DDR memory applications in desktops, notebooks, and graphic cards.
Buck Controller
o Quick-PWM with 100ns Load-Step Response
o Up to 95% Efficiency
o 2V to 28V Input Voltage Range
o 1.8V/2.5V Fixed or 0.7V to 5.5V Adjustable Output
o Up to 600kHz Selectable Switching Frequency
o Programmable Current Limit with Foldback
Capability
o 1.7ms Digital Soft-Start and Independent
Shutdown
o Overvoltage/Undervoltage-Protection Option
o Power-Good Window Comparator
LDO Section
o Fully Integrated VTT and VTTR Capability
o VTT has ±3A Sourcing/Sinking Capability
o VTT and VTTR Outputs Track VREFIN / 2
o All-Ceramic Output-Capacitor Designs
o 1.0V to 2.8V Input Voltage Range
o Power-Good Window Comparator
PIN-PACKAGE
28 5mm × 5mm TQFN
MAX8550ETI+
-40°C to +85°C
28 5mm × 5mm TQFN
MAX8551ETI
-40°C to +85°C
28 5mm × 5mm TQFN
MAX8551ETI+
-40°C to +85°C
28 5mm × 5mm TQFN
+Denotes a lead(Pb)-free/RoHS-compliant package.
PGND1
VDD
23
22
24
26
SKIP
(TP1 FOR
MAX8551)
GND
SHDNA
AVDD
27
25
SHDNB
TOP VIEW
28
Pin Configuration
+
TON
OVP/UVP
(N.C. FOR
MAX8551)
REF
1
21
DL
2
20
BST
3
19
LX
MAX8550
MAX8551
15
FB
14
7
REFIN
STBY
13
OUT
12
16
VTT
6
VTTI
VIN
POK2
11
DH
17
PGND2
18
5
9
4
10
ILIM
POK1
VTTS
DDR I and DDR II Memory Power Supplies
Desktop Computers
Notebooks and Desknotes
Graphic Cards
Game Consoles
RAID
Networking
TEMP RANGE
-40°C to +85°C
VTTR
Applications
PART
MAX8550ETI
8
The buck controller and LDO regulators are provided with
independent current limits. Adjustable lossless foldback
current limit for the buck regulator is achieved by monitoring the drain-to-source voltage drop of the low-side MOSFET. Additionally, overvoltage and undervoltage
protection mechanisms are built in. Once the overcurrent
condition is removed, the regulator is allowed to enter
soft-start again. This helps minimize power dissipation
during a short-circuit condition. The MAX8550/MAX8551
allow flexible sequencing and standby power management using the SHDNA, SHDNB, and STBY inputs.
Both the MAX8550 and MAX8551 are available in a
small 5mm × 5mm, 28-pin thin QFN package.
Ordering Information
SS
The PWM controller in the MAX8550/MAX8551 utilizes
Maxim’s proprietary Quick-PWM™ architecture with programmable switching frequencies of up to 600kHz. This
control scheme handles wide input/output voltage ratios
with ease and provides 100ns response to load transients while maintaining high efficiency and a relatively
constant switching frequency. The MAX8550 offers fully
programmable UVP/OVP and skip-mode options ideal in
portable applications. Skip mode allows for improved
efficiency at lighter loads. The MAX8551, which is targeted towards desktop and graphic-card applications,
does not offer the pulse-skip feature.
The VTT and VTTR outputs track to within 1% of VREFIN / 2.
The high bandwidth of this LDO regulator allows excellent transient response without the need for bulk capacitors, thus reducing cost and size.
5mm x 5mm Thin QFN
Typical Operating Circuit appears at end of data sheet.
Quick-PWM is a trademark of Maxim Integrated Products, Inc.
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.
19-3173; Rev 3; 4/13
MAX8550/MAX8551
Integrated DDR Power-Supply Solutions for
Desktops, Notebooks, and Graphic Cards
ABSOLUTE MAXIMUM RATINGS
VTTS to GND............................................-0.3V to (AVDD + 0.3V)
PGND1, PGND2 to GND .......................................-0.3V to +0.3V
REF Short Circuit to GND ...........................................Continuous
Continuous Power Dissipation (TA = +70°C)
28-Pin 5mm x 5mm TQFN (derate 35.7mW/°C
above +70°C).................................................................2.86W
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +165°C
Lead Temperature (soldering, 10s) .................................+300°C
VIN to GND .............................................................-0.3V to +30V
VDD, AVDD , VTTI to GND .........................................-0.3V to +6V
SHDNA, SHDNB, REFIN to GND..............................-0.3V to +6V
SS, POK1, POK2, SKIP, ILIM, FB to GND ................-0.3V to +6V
STBY, TON, REF, UVP/OVP to GND ........-0.3V to (AVDD + 0.3V)
OUT, VTTR to GND ..................................-0.3V to (AVDD + 0.3V)
DL to PGND1..............................................-0.3V to (VDD + 0.3V)
DH to LX ....................................................-0.3V to (VBST + 0.3V)
LX to BST..................................................................-6V to +0.3V
LX to GND .................................................................-2V to +30V
VTT to GND...............................................-0.3V to (VVTTI + 0.3V)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VIN = +15V, VDD = AVDD = V SHDNA = V SHDNB = VBST = VILIM = 5V, VOUT = VREFIN = VVTTI = 2.5V, UVP/OVP = STBY = FB = SKIP
= GND, PGND1 = PGND2 = LX = GND, TON = OPEN, VVTTS = VVTT, TA = -40°C to +85°C, unless otherwise noted. Typical values
are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MAIN PWM CONTROLLER
Input Voltage Range
Output Adjust Range
VIN
2
28
VDD, AVDD
4.5
5.5
VOUT
0.7
5.5
Output Voltage Accuracy
(Note 2)
Soft-Start Ramp Time
On-Time
Minimum Off-Time
VIN Quiescent Supply Current
tSS
tON
tOFF_MIN
0.693
0.7
0.707
FB = GND
2.47
2.5
2.53
FB = VDD
1.78
1.8
1.82
TON = GND (600kHz)
170
194
219
TON = REF (450kHz)
213
243
273
TON = OPEN (300kHz)
316
352
389
TON = AVDD (200kHz)
461
516
571
200
300
450
25
40
µA
1
5
µA
2.5
5
SHDNA = GND (only VTT and VTTR on)
2
4
STBY = AVDD (only VTTR and PWM on)
1
2
0.5
1
2
10
4.25
4.4
Rising edge of SHDNA to full current limit
VIN = 15V,
VOUT = 1.5V
(Note 3)
(Note 3)
1.7
SHDNA = SHDNB = GND
All on (PWM, VTT, and VTTR on)
AVDD Quiescent Supply Current
IAVDD
SHDNB = GND (only PWM on)
AVDD + VDD Shutdown Supply
Current
SHDNA = SHDNB = GND
AVDD Undervoltage-Lockout
Threshold
Rising edge of VIN
VDD Quiescent Supply Current
2
IVDD
V
FB = OUT
IIN
VIN Shutdown Supply Current
V
4.1
Hysteresis
50
Set VFB = 0.8V
1
V
ms
ns
ns
mA
µA
V
mV
5
µA
Maxim Integrated
MAX8550/MAX8551
Integrated DDR Power-Supply Solutions for
Desktops, Notebooks, and Graphic Cards
ELECTRICAL CHARACTERISTICS (continued)
(VIN = +15V, VDD = AVDD = V SHDNA = V SHDNB = VBST = VILIM = 5V, VOUT = VREFIN = VVTTI = 2.5V, UVP/OVP = STBY = FB = SKIP
= GND, PGND1 = PGND2 = LX = GND, TON = OPEN, VVTTS = VVTT, TA = -40°C to +85°C, unless otherwise noted. Typical values
are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
AVDD = 4.5V to 5.5V; IREF = 0
1.98
2
2.02
V
0.01
V
REFERENCE
Reference Voltage
VREF
Reference Load Regulation
IREF = 0 to 50µA
REF Undervoltage Lockout
VREF rising
1.93
V
Hysteresis
300
mV
FAULT DETECTION
OVP Trip Threshold
(Referred to Nominal VOUT)
UVP/OVP = AVDD (Note 4)
UVP Trip Threshold
(Referred to Nominal VOUT)
112
116
120
%
65
70
75
%
POK1 Trip Threshold
(Referred to Nominal VOUT)
Lower level, falling edge, 1% hysteresis
87
90
93
Upper level, rising edge, 1% hysteresis
107
110
113
POK2 Trip Threshold
(Referred to Nominal VVTTS
and VVTTR)
Lower level, falling edge, 1% hysteresis
87.5
90
92.5
Upper level, rising edge, 1% hysteresis
107.5
110
112.5
UVP Blanking Time
From rising edge of SHDNA
10
20
40
OVP, UVP, POK_ Propagation
Delay
OVP not applicable in MAX8551
POK_ Output Low Voltage
ISINK = 4mA
%
POK_ Leakage Current
ILIM Adjustment Range
%
10
VPOK_ = 5.5V, VFB = 0.8V, VVTTS = 1.3V
VILIM
0.25
ILIM Input Leakage Current
Current-Limit Threshold (Fixed)
PGND1 to LX
ms
µs
0.3
V
1
µA
2.00
V
0.1
µA
45
50
55
mV
Current-Limit Threshold
(Adjustable) PGND1 to LX
VILIM = 2V
170
200
235
mV
Current-Limit Threshold (Negative
Direction) PGND1 to LX
SKIP = AVDD (Note 4)
-75
-60
-45
mV
Current-Limit Threshold (Negative
Direction) PGND1 to LX
SKIP = AVDD, VILIM = 2V (Note 4)
-250
mV
3
mV
Thermal-Shutdown Threshold
+160
°C
Thermal-Shutdown Hysteresis
15
°C
Zero-Crossing Detection
Threshold PGND1 to LX
Maxim Integrated
3
MAX8550/MAX8551
Integrated DDR Power-Supply Solutions for
Desktops, Notebooks, and Graphic Cards
ELECTRICAL CHARACTERISTICS (continued)
(VIN = +15V, VDD = AVDD = V SHDNA = V SHDNB = VBST = VILIM = 5V, VOUT = VREFIN = VVTTI = 2.5V, UVP/OVP = STBY = FB = SKIP
= GND, PGND1 = PGND2 = LX = GND, TON = OPEN, VVTTS = VVTT, TA = -40°C to +85°C, unless otherwise noted. Typical values
are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
1
4
Ω
DL Gate-Driver On-Resistance in
High State
1
4
Ω
DL Gate-Driver On-Resistance in
Low State
0.5
3
Ω
MOSFET DRIVERS
DH Gate-Driver On-Resistance
Dead Time (Additional to
Adaptive Delay)
VBST - VLX = 5V
DH falling to DL rising
30
DL falling to DH rising
30
ns
INPUTS AND OUTPUTS
Logic Input Threshold
(SHDN_, STBY, SKIP (Note 4))
Rising edge
Hysteresis
Logic Input Current
(SHDN_, STBY, SKIP (Note 4))
Dual-Mode™ Input Logic
Levels (FB)
1.7
0.05
2.1
-0.1
High
V
µA
V
AVDD 0.4
3.15
3.85
REF
1.65
2.35
Low
OUT Input Resistance
µA
+0.1
Floating
Logic Input Current
(TON, OVP/UVP (Note 4))
V
mV
+1
Low (2.5V output)
High (1.8V output)
2.20
225
-1
Input Bias Current (FB)
Four-Level Input Logic Levels
(TON, OVP/UVP (Note 4))
1.20
0.5
-3
+3
FB = GND
90
175
350
FB = AVDD
70
135
270
FB adjustable mode
400
800
1600
25
OUT Discharge-Mode
On-Resistance
(Note 4)
10
DL Turn-On Level During
Discharge Mode
(Measured at OUT)
(Note 4)
0.3
µA
kΩ
Ω
V
Dual Mode is a trademark of Maxim Integrated Products, Inc.
4
Maxim Integrated
MAX8550/MAX8551
Integrated DDR Power-Supply Solutions for
Desktops, Notebooks, and Graphic Cards
ELECTRICAL CHARACTERISTICS (continued)
(VIN = +15V, VDD = AVDD = V SHDNA = V SHDNB = VBST = VILIM = 5V, VOUT = VREFIN = VVTTI = 2.5V, UVP/OVP = STBY = FB = SKIP
= GND, PGND1 = PGND2 = LX = GND, TON = OPEN, VVTTS = VVTT, TA = -40°C to +85°C, unless otherwise noted. Typical values
are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
LINEAR REGULATORS (VTTR AND VTT)
VTTI Input Voltage Range
VVTTI
VTTI Supply Current
IVTTI
REFIN Input Impedance
VREFIN = 2.5V
VREFIN
VREFIN rising
REFIN Lockout Threshold
Soft-Start Charge Current
ILOAD(MAX) - ⎜
⎟
2
⎝
⎠
where ILIM(VAL) equals the minimum valley current-limit
threshold voltage divided by the on-resistance of Q2
(RDS(ON)Q2). For the 50mV default setting, connect ILIM
to AVDD. In adjustable mode, the valley current-limit
threshold is precisely 1/10th* the voltage seen at ILIM.
For an adjustable threshold, connect a resistive divider
from REF to GND with ILIM connected to the center tap.
The external 250mV to 2V adjustment range corresponds
to a 25mV to 200mV valley current-limit threshold. When
adjusting the current limit, use 1% tolerance resistors and
*In the negative direction, the adjustable current limit is typically
-1/8th the voltage seen at ILIM.
22
Maxim Integrated
MAX8550/MAX8551
Integrated DDR Power-Supply Solutions for
Desktops, Notebooks, and Graphic Cards
a divider current of approximately 10µA to prevent significant inaccuracy in the valley current-limit tolerance.
Foldback Current Limit
Alternately, foldback current limit can be implemented
if the UVP latch option is not available. Foldback current limit reduces the power dissipation of external
components so they can withstand indefinite overload
and short circuit, with automatic recovery after the overload or short circuit is removed. To implement foldback
current limit, connect a resistor from VOUT to ILIM (R6
in Figure 7 and the Typical Applications Circuit), in
addition to the resistor-divider network (R4 and R5)
used for setting the adjustable current limit as shown in
Figure 7.
The following is a procedure for calculating the value of
R4, R5, and R6:
1) Calculate the voltage, VILIM(NOM), required at ILIM
when the output voltage is at nominal:
⎛ LIR ⎞
VILIM (NOM ) = 10 × ILOAD(MAX) × ⎜1⎟
2 ⎠
⎝
× RDS(ON)Q2
2) Pick a percentage of foldback, PFB, from 15%
to 40%.
3) Calculate the voltage, VILIM(0V), when the output is
shorted (0V):
VOUT
REF
CREF
MAX8550/
MAX8551
R4
ILIM
R6
GND
R5
VILIM(0V) = PFB × VILIM(NOM)
4) The value for R4 can be calculated as:
R4 =
2V - VILIM(0V)
10µA
5) The parallel combination of R5 and R6, denoted
R56, is calculated as:
⎛ 2V ⎞
R56 = ⎜
⎟ - R4
⎝ 10µA ⎠
6) Then R6 can be calculated as:
R6 =
VOUT × R4 × R56
⎡V
- VILIM(NOM) - VILIM(0V) × R4 -⎤
⎥
⎢ OUT
⎥
⎢
⎥
⎢ VILIM(NOM) − VILIM(0V) × R56
⎦
⎣
(
((
(
)
))
)
7) Then R5 is calculated as:
R5 =
R6 × R56
R6 - R56
Boost-Supply Diode and
Capacitor Selection (Buck)
A low-current Schottky diode, such as the CMDSH-3
from Central Semiconductor, works well for most applications. Do not use large-power diodes, because higher junction capacitance can charge up the voltage at
BST to the LX voltage and this exceeds the absolute
maximum rating of 6V. The boost capacitor should be
0.1µF to 4.7µF, depending on the input and output voltages, external components, and PC board layout. The
boost capacitance should be as large as possible to
prevent it from charging to excessive voltage, but small
enough to adequately charge during the minimum lowside MOSFET conduction time, which happens at maximum operating duty cycle (this occurs at minimum
input voltage). In addition, ensure that the boost capacitor does not discharge to below the minimum gate-tosource voltage required to keep the high-side MOSFET
Figure 7. Foldback Current Limit
Maxim Integrated
23
MAX8550/MAX8551
Integrated DDR Power-Supply Solutions for
Desktops, Notebooks, and Graphic Cards
C1
0.01µF
VTTI
C2
10µF
VTT
1.25V / ±1.5A
REFIN
AVDD
VTT
C4
60µF
VTTS
MAX8550
PGND2
VTTR
1.25V / 10mA
R1
10Ω
VDD
C6
1µF
VIN (4.5V TO 28V)
VIN
R3
100kΩ
BST
C7
0.22µF
POK
POK1
C8
2 x 10µF
SKIP
DH
Q1
IRF7821
N-CHANNEL
30V, 9mW
L1
TOKO FDA1254-1R0M
1.0µH, 21A, 1.6mΩ
TON
GND
C9
3.9nF
C14
470µF
(OPTIONAL)
LX
POK2
2.5V / 12A
SS
C10
0.22µF
DL
REF
R5
20kΩ
5V
BIAS
SUPPLY
C5
4.7µF
D1
CMOSH-3
VTTR
OVP/UVP
R2
100kΩ
C3
1µF
Q2
IRF7832
N-CHANNEL
30V,5mW
C11
150µF
C13
1µF
PGND1
R4
187kΩ
ILIM
SHDNA
FB
SHDNB
C11, C12 (150mF, 4V,
25mW, LOW-ESR POS
CAPACITOR (D2E)
SANYO 4TPE150M
ON
R6
41.2kΩ
C12
150µF
OFF
OUT
STBY
Figure 8. Typical Applications Circuit
fully enhanced for lowest on-resistance. This minimum
gate-to-source voltage (VGS(MIN)) is determined by:
VGS(MIN) = VDD x
QG
CBOOST
where VDD is 5V, QG is the total gate charge of the
high-side MOSFET, and CBOOST is the boost-capacitor
24
value where CBOOST is C7 in the Typical Applications
Circuit (Figure 8).
Transient Response (Buck)
The inductor ripple current also affects transientresponse performance, especially at low VIN - VOUT differentials. Low inductor values allow the inductor
current to slew faster, replenishing charge removed
from the output filter capacitors by a sudden load step.
Maxim Integrated
MAX8550/MAX8551
Integrated DDR Power-Supply Solutions for
Desktops, Notebooks, and Graphic Cards
The output sag is also a function of the maximum duty
factor, which can be calculated from the on-time and
minimum off-time:
⎡V
⎤
× K
L × ∆ILOAD(MAX)2 ⎢ OUT
+ t OFF(MIN) ⎥
VIN
⎣
⎦
VSAG =
⎡ ( VIN - VOUT ) × K
⎤
2COUT × VOUT ⎢
+ t OFF(MIN) ⎥
VIN
⎢⎣
⎥⎦
where t OFF(MIN) is the minimum off-time (see the
Electrical Characteristics) and K is from Table 1.
The overshoot during a full-load to no-load transient
due to stored inductor energy can be calculated as:
VSOAR =
∆ILOAD(MAX)2 × L
2 × COUT × VOUT
Applications Information
Dropout Performance (Buck)
The output-voltage adjustable range for continuousconduction operation is restricted by the nonadjustable
minimum off-time one-shot. For best dropout performance, use the slower (200kHz) on-time setting. When
working with low input voltages, the duty-factor limit
must be calculated using worst-case values for on- and
off-times. Manufacturing tolerances and internal propagation delays introduce an error to the TON K-factor.
This error is greater at higher frequencies (see Table
1). Also, keep in mind that transient-response performance of buck regulators operated too close to
dropout is poor, and bulk output capacitance must
often be added (see the VSAG equation in the Design
Procedure section).
The absolute point of dropout is when the inductor current ramps down during the minimum off-time (∆IDOWN)
as much as it ramps up during the on-time (∆IUP). The
ratio h = ∆IUP / ∆IDOWN indicates the controller’s ability
to slew the inductor current higher in response to
increased load, and must always be greater than 1. As
h approaches 1, the absolute minimum dropout point,
the inductor current cannot increase as much during
each switching cycle, and V SAG greatly increases,
unless additional output capacitance is used.
A reasonable minimum value for h is 1.5, but adjusting
this up or down allows trade-offs between VSAG, output
capacitance, and minimum operating voltage. For a
given value of h, the minimum operating voltage can be
calculated as:
Maxim Integrated
⎤
⎡
⎥
⎢
⎢ VOUT × VDROP1 ⎥
VIN(MIN) = ⎢
⎥ + VDROP2 - VDROP1
⎛ h × t OFF(MIN) ⎞ ⎥
⎢
1
⎜
⎟⎥
⎢
K
⎝
⎠⎦
⎣
where VDROP1 and VDROP2 are the parasitic voltage
drops in the discharge and charge paths (see the OnTime One-Shot (TON) section), tOFF(MIN) is from the
Electrical Characteristics, and K is taken from Table 1.
The absolute minimum input voltage is calculated with
h = 1.
If the calculated VIN(MIN) is greater than the required
minimum input voltage, then the operating frequency
must be reduced or output capacitance added to
obtain an acceptable VSAG. If operation near dropout is
anticipated, calculate VSAG to be sure of adequate
transient response.
A dropout design example follows:
VOUT = 2.5V
fSW = 600kHz
K = 1.7µs
tOFF(MIN) = 450ns
VDROP1 = VDROP2 = 100mV
h = 1.5
⎤
⎡
⎥
⎢
2
5
0
1
+
.
V
.
V
⎥ + 0.1V - 0.1V = 4.3V
VIN(MIN) = ⎢⎢
⎛ 1.5V × 450ns ⎞ ⎥
⎢1 - ⎜
⎟⎥
1.7µs
⎢⎣
⎝
⎠ ⎥⎦
Voltage Positioning (Buck)
In applications where fast-load transients occur, the
output voltage changes instantly by RESR × COUT ×
∆ILOAD. Voltage positioning allows the use of fewer output capacitors for such applications, and maximizes
the output-voltage AC and DC tolerance window in
tight-tolerance applications.
Figure 9 shows the connection of OUT and FB in a voltage-positioned circuit. In nonvoltage-positioned circuits, the MAX8550/MAX8551 regulate at the output
capacitor. In voltage-positioned circuits, the MAX8550/
MAX8551 regulate on the inductor side of the voltagepositioning resistor. VOUT is reduced to:
VOUT(VPS) = VOUT(NO _ LOAD) - RPOS × ILOAD
25
MAX8550/MAX8551
Integrated DDR Power-Supply Solutions for
Desktops, Notebooks, and Graphic Cards
+5V BIAS
SUPPLY
AVDD
VDD
IN
VIN
BST
MAX8550/
MAX8551
DH
RPOS
VOLTAGEPOSITIONED
OUTPUT
LX
DL
PGND1
GND
FB
OUT
Figure 9. Voltage-Positioned Output
PC Board Layout Guidelines
Careful PC board layout is critical to achieve low
switching losses and clean, stable operation. The
switching power stage requires particular attention. If
possible, mount all of the power components on the top
side of the board, with their ground terminals flush
against one another. Follow these guidelines for good
PC board layout:
• Keep the high-current paths short, especially at the
ground terminals. This practice is essential for stable, jitter-free operation.
• Keep the power traces and load connections short.
This practice is essential for high efficiency. Using
thick copper PC boards (2oz vs. 1oz) can enhance
full-load efficiency by 1% or more. Correctly routing
PC board traces is a difficult task that must be
approached in terms of fractions of centimeters,
where a single mΩ of excess trace resistance causes a measurable efficiency penalty.
• The LX and PGND1 connections to the low-side
MOSFET for current sensing must be made using
Kelvin-sense connections.
• When trade-offs in trace lengths must be made, it is
preferable to allow the inductor-charging path to be
made longer than the discharge path. For example,
it is better to allow some extra distance between the
input capacitors and the high-side MOSFET than to
allow distance between the inductor and the low26
side MOSFET or between the inductor and the output filter capacitor.
• Route high-speed switching nodes (BST, LX, DH,
and DL) away from sensitive analog areas (REF, FB,
and ILIM).
• Input ceramic capacitors must be placed as close
as possible to the high-side MOSFET drain and the
low-side MOSFET source. Position the MOSFETs so
the impedance between the input capacitor terminals and the MOSFETs is as low as possible.
Special Layout Considerations for LDO Section
The capacitor (or capacitors) at VTT should be placed
as close to VTT and PGND2 (pins 12 and 11) as possible to minimize the series resistance/inductance of the
trace. The PGND2 side of the capacitor must be short
with a low-impedance path to the exposed pad underneath the IC. The exposed pad must be star-connected
to GND (pin 24), PGND1 (pin 23), and PGND2 (pin 11).
A narrower trace can be used to connect the output
voltage on the VTT side of the capacitor back to VTTS
(pin 9). However, keep this trace well away from potentially noisy signals such as PGND1 or PGND2. This
prevents noise from being injected into the error amplifier’s input. For best performance, the VTTI bypass
capacitor must be placed as close to VTTI (pin 13) as
possible. REFIN (pin 14) should be separately routed
with a clean trace and adequately bypassed to GND.
Refer to the MAX8550 evaluation kit data sheet for PC
board guidelines.
Maxim Integrated
MAX8550/MAX8551
Integrated DDR Power-Supply Solutions for
Desktops, Notebooks, and Graphic Cards
Typical Operating Circuit
C1
0.01µF
REFIN
VTTI
C3
1µF
C2
VTT
0.9V - 1.25V / 1.5A
AVDD
VTT
R1
10Ω
VTTS
C4
VTTR
0.9V - 1.25V / 10mA
VTTR
C5
MAX8550/
MAX8551
VIN (4.5V TO 28V)
VIN
C6
OVP/UVP
R2
5V
BIAS
SUPPLY
VDD
PGND2
BST
R3
C8
C7
POK
POK1
LX
Q1
POK2
SKIP
DH
TON
GND
L1
Q2
C9
SS
1.8V - 2.5V / 12A
DL
C10
C11
REF
PGND1
R4
R5
ILIM
SHDNA
FB
SHDNB
ON
R6
Maxim Integrated
OUT
OFF
STBY
27
MAX8550/MAX8551
Integrated DDR Power-Supply Solutions for
Desktops, Notebooks, and Graphic Cards
Package Information
Chip Information
PROCESS: BiCMOS
28
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but the
drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE NO.
LAND
PATTERN NO.
28 TQFN-EP
T2855-6
21-0140
90-0026
Maxim Integrated
MAX8550/MAX8551
Integrated DDR Power-Supply Solutions for
Desktops, Notebooks, and Graphic Cards
Revision History
REVISION
NUMBER
REVISION
DATE
3
4/13
DESCRIPTION
Added MAX8551ETI+ to Ordering Information
PAGES
CHANGED
1
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent
licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and
max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 ________________________________ 29
© 2013 Maxim Integrated Products, Inc.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
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