MAX8632ETI+TG51

19-3623; Rev 1; 10/05 KIT ATION EVALU LE B A IL A AV Integrated DDR Power-Supply Solution for Desktops, Notebooks, and Graphic Cards Features The MAX8632 integrates a synchronous-buck PWM controller to generate VDDQ, a sourcing and sinking LDO linear regulator to generate VTT, and a 10mA reference output buffer to generate VTTR. The buck controller drives two external n-channel MOSFETs to generate output voltages down to 0.7V from a 2V to 28V input with output currents up to 15A. The LDO can sink or source up to 1.5A continuous and 3A peak current. Both the LDO output and the 10mA reference buffer output can be made to track the REFIN voltage. These features make the MAX8632 ideally suited for DDR memory applications in desktops, notebooks, and graphic cards. The PWM controller in the MAX8632 utilizes Maxim’s proprietary Quick-PWM™ architecture with programmable switching frequencies of up to 600kHz. This control scheme handles wide input/output voltage ratios with ease and provides 100ns response to load transients while maintaining high efficiency and a relatively constant switching frequency. The MAX8632 offers fully programmable UVP/OVP and skip-mode options ideal in portable applications. Skip mode allows for improved efficiency at lighter loads. The VTT and VTTR outputs track to within 1% of VREFIN / 2. The high bandwidth of this LDO regulator allows excellent transient response without the need for bulk capacitors, thus reducing cost and size. Buck Controller ♦ Quick-PWM with 100ns Load-Step Response ♦ Up to 95% Efficiency ♦ 2V to 28V Input Voltage Range ♦ 1.8V/2.5V Fixed or 0.7V to 5.5V Adjustable Output ♦ Up to 600kHz Selectable Switching Frequency ♦ Programmable Current Limit with Foldback Capability ♦ 1.7ms Digital Soft-Start ♦ Independent Shutdown and Standby Controls ♦ Overvoltage-/Undervoltage-Protection Option ♦ Power-Good Window Comparator LDO Section ♦ Fully Integrated VTT and VTTR Capability ♦ VTT Has ±3A Sourcing/Sinking Capability ♦ Only 20µF Ceramic Capacitance Required for VTT ♦ VTT and VTTR Outputs Track VREFIN / 2 ♦ All-Ceramic Output-Capacitor Designs ♦ 1.0V to 2.8V Input Voltage Range ♦ Power-Good Window Comparator + Denotes lead-free packaging. * EP = Exposed pad. 19 18 FB DH 20 VIN LX 21 OUT BST TOP VIEW DL Pin Configuration 17 16 15 VDD 22 14 REFIN PGND1 23 13 VTTI GND 24 12 VTT SKIP 25 11 PGND2 AVDD 26 10 VTTR SHDN 27 9 VTTS TPO 28 8 SS 2 3 4 5 6 7 POK1 POK2 STBY 1 ILIM MAX8632 REF DDR I and DDR II Memory Power Supplies Desktop Computers Notebooks and Desknotes Graphic Cards Game Consoles RAID Networking TEMP RANGE PIN-PACKAGE OVP/UVP Applications PART MAX8632ETI+ -40°C to +85°C 28 Thin QFN-EP* 5mm × 5mm TON The buck controller and LDO regulators are provided with independent current limits. Adjustable lossless foldback current limit for the buck regulator is achieved by monitoring the drain-to-source voltage drop of the low-side MOSFET. Additionally, overvoltage and undervoltage protection mechanisms are built in. Once the overcurrent condition is removed, the regulator is allowed to enter soft-start again. This helps minimize power dissipation during a short-circuit condition. The MAX8632 allows flexible sequencing and standby power management using the SHDN and STBY inputs, which support all DDR operating states. The MAX8632 is available in a small 5mm × 5mm, 28pin thin QFN package. Ordering Information 5mm x 5mm THIN QFN Typical Operating Circuit appears at end of data sheet. Quick-PWM is a trademark of Maxim Integrated Products, Inc. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX8632 General Description MAX8632 Integrated DDR Power-Supply Solution for Desktops, Notebooks, and Graphic Cards ABSOLUTE MAXIMUM RATINGS VTTS to GND............................................-0.3V to (AVDD + 0.3V) PGND1, PGND2, TP0 to GND ...............................-0.3V to +0.3V REF Short Circuit to GND ...........................................Continuous Continuous Power Dissipation (TA = +70°C) 28-Pin 5mm x 5mm Thin QFN (derate 35.7mW/°C above +70°C).................................................................2.86W Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C VIN to GND .............................................................-0.3V to +30V VDD, AVDD , VTTI to GND .........................................-0.3V to +6V SHDN, REFIN to GND ..............................................-0.3V to +6V SS, POK1, POK2, SKIP, ILIM, FB to GND ................-0.3V to +6V STBY, TON, REF, UVP/OVP to GND ........-0.3V to (AVDD + 0.3V) OUT, VTTR to GND ..................................-0.3V to (AVDD + 0.3V) DL to PGND1..............................................-0.3V to (VDD + 0.3V) DH to LX ....................................................-0.3V to (VBST + 0.3V) LX to BST..................................................................-6V to +0.3V LX to GND .................................................................-2V to +30V VTT to GND...............................................-0.3V to (VVTTI + 0.3V) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VIN = +15V, VDD = AVDD = V SHDN = STBY = VBST = VILIM = 5V, VOUT = VREFIN = VVTTI = 2.5V, UVP/OVP = TP0 = FB = SKIP = GND, PGND1 = PGND2 = LX = GND, TON = OPEN, VVTTS = VVTT, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS MAIN PWM CONTROLLER Input Voltage Range Output Adjust Range VIN 2 28 VDD, AVDD 4.5 5.5 VOUT Output Voltage Accuracy (Note 2) Soft-Start Ramp Time tSS 0.7 0.693 0.7 0.707 FB = GND 2.47 2.5 2.53 FB = VDD 1.78 1.8 1.82 Rising edge of SHDN to full current limit TON = GND (600kHz) On-Time Minimum Off-Time VIN Quiescent Supply Current tON tOFF_MIN AVDD Quiescent Supply Current VIN = 15V, VOUT = 1.5V (Note 3) IAVDD IVDD 219 213 243 273 352 389 TON = AVDD (200kHz) 461 516 571 200 300 450 ns 25 40 µA 1 5 µA STBY = GND (only VTTR and PWM on) Rising edge of VIN ms 194 316 All on (PWM, VTT, and VTTR on) AVDD Undervoltage-Lockout Threshold V TON = open (300kHz) SHDN = GND SHDN = GND 2 170 V TON = REF (450kHz) (Note 3) AVDD + VDD Shutdown Supply Current VDD Quiescent Supply Current 1.7 IIN VIN Shutdown Supply Current 5.5 FB = OUT V 2.5 5 1 2 20 4.05 4.25 Hysteresis 50 Set VFB = 0.8V 1 _______________________________________________________________________________________ 4.40 ns mA µA V mV 5 µA Integrated DDR Power-Supply Solution for Desktops, Notebooks, and Graphic Cards (VIN = +15V, VDD = AVDD = V SHDN = STBY = VBST = VILIM = 5V, VOUT = VREFIN = VVTTI = 2.5V, UVP/OVP = TP0 = FB = SKIP = GND, PGND1 = PGND2 = LX = GND, TON = OPEN, VVTTS = VVTT, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS AVDD = 4.5V to 5.5V; IREF = 0 1.98 2 2.02 V 0.01 V REFERENCE Reference Voltage VREF Reference Load Regulation IREF = 0 to 50µA REF Undervoltage Lockout VREF rising 1.93 V Hysteresis 300 mV FAULT DETECTION OVP Trip Threshold (Referred to Nominal VOUT) UVP/OVP = AVDD UVP Trip Threshold (Referred to Nominal VOUT) 112 116 120 % 65 70 75 % POK1 Trip Threshold (Referred to Nominal VOUT) Lower level, falling edge, 1% hysteresis 87 90 93 Upper level, rising edge, 1% hysteresis 107 110 113 POK2 Trip Threshold (Referred to Nominal VVTTS and VVTTR) Lower level, falling edge, 1% hysteresis 87.5 90 92.5 Upper level, rising edge, 1% hysteresis 107.5 110 112.5 % POK2 Disable Threshold (Measured at REFIN) VREFIN rising (hysteresis = 75mV typ) 0.7 UVP Blanking Time From rising edge of SHDN 10 OVP, UVP, POK_ Propagation Delay 20 0.9 V 40 ms 10 POK_ Output Low Voltage ISINK = 4mA POK_ Leakage Current ILIM Adjustment Range % VPOK_ = 5.5V, VFB = 0.8V, VVTTS = 1.3V VILIM 0.25 ILIM Input Leakage Current Current-Limit Threshold (Fixed) PGND1 to LX µs 0.3 V 1 µA 2.00 V 0.1 µA 45 50 55 mV Current-Limit Threshold (Adjustable) PGND1 to LX VILIM = 2V 170 200 235 mV Current-Limit Threshold (Fixed, Negative Direction) PGND1 to LX SKIP = AVDD -75 -60 -45 mV Current-Limit Threshold (Adjustable, Negative Direction) PGND1 to LX SKIP = AVDD, VILIM = 2V -250 mV 3 mV Thermal-Shutdown Threshold +160 °C Thermal-Shutdown Hysteresis 15 °C Zero-Crossing Detection Threshold PGND1 to LX _______________________________________________________________________________________ 3 MAX8632 ELECTRICAL CHARACTERISTICS (continued) MAX8632 Integrated DDR Power-Supply Solution for Desktops, Notebooks, and Graphic Cards ELECTRICAL CHARACTERISTICS (continued) (VIN = +15V, VDD = AVDD = V SHDN = STBY = VBST = VILIM = 5V, VOUT = VREFIN = VVTTI = 2.5V, UVP/OVP = TP0 = FB = SKIP = GND, PGND1 = PGND2 = LX = GND, TON = OPEN, VVTTS = VVTT, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 1 4 Ω DL Gate-Driver On-Resistance in High State 1 4 Ω DL Gate-Driver On-Resistance in Low State 0.5 3 Ω MOSFET DRIVERS DH Gate-Driver On-Resistance Dead Time (Additional to Adaptive Delay) VBST - VLX = 5V DH falling to DL rising 30 DL falling to DH rising 50 ns INPUTS AND OUTPUTS Logic Input Threshold (SHDN, STBY, SKIP) Rising edge Logic Input Current (SHDN, STBY, SKIP) Dual-Mode™ Input Logic Levels (FB) 1.7 0.05 2.1 -0.1 High µA V 3.15 3.85 1.65 2.35 0.5 -3 +3 µA FB = GND 90 175 FB = AVDD 70 135 270 FB adjustable mode 400 800 1600 10 25 Ω 0.1 0.20 V OUT Discharge-Mode On-Resistance DL Turn-On Level During Discharge Mode (Measured at OUT) 0.01 Dual Mode is a trademark of Maxim Integrated Products, Inc. 4 V +0.1 REF Low OUT Input Resistance µA AVDD 0.4 Floating Logic Input Current (TON, OVP/UVP) V mV +1 Low (2.5V output) High (1.8V output) 2.20 225 -1 Input Bias Current (FB) Four-Level Input Logic Levels (TON, OVP/UVP) 1.20 Hysteresis _______________________________________________________________________________________ 350 kΩ Integrated DDR Power-Supply Solution for Desktops, Notebooks, and Graphic Cards (VIN = +15V, VDD = AVDD = V SHDN = STBY = VBST = VILIM = 5V, VOUT = VREFIN = VVTTI = 2.5V, UVP/OVP = TP0 = FB = SKIP = GND, PGND1 = PGND2 = LX = GND, TON = OPEN, VVTTS = VVTT, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS LINEAR REGULATORS (VTTR AND VTT) VTTI Input Voltage Range VVTTI VTTI Supply Current IVTTI REFIN Input Impedance VREFIN = 2.5V VREFIN 12 0.01 ISS 20 1 VTT, VTTR UVLO Threshold (Measured at OUT) Soft-Start Charge Current ILOAD(MAX) -   2   where ILIM(VAL) equals the minimum valley current-limit threshold voltage divided by the on-resistance of Q2 (RDS(ON)Q2). For the 50mV default setting, connect ILIM to AVDD. In adjustable mode, the valley current-limit threshold is precisely 1/10th* the voltage seen at ILIM. For an adjustable threshold, connect a resistive divider from REF to GND with ILIM connected to the center tap. The external 250mV to 2V adjustment range corresponds to a 25mV to 200mV valley current-limit threshold. When adjusting the current limit, use 1% tolerance resistors and a divider current of approximately 10µA to prevent significant inaccuracy in the valley current-limit tolerance. Foldback Current Limit Alternately, foldback current limit can be implemented if the UVP latch option is not available. Foldback current limit reduces the power dissipation of external components so they can withstand indefinite overload and short circuit, with automatic recovery after the overload or short circuit is removed. To implement foldback current limit, connect a resistor from VOUT to ILIM (R6 in Figures 7 and 8), in addition to the resistor-divider *In the negative direction, the adjustable current limit is typically -1/8th the voltage seen at ILIM. 22 ______________________________________________________________________________________ Integrated DDR Power-Supply Solution for Desktops, Notebooks, and Graphic Cards The following is a procedure for calculating the value of R4, R5, and R6: 1) Calculate the voltage, VILIM(NOM), required at ILIM when the output voltage is at nominal:  LIR  VILIM(NOM) = 10 × ILOAD(MAX) × 1  2  × RDS(ON)Q2 VILIM(0V) = PFB × VILIM(NOM) 4) The value for R4 can be calculated as: 2V - VILIM(0V) 10µA 5) The parallel combination of R5 and R6, denoted R56, is calculated as:  2V  R56 =   - R4  10µA  VOUT REF VOUT × R4 × R56 V - VILIM(NOM) - VILIM(0V) × R4 -  OUT     VILIM(NOM) − VILIM(0V) × R56    ( (( ( ) R4 R5 )) ) 7) Then R5 is calculated as: R6 × R56 R6 - R56 Boost-Supply Diode and Capacitor Selection (Buck) A low-current Schottky diode, such as the CMDSH-3 from Central Semiconductor, works well for most applications. Do not use large-power diodes, because higher junction capacitance can charge up the voltage at BST to the LX voltage and this exceeds the absolute maximum rating of 6V. The boost capacitor should be 0.1µF to 4.7µF, depending on the input and output voltages, external components, and PC board layout. The boost capacitance should be as large as possible to prevent it from charging to excessive voltage, but small enough to adequately charge during the minimum lowside MOSFET conduction time, which happens at maximum operating duty cycle (this occurs at minimum input voltage). In addition, ensure that the boost capacitor does not discharge to below the minimum gate-tosource voltage required to keep the high-side MOSFET fully enhanced for lowest on-resistance. This minimum gate-to-source voltage (VGS(MIN)) is determined by: VGS(MIN) = VDD x CREF MAX8632 R6 = R5 = 2) Pick a percentage of foldback, PFB, from 15% to 40%. 3) Calculate the voltage, VILIM(0V), when the output is shorted (0V): R4 = 6) Then R6 can be calculated as: MAX8632 network (R4 and R5) used for setting the adjustable current limit as shown in Figure 7. QG CBOOST where VDD is 5V, QG is the total gate charge of the high-side MOSFET, and CBOOST is the boost-capacitor value where CBOOST is C7 in Figure 8. ILIM R6 GND Figure 7. Foldback Current Limit ______________________________________________________________________________________ 23 MAX8632 Integrated DDR Power-Supply Solution for Desktops, Notebooks, and Graphic Cards R6 20Ω VTTI C2 10µF VTT 1.25V / ±1.5A C1 0.1µF REFIN AVDD VTT C4 20µF VTTS C5 4.7µF D1 CMDSH-3 VIN (4.5V TO 28V) VIN R3 100kΩ BST C7 0.22µF POK1 POK1 POK2 POK2 SKIP C8 2 x 10µF C14 470µF (OPTIONAL) LX DH Q1 IRF7821 n-CHANNEL 30V, 9mΩ L1 TOKO FDA1254-1R0M 1.0µH, 21A, 1.6mΩ TON GND C9 3.9nF 2.5V / 12A SS C10 0.22µF DL REF R5 47.5kΩ 5V BIAS SUPPLY VDD VTTR C6 1µF OVP/UVP R2 100kΩ R1 10Ω MAX8632 PGND2 VTTR 1.25V / 10mA C3 1µF Q2 IRF7832 n-CHANNEL 30V,5mΩ C12 150µF C11 150µF C13 1µF PGND1 R4 100kΩ ILIM SHDN FB STBY C11, C12 (150µF, 4V, 25mΩ, LOW-ESR POS CAPACITOR (D2E) SANYO 4TPE150M ON OUT OFF TP0 Figure 8. Typical Application Circuit Transient Response (Buck) The inductor ripple current also affects transientresponse performance, especially at low VIN - VOUT differentials. Low inductor values allow the inductor current to slew faster, replenishing charge removed from the output filter capacitors by a sudden load step. The output sag is also a function of the maximum duty factor, which can be calculated from the on-time and minimum off-time: 24 V  × K L × ∆ILOAD(MAX)2  OUT + t OFF(MIN)  VIN   VSAG =  ( VIN - VOUT ) × K  2COUT × VOUT  + t OFF(MIN)  VIN   where t OFF(MIN) is the minimum off-time (see the Electrical Characteristics) and K is from Table 1. ______________________________________________________________________________________ Integrated DDR Power-Supply Solution for Desktops, Notebooks, and Graphic Cards VSOAR = ∆ILOAD(MAX)2 × L 2 × COUT × VOUT Applications Information Dropout Performance (Buck) The output-voltage adjustable range for continuousconduction operation is restricted by the nonadjustable minimum off-time one-shot. For best dropout performance, use the slower (200kHz) on-time setting. When working with low input voltages, the duty-factor limit must be calculated using worst-case values for on- and off-times. Manufacturing tolerances and internal propagation delays introduce an error to the TON K-factor. This error is greater at higher frequencies (see Table 1). Also, keep in mind that transient-response performance of buck regulators operated too close to dropout is poor, and bulk output capacitance must often be added (see the VSAG equation in the Design Procedure section). The absolute point of dropout is when the inductor current ramps down during the minimum off-time (∆IDOWN) as much as it ramps up during the on-time (∆IUP). The ratio h = ∆IUP / ∆IDOWN indicates the controller’s ability to slew the inductor current higher in response to increased load, and must always be greater than 1. As h approaches 1, the absolute minimum dropout point, the inductor current cannot increase as much during each switching cycle, and V SAG greatly increases, unless additional output capacitance is used. A reasonable minimum value for h is 1.5, but adjusting this up or down allows trade-offs between VSAG, output capacitance, and minimum operating voltage. For a given value of h, the minimum operating voltage can be calculated as:      VOUT + VDROP1  VIN(MIN) =  + VDROP2 - VDROP1  h × t OFF(MIN)   1     K   where VDROP1 and VDROP2 are the parasitic voltage drops in the discharge and charge paths (see the OnTime One-Shot (TON) section), tOFF(MIN) is from the Electrical Characteristics, and K is taken from Table 1. The absolute minimum input voltage is calculated with h = 1. If the calculated VIN(MIN) is greater than the required minimum input voltage, then the operating frequency must be reduced or output capacitance added to obtain an acceptable VSAG. If operation near dropout is anticipated, calculate V SAG to be sure of adequate transient response. A dropout design example follows: VOUT = 2.5V fSW = 600kHz K = 1.7µs tOFF(MIN) = 450ns VDROP1 = VDROP2 = 100mV h = 1.5   VIN(MIN) =   1    2.5V + 0.1V  + 0.1V - 0.1V = 4.3V  1.5 × 450ns     1.7µs    Voltage Positioning (Buck) In applications where fast-load transients occur, the output voltage changes instantly by RESR × COUT × ∆ILOAD. Voltage positioning allows the use of fewer output capacitors for such applications, and maximizes the output-voltage AC and DC tolerance window in tight-tolerance applications. Figure 9 shows the connection of OUT and FB in a voltage-positioned circuit. In nonvoltage-positioned circuits, the MAX8632 regulates at the output capacitor. In voltage-positioned circuits, the MAX8632 regulates on the inductor side of the voltage-positioning resistor. VOUT is reduced to: VOUT(VPS) = VOUT(NO _ LOAD) - RPOS × ILOAD PC Board Layout Guidelines Careful PC board layout is critical to achieve low switching losses and clean, stable operation. The switching power stage requires particular attention. If possible, mount all the power components on the top side of the board, with their ground terminals flush against one another. Follow these guidelines for good PC board layout: • Keep the high-current paths short, especially at the ground terminals. This practice is essential for stable, jitter-free operation. • Keep the power traces and load connections short. This practice is essential for high efficiency. Using ______________________________________________________________________________________ 25 MAX8632 The overshoot during a full-load to no-load transient due to stored inductor energy can be calculated as: MAX8632 Integrated DDR Power-Supply Solution for Desktops, Notebooks, and Graphic Cards +5V BIAS SUPPLY AVDD VDD IN VIN BST MAX8632 DH RPOS VOLTAGEPOSITIONED OUTPUT LX DL PGND1 GND FB OUT Figure 9. Voltage-Positioned Output • • • • 26 thick copper PC boards (2oz vs. 1oz) can enhance full-load efficiency by 1% or more. Correctly routing PC board traces is a difficult task that must be approached in terms of fractions of centimeters, where a single mΩ of excess trace resistance causes a measurable efficiency penalty. The LX and PGND1 connections to the low-side MOSFET for current sensing must be made using Kelvin-sense connections. When trade-offs in trace lengths must be made, it is preferable to allow the inductor-charging path to be made longer than the discharge path. For example, it is better to allow some extra distance between the input capacitors and the high-side MOSFET than to allow distance between the inductor and the lowside MOSFET or between the inductor and the output filter capacitor. Route high-speed switching nodes (BST, LX, DH, and DL) away from sensitive analog areas (REF, FB, and ILIM). Input ceramic capacitors must be placed as close as possible to the high-side MOSFET drain and the low-side MOSFET source. Position the MOSFETs so the impedance between the input capacitor terminals and the MOSFETs is as low as possible. Special Layout Considerations for LDO Section The capacitor (or capacitors) at VTT should be placed as close to VTT and PGND2 (pins 12 and 11) as possible to minimize the series resistance/inductance of the trace. The PGND2 side of the capacitor must be short with a low-impedance path to the exposed pad underneath the IC. The exposed pad must be star-connected to GND (pin 24) and PGND2 (pin 11). Connect PGND1 (pin 23) separately to the nearby PGND plane at the source of the low-side MOSFET. Do not connect this pin directly to the exposed pad as this can inject undesirable switching noise into the clean analog GND. Instead, PGND1 (pin 23) is connected to PGND2 (pin 11) by the large PGND plane. A narrower trace can be used to connect the output voltage on the VTT side of the capacitor back to VTTS (pin 9). For best performance, the VTTI bypass capacitor must be placed as close to VTTI (pin 13) as possible. REFIN (pin 14) should be separately routed with a clean trace and adequately bypassed to GND. Refer to the MAX8632 evaluation kit data sheet for PC board guidelines. ______________________________________________________________________________________ Integrated DDR Power-Supply Solution for Desktops, Notebooks, and Graphic Cards R8 C1 REFIN VTTI C2 C3 VTT 0.9V - 1.25V / 1.5A AVDD VTT C4 R1 VTTS 5V BIAS SUPPLY VDD PGND2 C5 VTTR 0.9V - 1.25V / 10mA VTTR C6 VIN (4.5V TO 28V) VIN OVP/UVP R2 D1 MAX8632 BST R3 C8 C7 POK1 POK1 POK2 POK2 LX Q1 SKIP DH TON GND L1 Q2 C9 SS 1.8V - 2.5V / 12A DL C10 C11 REF PGND1 R4 R5 ILIM SHDN FB STBY ON R7 R6 OUT OFF TP0 Chip Information TRANSISTOR COUNT: 5100 PROCESS: BiCMOS ______________________________________________________________________________________ 27 MAX8632 Typical Operating Circuit Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) QFN THIN.EPS MAX8632 Integrated DDR Power-Supply Solution for Desktops, Notebooks, and Graphic Cards 28 ______________________________________________________________________________________ Integrated DDR Power-Supply Solution for Desktops, Notebooks, and Graphic Cards Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 29 © 2005 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc. MAX8632 Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)