19-0587; Rev 3; 6/10
KIT
ATION
EVALU
E
L
B
AVAILA
High-Efficiency, Low-IQ, PMICs with Dynamic
Voltage Management for Mobile Applications
The MAX8660/MAX8661 power management ICs
(PMICs) power applications processors (APs) in smart
cellular phones, PDAs, Internet appliances, and other
portable devices.
Four step-down DC-DC outputs, three linear regulators,
and an 8th always-on LDO are integrated with powermanagement functions. Two dynamically controlled DCDC outputs power the processor core and internal memory. Two other DC-DC converters power I/O, memory,
and other peripherals. Additional functions include on/off
control for outputs, low-battery detection, reset output,
and a 2-wire I2C serial interface. The MAX8661 functions
the same as the MAX8660, except it lacks the REG1
step-down regulator and the REG7 linear regulator.
All step-down DC-to-DC outputs use fast 2MHz PWM
switching and tiny external components. They automatically switch from PWM to high-efficiency, light-load
operation to reduce operating current and extend battery life. In addition, a forced-PWM option allows lownoise operation at all loads. Overvoltage lockout protects the device against inputs up to 7.5V.
Applications
PDAs, Palmtops, and Wireless Handhelds
Smart Cell Phones
Personal Media Players
Portable GPS Navigation
Digital Cameras
Features
o Optimized for Marvell’s PXA300 and Armada 100
Family of Processors
o Protected to 7.5V—Shutdown Above 6.3V
o Four Synchronous Step-Down Converters
REG1, REG2, REG3, REG4
o Four LDO Regulators
REG5, REG6, REG7, REG8
o 2MHz Switching Allows Small Components
o Low, 20µA Deep-Sleep Current
o Low-Battery Monitor and Reset Output
Ordering Information
PART
PIN-PACKAGE
MAX8660ETL+
MAX8660ETL/V+
OPTIONS
40 Thin QFN
V1: 3.3V, 3.0V, 2.85V
V2: 3.3V, 2.5V, 1.8V
V3: 1.4V (default)
V4: 1.4V (default)
40 Thin QFN
V1: 3.3V, 3.0V, 2.85V
V2: 3.3V, 2.5V, 1.8V
V3: 1.4V (default)
V4: 1.4V (default)
Note: All devices are specified over the -40°C to 85°C operating
temperature range.
+Denotes lead(Pb)-free/RoHS-compliant package.
/V denotes an automotive qualified part.
Ordering Information continued at end of data sheet.
Simplified Functional Diagram
LBF
LBR
MR
RAMP
PG3
EN5
LX3
PV3
RSO
TOP VIEW
V3
Pin Configuration
30 29 28 27 26 25 24 23 22 21
MAIN BATTERY
20 V8
EN34 31
IN
19 AGND
EN2 32
SRAD 33
LBR
17 IN8
MAX8660ETL+
MAX8660AETL+
MAX8660BETL+
MAX8661ETL+
LX1 (N.C.) 35
PV1 (PV) 36
EN1 (GND) 37
14 PV2
V1 (GND) 38
13 LBO
SET1 (GND) 39
12 SDA
EXPOSED PAD (EP)
11 SCL
SET2
8
9
10
V2
PG4
7
V7 (N.C.)
6
V6
5
IN67 (IN6)
4
LX4
V5
3
PV4
2
IN5
V4 40
1
LBF
16 PG2
15 LX2
THIN QFN
5mm x 5mm x 0.8mm
VCC_IO: (PIN PROG)
3.3V/3.0V/2.85V AT 1.2A
V2
VCC_MEM: (PIN PROG)
1.8V/2.5V/3.3V AT 0.9A
V3
VCC_APPS: (I2C PROG)
0.725V TO 1.8V, DVM AT 1.6A
V4
VCC_SRAM: (I2C PROG)
0.725V TO 1.8V, DVM AT 0.4A
VCC_MVT: (I2C PROG)
1.7V TO 2.0V AT 200mA
MAX8660
18 IN
PG1 (GND) 34
V1
nBATT_FAULT
LBO
nRESET
RSO
MR
I2C
INTERFACE
V5
SCL
SDA
SYS_EN
EN1,2,5
PWR_EN
EN34
V6
VCC_CARD1: (I2C PROG)
1.8V TO 3.3V AT 500mA
V7
VCC_CARD2: (I2C PROG)
1.8V TO 3.3V AT 500mA
V8
VCC_BBATT:
3.3V ALWAYS ON AT 30mA
( ) ARE FOR THE MAX8661
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX8660/MAX8660A/MAX8660B/MAX8661
General Description
MAX8660/MAX8660A/MAX8660B/MAX8661
High-Efficiency, Low-IQ, PMICs with Dynamic
Voltage Management for Mobile Applications
Table of Contents
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Simplified Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Maxim vs. Marvell PXA3xx Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Step-Down DC-DC Converters (REG1–REG4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
REG1 (VCC_IO) Step-Down DC-DC Converter (MAX8660 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
REG2 (VCC_IO, VCC_MEM) Step-Down DC-DC Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
REG3 (VCC_APPS) Step-Down DC-DC Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
REG4 (VCC_SRAM) Step-Down DC-DC Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
REG1–REG4 Step-Down DC-DC Converter Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
REG1–REG4 Synchronous Rectification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
REG1/REG2 100% Duty-Cycle Operation (Dropout) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Linear Regulators (REG5–REG8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
REG5 (VCC_MVT, VCC_BG, VCC_OSC13M, VCC_PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
REG6/REG7 (VCC_CARD1, VCC_CARD2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
REG8 (VCC_BBATT) Always-On Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Ramp-Rate Control (RAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Enable Signals (EN_, PWR_EN, SYS_EN, I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
REG3/REG4 Enable (EN34, EN3, EN4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Power-Up and Power-Down Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Marvell PXA3xx Power Configuration Register (PCFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Voltage Monitors, Reset, and Undervoltage-Lockout Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Undervoltage and Overvoltage Lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Reset Output (RSO) and MR Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Low-Battery Detector (LBO, LBF, LBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Internal Off-Discharge Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Thermal-Overload Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
START and STOP Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Acknowledge Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Slave Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
I2C Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2
High-Efficiency, Low-IQ, PMICs with Dynamic
Voltage Management for Mobile Applications
Design Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Setting the Output Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Inductor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Input Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Output Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Step-Down Converter Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
PCB Layout and Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Package Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Chip Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Tables
Table 1. Maxim and Marvell PXA3xx Power Domain Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 2. Maxim and Marvell PXA3xx Digital Signal Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 3. SET1 Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 4. SET2 Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 5. Enable Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 6. Truth Table for V3/V4 Enable Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 7. Power Modes and Corresponding Quiescent Operating Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 8. Internal Off-Discharge Resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 9. I2C Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 10. DVM Voltage Change Register (VCC1, 0x20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 11. Serial Codes for V3 (VCC_APPS) and V4 (VCC_SRAM) Output Voltages. . . . . . . . . . . . . . . . . . . . . . 37
Table 12. Serial Codes for V5 Output Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 13. Serial Codes for V6 and V7 Output Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figures
Figure 1. Example MAX8660 Connection to Marvell PXA3xx Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 2. Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 3. Typical Applications Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 4. Soft-Start and Voltage-Change Ramp Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 5. V3/V4 Enable Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 6. Power-Up Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 7. Low-Battery Detector Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 8. START and STOP Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 9. Acknowledge Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 10. Slave Address Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Figure 11. Writing to the MAX8660/MAX8661 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Figure 12. Step-Down Converter Maximum Output Current Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
3
MAX8660/MAX8660A/MAX8660B/MAX8661
Table of Contents (continued)
MAX8660/MAX8660A/MAX8660B/MAX8661
High-Efficiency, Low-IQ, PMICs with Dynamic
Voltage Management for Mobile Applications
ABSOLUTE MAXIMUM RATINGS
IN, IN5, IN6, IN67, EN2, EN34, EN5, LBO, RSO, MR, SET1,
SET2, V1, V2, V3, V4, SCL, SDA,
SRAD to AGND..................................................-0.3V to +7.5V
LBF, LBR, EN1, RAMP to AGND .................-0.3V to (VIN + 0.3V)
V8 to AGND................................................-0.3V to (VIN8 + 0.3V)
V5 to AGND................................................-0.3V to (VIN5 + 0.3V)
V6, V7 to AGND........................................-0.3V to (VIN67 + 0.3V)
PV1 to PG1 ............................................................-0.3V to +7.5V
PV2 to PG2 ............................................................-0.3V to +7.5V
PV3 to PG3 ............................................................-0.3V to +7.5V
PV4 to PG4 ............................................................-0.3V to +7.5V
PV, PV1, PV2, PV3, PV4, IN8 to IN ........................-0.3V to +0.3V
LX1 Continuous RMS Current (Note 1) .................................2.3A
LX2 Continuous RMS Current (Note 1) .................................2.0A
LX3 Continuous RMS Current (Note 1) .................................2.6A
LX4 Continuous RMS Current (Note 1) .................................1.0A
PG1, PG2, PG3, PG4, EP to AGND.......................-0.6V to +0.6V
GND to AGND ......................................................-0.3V to +0.3V
All REGx Output Short-Circuit Duration......................Continuous
Continuous Power Dissipation (TA = +70°C)
40-Pin Thin QFN (derate 35.7mW/°C above +70°C).....2857mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
Note 1: LX_ has internal clamp diodes to PG_ and PV_. Applications that forward bias these diodes must take care not to exceed
the IC’s package power-dissipation limits.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VIN = VIN5 = VIN67 = VIN8 = 3.6V, Figure 3, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
PARAMETER
PV1, PV2, PV3, PV4, IN, IN8
Supply Voltage Range
SYMBOL
VIN
IN Undervoltage-Lockout
Threshold
VUVLO
IN Overvoltage-Lockout
Threshold
VOVLO
Input Current
4
IIN + IPV1 +
IPV2 + IPV3 +
IPV4 + IIN5 +
IIN67 + IIN8
CONDITIONS
PV1, PV2, PV3, PV4, IN, and IN8 must be
connected together externally
MIN
TYP
2.6
MAX
UNITS
6.0
V
VIN rising
2.250
2.400
2.550
VIN falling
2.200
2.350
2.525
VIN rising
6.20
6.35
6.50
VIN falling
6.00
6.15
6.30
No load;
SDA = SCL = V8
Only V8 on (deep-sleep
power mode)
20
V1, V2, and V8 on;
V1 and V2 in normal (skip)
operating mode
50
V1, V2, V5, and V8 on
(sleep power mode);
V1 and V2 in normal (skip)
operating mode
90
V
V
µA
V1, V2, V3, V4, V5, and V8 on
(run power mode);
V1, V2, V3, and V4 in normal
(skip) operating mode
140
V1, V2, V3, V4, V5, V6, V7,
and V8 (all on);
V1, V2, V3, and V4 in normal
(skip) operating mode
250
Undervoltage lockout, VIN = 2.2V
1.5
Overvoltage lockout, VIN = 6.5V
25
High-Efficiency, Low-IQ, PMICs with Dynamic
Voltage Management for Mobile Applications
(VIN = VIN5 = VIN67 = VIN8 = 3.6V, Figure 3, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
PARAMETER
PWM Switching Frequency
SYMBOL
CONDITIONS
fSW
MIN
TYP
MAX
UNITS
1.9
2.0
2.1
MHz
REG1—SYNCHRONOUS STEP-DOWN DC-DC CONVERTER (MAX8660, MAX8660A, MAX8660B only)
V1 Voltage
Accuracy (MAX8860/MAX8860B)
V1 Voltage Accuracy (MAX8660A)
V1
V1
V1 Load Regulation
SET1 = IN, VPV1 = 4.2V, load = 600mA
3.250
3.300
3.350
SET1 not connected, VPV1 = 3.6V,
load = 600mA
2.955
3.000
3.045
SET1 = AGND, VPV1 = 3.6V, load = 600mA
SET1 = IN, VPV1 = 4.2V, load = 600mA
2.807
2.463
2.850
2.500
2.893
2.538
SET1 not connected, VPV1 = 3.6V,
load = 600mA
1.970
2.000
2.030
SET1 = AGND, VPV1 = 3.6V, load = 600mA
1.773
1.800
1.827
Load = 0 to 1200mA
V
V
-1.5
%/A
V1 Line Regulation
0.15
%/V
SET1 Input Leakage Current
0.01
µA
V1 Dropout Voltage
Load = 800mA (Notes 3, 4)
150
Load = 1200mA (Notes 3, 4)
200
mV
p-Channel On-Resistance
RP1
0.12
Ω
n-Channel On-Resistance
RN1
0.15
Ω
p-Channel Current-Limit
Threshold
ILIM1
1.5
n-Channel Zero-Crossing
Threshold
n-Channel Negative Current Limit
REG1 Maximum Output Current
Forced-PWM mode only
IOUT1
2.6V ≤ VPV1 ≤ 6V (Note 5)
VPV1 = 6V, LX1 =
PG1 or PV1,
VEN1 = 0V
TA = +25°C
2.2
-2
mA
-975
mA
5
µA
A
±0.03
+2
µA
±0.2
TA = +85°C
A
25
1.2
V1 Bias Current
LX1 Leakage Current
1.8
Soft-Start Ramp Rate
(MAX8660/MAX8860B)
To V1 = 3.3V (total ramp time is 450µs for
all V1 output voltages)
5
7
9
mV/µs
Soft-Start Ramp Rate
(MAX8660A)
To V1 = 2.5V (total ramp time is 450µs for
all V1 output voltages)
3
5
7
mV/µs
V5 to V1 Enable Time
tVMHVSH1
Figure 6
Internal Off-Discharge Resistance
Minimum Duty Cycle
Maximum Duty Cycle
Forced-PWM mode only, min duty cycle in
skip mode is 0%
350
µs
650
Ω
16.7
%
100
%
5
MAX8660/MAX8660A/MAX8660B/MAX8661
ELECTRICAL CHARACTERISTICS (continued)
MAX8660/MAX8660A/MAX8660B/MAX8661
High-Efficiency, Low-IQ, PMICs with Dynamic
Voltage Management for Mobile Applications
ELECTRICAL CHARACTERISTICS (continued)
(VIN = VIN5 = VIN67 = VIN8 = 3.6V, Figure 3, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
REG2—SYNCHRONOUS STEP-DOWN DC-DC CONVERTER
SET2 = IN, VPV2 = 4.2V, load = 600mA
V2 Voltage
Accuracy (MAX8660/MAX8860B)
V2 Voltage Accuracy (MAX8660A)
V2
V2
V2 Load Regulation
SET2 not connected, VPV2 = 3.6V,
load = 600mA
MIN
TYP
MAX
3.250
3.300
3.350
2.463
2.500
2.538
SET2 = AGND, VPV2 = 3.6V, load = 600mA
1.773
1.800
1.827
SET2 = IN, VPV2 = 4.2V, load = 600mA
2.463
2.500
2.538
SET2 not connected, VPV2 = 3.6V,
load = 600mA
1.970
2.000
2.030
SET2 = AGND, VPV2 = 3.6V, load = 600mA
1.773
1.800
1.827
Load = 0 to 900mA
UNITS
V
V
-1.7
%/A
V2 Line Regulation
0.15
%/V
SET2 Input Leakage Current
0.01
µA
225
mV
Ω
V2 Dropout Voltage
Load = 900mA (Notes 3, 4)
p-Channel On-Resistance
RP2
0.18
n-Channel On-Resistance
RN2
0.15
p-Channel Current-Limit Threshold
ILIM2
1.10
n-Channel Zero Crossing Threshold
n-Channel Negative Current Limit
REG2 Maximum Output Current
Forced-PWM mode only
IOUT2
2.6V ≤ VPV2 ≤ 6V (Note 5)
Ω
1.50
25
mA
mA
A
5
VPV2 = 6V,
LX2 = PG2 or PV2,
VEN2 = 0V
LX2 Leakage Current
TA = +25°C
+2
0.2
2
tVMHVSH2 Figure 6
Internal Off-Discharge Resistance
Forced-PWM mode only; min duty cycle in
skip mode is 0%
Minimum Duty Cycle
±0.03
µA
µA
TA = +85°C
To V2 = 1.8V (total ramp time is 450µs for
all V2 output voltages)
Soft-Start Ramp Rate
-2
A
-800
0.9
V2 Bias Current
V5 to V2 Enable Time
1.30
Maximum Duty Cycle
4
6
mV/µs
350
µs
650
Ω
16.7
%
100
%
REG3—SYNCHRONOUS STEP-DOWN DC-DC CONVERTER
V3 Output Voltage Accuracy
V3
MAX8860/MAX8660A/MAX8661 REG3
default output voltage, VPV3 = 3.6V,
load = 600mA
1.379
MAX8860B REG3 default output voltage,
VPV3 = 3.6V, load = 600mA
1.133
REG3 serial programmed from 0.9V to 1.8V,
load = 600mA (Note 6)
1.400
1.421
V
1.150
-1.5
1.167
+1.5
%
V3 Load Regulation
Load = 0 to 1600mA
-17
mV/A
V3 Line Regulation
(Note 7)
0.05
%/V
p-Channel On-Resistance
RP3
0.12
Ω
n-Channel On-Resistance
RN3
0.08
Ω
6
High-Efficiency, Low-IQ, PMICs with Dynamic
Voltage Management for Mobile Applications
(VIN = VIN5 = VIN67 = VIN8 = 3.6V, Figure 3, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
PARAMETER
SYMBOL
p-Channel Current-Limit Threshold
ILIM3
CONDITIONS
MIN
TYP
MAX
1.85
2.15
2.45
n-Channel Zero-Crossing Threshold
n-Channel Negative Current Limit
REG3 Maximum Output Current
Forced-PWM mode only
IOUT3
2.6V ≤ VPV3 ≤ 6V (Note 5)
VPV3 = 6V, LX3 = PG3 or
PV3, VEN34 = 0V
LX3 Leakage Current
-2
TA = +85°C
MAX8660/MAX8660A/MAX8661, RRAMP =
56kΩ to 1.4V
MAX8660B, RRAMP = 56kΩ to 1.15V
Soft-Start Ramp Rate
V3 Dynamic-Change Ramp Rate
EN34 to V3 Enable Time
TA = +25°C
tPHLVTH3
mA
-0.8
A
0.01
µA
A
+0.03
+2
0.24
8
µA
mV/µs
6.7
RRAMP = 56kΩ
10
MAX8660/MAX8660A/MAX8661, powering
up to 1.4V, Figure 6, RRAMP = 56kΩ
400
MAX8660B, powering up to 1.15V, Figure 6,
RRAMP = 56kΩ
400
mV/µs
µs
Internal Off-Discharge Resistance
Forced-PWM mode only, min duty cycle in
skip mode is 0%
Minimum Duty Cycle
A
25
1.6
V3 Bias Current
UNITS
Maximum Duty Cycle
550
Ω
16.7
%
100
%
REG4—SYNCHRONOUS STEP-DOWN DC-DC CONVERTER
V4 Output Voltage Accuracy
V4
MAX8660/MAX8660A/MAX8661 REG4 default
output voltage, VPV4 = 3.6V, load = 200mA
1.379
1.400
1.421
MAX8660B REG4 default output voltage,
VPV4 = 3.6V, load = 200mA
1.133
1.150
1.167
REG4 serial programmed from 0.9V to 1.8V,
load = 200mA (Note 6)
V4 Load Regulation
V
-1.5
Load = 0 to 400mA
V4 Line Regulation
(Note 7)
+1.5
%
-40
mV/A
0.1
%/V
p-Channel On-Resistance
RP4
0.37
Ω
n-Channel On-Resistance
RN4
0.3
Ω
p-Channel Current-Limit Threshold
ILIM4
0.65
n-Channel Zero-Crossing Threshold
n-Channel Negative Current Limit
REG4 Maximum Output Current
Forced-PWM mode only
IOUT4
2.6V ≤ VPV4 ≤ 6V (Note 5)
Soft-Start Ramp Rate
V4 Dynamic-Change Ramp Rate
VPV4 = 6V, LX4 = PG4 or
PV4, VEN34 = 0V
0.90
TA = +25°C
TA = +85°C
MAX8660/MAX8660A/MAX8661,
RRAMP = 56kΩ to 1.4V
-2
A
25
mA
-975
mA
0.01
µA
0.4
V4 Bias Current
LX4 Leakage Current
0.78
A
±0.02
0.12
8
MAX8660B, RRAMP = 56kΩ to 1.15V
6.7
RRAMP = 56kΩ
10
+2
µA
mV/µs
mV/µs
7
MAX8660/MAX8660A/MAX8660B/MAX8661
ELECTRICAL CHARACTERISTICS (continued)
MAX8660/MAX8660A/MAX8660B/MAX8661
High-Efficiency, Low-IQ, PMICs with Dynamic
Voltage Management for Mobile Applications
ELECTRICAL CHARACTERISTICS (continued)
(VIN = VIN5 = VIN67 = VIN8 = 3.6V, Figure 3, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
PARAMETER
EN34 to V4 Enable Time
SYMBOL
tPHLVTH4
CONDITIONS
MIN
400
MAX8660B, powering up to 1.15V, Figure 6,
RRAMP = 56kΩ
400
Maximum Duty Cycle
REG5 LDO
IN5 Input Voltage Range
Forced-PWM mode only, minimum duty
cycle in skip mode is 0%
V5 Output Voltage
V5 Output Current Limit
VIN5
V5
UNITS
550
Ω
16.7
%
100
%
2.35
REG5 default output voltage, 2.35V ≤ VIN5 ≤
6V, load = 0 to 200mA
1.764
REG5 serial programmed from 1.7V to 2.0V,
2.35V ≤ VIN5 ≤ 6V, load = 0 to 200mA
-2
IOUT5
MAX
µs
Internal Off-Discharge Resistance
Minimum Duty Cycle
TYP
MAX8660/MAX8660A/MAX8661, powering
up to 1.4V, Figure 6, RRAMP = 56kΩ
225
1.800
350
VIN
V
1.836
V
+2
%
500
mA
V5 Output-Voltage Noise
10Hz to 100kHz, IOUT5 = 10mA
160
µVRMS
V5 Power-Supply Rejection
VIN5 = (V5 + 1V), IOUT5 = 10mA, f = 10kHz
40
dB
V5 Soft-Start Ramp Rate
Powering up to 1.8V (total ramp time is
225µs for all V5 output voltages)
EN5 to V5 Enable Time
tSEHVMH
V5 Dynamic-Change Ramp Rate
5
7
9
mV/µs
Figure 6
290
µs
RRAMP = 56kΩ
10
mV/µs
2
kΩ
Internal Off-Discharge Resistance
REG6, REG7 LDOs
IN67 Input Voltage Range
REG6 and REG7 Output Voltage
(POR Default to 0V, Set by Serial
Input)
VIN67
V6
V7
V6, V7 Dropout Voltage
V6, V7 Output Current Limit
IOUT6
IOUT7
Setting from 1.8V to 3.3V in 0.1V steps,
load = 0 to 300mA
VIN
V
-3
+3
%
100
mV
3V mode, load = 300mA (Note 3)
55
VIN67 = 3.6V
750
Powering up to 3.3V (total ramp time is
450µs for all V6/V7 output voltages)
V6, V7 Soft-Start Ramp Rate
2.35
5
Internal Off-Discharge Resistance
7
mA
9
mV/µs
Ω
350
REG8 ALWAYS-ON LDO
V8 Output Voltage
V8
V8 Dropout Voltage
V8 Output Current Limit
Load = 0 to 15mA
3.168
3.300
3.432
Load = 30mA
2.800
3.2
3.432
Load = 15mA (Note 3)
IOUT8
V8 = 2.5V
180
30
Internal Off-Discharge Resistance
70
V
mV
135
1.5
mA
kΩ
LOW-BATTERY DETECTOR (LBF, LBR, LBO)
Low-Battery Falling Threshold
VLBFTH
1.182
1.200
1.218
V
Low-Battery Rising Threshold
VLBRTH
1.231
1.250
1.268
V
8
High-Efficiency, Low-IQ, PMICs with Dynamic
Voltage Management for Mobile Applications
(VIN = VIN5 = VIN67 = VIN8 = 3.6V, Figure 3, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
PARAMETER
SYMBOL
LBO, RSO Output-High Leakage
Current
LBO Output Low Level
Minimum VIN for LBO Assertion
LBO Deassert Delay
tVBHBFH
CONDITIONS
MAX
UNITS
VIN = 6V, TA = +25°C
0.2
µA
2.6V ≤ VIN ≤ 6V, sinking 3mA
0.2
VIN = 1V, sinking 100µA
0.4
LBO is forced low when the device is in
UVLO
1
Figure 6
0
TA = +25°C
LBF and LBR Input Bias Current
MIN
-50
TA = +85°C
TYP
V
V
3
0
µs
+50
0.5
nA
RESET (MR, RSO)
RSO Threshold
RSO Deassert Delay
VRSOTH
tVBHRSTH
RSO Output-High Leakage
Current
RSO Output Low Level
Voltage on V8, falling, hysteresis is 5% (typ)
2.1
2.2
2.3
V
Figure 6
20
24
28
ms
VIN = 6V, TA = +25°C
0.2
µA
2.6V ≤ VIN ≤ 6V, sinking 3mA
0.2
VIN = 1V, sinking 100µA
0.4
Minimum VIN for RSO Assertion
RSO is forced low when the device is in
UVLO
MR Input High Level
2.6V ≤ VIN ≤ 6V
MR Input Low Level
2.6V ≤ VIN ≤ 6V
MR Input Leakage Current
VIN = 6V, TA = +25°C
MR Minimum Pulse Width
V
1
V
1.4
V
-0.2
tMR
0.4
V
+0.2
µA
1
µs
+160
°C
15
°C
THERMAL-OVERLOAD PROTECTION
Thermal-Shutdown Temperature
TJ rising
Thermal-Shutdown Hysteresis
ENABLE INPUTS (EN1, EN2, EN34, EN5)
EN_ Input High Level
2.6V ≤ VIN ≤ 6V
EN_ Input Low Level
2.6V ≤ VIN ≤ 6V
EN_ Input Leakage Current
VIN = 6V, TA = +25°C
1.4
V
-0.2
0.4
V
+0.2
µA
I2C LOGIC (SDA, SCL, SRAD)
SCL, SDA Input High Voltage
1.4
V
SCL, SDA Input Low Voltage
SCL, SDA Input Hysteresis
SCL, SDA Input Current
TA = +25°C, IN = AGND, VIN = 6V
SDA Output Low Voltage
2.6V ≤ VIN ≤ 6V, sinking 3mA
SRAD Input High Level
2.6V ≤ VIN ≤ 6V
SRAD Input Low Level
2.6V ≤ VIN ≤ 6V
SRAD Input Leakage Current
0.4
V
+10
µA
0.1
-10
V
0.2
1.4
o
VIN = 6V, TA = +25 C
-0.2
V
V
0.4
V
+0.2
µA
9
MAX8660/MAX8660A/MAX8660B/MAX8661
ELECTRICAL CHARACTERISTICS (continued)
MAX8660/MAX8660A/MAX8660B/MAX8661
High-Efficiency, Low-IQ, PMICs with Dynamic
Voltage Management for Mobile Applications
ELECTRICAL CHARACTERISTICS (continued)
(VIN = VIN5 = VIN67 = VIN8 = 3.6V, Figure 3, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
400
kHz
I2C
TIMING
Clock Frequency
Hold Time (Repeated) START
Condition
fSCL
tHD;STA
Figure 8
0.6
µs
CLK Low Period
tLOW
1.3
µs
CLK High Period
tHIGH
0.6
µs
Set-Up Time for a Repeated
START Condition
tSU;STA
Figure 8
0.6
µs
DATA Hold Time
tHD;DAT
Figure 9
0
µs
DATA Set-Up Time
tSU;DAT
Figure 9
100
ns
Set-Up Time for STOP Condition
tSU;STO
Figure 8
0.6
µs
1.3
µs
Bus-Free Time Between STOP
and START
Maximum Pulse Width of Spikes
that Must Be Suppressed by the
Input Filter of Both DATA and
CLK Signals
tBUF
50
ns
Note 2: Limits are 100% production tested at TA = +25°C. Limits over the operating temperature range are guaranteed through correlation using statistical quality control (SQC) methods.
Note 3: The dropout voltage is defined as VIN - VOUT when VOUT is 100mV below the nominal value of VOUT.
Note 4: Dropout voltage (VDO) is a function of the p-channel switch resistance (RP) and the inductor resistance (RL).
The given values assume RL = 50mΩ for the REG1 inductor and 67mΩ for the REG2 inductor:
VDO = ILOAD (RP + RL)
Note 5: The maximum output current is guaranteed by correlation to the p-channel current-limit threshold, p-channel on-resistance,
n-channel on-resistance, oscillator frequency, input voltage range, and output voltage range. The maximum output current
in the Electrical Characteristics table is the worst-case output current for the components shown in Figure 3 over then entire
specified range of input and output voltage. More output current may be available when alternate components and voltage
ranges are used. See the Step-Down Converter Output Current section for more information.
Note 6: Tested at 1.4V default output voltage for the MAX8660, MAX8660A, and MAX8661. Tested at 1.15V default output voltage
for the MAX8660B.
Note 7: All output voltages are possible in normal mode. In forced-PWM mode, the minimum output voltage is limited by 0.167 x
VIN. For example, with VIN = 5.688V, the minimum output is 0.95V.
10
High-Efficiency, Low-IQ, PMICs with Dynamic
Voltage Management for Mobile Applications
QUIESCENT CURRENT
vs. INPUT VOLTAGE
QUIESCENT CURRENT (µA)
80
70
60
50
40
30
20
2.5
MAX8660 toc02
SDA = SDL = V8
REG1–REG7 DISABLED
REG8 IS ALWAYS ON
90
2.4
SWITCHING FREQUENCY (MHz)
100
MAX8660/61 toc01
SWITCHING FREQUENCY
vs. INPUT VOLTAGE
10
2.3
2.2
2.1
2.0
1.9
1.8
1.7
1.6
0
1.5
2.5
3.0
3.5 4.0 4.5 5.0
INPUT VOLTAGE (V)
5.5
6.0
2.5
3.0
SWITCHING FREQUENCY
vs. TEMPERATURE
5.5
6.0
EN1/EN2/EN5 ENABLE RESPONSE
MAX8660 toc04
MAX8660 toc03
2.3
SWITCHING FREQUENCY (MHz)
3.5 4.0 4.5 5.0
INPUT VOLTAGE (V)
2.2
5V/div
EN1/EN2/EN5
2.1
1V/div
V2
1V/div
2.0
V5
1.9
1.8
1V/div
V1
1.7
-40
-15
10
35
TEMPERATURE (°C)
60
85
100µs/div
EN34 ENABLE RESPONSE
MAX8660 toc05
2V/div
EN34
500mV/div
V3
500mV/div
V4
MAX8660
RRAMP = 56kΩ
100µs/div
11
MAX8660/MAX8660A/MAX8660B/MAX8661
Typical Operating Characteristics
(Circuit of Figure 3, VIN = 3.6V, TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics (continued)
(Circuit of Figure 3, VIN = 3.6V, TA = +25°C, unless otherwise noted.)
80
75
VIN = 4.2V
70
65
VIN = 3.6V
60
VIN
1V/div
3.6V
3.2
ILOAD = 1000mA
3.0
2.8
2.6
V1 = 3.3V
L1 = 1.2µH
(TOKO DE2812C)
55
5.0V
100mV/div
V1
2.4
600mA LOAD,
V1 = 3.3V
3.3V OUTPUT
2.2
50
0.01
0.1
1
10
2.5
1000 10,000
100
3.0
LOAD CURRENT (mA)
3.36
3.32
-1.5%/A
3.28
3.26
3.34
3.32
3.30
3.28
3.26
3.24
3.24
FORCED-PWM
NORMAL
3.22
200
400
600
800
LOAD CURRENT (mA)
1000
1200
100
0
-40
-15
10
35
TEMPERATURE (°C)
60
85
REG 1 HEAVY-LOAD SWITCHING WAVEFORMS
REG1 LOAD TRANSIENT
150
600mA LOAD
3.20
0
200
50
3.22
3.20
THE NOMINAL ESR OF TOKO'S 1.2µH
DE2812C INDUCTOR IS 44mΩ. THE NOMINAL
p-CHANNEL RESISTANCE OF THE REG1 IS
120mΩ. THE SLOPE OF THIS LINE SHOWS THAT
THE TOTAL REG1 DROPOUT RESISTANCE OF AN
AVERAGE PART, BOARD, INDUCTOR
COMBINATION IS 172mΩ.
250
DROPOUT VOLTAGE (mV)
3.34
REG1 DROPOUT VOLTAGE vs. LOAD CURRENT
300
MAX8660 toc10
3.38
OUTPUT VOLTAGE (V)
3.36
3.30
40µs/div
6.0
3.40
MAX8660 toc09
VIN = 3.8V
3.38
5.5
REG1 OUTPUT VOLTAGE vs. TEMPERATURE
REG1 LOAD REGULATION
3.40
3.5 4.0 4.5 5.0
INPUT VOLTAGE (V)
MAX8660 toc11
EFFICIENCY (%)
85
ILOAD = 10mA
3.4
OUTPUT VOLTAGE (V)
90
DROPOUT
MAX8660 toc07
95
MAX8660 toc08
3.6
MAX8660 toc06
FORCED-PWM
NORMAL
REG1 LINE TRANSIENT
REG1 OUTPUT VOLTAGE vs. INPUT VOLTAGE
REG1 EFFICIENCY vs. LOAD CURRENT
100
OUTPUT VOLTAGE (V)
MAX8660/MAX8660A/MAX8660B/MAX8661
High-Efficiency, Low-IQ, PMICs with Dynamic
Voltage Management for Mobile Applications
0
200
400
600
800
LOAD CURRENT (mA)
1000
REG1 LIGHT-LOAD SWITCHING WAVEFORMS
MAX8660 toc13
MAX8660 toc12
1200
MAX8660 toc14
V1 = 3.3V
3.8V INPUT
V1
100mV/div
2V/div
VLX1
2mV/div
V1
VLX1
2V/div
V1
20mV/div
800mA
500mA/div
IV1
4.2V INPUT
1A LOAD
40µs/div
12
1A/div
IL1
10mA
400ns/div
IL1
200mA/div
0A
0A
3.8V INPUT, 20mA LOAD
2µs/div
High-Efficiency, Low-IQ, PMICs with Dynamic
Voltage Management for Mobile Applications
REG2 OUTPUT VOLTAGE
vs. INPUT VOLTAGE
REG2 EFFICIENCY vs. LOAD CURRENT
90
80
VIN = 4.2V
75
70
1.90
VIN = 3.6V
65
VIN
1V/div
3.6V
1.85
1.80
800mA LOAD
1.75
100mV/div
V2
60
1.70
450mA LOAD,
V2 = 1.8V
V2 = 1.8V
1.65
50
1
10
100
LOAD CURRENT (mA)
2.5
1000
REG2 LOAD REGULATION
3.0
3.5 4.0 4.5 5.0
INPUT VOLTAGE (V)
5.5
6.0
40µs/div
REG2 DROPOUT VOLTAGE vs. LOAD CURRENT
REG2 OUTPUT VOLTAGE vs. TEMPERATURE
1.90
MAX8660 toc18
1.85
VIN = 3.6V
1.86
OUTPUT VOLTAGE (V)
1.83
-1.7%/A
1.81
1.79
800mA LOAD
1.88
1.77
300
MAX8660 toc19
0.1
250
DROPOUT VOLTAGE (mV)
0.01
1.84
1.82
1.80
1.78
1.76
1.74
FORCED-PWM
NORMAL
400
600
LOAD CURRENT (mA)
800
0
-40
-15
10
35
TEMPERATURE (°C)
60
0
85
REG2 HEAVY-LOAD SWITCHING WAVEFORMS
REG2 LOAD TRANSIENT
VLX2
2V/div
600mA
200mA/div
VLX2
2mV/div V2
IL2
1A/div
800mA LOAD
V2 = 1.8V
400ns/div
1000
REG2 LIGHT-LOAD SWITCHING WAVEFORMS
V2
10mA
20µs/div
400
600
800
LOAD CURRENT (mA)
MAX8660 toc23
100mV/div
IV2
200
MAX8660 toc22
MAX8660 toc21
V2
100
50
1.70
200
150
THE NOMINAL ESR OF TOKO'S 2.0µH
DE2812C INDUCTOR IS 67mΩ. THE NOMINAL
p-CHANNEL RESISTANCE OF THE REG2 IS
180mΩ. THE SLOPE OF THIS LINE SHOWS
THAT THE TOTAL REG2 DROPOUT
RESISTANCE OF AN AVERAGE
PART, BOARD, INDUCTOR
COMBINATION IS 255mΩ.
1.72
1.75
0
200
MAX8660 toc20
L2 = 2.0µH
(TOKO DE2812C)
55
OUTPUT VOLTAGE (V)
5.0V
10mA LOAD
OUTPUT VOLTAGE (V)
EFFICIENCY (%)
85
MAX8660 toc17
MAX8660 toc16
FORCED-PWM
NORMAL
REG2 LINE TRANSIENT
1.95
MAX8660 toc15
95
2V/div
20mV/div
IL2
200mA/div
0A
30mA LOAD
0A
2µs/div
13
MAX8660/MAX8660A/MAX8660B/MAX8661
Typical Operating Characteristics (continued)
(Circuit of Figure 3, VIN = 3.6V, TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics (continued)
(Circuit of Figure 3, VIN = 3.6V, TA = +25°C, unless otherwise noted.)
REG3
EFFICIENCY vs. LOAD CURRENT
75
70
VIN = 4.2V
65
VIN = 3.6V
60
ILOAD = 1000mA
1.43
V3 = 1.4V
L3 = 1.2µH
(TOKO DE2812C)
55
MAX8660 toc26
1.44
OUTPUT VOLTAGE (V)
5.0V
VIN
1V/div
3.6V
1.42
1.41
1.40
1.39
1.38
50mV/div
V3
1.37
1.36
800mA LOAD, V3 = 1.4V
1.35
50
0.01
0.1
1
10
100
LOAD CURRENT (mA)
2.5
1000 10,000
REG3 LOAD REGULATION
VIN = 3.6V
1.43
FORCED-PWM
NORMAL
3.5 4.0 4.5 5.0
INPUT VOLTAGE (V)
5.5
40µs/div
6.0
REG3 VOLTAGE CHANGE RESPONSE
REG3 OUTPUT VOLTAGE vs. TEMPERATURE
1.48
1.46
OUTPUT VOLTAGE (V)
1.42
1.41
1.40
1.39
1.38
MAX8660 toc29
1.50
MAX8660 toc27
1.44
3.0
MAX8660 toc28
EFFICIENCY (%)
80
REG3 LINE TRANSIENT
1.45
MAX8660 toc25
FORCED-PWM
NORMAL
85
REG3 OUTPUT VOLTAGE
vs. INPUT VOLTAGE
MAX8660 toc24
90
OUTPUT VOLTAGE (V)
MAX8660/MAX8660A/MAX8660B/MAX8661
High-Efficiency, Low-IQ, PMICs with Dynamic
Voltage Management for Mobile Applications
RRAMP
= 56kΩ
V3
RISING
1.44
V3
FALLING
1.38
RRAMP = 248kΩ
500mV/div
1.36
0.725V
RRAMP
= 56kΩ
ILOAD = 1000mA
ACTIVE RAMP-DOWN ENABLED
1.30
0
200 400 600 800 1000 1200 1400 1600
LOAD CURRENT (mA)
-40
REG3 LOAD TRANSIENT
-15
10
35
TEMPERATURE (°C)
VLX3
REG3 LIGHT-LOAD SWITCHING WAVEFORMS
MAX8660 toc32
2V/div
V3
900mA
VLX3
2mV/div
V3
1A/div
IL3
IL3
500mA/div
10mA
100µs/div
85
MAX8660 toc31
50mV/div
V3
60
REG3 HEAVY-LOAD SWITCHING WAVEFORMS
MAX8660 toc30
IV3
RRAMP = 248kΩ
1.8V
1.40
1.32
1.36
500mV/div
0.725V
1.42
1.34
1.37
1.8V
2V/div
20mV/div
200mA/div
0A
0A
1500mA LOAD
20µs/div
14
400ns/div
30mA LOAD
2µs/div
High-Efficiency, Low-IQ, PMICs with Dynamic
Voltage Management for Mobile Applications
REG4
EFFICIENCY vs. LOAD CURRENT
REG4 OUTPUT VOLTAGE
vs. INPUT VOLTAGE
90
80
75
VIN = 4.2V
70
65
ILOAD = 300mA
1.41
OUTPUT VOLTAGE (V)
EFFICIENCY (%)
85
VIN = 3.6V
MAX8660 toc35
MAX8660 toc34
FORCED-PWM
NORMAL
REG4 LINE TRANSIENT
1.42
MAX8660 toc33
95
5.0V
VIN
1.39
1.38
1.37
L4 = 4.7µH
(TOKO DE2812C)
1.36
200mA LOAD, V5 = 1.4V
V4 = 1.4V
50
1.35
0.1
1
10
100
LOAD CURRENT (mA)
1000
2.5
REG4 LOAD REGULATION
5.5
40µs/div
6.0
FORCED-PWM
NORMAL
1.50
MAX8660 toc36
VIN = 3.6V
3.5 4.0 4.5 5.0
INPUT VOLTAGE (V)
REG4 VOLTAGE CHANGE RESPONSE
REG4 OUTPUT VOLTAGE vs. TEMPERATURE
1.44
1.43
3.0
MAX8660 toc38
MAX8660 toc37
0.01
400mA LOAD
1.45
RRAMP
= 56kΩ
1.41
1.40
1.39
1.38
500mV/div
RRAMP = 248kΩ
1.40
1.8V
1.35
V4
FALLING
RRAMP = 248kΩ
500mV/div
1.30
0.725V
RRAMP
= 56kΩ
1.25
1.37
1.8V
V4
RISING 0.725V
1.42
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
10mV/div
V4
60
55
1V/div
3.6V
1.40
ACTIVE RAMP-DOWN ENABLED
1.36
1.20
0
100
200
300
LOAD CURRENT (mA)
400
-40
-15
10
35
TEMPERATURE (°C)
60
REG4 HEAVY-LOAD SWITCHING WAVEFORMS
REG4 LOAD TRANSIENT RESPONSE
REG4 LIGHT-LOAD SWITCHING WAVEFORMS
MAX8660 toc41
MAX8660 toc40
MAX8660 toc39
VLX4
V4
100µs/div
85
2V/div
50mV/div
2V/div
VLX4
20mV/div
V4
V4
2mV/div
IL4
200mA/div I
L4
350mA
IV4
10mA
200mA/div
20µs/div
200mA LOAD
400ns/div
200mA/div
0A
18mA LOAD
0A
2µs/div
15
MAX8660/MAX8660A/MAX8660B/MAX8661
Typical Operating Characteristics (continued)
(Circuit of Figure 3, VIN = 3.6V, TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics (continued)
(Circuit of Figure 3, VIN = 3.6V, TA = +25°C, unless otherwise noted.)
1.81
1.80
1.79
1.78
100mA LOAD
1.82
OUTPUT VOLTAGE (V)
1.82
OUTPUT VOLTAGE (V)
1.82
REG5 OUTPUT VOLTAGE vs. TEMPERATURE
1.83
MAX8660 toc43
MAX8660 toc42
100mA LOAD
OUTPUT VOLTAGE (V)
REG5 OUTPUT VOLTAGE vs. LOAD CURRENT
1.83
1.81
1.80
1.79
1.78
1.77
3.0
3.5 4.0 4.5 5.0
INPUT VOLTAGE (V)
5.5
6.0
1.80
1.79
1.77
0
50
100
150
LOAD CURRENT (mA)
200
-40
-15
REG5 LOAD TRANSIENT RESPONSE
REG5 LINE TRANSIENT
10
35
TEMPERATURE (°C)
60
85
REG5 VOLTAGE CHANGE RESPONSE
MAX8660 toc46
MAX8660 toc45
100mA LOAD
1.81
1.78
1.77
2.5
MAX8660 toc44
REG5 OUTPUT VOLTAGE vs. INPUT VOLTAGE
1.83
MAX8660 toc47
5.0V
VIN
V5
3.6V
50mV/div
RRAMP = 56kΩ
1V/div
2.0V
100mV/div
V5
1.725V
IV5
V5
180mA
10mALOAD, V5 = 1.8V
100mA
100mA LOAD, V5 = 1.8V
100mA/div
40µs/div
20µs/div
REG5 OUTPUT NOISE SPECTRAL
DENSITY vs. FREQUENCY
REG5 OUTPUT NOISE (0.1Hz TO 10Hz)
40µs/div
REG5 PSRR vs. FREQUENCY
MAX8660 toc49
80
MAX8660 toc48
10,000
RLOAD = 180Ω
70
MAX8660 toc50
20mV/div
60
1000
10µV/div
PSRR (dB)
NOISE DENSITY (nV/√(Hz))
MAX8660/MAX8660A/MAX8660B/MAX8661
High-Efficiency, Low-IQ, PMICs with Dynamic
Voltage Management for Mobile Applications
50
40
30
100
20
10
10
0
0.01
16
0.1
1
10
FREQUENCY (kHz)
100
1s/div
0.01
0.1
1
10
FREQUENCY (kHz)
100
High-Efficiency, Low-IQ, PMICs with Dynamic
Voltage Management for Mobile Applications
3.0
1.80
1.79
1.86
4.2V INPUT
3.3V OUTPUT
2.5
2.0
1.5
1.78
3.5 4.0 4.5 5.0
INPUT VOLTAGE (V)
5.5
6.0
1.80
1.78
1.76
1.70
0
100 200 300 400 500 600 700 800 900
LOAD CURRENT (mA)
-40
-15
10
35
TEMPERATURE (°C)
60
85
REG6/REG7 LOAD TRANSIENT
REG6/REG7 LINE TRANSIENT
MAX8660 toc55
MAX8660 toc54
5.0V
VIN
1V/div
3.6V
50mV/div
V6/V7
300mA
20mV/div
V6/V7
IV6/IV7
100mA/div
10mA
V6/V7 = 1.8V
300mA LOAD, V6/V7 = 1.8V
10µs/div
40µs/div
MAX8660 toc56
I2C ENABLE SIGNAL
140
2V/div
VSDA
60µs
500mV/div
V6/V7
THE SLOPE OF THESE LINES
SHOWS THAT THE REG6/REG7
DROPOUT RESISTANCE OF AN
AVERAGE PART MOUNTED ON THE MAXIM
EVALUATION KIT IS 205mΩ.
120
100
80
MAX8660 toc57
REG6/REG7 DROPOUT OUTPUT VOLTAGE
vs. LOAD CURRENT
REG6/REG7 ENABLE WAVEFORM
DROPOUT VOLTAGE (mV)
3.0
1.82
1.72
1.0
2.5
1.84
1.74
2.4V INPUT
1.8V OUTPUT
1.77
300mA LOAD
1.88
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
1.81
1.90
MAX8660 toc52
100mA LOAD
1.82
OUTPUT VOLTAGE (V)
3.5
MAX8660 toc51
1.83
REG6/REG7 OUTPUT VOLTAGE
vs. TEMPERATURE
REG6/REG7 OUTPUT VOLTAGE
vs. LOAD CURRENT
MAX8660 toc53
REG6/REG7 OUTPUT VOLTAGE
vs. INPUT VOLTAGE
3.0V OUTPUT
60
40
3.3V OUTPUT
20
0
100µs/div
0
100
200
300
400
LOAD CURRENT (mA)
500
17
MAX8660/MAX8660A/MAX8660B/MAX8661
Typical Operating Characteristics (continued)
(Circuit of Figure 3, VIN = 3.6V, TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics (continued)
(Circuit of Figure 3, VIN = 3.6V, TA = +25°C, unless otherwise noted.)
REG8 LOAD REGULATION
REG8 OUTPUT VOLTAGE vs. INPUT VOLTAGE
MAX8660 toc59
3.2
VIN = 3.6V
3.8
3.6
3.4
3.0
3.2
V8 (V)
OUTPUT VOLTAGE (V)
4.0
MAX8660 toc58
5mA LOAD
3.4
2.8
3.0
2.8
2.6
2.6
2.4
2.4
2.2
2.2
2.0
2.0
2.5
3.0
3.5 4.0 4.5 5.0
INPUT VOLTAGE (V)
5.5
0
6.0
10
20
30 40 50 60
LOAD CURRENT (mA)
70
80
REG8 LINE TRANSIENT
REG8 OUTPUT VOLTAGE vs. TEMPERATURE
MAX8660 toc61
MAX8660 toc60
3.40
5mA LOAD
3.38
3.36
OUTPUT VOLTAGE (V)
5.0V
VIN
1V/div
3.6V
3.34
3.32
3.30
3.28
50mV/div
3.26
V8
3.24
3.22
10mA LOAD
3.20
-15
10
35
TEMPERATURE (°C)
60
40µs/div
85
REG8 DROPOUT VOLTAGE vs. LOAD CURRENT
REG8 LOAD TRANSIENT
MAX8660 toc62
400
THE SLOPE OF THIS LINE
SHOWS THAT THE REG8 DROPOUT
RESISTANCE OF AN AVERAGE PART
MOUNTED ON THE MAXIM
EVALUATION KIT IS 12.4Ω.
350
50mV/div
V8
15mA
IV8
10mA/div
5mA
MAX8660 toc63
-40
DROPOUT VOLTAGE (mV)
MAX8660/MAX8660A/MAX8660B/MAX8661
High-Efficiency, Low-IQ, PMICs with Dynamic
Voltage Management for Mobile Applications
300
250
200
150
100
50
0
10µs/div
18
0
5
10
15
20
LOAD CURRENT (mA)
25
30
High-Efficiency, Low-IQ, PMICs with Dynamic
Voltage Management for Mobile Applications
PIN
MAX8660 MAX8661
1
1
NAME
FUNCTION
IN5
REG5 Power Input. Connect IN5 to IN to ensure V5 rises first to meet the Marvell PXA3xx
processor’s sequencing requirements. If adherence to this sequencing specification is not
required, connect IN5 to V1, V2, or another supply between 2.35V and VIN. See the Linear
Regulators (REG5–REG8) section for more information.
REG5 Linear-Regulator Output. V5 defaults to 1.8V and is adjustable from 1.7V to 2.0V through
the serial interface. The input to the V5 regulator is IN5. Use V5 to power VCC_MVT, VCC_BG,
VCC_OSC13M, and VCC_PLL on Marvell PXA3xx processors. V5 is internally pulled to AGND
through 2kΩ when REG5 is shut down.
—
2
V5
3
3
PV4
REG4 Power Input. Connect a 4.7µF ceramic capacitor from PV4 to PG4. All PV pins and IN must
be connected together externally.
4
4
LX4
REG4 Switching Node. Connect LX4 to the REG4 inductor. LX4 is high impedance when REG4 is
shut down.
5
5
PG4
REG4 Power Ground. Connect PG1, PG2, PG3, PG4, and AGND together. Refer to the MAX8660 EV
kit data sheet for more information.
6
6
SET2
REG2 Voltage Select Input. SET2 is a tri-level logic input. Connect SET2 to select the V2 output
voltage as detailed in Table 4. The REG2 output voltage selected by SET2 is latched at the end of
the REG2 soft-start period. Changes to SET2 after the startup period have no effect.
REG6 Linear-Regulator Output. REG6 is activated and programmed through the serial interface to
output from 1.8V to 3.3V in 0.1V steps. REG6 is off by default. V6 is internally pulled to AGND
through 350Ω when REG6 is shut down. V6 optionally powers VCC_CARD1 on Marvell PXA3xx
processors.
7
7
V6
8
—
IN67
REG6 and REG7 Power Input. IN67 is typically connected to IN. IN67 can also be connected to
any supply between 2.35V to VIN.
—
8
IN6
REG6 Power Input. IN6 is typically connected to IN. IN6 can also be connected to any supply
between 2.35V to VIN.
REG7 Linear-Regulator Output. REG7 is activated and programmed through the serial interface to
output from 1.8V to 3.3V in 0.1V steps. REG7 is off by default. V7 is internally pulled to AGND
through 350Ω when REG7 is shut down. V7 optionally powers VCC_CARD2 on Marvell PXA3xx
processors.
9
—
V7
—
9
N.C.
10
10
V2
11
11
SCL
Serial-Clock Input. See the I 2C Interface section.
12
12
SDA
Serial-Data Input. See the I 2C Interface section.
13
13
LBO
Low-Battery Output. LBO is an open-drain output that pulls low when LBF is below its threshold.
LBO typically connects to the nBATT_FAULT input of the applications processor to indicate that
the battery has been removed or discharged.
14
14
PV2
REG2 Power Input. Connect a 4.7µF ceramic capacitor from PV2 to PG2. All PV pins and IN must
be connected together externally.
15
15
LX2
REG2 Switching Node. Connect LX2 to the REG2 inductor. LX2 is high impedance when REG2 is
shut down.
No Internal Connection
REG2 Voltage Sense Input. Connect V2 directly to the REG2 output voltage. The output voltage of
REG2 is selected by SET2. V2 is internally pulled to AGND through 650Ω when REG2 is shut
down. V2 powers VCC_MEM on Marvell PXA3xx processors.
19
MAX8660/MAX8660A/MAX8660B/MAX8661
Pin Description
MAX8660/MAX8660A/MAX8660B/MAX8661
High-Efficiency, Low-IQ, PMICs with Dynamic
Voltage Management for Mobile Applications
Pin Description (continued)
PIN
MAX8660 MAX8661
FUNCTION
16
16
PG2
REG2 Power Ground. Connect PG1, PG2, PG3, PG4, and AGND together. Refer to the MAX8660 EV
kit data sheet for more information.
17
17
IN8
REG8 Input Power Connection. IN8 must be connected to IN.
18
18
IN
Main Battery Input. This input provides power to the IC. Connect a 0.47µF ceramic capacitor from
IN to AGND.
19
19
AGND
Analog Ground. Connect PG1, PG2, PG3, PG4, and AGND together. Refer to the MAX8660 EV kit
data sheet for more information.
20
20
V8
REG8 Always-On 3.3V LDO Output. REG8 is the first regulator that powers up in the
MAX8660/MAX8661. REG8 is supplied from IN and supplies up to 30mA. V8 is internally pulled to
AGND through 1.5kΩ during IN undervoltage or overvoltage lockout. Connect V8 to VCC_BBATT
on Marvell PXA3xx processors.
21
21
LBF
Low-Battery Detect Falling Input. The LBF threshold is 1.20V. Connect LBF to LBR for 50mV
hysteresis. Use a three-resistor voltage-divider for larger hysteresis. LBF sets the falling voltage at
which LBO goes low. See the Low-Battery Detector (LBO, LBF, LBR) section for more information.
22
22
LBR
Low-Battery Detect Rising Input. The LBR threshold is 1.25V. Connect LBF to LBR for 50mV
hysteresis. Use a three-resistor voltage-divider for larger hysteresis. LBR sets the rising voltage at
which LBO goes high. See the Low-Battery Detector (LBO, LBF, LBR) section for more
information.
23
23
MR
Manual Reset Input. A low MR input causes RSO to go low and resets all serial programmed
registers to their default values. See the Reset Output (RSO) and MR Input section for more
information.
24
24
RAMP
Ramp-Rate Input. Connect a resistor from RAMP to AGND to set the regulator ramp rates. See the
Ramp-Rate Control (RAMP) section for more information.
25
25
EN5
REG5 Enable Input. Drive EN5 high to turn on REG5. EN5 has hysteresis so an RC can be used to
implement manual sequencing with respect to other inputs. EN5 is typically driven by the SYS_EN
output of an Marvell PXA3xx processor.
26
26
PG3
REG3 Power Ground. Connect PG1, PG2, PG3, PG4, and AGND together. Refer to the MAX8660 EV
kit data sheet for more information.
27
27
LX3
REG3 Switching Node. Connect LX3 to the REG3 inductor. LX3 is high impedance when REG3 is
shut down.
28
28
PV3
REG3 Power Input. Connect a 4.7µF ceramic capacitor from PV3 to PG3. All PV pins and IN must
be connected together externally.
Open-Drain Reset Output. RSO typically connects to the nRESET input on an applications
processor. An output low from the MAX8660/MAX8661 RSO resets all serial programmed
registers to their default values and causes the processor to enter its reset state. See the Reset
Output (RSO) and MR Input section for more information.
29
29
RSO
30
30
V3
REG3 Voltage Sense Input. Connect V3 directly to the REG3 output voltage. The output voltage is
adjustable from 0.725V to 1.8V through the serial interface. V3 is internally pulled to AGND through
550Ω when REG3 is shut down. V3 connects to VCC_APPS on Marvell PXA3xx processors.
EN34
REG3 and REG4 Active-High Hardware Enable Input. Drive EN34 high to enable both REG3 and
REG4. Drive EN34 low to allow the serial interface to enable REG3 and REG4 independently.
EN34 has hysteresis so an RC can be used to implement manual sequencing with respect to
other inputs. EN34 is typically driven by the PWR_EN output of an Marvell PXA3xx processor. See
the REG3/REG4 Enable (EN34, EN3, EN4) section for more information.
31
20
NAME
31
High-Efficiency, Low-IQ, PMICs with Dynamic
Voltage Management for Mobile Applications
PIN
MAX8660 MAX8661
32
32
NAME
FUNCTION
EN2
REG2 Enable Input. Drive EN2 high to turn on REG2. EN2 has hysteresis so that an RC can be
used to implement manual sequencing with respect to other inputs. EN2 is typically driven by the
SYS_EN output of an Marvell PXA3xx processor.
33
33
SRAD
Serial-Address Input. Connect SRAD to AGND for a 7-bit slave address of 0110 100 (0x68).
Connect SRAD to IN to change the address to 0110 101 (0x6A). The eighth slave address bit is
always zero since the MAX8660/MAX8661 are write-only. See the Slave Address section for more
information.
34
—
PG1
REG1 Power Ground. Connect PG1, PG2, PG3, PG4, and AGND together. Refer to the MAX8660 EV
kit data sheet for more information.
—
34
GND
Ground. Connect all GND pins to EP.
35
—
LX1
REG1 Switching Node. Connect LX1 to the REG1 inductor. LX1 is high impedance when REG1 is
shutdown.
—
35
N.C.
No Internal Connection
36
—
PV1
REG1 Power Input. Connect a 4.7µF ceramic capacitor from PV1 to PG1. All PV pins and IN must
be connected together externally.
—
36
PV
Power Input. All PV pins and IN must be connected together externally.
37
—
EN1
REG1 Enable Input. Drive EN1 high to turn on REG1. EN1 has hysteresis so that an RC can be
used to implement manual sequencing with respect to other inputs. EN1 is typically driven by the
SYS_EN output of an applications processor.
—
37
GND
Ground. Connect all GND pins to EP.
38
—
V1
—
38
GND
Ground. Connect all GND pins to EP.
39
—
SET1
REG1 Voltage Select Input. SET1 is a tri-level logic input. Connect SET1 to select the V1 output
voltage as detailed in Table 3. The REG1 output voltage selected by SET1 is latched at the end of
the REG1 soft-start period. Changes to SET1 after the startup period have no effect.
—
39
GND
Ground. Connect all GND pins to EP.
40
40
V4
REG4 Feedback Sense Input. Connect V4 directly to the REG4 output voltage. The REG4 output
voltage is adjustable from 0.725V to 1.8V with the serial interface. V4 is internally pulled to AGND
through 550Ω when REG4 is shut down. V4 powers VCC_SRAM on the applications processor.
EP
Exposed Pad. Connect the exposed pad to ground. Connecting the exposed pad to ground does
not remove the requirement for proper ground connections to PG1, PG2, PG3, PG4, and AGND.
The exposed pad is attached with epoxy to the substrate of the die, making it an excellent path to
remove heat from the IC.
—
—
REG1 Voltage Sense Input. Connect V1 directly to the REG1 output voltage. The output voltage of
REG1 is selected by SET1. Connect V1 to VCC_IOx of the applications processor. V1 is internally
pulled to AGND through 650Ω when REG1 is shut down.
21
MAX8660/MAX8660A/MAX8660B/MAX8661
Pin Description (continued)
MAX8660/MAX8660A/MAX8660B/MAX8661
High-Efficiency, Low-IQ, PMICs with Dynamic
Voltage Management for Mobile Applications
V1 3.3V AT 1200mA
1045mA
15mA
VCC_USB
5mA
VCC_TSI
MARVELL PXA3xx
PROCESSOR
AUXILIARY POWER
PERIPHERALS
MAX8660
10mA
VCC_I01
25mA
VCC_I03
50mA
VCC_I04
50mA
VCC_I06
55mA
VCC_LCD
20mA
VCC_MSL
50mA
VCC_DF
35mA
VCC_CI
135mA
IN
160mA
200mA
V2 1.8V AT 900mA
540mA
VCC_MEM
AUXILARY POWER
PERIPHERALS MEMORY
V3 0.725V TO 1.8V AT 1600mA
1600mA
VCC_APPS
V4 0.725V TO 1.8V AT 400mA
360mA
VCC_SRAM
40mA
AUXILIARY POWER
VCC_MVT
VCC_BG
V5 1.7V TO 2.0V (DEF 1.8V) AT 200mA
VCC_OSC13M
VCC_PLL
V6 1.8V TO 3.3V (DEF 0V) AT 500mA
15mA
485mA
SD/CF MEMORY
CARD 1
V7 1.8V TO 3.3V (DEF 0V) AT 500mA
15mA
485mA
5mA
I2C
POWER I2C
EN2
EN5
VCC_BBATT
AUXILIARY POWER
STANDARD I2C
EN1
VCC_CARD2
SD/CF MEMORY
CARD 2
V8 3.3V AT 30mA
25mA
VCC_CARD1
SDA {GPIO33}
SCL {GPIO32}
PWR_SDA
PWR_SCL
SYS_EN
EN34
PWR_EN
V8 (VCC_BBATT)
RSO
nRESET
LBO
nBATT_FAULT
Figure 1. Example MAX8660 Connection to Marvell PXA3xx Processor. This is one example only. Other connections are also supported.
22
High-Efficiency, Low-IQ, PMICs with Dynamic
Voltage Management for Mobile Applications
IN
REF
1.25V
PV1
TO BATT
BATTERY
LBF
(1.20V)
LBR
(1.25V)
UVLO
OVLO
AND
BATT
MON
LX1
STEP-DOWN
PWM
REG1
TO ALL
BLOCKS
OPEN-DRAIN LOW BATT OUT
TO nBATT_FAULT
PG1
ON
PWM
LBO
V1,
VCC_I0x, VCC_LCD,
VCC_MSL, VDD_USB,
VCC_DF, VDD_CI, VCC_TSI
MAX8660/MAX8660B: 3.3V, 3.0V, 2.85V
MAX8660A: 2.5V, 2.0V, 1.8V
1200mA
V1
(MAX8660/MAX8660A/MAX8660B ONLY)
MAX8660
MAX8661
AGND
LATCH
SET1
PV2
TO BATT
EN1
EN2
FROM CPU
SYS_EN
ON
LX2
TO IN
V8,
VCC_BBATT
(3.3V 30mA, ALWAYS ON)
IN8
STEP-DOWN
PWM
REG2
V8
LDO
REG8
HARDWARE
RESET INPUT
TO CPU
nRESET
PG2
V2
PWM
LATCH
MR
RESET
V8 < 2.4V
20ms
RSO
V2,
VCC_MEM
MAX8660/MAX8660B/MAX8661: 3.3V, 2.5V, 1.8V
MAX8660A: 2.5V, 2.0V, 1.8V
900mA
SET2
PV3
STEP-DOWN
PWM
REG3
TO BATT
LX3
V3,
VCC_APPS
0.725V TO 1.8V
(DEFAULT 1.4V for MAX8660/MAX8660A/MAX8661)
(DEFAULT 1.15V for MAX8660B)
1.6A
RAMP
RAMP
V6,
VCC_CARD1
0V/1.8–3.3V
(DEFAULT 0V) 500mA
ADJ
0.725V TO
1.8V
SET RATE
RAMP
PG3
V3
PWM
V6
ON
LDO
REG6
LOGICAL OR
(FIGURE 5)
EN34
FROM CPU
PWR_EN
PV4
TO V1, V2, OR IN
V7,
VCC_CARD2
0V/1.8–3.3V
(DEFAULT 0V) 500mA
(MAX8660/MAX8660A ONLY)
TO BATT
IN67 (IN6)
STEP-DOWN
PWM
REG4
V7
LX4
V4,
VCC_SRAM
0.725V TO 1.8V
(DEFAULT 1.4V for MAX8660/MAX8660A/MAX8661)
(DEFAULT 1.15V for MAX8660B)
400mA
RAMP
ADJ
0.725V TO
1.8V
LDO
REG7
PG4
V4
PWM
VCC_IOx
IN5
SCL
SDA
I2C SERIAL
INTERFACE
TO IN, V1 OR V2
V5
ADJ
1.7V TO
2.0V
RAMP LDO
REG5
EN5
SRAD
FROM CPU
SYS_EN
V5,
VCC_MVT, VCC_BG
1.7V TO 2.0V
(DEFAULT 1.8V)
200mA
EP
( ) ARE FOR THE MAX8661
AGND
PGND
Figure 2. Functional Diagram
23
MAX8660/MAX8660A/MAX8660B/MAX8661
BATT
MAX8660/MAX8660A/MAX8660B/MAX8661
High-Efficiency, Low-IQ, PMICs with Dynamic
Voltage Management for Mobile Applications
2.6V TO 6.0V
INPUT
R10
20Ω
IN
R1
1.82MΩ
18
IN
C22
0.47µF
IN
PV1
21
36
LBF
R2
80.6kΩ
22
LBR
V8
C11
4.7µF
U1
MAX8660
MAX8660A
MAX8660B
R3
1MΩ
PG1
V1
19
R5
300kΩ
LX1
AGND
PV2
13
LBO
32
31
EN34
25
EN5
39
SET1
6
SET2
33
C21
0.1µF
V8
20
V8
LX2
PG2
V2
PV3
EN5
L2
2.0µH
16
C7
10µF
10
28
L3
1.2µH
LX3
SET2
PG3
SRAD
V3
PV4
IN8
27
C3
10µF
30
3
C4
10µF
C5
10µF
IN
C18
4.7µF
L4
4.7µH
V8
LX4
PG4
V4
MR
4
V4
5
C8
10µF
40
C9
10µF
IN
IN5
1
C19
1µF
R7
300kΩ
V5
29
RSO
24
R4
56kΩ
12
11
SCL
PGND
Figure 3. Typical Applications Circuit
24
V3
26
V8
AGND
C6
10µF
IN
SET1
S1
SDA
V2
C12
4.7µF
R6
300kΩ
MR
C2
10µF
IN
15
EN34
C10
0.1µF
23
14
EN2
IN
17
C1
10µF
38
C15
4.7µF
EN1
EN2
V1
34
LBO
37
EN1
L1
1.2µH
35
RSO
V6
RAMP
IN67
C13
2.2µF
7
8
IN
V6
C20
1µF
SDA
SCL
V5
2
EP
V7
C17
4.7µF
V7
9
NOTE: REFERENCE DESIGNATORS MATCH MAX8660EVKIT
C16
4.7µF
High-Efficiency, Low-IQ, PMICs with Dynamic
Voltage Management for Mobile Applications
The MAX8660/MAX8661 PMICs are optimized for
devices using the applications processors, including
smart cellular phones, PDAs, Internet appliances, and
other portable devices requiring substantial computing
and multimedia capability and low power consumption.
The MAX8660/MAX8661 comply with the specifications
for Marvell’s PXA300 family (PXA3xx) and Marvell’s
Armada 100 family (PXA16x) of processors.
As shown in Figure 2, the MAX8660 integrates eight
high-performance, low-operating-current power supplies. REG1–REG4 are step-down DC-DC converters,
and REG5–REG8 are linear regulators. Other functions
include low-battery detection (LBO), a reset output
(RSO), a manual reset input (MR), and a 2-wire I2C serial interface. The MAX8661 functions the same as the
MAX8660, but does not have the REG1 step-down regulator and the REG7 linear regulator.
The operating input voltage range is from 2.6V to 6.0V,
allowing use with a 1-cell Li+ battery, 3-cell NiMH, or a
5V input. Input protection is provided with undervoltage
and overvoltage lockouts. Overvoltage lockout protects
the device against inputs up to 7.5V.
Maxim vs. Marvell PXA3xx Terminology
The MAX8660/MAX8661 are compatible with Marvell‘s
PXA3xx processor. Figure 1 shows one of many possible connections between the PXA3xx processor and
the MAX8660/MAX8661. To facilitate system development with PXA3xx processors, this document uses both
Maxim and Marvell terminology. Marvell terminology
appears in parentheses and italics. For example, this
document refers to “V8 (VCC_BBATT)” because the
MAX8660 V8 output powers the Marvell VCC_BBATT
power domain. Tables 1 and 2 outline Maxim and
Marvell terminology.
Table 1. Maxim and Marvell PXA3xx Power Domain Terminology
POWER DOMAIN
POWER DOMAIN
ACCEPTABLE VOLTAGE
COMPATIBLE MAXIM
POWER DOMAIN
VCC_IO1
VCC_IO3
VCC_IO4
VCC_IO6
1.8V ±10% or
3.0V ±10% or
3.3V ±10%
V1 or V2
• Peripheral I/O supply for UARTs, standard I2C,
power I2C, audio interface, SSPs, PWMs, etc.
(VCC_IO1,VCC_IO3, VCC_IO4, VCC_IO6)
VCC_LCD
VCC_MSL
VCC_CI
VCC_DF
1.8V ±10% or
3.0V ±10%
V1 or V2
•
•
•
•
DESCRIPTION
LCD interface logic (VCC_LCD)
Fast serial interface (VCC_MSL)
Camera flash interface (VCC_CI)
Data flash interface (VCC_DF)
VCC_MEM
1.8V ±100mV
V2
• I/O supply for high-speed memory
VCC_APPS
0.95V to 1.41V ±5%
V3
• Main processor core
VCC_SRAM
1.08V to 1.41V
±100mV
V4
• Internal SRAM memory
VCC_MVT
VCC_BG
VCC_OSC13M
VCC_PLL
1.8V
±100mV
V5
•
•
•
•
VCC_CARD1
1.8V ±10% or
3.0V ±10% or
3.3V ±10%
V6
• Removable storage and USIM card supply
VCC_CARD2
1.8V ±10% or
3.0V ±10% or
3.3V ±10%
V7
• Removable storage and USIM card supply
VCC_BBATT
3.0V ±1V
V8
• Regulated battery voltage
VCC_USB
3.3V ±300mV
V1 or V2
(if programmed to 3.3V)
• Universal serial bus (VCC_USB)
VCC_TSI
3.3V ±300mV
V1 or V2
(if programmed to 3.3V)
• Touch-screen interface (VCC_TSI)
Internal logic and I/O blocks (VCC_MVT)
Bandgap reference (VCC_BG)
13MHz oscillator (VCC_OSC13M)
Phase-locked loop (PLL) and oscillator (VCC_PLL)
25
MAX8660/MAX8660A/MAX8660B/MAX8661
Detailed Description
MAX8660/MAX8660A/MAX8660B/MAX8661
High-Efficiency, Low-IQ, PMICs with Dynamic
Voltage Management for Mobile Applications
Table 2. Maxim and Marvell PXA3xx Digital Signal Terminology
MAXIM
MARVELL
DESCRIPTION
EN34
PWR_EN
Active-High Enable Signal for Processor Core Power. The applications processor drives this
PWR_EN signal high to exit sleep mode. The processor’s PWR_EN logic is powered by the
MAX8660/MAX8661 “always on” V8 (VCC_BBATT) regulator during sleep mode.
EN1, EN2, EN5
SYS_EN
Active-High Enable Signal for Peripheral Power Supplies. The applications processor drives
this SYS_EN signal high to enter run mode.
RSO
nRESET
Active-Low Reset. The MAX8660/MAX8661 drive this signal low to reset the processor.
When RSO goes low, the MAX8660/MAX8661 I2C registers are reset to their default values.
LBO
nBATT_FAULT
SDA
GPIO33
PWR_SDA
I2C Serial-Data Input/Output. The MAX8660/MAX8861 SDA generally connects to both the
Marvell PXA3xx processor’s standard I2C data line (GPIO33) and its dedicated power I2C
data line. This connection operates as an I2C multimaster system with the
MAX8660/MAX8661 accepting commands from both the standard I2C and the power I2C.
SCL
GPIO32
PWR_SCL
I2C Serial Clock. The MAX8660/MAX8661 SCL generally connects to both the Marvell
PXA3xx processor’s standard I2C clock line (GPIO32) and its dedicated power I2C clock
line. This connection operates as an I2C multimaster system with the MAX8660/MAX8661
accepting commands from both the standard I2C and the power I2C.
Active-Low Battery Fault. The MAX8660/MAX8661 drive this signal low to signal the
processor that the battery has been removed or discharged.
Step-Down DC-DC Converters
(REG1–REG4)
REG1 (VCC_IO) Step-Down DC-DC Converter
(MAX8660 Only)
REG1 is a high-efficiency (REG1 + REG8 IQ = 40µA)
2MHz current-mode step-down converter that outputs
up to 1200mA with efficiency up to 96% (see the
Typical Operating Characteristics). The output voltage
(V1) is selected with the SET1 input as shown in Table
3. The REG1 output voltage selection is latched at the
end of the REG1 soft-start period. Changes in SET1
after the startup period have no effect.
EN1 is a dedicated enable input for REG1. Drive EN1
high to enable REG1 or drive EN1 low to disable REG1.
EN1 has hysteresis so that an RC may be used to
implement manual sequencing with respect to other
inputs. In systems based on Marvell PXA3xx processors, EN1, EN2, and EN5 are typically connected to
SYS_EN (Table 2).
The REG1 step-down regulator operates in either normal or forced-PWM mode. See the REG1–REG4 StepDown DC-DC Converter Operating Modes section for
more information.
REG1 has an on-chip synchronous rectifier. See the
REG1–REG4 Synchronous Rectification section for
more information.
The REG1 regulator allows 100% duty-cycle operation.
See the REG1/REG2 100% Duty-Cycle Operation
(Dropout) section for more information.
26
Table 3. SET1 Logic
SET1*
MAX8660/
MAX8660B: V1 (V)
MAX8660A: V1 (V)
IN
3.3
2.5
UNCONNECTED
3.0
2.0
GROUND
2.85
1.8
*SET1 is latched after REG1 startup.
Table 4. SET2 Logic
SET2*
MAX8660/MAX8660B/
MAX8661: V2 (V)
MAX8660A: V2 (V)
IN
3.3
2.5
UNCONNECTED
2.5
2.0
GROUND
1.8
1.8
*SET2 is latched after REG2 startup.
REG2 (VCC_IO, VCC_MEM)
Step-Down DC-DC Converters
REG2 is a high-efficiency (REG2 + REG8 IQ = 40µA)
2MHz current-mode step-down DC-DC converter that
outputs up to 900mA with efficiency up to 96%. The output voltage is selected with the SET2 input as shown in
Table 4. The REG2 output voltage selection is latched
at the end of the REG2 soft-start period. Changes in
SET2 after the startup period have no effect.
High-Efficiency, Low-IQ, PMICs with Dynamic
Voltage Management for Mobile Applications
The REG2 regulator has an on-chip synchronous rectifier.
See the REG1–REG4 Synchronous Rectification section
for more information.
The REG2 regulator allows 100% duty-cycle operation.
See the REG1/REG2 100% Duty-Cycle Operation
(Dropout) section for more information.
REG3 (VCC_APPS) Step-Down DC-DC Converters
REG3 is a high-efficiency (REG3 + REG8 IQ = 45µA)
2MHz current-mode step-down converter that has an
I2C-adjustable output voltage from 0.725V to 1.800V in
25mV increments with efficiency up to 92%. The default
REG3 output voltage is 1.4V for the MAX8660/
MAX8660A/MAX8661, and 1.15V for the MAX8660B
(contact factory for other default voltages). REG3 delivers up to 1.6A. See the I2C Interface section for details
on how to adjust the output voltage.
REG3 has an I2C enable bit (EN3) and a shared hardware enable pin (EN34). See the REG3/REG4 Enable
(EN34, EN3, EN4) section for more information.
The REG3 step-down regulator operates in either normal or forced-PWM mode. See the REG1–REG4 StepDown DC-DC Converter Operating Modes section for
more information.
The REG3 regulator has an on-chip synchronous rectifier.
See the REG1–REG4 Synchronous Rectification section
for more information.
REG4 (VCC_SRAM) Step-Down DC-DC Converters
REG4 is a high-efficiency (REG4 + REG8 IQ = 45µA)
2MHz current-mode step-down converter that has an
I2C-adjustable output voltage from 0.725V to 1.800V in
25mV increments with efficiency up to 92%. The default
REG4 output voltage is 1.4V for the MAX8660/
MAX8660A/MAX8661, and 1.15V for the MAX8660B
(contact factory for other default voltages). REG4 delivers up to 400mA. See the I 2C Interface section for
details on how to adjust the output voltage.
REG4 has an I2C enable bit (EN4) and a shared hardware enable pin (EN34). See the REG3/REG4 Enable
(EN34, EN3, EN4) section for more information.
The REG4 step-down regulator operates in either normal or forced-PWM mode. See the REG1–REG4 StepDown DC-DC Converter Operating Modes section for
more information.
The REG4 regulator has an on-chip synchronous rectifier.
See the REG1–REG4 Synchronous Rectification section
for more information.
REG1–REG4 Step-Down
DC-DC Converter Operating Modes
REG1–REG4 independently operate in one of two
modes: normal or forced PWM. At power-up or after a
reset, REG1–REG4 default to normal operation. Activate
forced-PWM mode by setting bits in the FPWM register
(Table 9) with the I2C interface. The FPWM bits can be
changed at any time.
In forced-PWM mode, a converter operates with a constant 2MHz switching frequency regardless of output
load. The MAX8660/MAX8661 regulate the output voltage by modulating the switching duty cycle. ForcedPWM mode is ideal for low-noise systems because
output voltage ripple is small (< 10mVP-P) and switching harmonics occur at multiples of the constantswitching frequency and are easily filtered. However,
light-load power consumption in forced-PWM mode is
higher than that of normal mode (Table 7).
Normal operation offers improved efficiency at light
loads by switching only as necessary to supply the
load. With moderate to heavy loading, the regulator
switches at a fixed 2MHz switching frequency as it
does in forced-PWM mode. This transition to fixed-frequency switching occurs at the load current specified
in the following equation:
V − VOUT
VOUT
IOUT ≅ IN
x
2xL
VIN x fSW
REG1–REG4 Synchronous Rectification
Internal n-channel synchronous rectifiers eliminate the
need for external Schottky diodes and improve efficiency.
The synchronous rectifier turns on during the second
half of each switching cycle (off-time). During this time,
the voltage across the inductor is reversed, and the
inductor current ramps down. In PWM mode, the synchronous rectifier turns off at the end of the switching
cycle. In normal mode, the synchronous rectifier turns
off when the inductor current falls below 25mA or at the
end of the switching cycle, whichever occurs first.
REG1/REG2 100% Duty-Cycle Operation (Dropout)
The REG1 and REG2 step-down DC-DC converters
operate with 100% duty cycle when the supply voltage
approaches the output voltage. This allows these
27
MAX8660/MAX8660A/MAX8660B/MAX8661
EN2 is a dedicated enable input for REG2. Drive EN2
high to enable REG2 or drive EN2 low to disable REG2.
EN2 has hysteresis so that an RC may be used to
implement manual sequencing with respect to other
inputs. In systems based on Marvell PXA3xx, EN1,
EN2, and EN5 are typically connected to SYS_EN
(Table 2).
The REG2 step-down regulator operates in either normal or forced-PWM mode. See the REG1–REG4 StepDown DC-DC Converter Operating Modes section for
more information.
converters to maintain regulation until the input voltage
falls below the desired output voltage plus the dropout
voltage specification of the converter. During 100%
duty-cycle operation, the high-side p-channel MOSFET
turns on constantly, connecting the input to the output
through the inductor. The dropout voltage (VDO) is calculated as follows:
VDO = ILOAD (RP + RL)
where:
RP = p-channel power switch RDS(ON)
RL = external inductor ESR
The REG1 dropout voltage is 200mV with a 1200mA
load (with inductor resistance = 50mΩ). The REG2
dropout voltage is 225mV with a 900mA load (with
inductor resistance = 67mΩ).
Linear Regulators (REG5–REG8)
REG5 (VCC_MVT, VCC_BG,
VCC_OSC13M, VCC_PLL)
REG5 is a linear regulator with an I2C-adjustable output
voltage from 1.700V to 2.000V in 25mV increments
(REG5 + REG8 IQ = 55µA). The default REG5 voltage is
1.8V. REG5 delivers up to 200mA. See the I2C Interface
section for details on how to adjust the output voltage.
The power input for the REG5 linear regulator is IN5. The
IN5 input voltage range extends down to 2.35V. Note that
in the Marvell PXA3xx specification, VCC_MVT is enabled
by SYS_EN (along with V1 and V2), but must not rise after
V1 (VCC_IO) or V2 (VCC_MEM). This requirement dictates that IN5 be connected to IN and not V1 or V2.
EN5 is a dedicated enable input for REG5. Drive EN5
high to enable REG5. Drive EN5 low to disable REG5.
EN5 has hysteresis so that an RC may be used to implement manual sequencing with respect to other inputs. In
systems with Marvell PXA3xx processors, EN1, EN2,
and EN5 are typically connected to SYS_EN (Table 2).
REG6/REG7 (VCC_CARD1, VCC_CARD2)
The REG6/REG7 linear regulators supply up to 500mA
each (REG6 or REG 7 + REG8 IQ = 85µA). The output
voltages, V6 and V7, are programmable through the serial interface from 1.8V to 3.3V in 0.1V steps (Table 13).
See the I2C Interface section for details on changing the
V6 or V7 voltage. On the MAX8660, the combined
power input for the REG6 and REG7 linear regulators is
IN67. On the MAX8661, IN6 is the power input for REG6
(REG7 is not available on the MAX8661).
REG6 and REG7 are disabled by default and must be
enabled using the I2C serial interface. REG6 and REG7
have independent enable bits in the OVER2 register:
EN6 and EN7 (Table 9). To enable the regulators, set
the corresponding enable bit.
28
REG8 (VCC_BBATT) Always-On Regulator
The output of REG8 (V8) is always active when the input
voltage (VIN) is above the undervoltage-lockout threshold
of 2.55V (max) and below the overvoltage-lockout threshold of 6.0V (min). The REG8 linear regulator is supplied
from IN and its output regulates to 3.3V and supplies up
to 30mA. The internal REG8 pass element is 12Ω in
dropout, providing a 180mV dropout voltage with a 15mA
output current. Connect V8 to VCC_BBATT for applications that use Marvell PXA3xx processors. The RSO output goes low if V8 is less than 2.2V (falling typ).
Ramp-Rate Control (RAMP)
REG1 and REG2 have a fixed soft-start ramp that eliminates input current spikes when they are enabled; 200µs
after being enabled, REG1 and REG2 linearly ramp from
0V to the set output voltage in 450µs. When these regulators are disabled, the output voltage decays at a rate
determined by the output capacitance, internal 650Ω
discharge resistance, and the external load.
The REG3 and REG4 output voltage have a variable linear ramp rate that is set by a resistor connected from
RAMP to AGND (RRAMP). This resistor controls the output-voltage ramp rate during soft-start and a positive
voltage change (i.e., 1.0V to 1.4V). The negative voltage change (i.e., 1.4V to 1.0V) is controlled in forcedPWM mode, and when the ARD bit is set in normal
mode (Table 9). Figure 4 shows the relationship
RAMP RATES vs. RAMP-RATE RESISTOR
12
10
RAMP RATE (mV/µs)
MAX8660/MAX8660A/MAX8660B/MAX8661
High-Efficiency, Low-IQ, PMICs with Dynamic
Voltage Management for Mobile Applications
REG3/4 SSRR TO:
1V
1.4V
1.8V
8
6
REG3/4/5 DCRR
4
2
0
10
100
RRAMP (kΩ)
1000
REG3 / REG4 SOFT − START RAMP RATE (SSRR) :
1.4 × VOUT [ V ]
⎡ mV ⎤
SSRR ⎢
⎥ = 0.0014848 × (2.2 × (R
µ
s
⎦
⎣
RAMP [kΩ ] + 13.5) + 9)
ATE (DCRR)
REG3 / REG4 / REG5 DYNAMIC − CHANGE RAMP RA
12500
⎡ mV ⎤
DCRR ⎢
⎥ = 8 x (2.2 × (R
µ
s
⎦
⎣
RAMP [kΩ ] + 13.5) + 9)
Figure 4. Soft-Start and Voltage-Change Ramp Rates
High-Efficiency, Low-IQ, PMICs with Dynamic
Voltage Management for Mobile Applications
(i.e., 1.8V to 2.5V) ramp-rate control. During a positive
voltage change, the output-voltage dV/dt is as fast as
possible. To avoid this fast output dV/dt, disable REG6
or REG7 before changing the output. With this method,
the soft-start ramp rate limits the output dV/dt, and
therefore, the input current is controlled. During a negative voltage change (i.e., 2.5V to 1.8V), the REG6 or
REG7 output voltage decays at a rate determined by
the output capacitance and the external load. When
REG6 or REG7 is disabled, the output voltage decays
at a rate determined by the output capacitance, internal
350Ω discharge resistance, and the external load.
Power Sequencing
Enable Signals (EN_, PWR_EN, SYS_EN, I 2C)
As shown in Table 5, the MAX8660/MAX8661 feature
numerous enable signals for flexibility in many applications. In a typical application with the Marvell PXA3xx
processor, many of these enable signals are connected
together. EN1, EN2, and EN5 typically connect to the
SYS_EN output. With this connection, REG5 is the first
supply to rise (if IN5 is connected to IN). EN34 typically
connects to Marvell’s PWR_EN output. Alternatively,
REG3 and REG4 can be activated by the I2C interface
(see the REG3/REG4 Enable (EN34, EN3, EN4) section
for more information). REG6 and REG7 are activated by
the serial interface. REG8 has no enable input and
always remains on as long the MAX8660/MAX8661 are
powered between the UVLO and OVLO range. All regulators are forced off during UVLO and OVLO. See the
Undervoltage and Overvoltage Lockout section for
more information.
Note: The logic that controls the Marvell PXA3xx
processor SYS_EN and PWR_EN signals is powered
from the VCC_BBATT power domain.
Table 5. Enable Signals
POWER DOMAIN
MAXIM ENABLE SIGNAL
HARDWARE
SOFTWARE
V1 (VCC_IO) (MAX8660/MAX8660A only)
EN1
—
V2 (VCC_MEM)
EN2
—
V5 (VCC_MVT)
EN5
V3 (VCC_APPS)
V4 (VCC_SRAM)
EN34
SYS_EN
—
EN3 (OVER1)
EN4 (OVER1)
V6 (VCC_CARD1)
—
EN6 (OVER2)
V7 (VCC_CARD2) (MAX8660/MAX8660A only)
—
EN7 (OVER2)
V8 (VCC_BBATT)
APPLICATIONS PROCESSOR
ENABLE SIGNAL
Always on
PWR_EN &
PWR_I2C
Standard I2C
—
29
MAX8660/MAX8660A/MAX8660B/MAX8661
between RRAMP and the output-voltage ramp rates. A
56kΩ R RAMP satisfies the typical requirements of
Marvell PXA3xx processors; 200µs after being enabled,
REG3 and REG4 linearly ramp from 0V to the set output
voltage at the rate set by R RAMP . When REG3 and
REG4 are disabled, the output voltage decays at a rate
determined by the output capacitance, internal 550Ω
discharge resistance, and the external load.
Active ramp-down functionality is inherent in forcedPWM operation. In normal-mode operation, active ramp
down is enabled by setting ARD3 and ARD4 (Table 9).
With “active ramp-down” enabled, the regulator output
voltage ramps down at the rate set by RRAMP. With small
loads, the regulator must sink current from the output
capacitor to actively ramp down the output voltage. In
normal mode, with “active ramp-down” disabled, the
regulator output voltage ramps down at the rate determined by the output capacitance and the external load;
small loads result in an output-voltage decay that is slower than that specified by RRAMP, large loads (> COUT x
RAMPRATE) result in an output-voltage decay that is no
faster than that specified by RRAMP.
80µs after being enabled, REG5 linearly ramps from 0V
to the set output voltage in 225µs. The ramp rate during
a positive voltage change (i.e., 1.8V to 1.9V) is set with
RRAMP. During a negative voltage change (i.e., 1.9V to
1.8V), the REG5 output voltage decays at a rate determined by the output capacitance and the external load;
however, ramp-down is no faster than the rate specified
by RRAMP. When REG5 is disabled, the output voltage
decays at a rate determined by the output capacitance,
internal 2kΩ discharge resistance, and the external load.
60µs after being enabled by I2C, REG6 and REG7 linearly ramp from 0V to the set output voltage in 450µs.
REG6 and REG7 do not have positive voltage-change
MAX8660/MAX8660A/MAX8660B/MAX8661
High-Efficiency, Low-IQ, PMICs with Dynamic
Voltage Management for Mobile Applications
REG3/REG4 Enable (EN34, EN3, EN4)
REG3 and REG4 have independent I 2C enable bits
(EN3, EN4) and a shared hardware-enable input
(EN34). As shown in Figure 5, the EN34 hardwareenable input is logically ORed with the I2C enable bits.
Table 6 is the truth table for the V3/V4 enable logic.
Note that to achieve a pure I2C enable/disable, connect
EN34 to ground. Similarly, to achieve a pure hardware
enable/disable, leave the I2C enable bits at their default
value (EN3 = EN4 = 0 = off); V3 and V4 cannot be independently enabled/disabled using only hardware.
Note: A low MR drives RSO low and returns the I2C
registers to their default values: EN3 = 0 and EN4 = 0.
PV3
BATT
LX3
V3
(VCC_APPS)
REG3
EN34
Power Modes
The MAX8660/MAX8661 provide numerous enable signals (Table 5) and support any combination for enabling
and disabling their supplies with these signals. Table 7
shows several power modes defined for PXA3xx
processors along with their corresponding MAX8660/
MAX8661 quiescent operating currents.
Power-Up and Power-Down Timing
Figure 6 shows the power-up sequence for the Marvell
PXA3xx family of processors. In general, the supplies
should power up in the following order:
1) POWER-UP: V8 V5 V1 and V2 V3 and V4
2) REG6 and REG7 typically power external card slots
and can be powered up and down based on application requirements.
Note that the Marvell PXA3xx processor controls
EN1/EN2/EN5 with the same SYS_EN signal, yet Marvell’s
timing diagrams show that V5 is supposed to power up
before V1 and V2. Because of the PXA3xx family’s timing
parameters, most systems connect EN1/EN2/EN5
together and drive them with SYS_EN. When powering
up, this connection ensures that V5 powers up before
V1 and V2 (only when V5 is powered from IN).
PG3
ON
SDA
SCL
EN3
PV4
I2C
BATT
EN4
ON
V4
(VCC_SRAM)
LX4
REG4
PG4
Figure 5. V3/V4 Enable Logic
Table 6. Truth Table for V3/V4 Enable Logic
I2C BITS
HARDWARE INPUT
V4
0 (default)
OFF
OFF
0
1
OFF
ON
1
0
ON
OFF
1
1
ON
ON
X
X
ON
ON
EN3
EN4
0
0 (default)
0
0
X
1
X = Don’t care.
30
V3
EN34
Marvell PXA3xx Power
Configuration Register (PCFR)
The MAX8660/MAX8661 comply with the Marvell
PXA3xx power I2C register specifications. This allows
the PMIC to be used along with the processor with littleto-no software development. As shown in Table 9, there
are many I2C registers, but since the processor automatically updates the PMIC through its power I2C interface, only the REG6 and REG7 enable bits need be
programmed to fully utilize the PMIC.
The Marvell PXA3xx processor contains a power management unit general configuration register (PCFR).
The default values of this register are compliant with the
MAX8660/MAX8661. However, wake-up performance
can be optimized using this register:
• The PCFR register contains timers for the SYS_DEL
and PWR_DEL timing parameters as shown in Figure
6. Each timer defaults to 125ms. When using the
MAX8660/MAX8661, these timers may be shortened to
2ms to speed up the overall system wake-up delay.
• Enabling the “shorten wake-up delay” function
(SWDD bit) bypasses the SYS_DEL and PWR_DEL
timers and uses voltage detectors on the Marvell
PXA3xx processor to optimize the overall system
wake-up delay.
High-Efficiency, Low-IQ, PMICs with Dynamic
Voltage Management for Mobile Applications
POWER
MODE
POWER
DOMAIN
STATE
MAX8660 QUIESCENT
OPERATING CURRENT (FIGURE 3)
NORMAL
FORCED-PWM
OPERATING MODE
MODE
DIGITAL
CONTROL
STATE
V1, V2, V3, V4, V5, V6, V7, EN1/EN2/EN5 (SYS_EN) and EN34 (PWR_EN)
and V8 are on
are asserted; V6, V7 are enabled by I2C
V1, V2, V3, V4, V5,
EN1/EN2/EN5 (SYS_EN) and EN34 (PWR_EN)
RUN, IDLE,
and V8 are on
are asserted
and
STANDBY
V6 and V7 are off
V6, V7 are disabled by I2C (default)
ALL ON
V1, V2, V5, and V8 are on
SLEEP
DEEP
SLEEP
250µA
23mA
140µA
22.9mA
90µA
10mA
EN1/EN2/EN5 (SYS_EN) are asserted
EN34 (PWR_EN) is deasserted; V6, V7 are
V3, V4, V6, and V7 are off
disabled by I2C (default)
EN1/EN2/EN5 (SYS_EN) and EN34 (PWR_EN)
All supplies off except V8
are deasserted; V6, V7 are disabled by I2C
20µA
Note: Forced-PWM currents are measured on the MAX8660 EV kit. Currents vary with step-down inductor and output capacitor tolerance.
V8
(VCC_BBATT)
tVBHRSTH = 20ms, MIN (TIMED BY PMIC)
RSO
(nRESET)
tVBHBFH = 0s, MIN (TIMED BY PMIC)
LBO
(nBATT_FAULT)
tBFHSEH = 93.75µs, MAX (TIMED BY MARVELL PXA3xx)
tBSTHSEH = 2.05s, MAX (TIMED BY MARVELL PXA3xx)
EN1/EN2/EN5
(SYS_EN)
tSEHVMH = SYS_DEL TIME, MAX (TIMED BY PMIC)
V5
(VCC_MVT)
tVMHVSH1 = SYS_DEL TIME, tSEHVMH, MAX (TIMED BY PMIC)
V1
(VCC_IO)
tVMHVSH2 = SYS_DEL TIME - t, tSEHVMH, MAX (TIMED BY PMIC)
V2
(VCC_MEM)
tSEHPH = SYS_DEL TIME + 152µs, MIN
tSEHPH = SYS_DEL TIME + 153µs, MAX (TIMED BY MARVELL PXA3xx)
EN34
(PWR_EN)
SCL FROM AP
(PWR_SCL)
SCA FROM AP
(PWR_SDA)
nRESET_OUT*
FROM AP
tSHROH = SYS_DEL TIME +213µs, MIN
tSHROH = SYS_DEL TIME +214µs, MAX (TIMED BY MARVELL PXA3xx)
V3
(VCC_APPS)
tPHLVTH3 = PWR_DEL TIME (TIMED BY PMIC)
V4
(VCC_SRAM)
tPHLVTH4 = PWR_DEL TIME (TIMED BY PMIC)
*THE MAX8660/MAX8661 DO NOT DIRECTLY USE THE MARVELL PXA3xx PROCESSOR’S nRESET_OUT LOGIC OUTPUT.
Figure 6. Power-Up Timing
31
MAX8660/MAX8660A/MAX8660B/MAX8661
Table 7. Power Modes and Corresponding Quiescent Operating Currents
MAX8660/MAX8660A/MAX8660B/MAX8661
High-Efficiency, Low-IQ, PMICs with Dynamic
Voltage Management for Mobile Applications
Voltage Monitors, Reset,
and Undervoltage-Lockout Functions
Undervoltage and Overvoltage Lockout
When the V IN is below V UVLO (typically 2.35V), the
MAX8660/MAX8661 enter its undervoltage-lockout
mode (UVLO). UVLO forces the device to a dormant
state. In UVLO, the input current is very low (1.5µA)
and all regulators are off. RSO and LBO are forced low
when the input voltage is between 1V (typ) and VUVLO.
The I2C does not function in UVLO, and the I2C register
contents are reset in UVLO.
When the input voltage is above VOVLO (typically 6.35V)
the MAX8660/MAX8661 enter overvoltage-lockout mode
(OVLO). OVLO mode protects the MAX8660/
MAX8661 from high-voltage stress. In OVLO, the input
current is 25µA and all regulators are off. RSO is held
low, the I2C does not function, and register contents are
reset in OVLO. LBO continues to function in OVLO; however, since LBO is typically pulled up to V8
(VCC_BBATT), LBO appears to go low in OVLO because
V8 is disabled. Alternatively, LBO may be pulled up to IN.
Reset Output (RSO) and MR Input
RSO is an open-drain reset output. As shown in Figure
1, RSO typically connects to the nRESET input of the
applications processor and is pulled up to V8
(VCC_BBATT). A low on nRESET causes the processor
to enter its reset state.
RSO is forced low when one or more of the following
conditions occur:
• MR is low.
• V8 is below VRSOTH (2.2V falling typ).
• VIN is below VUVLO (2.35V typ).
• VIN is above VOVLO (6.35V typ).
RSO is high impedance when all of the following conditions are satisfied:
• MR is high.
• V8 is above VRSOTH (2.35V rising typ).
• VUVLO < VIN < VOVLO.
• The RSO deassert delay (tVBHRSTH = 24ms typ) has
expired.
When RSO goes low, the MAX8660/MAX8661 I2C registers are reset to their default values.
If the MR feature is not required, connect MR high. If
the RSO feature is not required, connect RSO low.
Low-Battery Detector (LBO, LBF, LBR)
LBO is an open-drain output that typically connects to the
nBATT_FAULT input of the applications processor to indicate that the battery has been removed or discharged
(Figure 1). LBO is typically pulled up to V8 (VCC_BBATT).
32
LBR and LBF monitor the input voltage (usually a battery) and trigger the LBO output (Figure 7). The truth
table in Figure 7 shows that LBO is high impedance
when the voltage from LBR to AGND (VLBR) exceeds
the low-battery rising threshold (VLBRTH = 1.25V typ).
LBO is low when the voltage from LBF to AGND (VLBF)
falls below the low-battery falling threshold (VLBFTH =
1.20V typ). On power-up, the LBR threshold must be
exceeded before LBO deasserts.
Connecting LBF to LBR and to a two-resistor voltagedivider sets a 50mV hysteresis referred to LBF (hysteresis at the battery voltage is scaled up by the resistor
value), connecting LBF and LBR separately to a threeresistor voltage-divider (Figure 7) allows the falling
threshold and rising threshold to be set separately
(achieving larger hysteresis). The Figure 7 resistor values are selected as a function of the desired falling
(VLBOF) and rising (VLBOR) thresholds as follows:
First, select R3 in the 100kΩ to 1MΩ range:
⎛
⎞
VLBOR
V
x ⎜1 − LBFTH ⎟
VLBRTH ⎝
VLBOF ⎠
⎛V
⎞
x VLBOR
R2 = R 3 x ⎜ LBFTH
− 1⎟
⎝ VLBRTH x VLBOF
⎠
R1 = R 3 x
V8
(VCC_BBATT)
IN
+
MAX8660
MAX8661
R1
LBO
LBF
S
Q
AGND
VLBFTH
1.200V
R2
LBR
R
R3
VLBRTH
1.250V
TRUTH TABLE
LBF
VLBF < VLBFTH
VLBF < VLBFTH
LBR
VLBR < VLBRTH
VLBR > VLBRTH
LBO
0
0
VLBF > VLBFTH
VLBF > VLBFTH
VLBR < VLBRTH
VLBR > VLBRTH
HOLD
1
Figure 7. Low-Battery Detector Functional Diagram
High-Efficiency, Low-IQ, PMICs with Dynamic
Voltage Management for Mobile Applications
For example, to set VLBOR to 3.6V and VLBOF to 3.2V,
choose R3 to be 1MΩ. Then, R1 = 1.8MΩ and
R2 = 80kΩ.
If the low-battery-detector feature is not required, connect LBO to ground and connect LBF and LBR to IN.
Internal Off-Discharge Resistors
Each regulator on the MAX8660/MAX8661 has an internal resistor that discharges the output capacitor when
the regulator is off (Table 8). The internal discharge
resistors pull their respective output to ground when the
regulator is off, ensuring that load circuitry always powers down completely. The internal off-discharge resistors are active when a regulator is disabled, when the
device is in OVLO, and when the device is in UVLO
with VIN greater than 1.0V. With VIN less than 1.0V, the
internal off-discharge resistors may not activate.
Thermal-Overload Protection
Thermal-overload protection limits total power dissipation in the MAX8660/MAX8661. When internal thermal
sensors detect a die temperature in excess of +160°C,
the corresponding regulator(s) are shut down, allowing
the IC to cool. The regulators turn on again after the
junction cools by 15°C, resulting in a pulsed output during continuous thermal-overload conditions.
A thermal overload on any of REG1 through REG5 only
shuts down the overloaded regulator. An overload on
REG6 or REG7 shuts down both regulators together.
During thermal overload, REG8 is not turned off, and
the I2C interface and voltage monitors remain active.
Table 8. Internal Off-Discharge Resistor
REGULATOR
INTERNAL OFF-DISCHARGE
RESISTOR VALUE
REG1
650Ω ±30%
REG2
650Ω ±30%
REG3
550Ω ±30%
REG4
550Ω ±30%
REG5
2kΩ ±30%
REG6
350Ω ±30%
REG7
350Ω ±30%
REG8
1.5kΩ ±30%
I2C Interface
An I2C-compatible, 2-wire serial interface controls a
variety of MAX8660/MAX8661 functions:
• The output voltages of V3–V7 are set by the serial
interface.
• Each of the four step-down DC-DC converters
(REG1–REG4) can be put into forced-PWM operation.
• REG3 and REG4 can be enabled by the serial interface or by a hardware-enable pin (EN34). See the
REG3/REG4 Enable (EN34, EN3, EN4) section for
more information.
• REG6 and REG7 are activated only by the serial interface.
The serial interface operates whenever VIN is between
VUVLO (typically 2.40V) and VOVLO (typically 6.35V).
When VIN is outside the I2C operation range, the I2C
registers are reset to their default values.
The serial interface consists of a bidirectional serial-data
line (SDA) and a serial-clock input (SCL). The MAX8660/
MAX8661 are slave-only devices, relying upon a master
to generate a clock signal. The master (typically the
applications processor) initiates data transfer on the bus
and generates SCL to permit data transfer.
I2C is an open-drain bus. SDA and SCL require pullup
resistors (500Ω or greater). Optional resistors (24Ω) in
series with SDA and SCL protect the device inputs from
high-voltage spikes on the bus lines. Series resistors also
minimize cross-talk and undershoot on bus signals.
The Marvell PXA3xx specification contains an extensive
list of registers for various functions, not all of which are
provided on the MAX8660/MAX8661. The list in Table 9 is
a subset of the Marvell list as it relates to functions included in the PMIC. Even though the MAX8660/MAX8661 use
a subset of the specified registers, they acknowledge
writes to the entire register space (0x00 to 0xFF).
In Marvell PXA3xx applications, the pullups are typically
to VCC_IOx.
Data Transfer
One data bit is transferred during each SCL clock
cycle. The data on SDA must remain stable during the
high period of the SCL clock pulse. Changes in SDA
while SCL is high are control signals (see the START
and STOP Conditions section for more information).
Each transmit sequence is framed by a START (S) condition and a STOP (P) condition. Each data packet is 9 bits
long; 8 bits of data followed by the acknowledge bit. The
MAX8660/MAX8661 suport data transfer rates with SCL
frequencies up to 400kHz.
33
MAX8660/MAX8660A/MAX8660B/MAX8661
where VLBOR is the rising voltage at the top of R1 (typically VIN) when LBO goes high, and VLBOF is the falling
voltage at the top of R1 when LBO goes low.
34
OVER1*
OVER2
VCC1*
ADTV1*
ADTV2*
SDTV1*
SDTV2*
MDTV1
MDTV2
L12VCR
FPWM
0x10
0x12
0x20
0x23
0x24
0x29
0x2A
0x32
0x33
0x39
0x80
W
W
W
W
W
W
W
W
W
W
W
R/W
Default
Voltage-Change Control Register. Independently specifies
that the V3, V4, and V5 output voltage must follow either
target register 1 or 2. See Table 10.
Forced-PWM Register. The FPWM_ bits allow V1, V2, V3, and
V4 to independently operate in either skip mode or forcedPWM mode. See the REG1–REG4 Step-Down DC-DC
Converter Operating Modes section for more information. The
ARD_ bits allow the output voltage to be actively ramped
down during negative voltage transitions See the Ramp-Rate
Control (RAMP) section for more information. Note that this is
a Maxim custom register that is not required by the Marvell
PXA3xx processor.
LDO1 and LDO2 Voltage-Control Register (V6 and V7 on
MAX8660). Specifies the V6 and V7 output voltage. V6 and
V7 are enabled/disabled with OVER2.
VCC_MVT (V5) DVM Target Voltage 2 Register. Sets target 2
voltage for V5.
VCC_MVT (V5) Target Voltage 1 Register. Sets target 1
voltage for V5.
VCC_SRAM (V4) DVM Target Voltage 2 Register. Sets target
2 voltage for V4.
VCC_SRAM (V4) DVM Target Voltage 1 Register. Sets target
1 voltage for V4.
VCC_APPS (V3) DVM Target Voltage 2 Register. Sets target 2
voltage for V3.
Default
Default
Default
Default
Default
Default
Default
Default
Default
Output-Voltage Enable Register 2. Enables/disables V6 and
V7. See the REG6/REG7 (VCC_CARD1, VCC_CARD2) section
for more information.
VCC_APPS (V3) DVM Target Voltage 1 Register. Sets target 1
voltage for V3.
Default
Output-Voltage Enable Register 1. Enables/disables V3 and
V4. See the REG3/REG4 Enable (EN34, EN3, EN4) section for
more information.
FUNCTION
0
0
R
0
R
0
R
0
R
0
R
0
R
0
SVS
0
—
0
R
5
0
—
0
0
—
0
0
0
1
1
1
1
0
0
R
0
EN7**
0
AVS
0
EN6
0
R
0
1
2
EN4
(S_EN)
0
1
0
1
0
1
0
1
1
0
0
FPWM4
0
0
0
0
FPWM3
0
0
FPWM2
0
V6 Voltage—See Table 13
1
V5 (VCC_MVT) Target 2—See Table 12
0
V5 (VCC_MVT) Target 1—See Table 12
1
V4 (VCC_SRAM) Target 2—See Table 11
1
V4 (VCC_SRAM) Target 1—See Table 11
1
V3 (VCC_APPS) Target 2—See Table 11
1
** Maintain these bits at their default 0 value for the MAX8661.
* These registers are accessed by the power I2C bus of the Marvell PXA3xx processor.
0
0
0
0
1
1
1
0
FPWM1**
1
0
AGO
0
—
0
EN3
(A_EN)
V3 (VCC_APPS) Target 1—See Table 11
0
R
0
—
0
R
3
DATA BIT
Note: The MAX8660/MAX8661 acknowledge attempts to write to the entire address space from 0x00 to 0xFF, even though only a subset of those
addresses actually exist in the IC.
0
ARD3
0
0
—
0
R
4
SGO
V7 Voltage—See Table 13
ARD4
0
0
R
R
0
0
R
R
0
0
0
0
R
0
R
0
R
0
R
R
R
0
R
R
0
0
MGO
0
—
0
R
6
0
MVS
0
R
0
R
7
R means these data locations are designated reserved in the Marvell PXA3xx specification.
REGISTER
NAME
REGISTER
ADDRESS
Table 9. I2C Registers
MAX8660/MAX8660A/MAX8660B/MAX8661
High-Efficiency, Low-IQ, PMICs with Dynamic
Voltage Management for Mobile Applications
High-Efficiency, Low-IQ, PMICs with Dynamic
Voltage Management for Mobile Applications
Sr
P
SDA
tSU;STA
tSU;STO
SCL
tHD;STA
tHD;STA
Figure 8. START and STOP Conditions
START and STOP Conditions
When the serial interface is inactive, SDA and SCL idle
high. A master device initiates communication by issuing
a START condition. A START condition is a high-to-low
transition on SDA with SCL high. A STOP condition is a
low-to-high transition on SDA, while SCL is high (Figure 8).
A START condition from the master signals the beginning of a transmission to the MAX8660/MAX8661. The
master terminates transmission by issuing a notacknowledge followed by a STOP condition (see the
Acknowledge Bit section for more information). The
STOP condition frees the bus. To issue a series of commands to the slave, the master may issue repeated
start (Sr) commands instead of a stop command in
order to maintain control of the bus. In general, a
repeated start command is functionally equivalent to a
regular start command.
When a STOP condition or incorrect address is detected,
the MAX8660/MAX8661 internally disconnect SCL from
the serial interface until the next START condition, minimizing digital noise and feedthrough.
Acknowledge Bit
Both the master and the MAX8660/MAX8661 (slave)
generate acknowledge bits when receiving data. The
acknowledge bit is the last bit of each 9-bit data packet.
To generate an acknowledge (A), the receiving device
must pull SDA low before the rising edge of the acknowledge-related clock pulse (ninth pulse) and keep it low
during the high period of the clock pulse (Figure 9). To
generate a not acknowledge (A), the receiving device
allows SDA to be pulled high before the rising edge of
the acknowledge-related clock pulse and leaves it high
during the high period of the clock pulse.
Monitoring the acknowledge bits allows for detection of
unsuccessful data transfers. An unsuccessful data
transfer occurs if a receiving device is busy or if a system fault has occurred. In the event of an unsuccessful
data transfer, the bus master should reattempt communication at a later time.
Slave Address
A bus master initiates communication with a slave
device (MAX8660/MAX8661) by issuing a START condition followed by the slave address. As shown in Figure
10, the slave address byte consists of 7 address bits
and a read/write bit (R/W). After receiving the proper
address, the MAX8660/MAX8661 issue an acknowledge
by pulling SDA low during the ninth clock cycle. Note
that the R/W bit is always zero since the MAX8660/
MAX8661 are write only.
The Marvell PXA3xx processor supports 0x68 (SRAD =
GND) as the I2C slave address.
NOT ACKNOWLEDGE
S
ACKNOWLEDGE
SDA
tSU;DAT
SCL
1
2
tHD;DAT
8
9
Figure 9. Acknowledge Bits
SLAVE ADDRESS (WRITE)
SRAD
BINARY
0b 0110 1000
0b 0110 1010
0 (GND)
1 (IN)
S
HEXADECIMAL
0x68
0x6A
ACKNOWLEDGE
R/W = 0
(WRITE ONLY)
SDA
0
1
1
0
1
0
SRAD
0
A
SCL
1
2
3
4
5
6
7
8
9
Figure 10. Slave Address Byte
35
MAX8660/MAX8660A/MAX8660B/MAX8661
S
MAX8660/MAX8660A/MAX8660B/MAX8661
High-Efficiency, Low-IQ, PMICs with Dynamic
Voltage Management for Mobile Applications
Table 10. DVM Voltage-Change Register (VCC1, 0x20)
REGISTER
ADDRESS
0x20
REGISTER
NAME
VCC1
BIT
NAME
7
MVS
6
MGO
5
SVS
4
SGO
3
R
2
R
1
AVS
0
AGO
FUNCTION
V5 (VCC_MVT) voltage select:
0—Ramp V5 to voltage selected by MDTV1 (default)
1—Ramp V5 to voltage selected by MDTV2
Start V5 (VCC_MVT) voltage change:
0—Hold V5 at current level (default)
1—Ramp V5 as selected by MVS
V4 (VCC_SRAM) voltage select:
0—Ramp V4 to voltage selected by SDTV1 (default)
1—Ramp V4 to voltage selected by SDTV2
Start V4 (VCC_SRAM) voltage change:
0—Hold V4 at current level (default)
1—Ramp V4 as selected by SVS
Reserved
Reserved
V3 (VCC_APPS) voltage select:
0—Ramp V3 to voltage selected by ADTV1 (default)
1—Ramp V3 to voltage selected by ADTV2
Start V3 (VCC_APPS) voltage change:
0—Hold V3 at current level (default)
1—Ramp V3 as selected by AVS
I 2C Write Operation
The MAX8660/MAX8661 are write-only devices and
recognize the “write byte” protocol as defined in the
SMBus specification and shown in section A of Figure
11. The “write byte” protocol allows the I 2C master
device to send 1 byte of data to the slave device. The
“write byte” protocol requires a register pointer address
for the subsequent write. The MAX8660/MAX8661
acknowledge any register pointer even though only a
subset of those registers actually exists in the device.
The “write byte” protocol is as follows:
1) The master sends a start command.
2) The master sends the 7-bit slave address followed
by a write bit.
3) The addressed slave asserts an acknowledge by
pulling SDA low.
4) The master sends an 8-bit register pointer.
5) The slave acknowledges the register pointer.
6) The master sends a data byte.
7) The slave updates with the new data.
8) The slave acknowledges the data byte.
9) The master sends a STOP condition.
In addition to the write-byte protocol, the MAX8660/
MAX8661 recognize the multiple byte register-data pair
protocol as shown in section B of Figure 11. This protocol allows the I2C master device to address the slave
only once and then send data to multiple registers in a
random order. Registers may be written continuously
until the master issues a STOP condition.
The multiple-byte register-data pair protocol is as
follows:
1) The master sends a start command.
2) The master sends the 7-bit slave address followed
by a write bit.
3) The addressed slave asserts an acknowledge by
pulling SDA low.
4) The master sends an 8-bit register pointer.
5) The slave acknowledges the register pointer.
6) The master sends a data byte.
7) The slave updates with the new data.
8) The slave acknowledges the data byte.
9) Steps 5 to 7 are repeated as many times as
the master requires. Registers may be accessed in
random order.
10)The master sends a STOP condition.
36
High-Efficiency, Low-IQ, PMICs with Dynamic
Voltage Management for Mobile Applications
REGISTER
ADDRESS
REGISTER
NAME
DATA
BYTE
OUTPUT
VOLTAGE (V)*
0x00
0.725
0x01
0.750
0x02
0.775
0x03
0.800
0x04
0.825
0x05
0.850
0x06
0.875
0x07
0.900
0x08
0.925
0x09
0.950
0x0A
0.975
0x0B
1.000
0x0C
1.025
0x0D
1.050
0x0E
1.075
0x0F
1.100
0x10
1.125
0x11
1.150**
0x12
1.175
0x13
1.200
0x14
1.225
ADTV1
0x23
0x15
1.250
ADTV2
0x24
SDTV1
0x29
0x16
1.275
SDTV2
0x2A
0x17
1.300
0x18
1.325
0x19
1.350
0x1A
1.375
0x1B
1.400 (default)***
0x1C
1.425
0x1D
1.450
0x1E
1.475
0x1F
1.500
0x20
1.525
0x21
1.550
0x22
1.575
0x23
1.600
0x24
1.625
0x25
1.650
0x26
1.675
0x27
1.700
0x28
1.725
0x29
1.750
0x2A
1.775
0x2B
1.800
*Contact factory for other default voltages.
**MAX8660B default voltage is 1.15V.
***MAX8660/MAX8660A/MAX8661 default voltage is1.4V.
Table 12. Serial Codes for V5 Output
Voltage
REGISTER
ADDRESS
0x32
0x33
REGISTER
NAME
MDTV1
MDTV2
DATA
BYTE
OUTPUT
VOLTAGE (V)
0x00
0x01
0x02
0x03
1.700
1.725
1.750
1.775
0x04
1.800
(default)
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
1.825
1.850
1.875
1.900
1.925
1.950
1.975
2.000
Table 13. Serial Codes for V6 and V7
Output Voltages
REGISTER
ADDRESS
0x39
REGISTER
NAME
L12VCR
DATA
NIBBLE
OUTPUT
VOLTAGE (V)
0x0
1.8
(default)
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xA
0xB
0xC
0xD
0xE
0xF
1.9
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
37
MAX8660/MAX8660A/MAX8660B/MAX8661
Table 11. Serial Codes for V3 (VCC_APPS)
and V4 (VCC_SRAM) Output Voltages
MAX8660/MAX8660A/MAX8660B/MAX8661
High-Efficiency, Low-IQ, PMICs with Dynamic
Voltage Management for Mobile Applications
LEGEND
MASTER TO SLAVE
SLAVE TO MASTER
A. WRITING TO A SINGLE REGISTER WITH THE “WRITE BYTE” PROTOCOL
1
7
1
1
8
1
8
S
SLAVE ADDRESS
0
A
REGISTER POINTER
A
DATA
1
1
NUMBER OF BITS
A P
R/W
B. WRITING TO MULTIPLE REGISTERS WITH THE “MULTIPLE-BYTE REGISTER-DATA PAIR” PROTOCOL
1
S
7
SLAVE ADDRESS
1
1
8
1
8
1
0
A
REGISTER POINTER X
A
DATA X
A
8
1
8
1
REGISTER POINTER n
A
DATA n
A
8
1
8
1
REGISTER POINTER Z
A
DATA Z
NUMBER OF BITS
R/W
NUMBER OF BITS
1
NUMBER OF BITS
A P
Figure 11. Writing to the MAX8660/MAX8661
Design Procedure
Setting the Output Voltages
The REG1 and REG2 regulators each have three preset
voltages that are programmed with the SET1 and SET2
inputs. See the REG1 (VCC_IO) Step-Down DC-DC
Converter (MAX8660 Only) and REG2 (VCC_IO,
VCC_MEM) Step-Down DC-DC Converters sections for
more information. V8 is fixed at 3.3V and cannot be
changed.
V3–V7 are set by the I 2 C interface. See the I 2 C
Interface section for more information. Note that while
operating in forced-PWM mode with an input voltage
greater than 4.3V, the minimum output voltage of REG3
and REG4 is limited by the minimum duty cycle. In
forced-PWM mode, the minimum output voltage for
REG3 or REG4 is:
V3MIN = 0.167 x VPV3
V4 MIN = 0.167 x VPV4
Note that the above minimum voltage limitation does
not apply to normal-mode operation.
38
Inductor Selection
Calculate the inductor value (LIDEAL) for each of REG1
through REG4 as follows:
LIDEAL =
4 x VIN x D x (1 − D)
IOUT(MAX) x fOSC
This sets the peak-to-peak inductor current ripple to 1/4
the maximum output current. The oscillator frequency,
fOSC, is 2MHz, and the duty cycle, D, is:
V
D = OUT
VIN
Given LIDEAL, the peak-to-peak inductor ripple current
is 0.25 x IOUT(MAX). The peak inductor current is 1.125
x IOUT(MAX). Make sure that the saturation current of the
inductor exceeds the peak inductor current, and the
rated maximum DC inductor current exceeds the maximum output current (IOUT(MAX)). Inductance values
smaller than LIDEAL can be used to reduce inductor
size; however, if much smaller values are used, peak
inductor current rises and a larger output capacitance
may be required to suppress output ripple. Larger
High-Efficiency, Low-IQ, PMICs with Dynamic
Voltage Management for Mobile Applications
Input Capacitor Selection
The input capacitor in a step-down DC-DC converter
reduces current peaks drawn from the battery or other
input power source and reduces switching noise in the
controller. The impedance of the input capacitor at the
switching frequency should be less than that of the
input source so that high-frequency switching currents
do not pass through the input source.
The input capacitor must meet the input-ripple-current
requirement imposed by the step-down converter.
Ceramic capacitors are preferred due to their resilience
to power-up surge currents. Choose the input capacitor
so that the temperature rise due to input ripple current
does not exceed approximately 10°C. For a step-down
DC-DC converter, the maximum input ripple current is
1/2 of the output. This maximum input ripple current
occurs when the step-down converter operates at 50%
duty factor (VIN = 2 x VOUT).
Refer to the MAX8660 EV kit data sheet for specific
input capacitor recommendations.
Output Capacitor Selection
The step-down DC-DC converter output capacitor
keeps output ripple small and ensures control-loop stability. The output capacitor must also have low impedance at the switching frequency. Ceramic, polymer,
and tantalum capacitors are suitable, with ceramic
exhibiting the lowest ESR and lowest high-frequency
impedance.
Output ripple due to capacitance (neglecting ESR) is
approximately:
IL(PEAK )
VRIPPLE =
2π x fOSC x COUT
Additional ripple due to capacitor ESR is:
VRIPPLE(ESR) = IL(PEAK) x ESR
Refer to the MAX8660 EV kit data sheet for specific output capacitor recommendations.
Step-Down Converter Output Current
The maximum output current for each step-down converter is listed in the Electrical Characteristics table.
This current is guaranteed by correlation to the p-channel current-limit threshold, p-channel on-resistance, nchannel on-resistance, oscillator frequency, input
voltage range, and output voltage range. The maximum
output current in the Electrical Characteristics table is
for the components shown in Figure 3 over then entire
specified range of input and output voltage. For different components or voltage ranges, the maximum output current changes. Typically, inductors with a higher
inductance increase the maximum output current, but
they are physically larger and decrease the output voltage response time due to a load transient.
Calculate the maximum output current for a particular
application using following the two-step process (see
Figure 12). Use the maximum expected value for input
voltage (VIN). Using the minimum expected values for
the p-channel current-limit (ILIM), oscillator frequency
(f), and inductance (L) provides the absolute worstcase maximum output current (i.e., the lowest value).
TO FIND THE ABSOLUTE WORST -CASE MAXIMUM OUTPUT CURRENT FOR REG3 WITH VIN = 3.2V TO 4.2V,
VOUT = 1.2V, L = 1.2µH ±30%, AND RL = 50mΩ
V
+I
(R + RL ) 1.2V + 1.6 A(0.08Ω + 0.05Ω)
D = OUT OUTTAR N
=
= 0.34
VIN + IOUTTAR (RN − RP )
4.2V + 1.6 A(0.08Ω − 0.12Ω)
1.2V(1 − 0.34)
V
(1 − D)
1.85A −
ILIM − OUT
6 Hz) × (1.2 × 10−6 H × 0.7)
2
×
(
1
.
9
×
10
2× f ×L
= 1.56 A
=
IOUTMAX =
1− D
1 − 0.34
1 + (RN + RL )
1 + (0.08Ω + 0.05Ω)
2× f ×L
2 × (1.9 × 106 Hz) × (1.2 × 10−6 H × 0.7)
Figure 12. Step-Down Converter Maximum Output Current Example
39
MAX8660/MAX8660A/MAX8660B/MAX8661
inductance values than LIDEAL can be used to obtain
higher output current, but typically require physically
larger inductor size. Refer to the MAX8660 EV kit data
sheet for specific inductor recommendations.
MAX8660/MAX8660A/MAX8660B/MAX8661
High-Efficiency, Low-IQ, PMICs with Dynamic
Voltage Management for Mobile Applications
Conservative designers can choose to use the minimums for ILIM, f, and L, however, it is statistically rare
for all three of these parameters to be at the minimum
value in any one given design. A more practical
method is to look at the how each individual variable
degrades the maximum output current and then take
the RMS of each variables contribution. Refer to the
spreadsheet (www.maxim-ic.com/tools/other/software/MAX8660-step-down_output_current.xls) for
easy evaluation of the maximum output current. It provides results for both the absolute worst case and RMS
calculation methods.
1) Use the following equation to calculate the approximate duty cycle (D):
V
+I
(R + RL )
D = OUT OUTTAR N
VIN + IOUTTAR (RN − RP )
Power Dissipation
The MAX8660/MAX8661 have a thermal-shutdown feature that protects the IC from damage when the die temperature exceeds +160°C (see the Thermal-Overload
Protection section for more information). To prevent thermal overload and allow the maximum load current on
each regulator, it is important to ensure that the heat
generated by the MAX8660/MAX8661 can be dissipated
into the PC board. The exposed pad must be soldered to
the PC board, with multiple vias under the exposed pad
(EP) conducting heat to a ground plane.
The junction-to-case thermal resistance (θJC) of the
MAX8660/MAX8661 is 2.7°C/W. When properly mounted on a multilayer PC board, the junction-to-ambient
thermal resistance (θJA) is typically 28°C/W.
PCB Layout and Routing
where:
VOUT = output voltage
IOUTTAR = target (desired) output current—cannot
be more than the minimum p-channel current-limit
threshold
RN = n-channel on-resistance
RP = p-channel on-resistance
RL = external inductor’s ESR
VIN = input voltage—MAXIMUM
2) Use the following equation to calculate the maximum
output current (IOUTMAX):
V
(1 − D)
ILIM − OUT
2× f ×L
IOUTMAX =
1− D
1 + (RN + RL )
2× f ×L
where:
ILIM = p-channel current-limit threshold—MINIMUM
VOUT = output voltage
D = approximate duty cycle derived from step 1
f = oscillator frequency—MINIMUM
L = external inductor’s inductance—MINIMUM
RN = n-channel on-resistance
RL = external inductor’s ESR
40
Applications Information
Good printed circuit board (PCB) layout is necessary to
achieve optimal performance. Conductors carrying discontinuous currents and any high-current path must be
made as short and wide as possible.
Refer to the MAX8660 EV kit data sheet for an example
of a good PCB layout. Place the bypass capacitors for
each power input pair (IN to AGND, PV1 to PG1, PV2 to
PG2, PV3, to PG3, and PV4 to PG4) as close as possible
to the IC.
The exposed pad (EP) is the main path for heat to exit
the IC. Connect EP to the ground plane with multiple
vias to allow heat to dissipate from the device.
High-Efficiency, Low-IQ, PMICs with Dynamic
Voltage Management for Mobile Applications
PART
TOP VIEW
8660E
TLyww
+ aaaa
Ordering Information (continued)
8660AE
TLyww
+ aaaa
8661E
TLyww
+ aaaa
MAX8660AETL+
MAX8660BETL+
PIN-PACKAGE
40 Thin QFN
40 Thin QFN
V1: 3.3V, 3.0V, 2.85V
V2: 3.3V, 2.5V, 1.8V
V3: 1.15V (default)
V4: 1.15V (default)
40 Thin QFN
No REG1 and REG7
V2: 3.3V, 2.5V, 1.8V
V3: 1.4V (default)
V4: 1.4V (default)
“yww” is a date code.
“aaaa” is an assembly code.
+Denotes lead-free packaging and marks pin 1 location.
MAX8661ETL+
OPTIONS
V1: 2.5V, 2.0V, 1.8V
V2: 2.5V, 2.0V, 1.8V
V3: 1.4V (default)
V4: 1.4V (default)
Note: All devices are specified over the -40°C to 85°C operating
temperature range.
+Denotes lead(Pb)-free/RoHS-compliant package.
Chip Information
PROCESS: BiCMOS
41
MAX8660/MAX8660A/MAX8660B/MAX8661
Package Marking
MAX8660/MAX8660A/MAX8660B/MAX8661
High-Efficiency, Low-IQ, PMICs with Dynamic
Voltage Management for Mobile Applications
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the
package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the
package regardless of RoHS status.
42
PACKAGE TYPE
PACKAGE CODE
DOCUMENT NO.
40 TQFN
T4055-1
21-0140
High-Efficiency, Low-IQ, PMICs with Dynamic
Voltage Management for Mobile Applications
43
MAX8660/MAX8660A/MAX8660B/MAX8661
Package Information (continued)
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the
package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the
package regardless of RoHS status.
MAX8660/MAX8660A/MAX8660B/MAX8661
High-Efficiency, Low-IQ, PMICs with Dynamic
Voltage Management for Mobile Applications
Revision History
REVISION
NUMBER
REVISION
DATE
DESCRIPTION
PAGES
CHANGED
2
8/09
Added MAX8660B and automotive part options, and replaced Intel references with
Marvell
1, 2, 3, 5, 6, 7,
10, 11, 19–34,
36, 37
6/10
Added reference to Marvell’s Armada 100 family of processors, added soldering
temperature, corrected an error with REG4’s p-Channel Current Limit Threshold,
added Step-Down Converter Output Current section, improved data sheet
consistency and style
1, 2, 5, 6, 7, 10,
11, 12, 14, 15,
25, 26, 30, 33,
35, 39
3
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in
the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
44
_______________Maxim Integrated Products, Inc. 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000
© 2012 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
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