MAX8760ETL+TG51

19-3721; Rev 0; 5/05 KIT ATION EVALU E L B A AVAIL Dual-Phase, Quick-PWM Controller for AMD Mobile Turion 64 CPU Core Power Supplies ♦ ±0.75% VOUT Accuracy Over Line, Load, and Temperature (1.3V) ♦ Active Voltage Positioning with Adjustable Gain and Offset ♦ 6-Bit On-Board DAC: 0.375V to 1.55V Output Adjust Range ♦ Selectable 100kHz/200kHz/300kHz/550kHz Switching Frequency ♦ 4V to 28V Battery Input Voltage Range ♦ Adjustable Slew-Rate Control ♦ Drives Large Synchronous Rectifier MOSFETs ♦ Undervoltage and Thermal-Fault Protection ♦ Power Sequencing and Timing ♦ Selectable Suspend Voltage ♦ Soft-Start and Soft-Shutdown ♦ Selectable Single- or Dual-Phase Pulse Skipping Ordering Information PART TEMP RANGE MAX8760ETL -40°C to +100°C 40 Thin QFN 6mm x 6mm MAX8760ETL+ -40°C to +100°C 40 Thin QFN 6mm x 6mm Servers/Desktop Computers Quick-PWM is a trademark of Maxim Integrated Products, Inc. PGND DLS DHS LXS BSTS V+ 31 20 32 19 33 18 34 17 D4 D5 SKIP OAIN+ CMP 37 14 CMN CSN 38 13 OAINFB CCI GNDS 39 12 CCV CSP 40 11 GND 16 35 MAX8760 36 1 2 3 4 5 6 15 7 8 9 10 REF ILIM VCC Voltage-Positioned Step-Down Converters D3 30 29 28 27 26 25 24 23 22 21 SHDN OFS Multiphase CPU Core Supply LXM BSTM VROK D0 D1 D2 VDD TOP VIEW DLM DHM Pin Configuration Applications 6-Bit VID AMD Mobile Turion 64 CPU PIN-PACKAGE +Denotes lead-free package. TON SUS S0 S1 The MAX8760 is available in a low-profile, 40-pin 6mm x 6mm thin QFN package. For other CPU platforms, refer to the pin-to-pin compatible MAX1544, MAX1519/MAX1545, and MAX1532/MAX1546/MAX1547 data sheets. ♦ Dual-Phase, Quick-PWM Controller TIME The MAX8760 is a dual-phase, Quick-PWM™, stepdown controller for 6-bit VID AMD Mobile Turion™ 64 CPU core supplies. Dual-phase operation reduces input ripple current requirements and output voltage ripple while easing component selection and layout difficulties. The Quick-PWM control scheme provides instantaneous response to fast-load current steps. The MAX8760 includes active voltage positioning with adjustable gain and offset, reducing power dissipation and bulk output capacitance requirements. The MAX8760 is intended for two different notebook CPU core applications: stepping down the battery directly or stepping down the 5V system supply to create the core voltage. The single-stage conversion method allows this device to directly step down high-voltage batteries for the highest possible efficiency. Alternatively, two-stage conversion (stepping down the 5V system supply instead of the battery) at a higher switching frequency provides the minimum possible physical size. The MAX8760 complies with AMD’s desktop and mobile CPU specifications. The switching regulator features softstart and power-up sequencing, and soft-shutdown. The MAX8760 also features independent four-level logic inputs for setting the suspend voltage (S0, S1). The MAX8760 includes output undervoltage protection, thermal protection, and voltage regulator power-OK (VROK) output. When any of these protection features detect a fault, the controller shuts down. Features THIN QFN Turion is a trademark of AMD. ________________________________________________________________ Maxim Integrated Products For pricing delivery, and ordering information please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX8760 General Description MAX8760 Dual-Phase, Quick-PWM Controller for AMD Mobile Turion 64 CPU Core Power Supplies ABSOLUTE MAXIMUM RATINGS V+ to GND ..............................................................-0.3V to +30V VCC to GND ..............................................................-0.3V to +6V VDD to PGND............................................................-0.3V to +6V SKIP, SUS, D0–D5 to GND.......................................-0.3V to +6V ILIM, FB, OFS, CCV, CCI, REF, OAIN+, OAIN- to GND.........................................-0.3V to (VCC + 0.3V) CMP, CSP, CMN, CSN, GNDS to GND ......-0.3V to (VCC + 0.3V) TON, TIME, VROK, S0–S1 to GND..............-0.3V to (VCC + 0.3V) SHDN to GND (Note 1)...........................................-0.3V to +18V DLM, DLS to PGND ....................................-0.3V to (VDD + 0.3V) BSTM, BSTS to GND ..............................................-0.3V to +36V DHM to LXM ...........................................-0.3V to (VBSTM + 0.3V) LXM to BSTM............................................................-6V to +0.3V DHS to LXS..............................................-0.3V to (VBSTS + 0.3V) LXS to BSTS .............................................................-6V to +0.3V GND to PGND .......................................................-0.3V to +0.3V REF Short-Circuit Duration .........................................Continuous Continuous Power Dissipation (TA = +70°C) 40-Pin 6mm ✕ 6mm Thin QFN (derate 23.2mW/°C above +70°C) ...............................1.860W Operating Temperature Range .........................-40°C to +100°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Note 1: SHDN may be forced to 12V for the purpose of debugging prototype boards using the no-fault test mode, which disables fault protection and overlapping operation. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (Circuit of Figure 1, V+ = 15V, VCC = VDD = V SHDN = V SKIP = VS0 = VS1 = 5V, VFB = VCMP = VCMN = VCSP = VCSN = 1.3V, OFS = SUS = GNDS = D0–D5 = GND, TA = 0°C to +85°C, unless otherwise specified. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS PWM CONTROLLER Battery voltage, V+ Input Voltage Range V+ = 4.5V to 28V, includes load regulation error DC Output Voltage Accuracy (Note 2) Line Regulation Error Input Bias Current 4 28 4.5 5.5 DAC codes ≥ 1V -10 +10 DAC codes from 0.375V to 1V -15 +15 VCC, VDD VCC = 4.5V to 5.5V, V+ = 4.5V to 28V IFB, IGNDS IOFS FB, GNDS OFS OFS Input Range OFS Gain AOFS TIME Frequency Accuracy -0.1 +0.1 0 2 ∆VOUT/∆VOFS; ∆VOFS = VOFS - VREF, VOFS = 1V to 2V -0.129 -0.125 fTIME µA V -0.117 V/V -0.125 -20 AGNDS -0.117 +200 mV ∆VOUT/∆VGNDS 0.97 0.99 1.01 V/V 1000kHz nominal, RTIME = 15kΩ 900 1000 1100 500kHz nominal, RTIME = 30kΩ 460 500 540 250kHz nominal, RTIME = 60kΩ 225 250 275 Startup and shutdown, RTIME = 30kΩ 2 +2 -0.129 mV mV -2 ∆VOUT/∆VOFS; ∆VOFS = VOFS, VOFS = 0 to 1V GNDS Input Range GNDS Gain 5 V 125 _______________________________________________________________________________________ kHz Dual-Phase, Quick-PWM Controller for AMD Mobile Turion 64 CPU Core Power Supplies (Circuit of Figure 1, V+ = 15V, VCC = VDD = V SHDN = V SKIP = VS0 = VS1 = 5V, VFB = VCMP = VCMN = VCSP = VCSN = 1.3V, OFS = SUS = GNDS = D0–D5 = GND, TA = 0°C to +85°C, unless otherwise specified. Typical values are at TA = +25°C.) PARAMETER On-Time (Note 3) SYMBOL tON Minimum Off-Time (Note 3) tOFF(MIN) CONDITIONS MIN TYP MAX TON = GND (550kHz) 155 180 205 TON = REF (300kHz) 320 355 390 TON = open (200kHz) 475 525 575 TON = VCC (100kHz) 920 1000 1140 TON = GND 300 375 TON = VCC, open, or REF 400 480 1.70 3.20 mA V+ = 12V, VFB = VCCI = 1.2V UNITS ns ns BIAS AND REFERENCE Quiescent Supply Current (VCC) ICC Measured at VCC, FB forced above the regulation point, OAIN- = FB, VOAIN+ = 1.3V Quiescent Supply Current (VDD) IDD Measured at VDD, FB forced above the regulation point 20V) AC adapters. Low-current applications usually require less attention. The high-side MOSFET (NH) must be able to dissipate the resistive losses plus the switching losses at both VIN(MIN) and VIN(MAX). Calculate both of these sums. Ideally, the losses at VIN(MIN) should be roughly equal to losses at VIN(MAX), with lower losses in between. If the losses at VIN(MIN) are significantly higher than the losses at VIN(MAX), consider increasing the size of NH (reducing RDS(ON) but with higher CGATE). Conversely, if the losses at VIN(MAX) are significantly higher than the losses at VIN(MIN), consider reducing the size of NH (increasing RDS(ON) to lower CGATE). If VIN does not vary over a wide range, the minimum power dissipation occurs where the resistive losses equal the switching losses. Choose a low-side MOSFET that has the lowest possible on-resistance (RDS(ON)), comes in a moderate-sized package (i.e., one or two 8-pin SOs, DPAK, or D2PAK), and is reasonably priced. Ensure that the DL gate driver can supply sufficient current to support the gate charge and the current injected into the parasitic gate-to-drain capacitor caused by the high-side MOSFET turning on; otherwise, cross-conduction problems can occur (see the MOSFET Gate Driver section). MOSFET Power Dissipation Worst-case conduction losses occur at the duty factor extremes. For the high-side MOSFET (NH), the worstcase power dissipation due to resistance occurs at the minimum input voltage: ⎞2 ⎛V ⎞ ⎛ I PD (NH RESISTIVE) = ⎜ OUT ⎟ ⎜ LOAD ⎟ RDS(ON) ⎝ VIN ⎠ ⎝ η TOTAL ⎠ where ηTOTAL is the total number of phases. Generally, a small high-side MOSFET is desired to reduce switching losses at high input voltages. However, the RDS(ON) required to stay within package power dissipation often limits how small the MOSFET can be. Again, the optimum occurs when the switching losses equal the conduction (RDS(ON)) losses. Highside switching losses do not usually become an issue until the input is greater than approximately 15V. Calculating the power dissipation in high-side MOSFET (NH) due to switching losses is difficult since it must allow for difficult quantifying factors that influence the turn-on and turn-off times. These factors include the internal gate resistance, gate charge, threshold 34 voltage, source inductance, and PC board layout characteristics. The following switching-loss calculation provides only a very rough estimate and is no substitute for breadboard evaluation, preferably including verification using a thermocouple mounted on NH: ⎞ f ⎞ ⎛ I ⎛C PD (NH SWITCHING) = (VIN(MAX))2 ⎜ RSS SW ⎟ ⎜ LOAD ⎟ ⎝ IGATE ⎠ ⎝ η TOTAL ⎠ where CRSS is the reverse transfer capacitance of NH and IGATE is the peak gate-drive source/sink current (1A typ). Switching losses in the high-side MOSFET can become an insidious heat problem when maximum AC adapter voltages are applied due to the squared term in the C x V IN2 x f SW switching-loss equation. If the high-side MOSFET chosen for adequate RDS(ON) at low battery voltages becomes extraordinarily hot when biased from V IN(MAX) , consider choosing another MOSFET with lower parasitic capacitance. For the low-side MOSFET (NL), the worst-case power dissipation always occurs at maximum input voltage: ⎡ ⎛ VOUT ⎞ ⎤ ⎛ ILOAD ⎞ 2 PD (NL RESISTIVE) = ⎢1 − ⎜ ⎟⎥ ⎜ ⎟ RDS(ON) ⎝ VIN(MAX) ⎠ ⎦ ⎝ η TOTAL ⎠ ⎣ The worst-case for MOSFET power dissipation occurs under heavy overloads that are greater than ILOAD(MAX) but are not quite high enough to exceed the current limit and cause the fault latch to trip. To protect against this possibility, you can “overdesign” the circuit to tolerate: ∆I ⎛ ⎞ ILOAD = η TOTAL ⎜ IVALLEY(MAX) + INDUCTOR ⎟ ⎝ ⎠ 2 LIR ⎞ ⎛I = η TOTAL IVALLEY(MAX) + ⎜ LOAD(MAX) ⎟ ⎝ ⎠ 2 where I VALLEY(MAX) is the maximum valley current allowed by the current-limit circuit, including threshold tolerance and on-resistance variation. The MOSFETs must have a good-size heatsink to handle the overload power dissipation. Choose a Schottky diode (DL) with a forward voltage low enough to prevent the low-side MOSFET body diode from turning on during the dead time. As a general rule, select a diode with a DC current rating equal to 1/3 of the load current-per-phase. This diode is optional and can be removed if efficiency is not critical. Boost Capacitors The boost capacitors (CBST) must be selected large enough to handle the gate-charging requirements of the high-side MOSFETs. Typically, 0.1µF ceramic ______________________________________________________________________________________ Dual-Phase, Quick-PWM Controller for AMD Mobile Turion 64 CPU Core Power Supplies CBST = N x QGATE 200mV where N is the number of high-side MOSFETs used for one regulator, and QGATE is the gate charge specified in the MOSFET’s data sheet. For example, assume two IRF7811W n-channel MOSFETs are used on the high side. According to the manufacturer’s data sheet, a single IRF7811W has a maximum gate charge of 24nC (VGS = 5V). Using the above equation, the required boost capacitance would be: CBST = 2 x 24nC = 0.24µF 200mV Selecting the closest standard value, this example requires a 0.22µF ceramic capacitor. Current-Balance Compensation (CCI) The current-balance compensation capacitor (CCCI) integrates the difference between the main and secondary current-sense voltages. The internal compensation resistor (R CCI = 20kΩ) improves transient response by increasing the phase margin. This allows the dynamics of the current-balance loop to be optimized. Excessively large capacitor values increase the integration time constant, resulting in larger current differences between the phases during transients. Excessively small capacitor values allow the current loop to respond cycle-by-cycle but can result in small DC current variations between the phases. Likewise, excessively large resistor values can also cause DC current variations between the phases. Small resistor values reduce the phase margin, resulting in marginal stability in the current-balance loop. For most applications, a 470pF capacitor from CCI to the switching regulator’s output works well. Connecting the compensation network to the output (VOUT) allows the controller to feed-forward the output voltage signal, especially during transients. To reduce noise pickup in applications that have a widely distributed layout, it is sometimes helpful to connect the compensation network to the quiet analog ground rather than VOUT. Setting Voltage Positioning Voltage positioning dynamically lowers the output voltage in response to the load current, reducing the processor’s power dissipation. When the output is loaded, an operational amplifier (Figure 5) increases the signal fed back to the Quick-PWM controller’s feedback input. The adjustable amplification allows the use of standard, current-sense resistor values, and significantly reduces the power dissipated since smaller current-sense resistors can be used. The load transient response of this control loop is extremely fast, yet well controlled, so the amount of voltage change can be accurately confined within the limits stipulated in the microprocessor power-supply guidelines. The voltage-positioned circuit determines the load current from the voltage across the current-sense resistors (RSENSE = RCM = RCS) connected between the inductors and output capacitors, as shown in Figure 10. The voltage drop can be determined by the following equation: VVPS = AVPSILOADRSENSE η SUM RF AVPS = η TOTAL RB where ηSUM is the number of phases summed together for voltage-positioning feedback, and ηTOTAL is the total number of active phases. When the slave controller is disabled, the current-sense summation maintains the proper voltage-positioned slope. Select the positive input summing resistors so RFBS = RF and RA = RB. Minimum Input Voltage Requirements and Dropout Performance The nonadjustable minimum off-time one-shot and the number of phases restrict the output voltage adjustable range for continuous-conduction operation. For best dropout performance, use the slower (200kHz) on-time settings. When working with low input voltages, the duty-factor limit must be calculated using worst-case values for on- and off-times. Manufacturing tolerances and internal propagation delays introduce an error to the TON K factor. This error is greater at higher frequencies (Table 6). Also, keep in mind that transient response performance of buck regulators operated too close to dropout is poor, and bulk output capacitance must often be added (see the V SAG equation in the Design Procedure section). The absolute point of dropout is when the inductor current ramps down during the minimum off-time (∆IDOWN) as much as it ramps up during the on-time (∆IUP). The ratio h = ∆IUP/∆IDOWN is an indicator of the ability to slew the inductor current higher in response to ______________________________________________________________________________________ 35 MAX8760 capacitors work well for low-power applications driving medium-sized MOSFETs. However, high-current applications driving large, high-side, MOSFETs require boost capacitors larger than 0.1µF. For these applications, select the boost capacitors to avoid discharging the capacitor more than 200mV while charging the high-side MOSFET’s gates: MAX8760 Dual-Phase, Quick-PWM Controller for AMD Mobile Turion 64 CPU Core Power Supplies CMN CMP MAIN PHASE L1 RSENSE MAX8760 RA RB PC BOARD TRACE RESISTANCE OAIN+ RFBS ERROR COMPARATOR CPU SENSE POINT OAINFB RF RA SECOND PHASE L2 RB PC BOARD TRACE RESISTANCE RSENSE CSP CSN Figure 10. Voltage-Positioning Gain increased load, and must always be greater than 1. As h approaches 1, the absolute minimum dropout point, the inductor current cannot increase as much during each switching cycle and V SAG greatly increases unless additional output capacitance is used. A reasonable minimum value for h is 1.5, but adjusting this up or down allows tradeoffs between VSAG, output capacitance, and minimum operating voltage. For a given value of h, the minimum operating voltage can be calculated as: ⎡ ⎤ ⎢ V -V ⎥ FB VPS + VDROP1 ⎥ VIN(MIN) = η OUTPH ⎢ ⎢ ⎛ h x tOFF(MIN) ⎞ ⎥ 1 η ⎟⎥ ⎢ OUTPH ⎜⎝ ⎠⎦ K ⎣ + VDROP2 - VDROP1 + VVPS where ηOUTPH is the total number of out-of-phase switching regulators, VVPS is the voltage-positioning droop, VDROP1 and VDROP2 are the parasitic voltage drops in the discharge and charge paths (see the On-Time OneShot (TON) section), tOFF(MIN) is from the Electrical Characteristics table, and K is taken from Table 6. The absolute minimum input voltage is calculated with h = 1. If the calculated VIN(MIN) is greater than the required minimum input voltage, then reduce the operating frequency or add output capacitance to obtain an acceptable VSAG. If operation near dropout is anticipated, calculate VSAG to be sure of adequate transient response. 36 Dropout design example: VFB = 1.4V KMIN = 3µs for fSW = 300kHz tOFF(MIN) = 400ns VVPS = 3mV/A × 30A = 90mV VDROP1 = VDROP2 = 150mV (30A load) h = 1.5 and ηOUTPH = 2 ⎡ 1.4V - 90mV + 150mV ⎤ VIN(MIN) = 2 x ⎢ ⎥ ⎣ 1 - 2 x (0.4µs x 1.5 / 3.0µs ⎦ + 150mV - 150mV + 90mV = 4.96V Calculating again with h = 1 gives the absolute limit of dropout: ⎡ 1.4V - 90mV + 150mV ⎤ VIN(MIN) = 2 x ⎢ ⎥ ⎣ 1 - 2 x (0.4µs x 1.0 / 3.0µs ⎦ + 150mV - 150mV + 90mV = 4.07V Therefore, VIN must be greater than 4.1V, even with very large output capacitance, and a practical input voltage with reasonable output capacitance would be 5V. ______________________________________________________________________________________ Dual-Phase, Quick-PWM Controller for AMD Mobile Turion 64 CPU Core Power Supplies PC Board Layout Guidelines Careful PC board layout is critical to achieve low switching losses and clean, stable operation. The switching power stage requires particular attention (Figure 11). If possible, mount all the power components on the top side of the board with their ground terminals flush against one another. Follow these guidelines for good PC board layout: 1) Keep the high-current paths short, especially at the ground terminals. This is essential for stable, jitter-free operation. 2) Connect all analog grounds to a separate solid copper plane, which connects to the GND pin of the Quick-PWM controller. This includes the VCC bypass capacitor, REF and GNDS bypass capacitors, compensation (CC_) components, and the resistive dividers connected to ILIM and OFS. Each slave controller should also have a separate analog ground. Return the appropriate noise-sensitive slave components to this plane. Since the reference in the master is sometimes connected to the slave, it may be necessary to couple the analog ground in the master to the analog ground in the slave to prevent ground offsets. A low-value (≤10Ω) resistor is sufficient to link the two grounds. Keep the power traces and load connections short. This is essential for high efficiency. The use of thick copper PC boards (2oz vs. 1oz) can enhance full-load efficiency by 1% or more. Correctly routing PC board traces is a difficult task that must be approached in terms of fractions of centimeters, where a single mΩ of excess trace resistance causes a measurable efficiency penalty. Keep the high-current, gate-driver traces (DL, DH, LX, and BST) short and wide to minimize trace resistance and inductance. This is essential for high-power MOSFETs that require low-impedance gate drivers to avoid shoot-through currents. C_P, C_N, OAIN+, and OAIN- connections for current limiting and voltage positioning must be made using Kelvin-sense connections to guarantee the current-sense accuracy. When trade-offs in trace lengths must be made, it is preferable to allow the inductor-charging path to be made longer than the discharge path. For example, it is better to allow some extra distance between the input capacitors and the high-side MOSFET than to allow distance between the 3) 4) 5) 6) 7) 8) inductor and the low-side MOSFET or between the inductor and the output filter capacitor. Route high-speed switching nodes away from sensitive analog areas (REF, CCV, CCI, FB, C_P, C_N, etc). Make all pin-strap control input connections (SHDN, ILIM, SKIP, SUS, S_, TON) to analog ground or VCC rather than power ground or VDD. Layout Procedure Place the power components first, with ground terminals adjacent (low-side MOSFET source, CIN, COUT, and D1 anode). If possible, make all these connections on the top layer with wide, copper-filled areas. 1) Mount the controller IC adjacent to the low-side MOSFET. The DL gate traces must be short and wide (50 mils to 100 mils wide if the MOSFET is 1in from the controller IC). 2) 3) 4) Group the gate-drive components (BST diodes and capacitors, VDD bypass capacitor) together near the controller IC. Make the DC-to-DC controller ground connections as shown in the Standard Application Circuits. This diagram can be viewed as having four separate ground planes: input/output ground, where all the high-power components go; the power ground plane, where the PGND pin and V DD bypass capacitor go; the master’s analog ground plane, where sensitive analog components, the master’s GND pin, and VCC bypass capacitor go; and the slave’s analog ground plane, where the slave’s GND pin and VCC bypass capacitor go. The master’s GND plane must meet the PGND plane only at a single point directly beneath the IC. Similarly, the slave’s GND plane must meet the PGND plane only at a single point directly beneath the IC. The respective master and slave ground planes should connect to the high-power output ground with a short metal trace from PGND to the source of the low-side MOSFET (the middle of the star ground). This point must also be very close to the output capacitor ground terminal. Connect the output power planes (VCORE and system ground planes) directly to the output filter capacitor positive and negative terminals with multiple vias. Place the entire DC-to-DC converter circuit as close to the CPU as is practical. Chip Information TRANSISTOR COUNT: 11,015 PROCESS: BiCMOS ______________________________________________________________________________________ 37 MAX8760 Applications Information MAX8760 Dual-Phase, Quick-PWM Controller for AMD Mobile Turion 64 CPU Core Power Supplies KELVIN SENSE VIAS UNDER THE SENSE RESISTOR (REFER TO EVALUATION KIT) CPU MAIN PHASE SECONDARY PHASE OUTPUT COUT RSENSE COUT COUT COUT COUT COUT RSENSE INDUCTOR INDUCTOR CIN CIN CIN CIN CIN CIN POWER GROUND INPUT PLACE CONTROLLER ON BACK SIDE WHEN POSSIBLE, USING THE GROUND PLANE TO SHIELD THE IC FROM EMI VIAS TO POWER GROUND CONNECT THE EXPOSED PAD TO ANALOG GND VIA TO ANALOG GROUND POWER GROUND (2ND LAYER) CONNECT GND AND PGND TO THE CONTROLLER AT ONE POINT ONLY AS SHOWN ANALOG GROUND (2ND LAYER) Figure 11. PC Board Layout Example 38 ______________________________________________________________________________________ Dual-Phase, Quick-PWM Controller for AMD Mobile Turion 64 CPU Core Power Supplies QFN THIN.EPS Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 39 © 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc. MAX8760 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)