MAX8775ETJ+TG24

19-0670; Rev 0; 11/06 KIT ATION EVALU E L B AVAILA Dual and Combinable Graphics Core Controller for Notebook Computers PART TEMP RANGE PINPACKAGE MAX8775ETJ+ -40°C to +85°C 32 Thin QFN 5mm x 5mm GPU and I/O Power Supplies Tracking Output Power Supplies T3255-5 DL2 LX2 BST2 24 PGND TOP VIEW VDD Pin Configuration 2 to 4 Li+ Cells Battery-Powered Devices Media Center and Gaming Notebooks PKG CODE +Denotes lead-free package. LX1 Applications Ordering Information DL1 Configured in separate mode, the MAX8775 provides power to two dynamic voltage rails, one for the GPU core and the other for the I/O power rail. Configured in combined mode, the MAX8775 functions as a twophase, high-current, single-output GPU core regulator, powering the high-performance GPU engines used in gaming machines and media center notebooks. The REFIN voltage setting allows for multiple dynamic output voltages required by the different GPU operating and sleep states. Automatic fault blanking, forced-PWM operation, and transition control are achieved by detecting the voltage change at REFIN. Fixed-frequency operation with 180° out-of-phase interleaving minimizes input ripple current from the lowest input voltages up to the 26V maximum input. Current-mode control allows the use of low-ESR output capacitors. Internal integrators maintain high output accuracy over the full line-and-load range, in both forced-PWM mode and pulse-skipping mode. True differential current sensing provides accurate output current limit and current balance when operated in combined mode. Independent on/off and skip control allows flexible power sequencing and power management. Voltagecontrolled soft-start reduces inrush current. Soft-stop gradually ramps the output voltage down, preventing negative voltage dips. BST1 The MAX8775 is a dual, step-down, interleaved, fixedfrequency, switch-mode power-supply (SMPS) controller with synchronous rectification. It is intended for GPU cores and I/O power generation in battery-powered systems. Flexible configuration allows the MAX8775 to operate as two independent single-phase regulators, or as one high-current two-phase regulator. Features o Dual-Output, Fixed-Frequency, Current-Mode Control o Combinable Output for Higher Currents o Dynamic Output Voltages with Automatic Fault Blanking and Transition Control o True Out-of-Phase Operation o True Differential Current Sense for Accurate Current Limit and Current Balance o 4V to 26V Input Range o 100kHz to 600kHz Switching Frequency o 0.5V to 2.5V Adjustable Outputs o Internal Integrator for High Output Accuracy o Stable with Low-ESR Output Capacitors o Independent Selectable PWM and Skip-Mode Operation o Independent Power-Good Outputs o Soft-Start and Soft-Stop o 2.5V Precision Reference o < 1µA Typical Shutdown Current 23 22 21 20 19 18 17 DH1 25 16 ON1 26 15 ON2 CSL1 27 14 CSL2 13 CSH2 12 SKIP2 PGOOD1 30 11 PGOOD2 DTRANS 31 10 CCI2 9 SLEW2 CSH1 28 MAX8775 SKIP1 29 4 5 6 7 8 VCC REF REFIN2 OVP2 3 AGND 2 OSC OVP1 1 REFIN1 SLEW1 32 DH2 THIN QFN 5mm x 5mm ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX8775 General Description MAX8775 Dual and Combinable Graphics Core Controller for Notebook Computers ABSOLUTE MAXIMUM RATINGS VDD, VCC, CSH_, CSL_ to AGND............................-0.3V to +6V ON_, SKIP_, PGOOD_ to AGND ..............................-0.3V to +6V OVP_, REFIN_ to AGND ...........................................-0.3V to +6V DTRANS to AGND ....................................................-0.3V to +6V REF, OSC, SLEW_, CCI2 to AGND ...........-0.3V to (VCC + 0.3V) BST1, BST2 to AGND .............................................-0.3V to +36V LX1 to BST1..............................................................-6V to +0.3V LX2 to BST2..............................................................-6V to +0.3V DH1 to LX1 ..............................................-0.3V to (VBST1 + 0.3V) DH2 to LX2 ..............................................-0.3V to (VBST2 + 0.3V) DL1, DL2 to PGND .....................................-0.3V to (VDD + 0.3V) AGND to PGND .....................................................-0.3V to +0.3V REF Short Circuit to AGND.........................................Continuous REF Current ......................................................................+10mA Continuous Power Dissipation (TA = +70°C) 32-Pin, 5mm x 5mm, Thin QFN (derate 21.3mW/°C above +70°C) .............................1702mW Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (Circuit of Figure 1, VIN = 12V, SKIP_ = PGND = AGND, ON_ = VCC = 5V, separate mode, TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS INPUT SUPPLIES Input Voltage Range VCC Undervoltage Lockout Threshold Quiescent Supply Current (VCC) Quiescent Supply Current (VDD) 4 26 VBIAS VIN VCC, VDD 4.5 5.5 VUVLO Rising edge, 50mV typical hysteresis 4.1 V 4.25 4.5 V ICC CSL_ forced above their regulation points 1.5 2.5 mA IDD CSL_ forced above their regulation points, SKIP mode 200mV above nominal level When the overvoltage comparator trips, the faulted side sets the OV latch, forcing PGOOD_ low and DL_ high. An OV fault on one SMPS does not affect the operation of the other SMPS. The OV latch is cleared by cycling VCC below 1V or cycling both ON_ pins. Output Undervoltage Protection (UVP) Either output < 300mV below nominal level, UVP is enabled 6144 clock cycles (1/fOSC) after the output is enabled (ON_ going high) When the undervoltage comparator trips, the faulted side sets the UV latch, forcing PGOOD_ low and initiating the soft-shutdown sequence by pulsing only DL_. DL_ goes low after soft-shutdown. A UV fault on one SMPS does not affect the operation of the other SMPS. The UV latch is cleared by cycling VCC below 1V or cycling the respective ON_ pin. Shutdown ON1 and ON2 are driven low DL_ stays low after soft-shutdown is completed. All circuitry is shut down. Thermal Shutdown TJ > +160°C Exited by POR or cycling ON1 and ON2. DL1 and DL2 remain low. 22 ______________________________________________________________________________________ Dual and Combinable Graphics Core Controller for Notebook Computers Design Procedure Firmly establish the input voltage range and maximum load current before choosing a switching frequency and inductor operating point (ripple-current ratio). The primary design trade-off lies in choosing a good switching frequency and inductor operating point, and the following four factors dictate the rest of the design: • Input Voltage Range. The maximum value (VIN(MAX)) must accommodate the worst-case, high AC-adapter voltage. The minimum value (VIN(MIN)) must account for the lowest battery voltage after drops due to connectors, fuses, and battery selector switches. If there is a choice at all, lower input voltages result in better efficiency. • Maximum Load Current. There are two values to consider. The peak load current (I LOAD(MAX) ) determines the instantaneous component stresses and filtering requirements and thus drives output capacitor selection, inductor saturation rating, and the design of the current-limit circuit. The continuous load current (ILOAD) determines the thermal stresses and thus drives the selection of input capacitors, MOSFETs, and other critical heat-contributing components. • Switching Frequency. This choice determines the basic trade-off between size and efficiency. The optimal frequency is largely a function of maximum input voltage, due to MOSFET switching losses that are proportional to frequency and VIN2. The optimum frequency is also a moving target, due to rapid improvements in MOSFET technology that are making higher frequencies more practical. • Inductor Operating Point. This choice provides trade-offs between size and efficiency and between transient response and output ripple. Low inductor values provide better transient response and smaller physical size, but also result in lower efficiency and higher output ripple due to increased ripple currents. The minimum practical inductor value is one that causes the circuit to operate at the edge of critical conduction (where the inductor current just touches zero with every cycle at maximum load). Inductor values lower than this grant no further sizereduction benefit. The optimum operating point is usually found between 20% and 30% ripple current. When pulse skipping (SKIP_ low and light loads), the inductor value also determines the load-current value at which PFM/PWM switchover occurs. Inductor Selection The per-phase switching frequency and inductor operating point determine the inductor value as follows: VOUT (VIN − VOUT ) L= VINfOSCILOAD(MAX)LIR For example: ILOAD(MAX) = 15A, VIN = 12V, VOUT = 1.5V, fOSC = 300kHz, 30% ripple current or LIR = 0.3: L= 1.8V × (12V − 1.8V ) 12V × 300kHz × 15A × 0.3 = 0.97μH Find a low-loss inductor having the lowest possible DC resistance that fits in the allotted dimensions. For the selected inductance value, the actual peak-to-peak inductor ripple current (ΔIINDUCTOR) is defined by: ΔIINDUCTOR = VOUT (VIN − VOUT ) VINfOSCL Ferrite cores are often the best choice, although powdered iron is inexpensive and can work well at 200kHz. The core must be large enough not to saturate at the peak inductor current (IPEAK): IPEAK = ILOAD(MAX) + ΔIINDUCTOR 2 Transient Response The inductor ripple current also impacts transientresponse performance, especially at low VIN - VOUT differentials. Low inductor values allow the inductor current to slew faster, replenishing charge removed from the output filter capacitors by a sudden load step. The total output voltage sag is the sum of the voltage sag while the inductor is ramping up, and the voltage sag before the next pulse can occur: VSAG = L( ΔILOAD(MAX) ) 2 2COUT (VIN × DMAX − VOUT ) + ΔILOAD(MAX) (T − ΔT) COUT where D MAX is the maximum duty factor (see the Electrical Characteristics), T is the switching period (1 / f OSC), and ΔT equals V OUT / V IN x T when in PWM mode, or L x 0.2 x IMAX / (VIN - VOUT) when in skip ______________________________________________________________________________________ 23 MAX8775 Thermal-Fault Protection The MAX8775 features a thermal-fault protection circuit. When the junction temperature rises above +160°C, a thermal sensor sets the fault latches, pulls PGOOD_ low, and shuts down both SMPS controllers using the soft-shutdown sequence (see the Soft-Start and SoftShutdown section). Cycle VCC below 1V or toggle ON1 and ON2 to clear the fault latches and restart the controllers after the junction temperature cools by 15°C. MAX8775 Dual and Combinable Graphics Core Controller for Notebook Computers mode. The amount of overshoot during a full-load to noload transient due to stored inductor energy can be calculated as: VSOAR ≈ The current-sense method (Figure 10) and magnitude determine the achievable current-limit accuracy and power loss. The sense resistor can be determined by: RSENSE_ = VLIM_ / ILIMIT_ (ΔILOAD(MAX) )2L For the best current-sense accuracy and overcurrent protection, use a 1% tolerance current-sense resistor between the inductor and output as shown in Figure 10a. This configuration constantly monitors the inductor current, allowing accurate current-limit protection. However, the parasitic inductance of the current-sense resistor can cause current-limit inaccuracies, especially when using low-value inductors and current-sense resistors. This parasitic inductance (LESL) can be cancelled by adding an RC circuit across the sense resistor with an equivalent time constant: L CEQREQ = ESL RSENSE 2NPHCOUT VOUT where NPH is 2 in combined mode when both phases are active. Setting the Current Limit The minimum current-limit threshold must be great enough to support the maximum load current when the current limit is at the minimum tolerance value. The perphase peak inductor current occurs at ILOAD(MAX) plus half the ripple current; therefore: ILIMIT > ILOAD(MAX) ⎛ ΔIINDUCTOR ⎞ +⎜ ⎟ ⎝ ⎠ NPH 2 Alternatively, low-cost applications that do not require highly accurate current-limit protection may reduce the overall power dissipation by connecting a series RC circuit across the inductor (Figure 10b) with an equivalent time constant: where NPH is 2 in combined mode, and ILIMIT equals the minimum current-limit threshold voltage divided by the current-sense resistance (RSENSE_). For the 30mV default setting, the minimum current-limit threshold is 26mV. INPUT (VIN) DH_ NH CIN SENSE RESISTOR LESL L RSENSE CEQREQ = LX_ MAX8775 DL_ NL COUT CEQ REQ DL LESL RSENSE PGND CSH_ CSL_ a) OUTPUT SERIES RESISTOR SENSING INPUT (VIN) DH_ NH CIN INDUCTOR L RDCR RCS = LX_ MAX8775 DL_ NL PGND DL R1 R2 CEQ R2 = R DCR R1 + R2 COUT L RDCR = C EQ [ R11 + R21 ] CSH_ CSL_ b) LOSSLESS INDUCTOR SENSING Figure 10. Current-Sense Configurations 24 ______________________________________________________________________________________ Dual and Combinable Graphics Core Controller for Notebook Computers and: RDCR = L 1⎤ ⎡1 ×⎢ + CEQ ⎣ R1 R2 ⎥⎦ where RCS is the required current-sense resistance, and RDCR is the inductor’s series DC resistance. Use the worst-case inductance and RDCR values provided by the inductor manufacturer, adding some margin for the inductance drop over temperature and load. Output Capacitor Selection The output filter capacitor must have low enough equivalent series resistance (ESR) to meet output ripple and load-transient requirements, yet have high enough ESR to satisfy stability requirements. The output capacitance must be high enough to absorb the inductor energy while transitioning from full-load to no-load conditions without tripping the overvoltage fault protection. When using high-capacitance, low-ESR capacitors (see stability requirements), the filter capacitor’s ESR dominates the output voltage ripple. Therefore, the output capacitor’s size depends on the maximum ESR required to meet the output voltage ripple (VRIPPLE(P-P)) specifications: VRIPPLE(P−P) = RESRILOAD(MAX)LIR In Idle Mode, the inductor current becomes discontinuous, with peak currents set by the Idle Mode current-sense threshold (VIDLE = 0.2VLIMIT). In Idle Mode, the no-load output ripple can be determined as follows: V R VRIPPLE(P−P) = IDLE ESR RSENSE The actual capacitance value required relates to the physical size needed to achieve low ESR, as well as to the chemistry of the capacitor technology. Thus, the capacitor is usually selected by ESR and voltage rating rather than by capacitance value (this is true of tantalums, OS-CONs, polymers, and other electrolytics). When using low-capacity filter capacitors, such as ceramic capacitors, size is usually determined by the capacity needed to prevent V SAG and V SOAR from causing problems during load transients. Generally, once enough capacitance is added to meet the overshoot requirement, undershoot at the rising load edge is no longer a problem (see the VSAG and VSOAR equations in the Transient Response section). However, lowcapacity filter capacitors typically have high ESR zeros that may affect the overall stability (see the Output Capacitor Stability Considerations section). Output Capacitor Stability Considerations Stability is determined by the value of the output zero relative to the switching frequency. The boundary of instability is given by the following equation: f RESR < 2RSENSE and fESR ≤ SW π where: fESR = 1 (2πRESR + 4RSENSE )COUT For a typical 300kHz application, the output zero frequency must be well below 95kHz, preferably below 50kHz. Tantalum and OS-CON capacitors in widespread use at the time of publication have typical ESR zero frequencies of 25kHz. In the design example used for inductor selection, the ESR needed to support 25mV P-P ripple is 25mV/1.5A = 16.7mΩ. One 330µF/2.5V Sanyo polymer (TPE) capacitor provides 7mΩ (max) ESR. Together with the 1.5mΩ currentsense resistors, the output zero is 25kHz, zero is 25kHz, well within the bounds of stability. The MAX8775 is optimized for low-duty-cycle operations. Steady-state operation at 45% duty cycle or higher is not recommended. The easiest method for checking stability is to apply a very fast zero-to-max load transient and carefully observe the output voltage ripple envelope for overshoot and ringing. It can help to simultaneously monitor the inductor current with an AC current probe. Do not allow more than one cycle of ringing after the initial step-response under/overshoot. Input Capacitor Selection The input capacitor must meet the RMS ripple current requirement (IRMS) imposed by the switching currents. For a single step-down converter, the RMS input ripple current is defined by the output load current (IOUT), input voltage, and output voltage, with the worst-case condition occurring at VIN = 2VOUT: IRMS = IOUT VOUT (VIN − VOUT ) VIN For a dual +180° interleaved controller, the out-ofphase operation reduces the RMS input ripple current, effectively lowering the input capacitance requirements. When both outputs operate with a duty cycle less than 50% (VIN > 2VOUT), the RMS input ripple current is defined by the following equation: ⎛V ⎞ ⎛V ⎞ IRMS = ⎜ OUT1 ⎟ IOUT1(IOUT1 − IIN ) + ⎜ OUT2 ⎟ IOUT2 (IOUT2 − IIN ) ⎝ VIN ⎠ ⎝ VIN ⎠ ______________________________________________________________________________________ 25 MAX8775 R2 RCS = RDCR R1+ R2 MAX8775 Dual and Combinable Graphics Core Controller for Notebook Computers where IIN is the average input current: ⎛V ⎞ ⎛V ⎞ IIN = ⎜ OUT1 ⎟ IOUT1 + ⎜ OUT2 ⎟ IOUT2 ⎝ VIN ⎠ ⎝ VIN ⎠ In combined mode (REFIN2 = VCC) with both phases active, the input RMS current simplifies to: ⎛V ⎞⎛ 1 V ⎞ IRMS = IOUT ⎜ OUT ⎟ ⎜ − OUT ⎟ ⎝ VIN ⎠ ⎝ 2 VIN ⎠ For most applications, nontantalum chemistries (ceramic, aluminum, or OS-CON) are preferred due to their resistance to power-up surge currents typical of systems with a mechanical switch or connector in series with the input. Choose a capacitor that has less than 10°C temperature rise at the RMS input current for optimal reliability and lifetime. Power-MOSFET Selection Most of the following MOSFET guidelines focus on the challenge of obtaining high load-current capability when using high-voltage (> 20V) AC adapters. Lowcurrent applications usually require less attention. The high-side MOSFET (NH) must be able to dissipate the resistive losses plus the switching losses at both VIN(MIN) and VIN(MAX). Ideally, the losses at VIN(MIN) should be roughly equal to the losses at VIN(MAX), with lower losses in between. If the losses at VIN(MIN) are significantly higher, consider increasing the size of NH. Conversely, if the losses at VIN(MAX) are significantly higher, consider reducing the size of NH. If VIN does not vary over a wide range, optimum efficiency is achieved by selecting a high-side MOSFET (NH) that has conduction losses equal to the switching losses. Choose a low-side MOSFET (NL) that has the lowest possible on-resistance (RDS(ON)), comes in a moderatesized package (i.e., 8-pin SO, DPAK, or D2PAK), and is reasonably priced. Ensure that the MAX8775 DL_ gate driver can supply sufficient current to support the gate charge and the current injected into the parasitic drainto-gate capacitor caused by the high-side MOSFET turning on; otherwise, cross-conduction problems can occur. Switching losses are not an issue for the low-side MOSFET since it is a zero-voltage switched device when used in the step-down topology. Power-MOSFET Dissipation Worst-case conduction losses occur at the duty factor extremes. For the high-side MOSFET (NH), the worstcase power dissipation due to resistance occurs at minimum input voltage: 26 ⎛V ⎞ PD (NH Resistive) = ⎜ OUT ⎟ (ILOAD )2RDS(ON) ⎝ VIN ⎠ Generally, use a small high-side MOSFET to reduce switching losses at high input voltages. However, the RDS(ON) required to stay within package power-dissipation limits often limits how small the MOSFET can be. The optimum occurs when the switching losses equal the conduction (RDS(ON)) losses. High-side switching losses do not become an issue until the input is greater than approximately 15V. Calculating the power dissipation in high-side MOSFETs (NH) due to switching losses is difficult, since it must allow for difficult-to-quantify factors that influence the turn-on and turn-off times. These factors include the internal gate resistance, gate charge, threshold voltage, source inductance, and PCB layout characteristics. The following switching loss calculation provides only a very rough estimate and is no substitute for breadboard evaluation, preferably including verification using a thermocouple mounted on NH: ⎛ VIN(MAX)ILOADfSW ⎞ ⎛ QG(SW) ⎞ ⎟⎜ ⎟ PD (NH Switching) = ⎜⎝ IGATE ⎠ ⎝ IGATE ⎠ + COSSVIN(MAX)2fSW 2 where CRSS is the reverse transfer capacitance of NH, and IGATE is the peak gate-drive source/sink current (1A typ). Switching losses in the high-side MOSFET can become a heat problem when maximum AC adapter voltages are applied, due to the squared term in the switchingloss equation (C x VIN2 x fSW). If the high-side MOSFET chosen for adequate RDS(ON) at low battery voltages becomes extraordinarily hot when subjected to V IN(MAX) , consider choosing another MOSFET with lower parasitic capacitance. For the low-side MOSFET (NL), the worst-case power dissipation always occurs at maximum battery voltage: ⎡ ⎛ V ⎞⎤ 2 PD (NL Resistive) = ⎢1− ⎜ OUT ⎟ ⎥(ILOAD ) RDS(ON) V ⎢⎣ ⎝ IN(MAX) ⎠ ⎥⎦ The absolute worst case for MOSFET power dissipation occurs under heavy overload conditions that are greater than ILOAD(MAX), but are not high enough to exceed the current limit and cause the fault latch to trip. To protect against this possibility, “overdesign” the circuit to tolerate: ______________________________________________________________________________________ Dual and Combinable Graphics Core Controller for Notebook Computers where ILIMIT is the peak current allowed by the currentlimit circuit, including threshold tolerance and senseresistance variation. The MOSFETs must have a relatively large heatsink to handle the overload power dissipation. Choose a Schottky diode (DL) with a forward voltage drop low enough to prevent the low-side MOSFET’s body diode from turning on during the dead time. Boost Capacitors The boost capacitors (CBST) must be selected large enough to handle the gate charging requirements of the high-side MOSFETs. Typically, 0.1µF ceramic capacitors work well for low-power applications driving medium-sized MOSFETs. However, high-current applications driving large, high-side MOSFETs require boost capacitors larger than 0.1µF. For these applications, select the boost capacitors to avoid discharging the capacitor more than 200mV while charging the highside MOSFETs’ gates: CBST = QGATE 200mV where QGATE is the total gate charge specified in the high-side MOSFETs’ data sheet. For example, assume the SI7634DP n-channel MOSFET is used on the high side. According to the manufacturer’s data sheet, a single SI7634DP has a gate charge of 21nC (VGS = 5V). Using the above equation, the required boost capacitance would be: CBST = 13nC = 0.105μF 200mV Selecting the closest standard value, this example requires a 0.1µF ceramic capacitor. Applications Information Duty-Cycle Limits Minimum Input Voltage The minimum input operating voltage (dropout voltage) is restricted by the maximum duty-cycle specification (see the Electrical Characteristics table). However, keep in mind that the transient performance gets worse as the step-down regulators approach the dropout voltage, so bulk output capacitance must be added (see the voltage sag and soar equations in the Design Procedure section). The absolute point of dropout occurs when the inductor current ramps down during the off-time (ΔIDOWN) as much as it ramps up during the on-time (ΔIUP). This results in a minimum operating voltage defined by the following equation: ⎛ 1 ⎞ VIN(MIN) = VOUT + VCHG + h⎜ − 1⎟ (VOUT + VDIS ) ⎝ DMAX ⎠ where VCHG and VDIS are the parasitic voltage drops in the charge and discharge paths, respectively. A reasonable minimum value for h is 1.5, while the absolute minimum input voltage is calculated with h = 1. Maximum Input Voltage The MAX8775 controller includes a minimum on-time specification, which determines the maximum input operating voltage that maintains the selected switching frequency (see the Electrical Characteristics table). Operation above this maximum input voltage results in pulse-skipping operation, regardless of the operating mode selected by SKIP_. At the beginning of each cycle, if the output voltage is still above the feedback threshold voltage, the controller does not trigger an ontime pulse, effectively skipping a cycle. This allows the controller to maintain regulation above the maximum input voltage, but forces the controller to effectively operate with a lower switching frequency. This results in an input threshold voltage at which the controller begins to skip pulses (VIN(SKIP)): ⎛ ⎞ 1 VIN(SKIP) = VOUT ⎜ ⎟ ⎝ fOSCt ON(MIN) ⎠ where fOSC is the switching frequency selected by OSC. PCB Layout Guidelines Careful PCB layout is critical to achieving low switching losses and clean, stable operation. The switching power stage requires particular attention (Figure 11). If possible, mount all the power components on the top side of the board, with their ground terminals flush against one another. Follow these guidelines for good PCB layout: • Keep the high-current paths short, especially at the ground terminals. This practice is essential for stable, jitter-free operation. • Keep the power traces and load connections short. This practice is essential for high efficiency. Using thick copper PCB (2oz vs. 1oz) can enhance fullload efficiency by 1% or more. Correctly routing PCB traces is a difficult task that must be approached in terms of fractions of centimeters, ______________________________________________________________________________________ 27 MAX8775 ⎛ ΔI ⎞ ILOAD = ILIMIT − ⎜ INDUCTOR ⎟ ⎝ ⎠ 2 MAX8775 Dual and Combinable Graphics Core Controller for Notebook Computers where a single mΩ of excess trace resistance causes a measurable efficiency penalty. • Minimize current-sensing errors by connecting CSH_ and CSL_ directly across the current-sense resistor (RSENSE_). • When trade-offs in trace lengths must be made, it is preferable to allow the inductor charging path to be made longer than the discharge path. For example, it is better to allow some extra distance between the input capacitors and the high-side MOSFET than to allow distance between the inductor and the lowside MOSFET or between the inductor and the output filter capacitor. 2) Mount the controller IC adjacent to the low-side MOSFET, preferably on the back side opposite NL_ and NH_ to keep LX_, GND, DH_, and the DL_ gatedrive lines short and wide. The DL_ and DH_ gate traces must be short and wide (50 mils to 100 mils wide if the MOSFET is 1in from the controller IC) to keep the driver impedance low and for proper adaptive dead-time sensing. 3) Group the gate-drive components (BST_ capacitor, VDD bypass capacitor) together near the controller IC. Layout Procedure 4) Make the DC-DC controller ground connections as shown in Figures 1, 2, and 11. This diagram can be viewed as having two separate ground planes: power ground, where all the high-power components go; and an analog ground plane for sensitive analog components. The analog ground plane and power ground plane must meet only at a single point directly at the IC. 1) Place the power components first, with ground terminals adjacent (NL_ source, CIN, COUT_, and DL_ anode). If possible, make all these connections on the top layer with wide, copper-filled areas. 5) Connect the output power planes directly to the output filter capacitor positive and negative terminals with multiple vias. Place the entire DC-DC converter circuit as close to the load as is practical. • Route high-speed switching nodes (BST_, LX_, DH_, and DL_) away from sensitive analog areas (REF, REFIN_, CSH_, CSL_). 28 ______________________________________________________________________________________ Dual and Combinable Graphics Core Controller for Notebook Computers MAX8775 KELVIN SENSE VIAS UNDER THE SENSE RESISTOR (SEE EVALUATION KIT) KELVIN SENSE VIAS UNDER THE SENSE RESISTOR (SEE EVALUATION KIT) RSENSE OUTPUT 2 RSENSE OUTPUT 1 INDUCTOR COUT COUT COUT COUT INDUCTOR POWER GROUND CIN CIN INPUT PHASE 1 PHASE 2 CONNECT GND AND PGND THE CONTROLLER AT ONE POINT ONLY AS SHOWN VIA TO POWER GROUND CONNECT THE EXPOSED PAD TO ANALOG GND VCC BYPASS CAPACITOR REF BYPASS CAPACITOR VIA TO ANALOG GROUND Figure 11. PCB Layout Chip Information TRANSISTOR COUNT: 6372 PROCESS: BiCMOS ______________________________________________________________________________________ 29 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) QFN THIN.EPS MAX8775 Dual and Combinable Graphics Core Controller for Notebook Computers Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 30 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2006 Maxim Integrated Products is a registered trademark of Maxim Integrated Products. Inc.