MAX9152ESE+T

19-2003; Rev 0; 4/01 800Mbps LVDS/LVPECL-to-LVDS 2 x 2 Crosspoint Switch The MAX9152 can be programmed to connect any input to either or both outputs, allowing it to be used in the following configurations: 2 ✕ 2 crosspoint switch, 2:1 mux, 1:2 demux, 1:2 splitter, or dual repeater. This flexibility makes the MAX9152 ideal for protection switching in fault-tolerant systems, loopback switching for diagnostics, fanout buffering for clock/data distribution, and signal regeneration for communication over extended distances. Ultra-low 120psPK-PK (max) PRBS jitter ensures reliable communications in high-speed links that are highly sensitive to timing error, especially those incorporating clock-and-data recovery, or serializers and deserializers. The high-speed switching performance guarantees an 800Mbps data rate and less than 50ps (max) skew between channels. LVDS inputs and outputs are compatible with the TIA/EIA-644 LVDS standard. The LVDS inputs are designed to also accept LVPECL signals directly, and PECL signals with an attenuation network. The LVDS outputs are designed to drive 75Ω or 100Ω loads, and feature a selectable differential output resistance to minimize reflections. The MAX9152 is available in 16-pin TSSOP and SO packages, and consumes only 109mW while operating from a single +3.3V supply over the -40°C to +85°C temperature range. Features ♦ Pin-Programmable Configuration 2 x 2 Crosspoint Switch 2:1 Mux 1:2 Demux 1:2 Splitter Dual Repeater ♦ Ultra-Low 120psPK-PK (max) Jitter with 800Mbps, PRBS = 223 -1 Data Pattern ♦ Low 50ps (max) Channel-to-Channel Skew ♦ 109mW Power Dissipation ♦ Compatible with ANSI TIA/EIA-644 LVDS Standard ♦ Inputs Accept LVDS/LVPECL Signals ♦ LVDS Output Rated for 75Ω and 100Ω Loads ♦ Pin-Programmable Differential Output Resistance ♦ Pin-Compatible Upgrade to DS90CP22 (SO Package) ♦ Available in 16-Pin TSSOP Package (Half the Size of SO) Ordering Information PART MAX9152ESE MAX9152EUE PIN-PACKAGE 16 SO 16 TSSOP Pin Configuration appears at end of data sheet. Functional Diagram OUT0+ Applications Cell Phone Base Stations Add/Drop Muxes Digital Crossconnects DSLAMs Network Switches/Routers Protection Switching Loopback Diagnostics Clock/Data Distribution Cable Repeaters TEMP. RANGE -40°C to +85°C -40°C to +85°C OUT0- OUT1+ OUT1- MAX9152 EN0 SEL0 EN1 0 1 0 1 SEL1 IN0+ IN0IN1+ IN1- ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX9152 General Description The MAX9152 2 x 2 crosspoint switch is designed for applications requiring high speed, low power, and lownoise signal distribution. This device includes two LVDS/LVPECL inputs, two LVDS outputs, and two logic inputs that set the internal connections between differential inputs and outputs. MAX9152 800Mbps LVDS/LVPECL-to-LVDS 2 x 2 Crosspoint Switch ABSOLUTE MAXIMUM RATINGS Storage Temperature Range .............................-65°C to +150°C Junction Temperature ......................................................+150°C Operating Temperature Range ...........................-40°C to +85°C Lead Temperature (soldering, 10s) .................................+300°C ESD Protection Human Body Model, IN_+, IN_-, OUT_+, OUT_-........... ±7kV VCC to GND ...........................................................-0.3V to +4.0V IN_+, IN_-, OUT_+, OUT_- to GND .......................-0.3V to +4.0V EN_, SEL_, NC/RSEL to GND.....................-0.3V to (VCC + 0.3V) Short-Circuit Duration (OUT_+, OUT_-) .....................Continuous Continuous Power Dissipation (TA = +70°C) 16-Pin SO (derate 8.7mW/°C above +70°C)................696mW 16-Pin TSSOP (derate 9.4mW/°C above +70°C) .........755mW Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +3.6V, NC/RSEL = open for RL = 75Ω ±1%, NC/RSEL = high for RL = 100Ω ±1%, differential input voltage |VID| = 0.1V to VCC, input voltage (VIN+, VIN-) = 0 to VCC, EN_ = high, SEL0 = low, SEL1 = high, and TA = -40°C to +85°C. Typical values at VCC = +3.3V, |VID| = 0.2V, input common-mode voltage VCM = 1.2V, TA = +25°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS LVCMOS/LVTTL INPUTS (EN_, SEL_) Input High Voltage VIH 2.0 VCC V Input Low Voltage VIL GND 0.8 V Input High Current IIH VIN = VCC or 2.0V 0 20 µA Input Low Current IIL VIN = 0 or 0.8V -10 10 µA 2.0 VCC V GND 0.8 V 0 20 µA -10 10 µA NC/RSEL INPUT Input High Voltage VIH Input Low Voltage VIL Input High Current IIH VIN = VCC or 2.0V Input Low Current IIL VIN = 0 or 0.8V DIFFERENTIAL INPUTS (IN_+, IN_-) Differential Input High Threshold VTH Differential Input Low Threshold VTL Input Current IIN+, IIN- 100 -100 mV mV VIN+ = VCC or 0, VIN- = VCC or 0 -1 1 V I N + = 3. 6 V o r 0 , V I N - = 3 . 6 V or 0 , V CC = 0 -1 1 µA LVDS OUTPUTS (OUT_+, OUT_-) Differential Output Impedance (Note 2) RDIFF Differential Output Voltage VOD Change in Magnitude of VOD Between Complementary Output States Offset Common-Mode Voltage Change in Magnitude of VOS Between Complementary Output States 2 ∆VOD VOS ∆VOS NC/RSEL = low or open 60 90 118 NC/RSEL = high 85 122 155 280 382 470 mV 25 mV RL = 75Ω, NC/RSEL = open, Figure 1 RL = 100Ω, NC/RSEL = high, Figure 1 Ω RL = 75Ω, NC/RSEL = open, Figure 1 RL = 100Ω, NC/RSEL = high, Figure 1 RL = 75Ω, NC/RSEL = open, Figure 1 RL = 100Ω, NC/RSEL = high, Figure 1 1.150 1.430 V 25 mV RL = 75Ω, NC/RSEL = open, Figure 1 RL = 100Ω, NC/RSEL = high, Figure 1 _______________________________________________________________________________________ 800Mbps LVDS/LVPECL-to-LVDS 2 x 2 Crosspoint Switch (VCC = +3.0V to +3.6V, NC/RSEL = open for RL = 75Ω ±1%, NC/RSEL = high for RL = 100Ω ±1%, differential input voltage |VID| = 0.1V to VCC, input voltage (VIN+, VIN-) = 0 to VCC, EN_ = high, SEL0 = low, SEL1 = high, and TA = -40°C to +85°C. Typical values at VCC = +3.3V, |VID| = 0.2V, input common-mode voltage VCM = 1.2V, TA = +25°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS -12 -20 mA -12 -20 mA VID = +100mV, VOUT_+ = 0, other output open Output Short-Circuit Current Both Output Short-Circuit Current Output High-Z Current Power-Off Output Current IOS IOSB VID = -100mV, VOUT_- = 0, other output open VID = +100mV, VOUT_+ = 0, VOUT_- = 0 VID = -100mV, VOUT_+ = 0, VOUT_- = 0 IOZ+, IOZ- Disabled, VOUT_+ = VCC or 0, VOUT_- = VCC or 0 -1 1 µA IOFF+, IOFF- VCC = 0, VOUT_+ = 3.6V or 0, VOUT_- = 3.6V or 0 -1 1 µA SUPPLY CURRENT Supply Current ICC High-Z Supply Current ICCZ RL = 75Ω, CL = 5pF, enabled, quiescent, Figure 5 38 55 RL = 100Ω, CL = 5pF, enabled, quiescent, Figure 5 33 50 RL = 75Ω, CL = 5pF, enabled, switching at 400MHz (800Mbps), Figure 5 (Note 2) 58 70 RL = 100Ω, CL = 5pF, enabled, switching at 400MHz (800Mbps), Figure 5 (Note 2) 52 65 Disabled 15 25 mA mA AC ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +3.6V, NC/RSEL = open for RL = 75Ω ±1%, NC/RSEL = high for RL = 100Ω ±1%, CL = 5pF, differential input voltage |VID| = 0.15V to VCC, EN_ = high, SEL0 = low, SEL1 = high, differential input transition time = 0.6ns (20% to 80%), input voltage (VIN+, VIN-) = 0 to VCC, LVCMOS/LVTTL inputs = 0 to 3V with 2ns (10% to 90%) transition times, TA = -40°C to +85°C. Typical values at VCC = +3.3V, |VID| = 0.2V, VCM = 1.2V, TA = +25°C, unless otherwise noted.) (Notes 3, 4) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input to SEL Setup Time (Note 5) tSET Figures 2, 3 0.4 ns Input to SEL Hold Time (Note 5) tHOLD Figures 2, 3 0.6 ns SEL to Switched Output tSWITCH Figures 2, 3 1.8 3.5 ns Disable Time High to Z tPHZ Figure 4 3.8 ns Disable Time Low to Z tPLZ Figure 4 3.8 ns Enable Time Z to High tPZH Figure 4 3.2 ns Enable Time Z to Low tPZL Figure 4 3.2 ns Propagation Low-to-High Delay tPLHD Propagation High-to-Low Delay tPHLD 2.5 Figures 5, 6 1.7 2.3 3.4 VCC = +3.3V, TA = +25°C; Figures 5, 6 2.0 2.3 2.9 Figures 5, 6 1.7 2.3 3.4 VCC = +3.3V, TA = +25°C; Figures 5, 6 2.0 2.3 2.9 ns ns _______________________________________________________________________________________ 3 MAX9152 DC ELECTRICAL CHARACTERISTICS (continued) AC ELECTRICAL CHARACTERISTICS (continued) (VCC = +3.0V to +3.6V, NC/RSEL = open for RL = 75Ω ±1%, NC/RSEL = high for RL = 100Ω ±1%, CL = 5pF, differential input voltage |VID| = 0.15V to VCC, EN_ = high, SEL0 = low, SEL1 = high, differential input transition time = 0.6ns (20% to 80%), input voltage (VIN+, VIN-) = 0 to VCC, LVCMOS/LVTTL inputs = 0 to 3V with 2ns (10% to 90%) transition times, TA = -40°C to +85°C. Typical values at VCC = +3.3V, |VID| = 0.2V, VCM = 1.2V, TA = +25°C, unless otherwise noted.) (Notes 3, 4) PARAMETER SYMBOL Pulse Skew |tPLHD -tPHLD| (Note 6) tSKEW Output Channel-to-Channel Skew tCCS Output Low-to-High Transition Time (20% to 80%) tLHT Figures 5, 6 Output High-to-Low Transition Time (20% to 80%) tHLT Figures 5, 6 LVDS Data Path Peak-to-Peak Jitter (Note 7) CONDITIONS tJIT MIN TYP MAX UNITS Figures 5, 6 25 90 ps Figures 5, 7 20 50 ps 160 270 480 ps 160 270 480 ps VID = 200mV, VCM = 1.2V, 50% duty cycle, 800Mbps, input transition time = 600ps (20% to 80%) 10 30 VID = 200mV, VCM = 1.2V, PRBS = 223 - 1 data pattern, 800Mbps, input transition time = 600ps (20% to 80%) 65 ps 120 Note 1: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground except VTH, VTL, VID, VOD, and ∆VOD. Note 2: Guaranteed by design and characterization, not production tested. Note 3: AC parameters are guaranteed by design and characterization. Note 4: CL includes scope probe and test jig capacitance. Note 5: tSET and tHOLD time specify that data must be in a stable state before and after the SEL transition. Note 6: tSKEW is the magnitude difference of differential propagation delay over rated conditions; tSKEW = |tPHLD - tPLHD|. Note 7: Specification includes test equipment jitter. Typical Operating Characteristics (VCC = +3.3V, RL = 100Ω, NC/RSEL = high, CL= 5pF, input transition time = 600ps (20% to 80%), VID = 200mV, PRBS = 223 - 1 data pattern, VCM = +1.2V, TA = +25°C, unless otherwise noted.) DIFFERENTIAL OUTPUT VOLTAGE vs. LOAD 450 NC/RSEL = HIGH 350 250 4 38 36 34 32 150 CONDITIONS: 3.3V, PRBS = 223 -1 DATA PATTERN, |VID| = 200mV, VCM = +1.2V HORIZONTAL SCALE = 200ps/div VERTICAL SCALE = 100mV/div MAX9152 toc03 NC/RSEL = LOW OR OPEN 550 SUPPLY CURRENT vs. DATA RATE 40 MAX9152 toc02 DIFFERENTIAL OUTPUT VOLTAGE (mV) 650 SUPPLY CURRENT (mA) DIFFERENTIAL OUTPUT EYE PATTERN IN 1:2 SPLITTER MODE AT 800Mbps MAX9152 toc01 MAX9152 800Mbps LVDS/LVPECL-to-LVDS 2 x 2 Crosspoint Switch 30 50 75 100 125 150 LOAD RESISTOR (Ω) 175 200 100 200 300 400 500 600 DATA RATE (Mbps) _______________________________________________________________________________________ 700 800 800Mbps LVDS/LVPECL-to-LVDS 2 x 2 Crosspoint Switch VID = 0.2V VID = 0.8V 40 70 80 PEAK-TO-PEAK JITTER (ps) PEAK-TO-PEAK JITTER (ps) 60 90 MAX9152 toc05 80 MAX9152 toc04 70 VID = 0.2V 60 50 VID = 0.8V 40 300 400 500 600 700 800 100 200 DATA RATE (Mbps) 300 50 400 500 600 700 100 800 200 300 PEAK-TO-PEAK OUTPUT JITTER AT VCM = +0.4V vs. DATA RATE 600 700 800 PEAK-TO-PEAK OUTPUT JITTER AT VCM = +1.6V vs. DATA RATE 80 PEAK-TO-PEAK JITTER (ps) 70 500 VID = 0.4V 60 VID = 0.2V 50 40 MAX9152 toc08 80 400 DATA RATE (Mbps) DATA RATE (Mbps) MAX9152 toc07 200 60 30 30 100 VID = 0.2V VID = 0.8V VID = 0.4V VID = 0.4V 30 70 40 VID = 0.4V PEAK-TO-PEAK JITTER (ps) PEAK-TO-PEAK JITTER (ps) 80 50 PEAK-TO-PEAK OUTPUT JITTER AT VCM = +3.3V - (VID/2) vs. DATA RATE PEAK-TO-PEAK OUTPUT JITTER AT VCM = +1.2V vs. DATA RATE MAX9152 toc06 PEAK-TO-PEAK OUTPUT JITTER AT VCM = VID/2 vs. DATA RATE 70 60 VID = 0.8V VID = 0.4V 50 40 VID = 0.2V VID = 0.8V 30 30 100 200 300 400 500 600 DATA RATE (Mbps) 700 800 100 200 300 400 500 600 700 800 DATA RATE (Mbps) _______________________________________________________________________________________ 5 MAX9152 Typical Operating Characteristics (continued) (VCC = +3.3V, RL = 100Ω, NC/RSEL = high, CL= 5pF, input transition time = 600ps (20% to 80%), VID = 200mV, PRBS = 223 - 1 data pattern, VCM = +1.2V, TA = +25°C, unless otherwise noted.) 800Mbps LVDS/LVPECL-to-LVDS 2 x 2 Crosspoint Switch MAX9152 Pin Description PIN NAME 1, 2 SEL1, SEL0 LVCMOS/LVTTL Logic Inputs. Allow the switch to be configured as a mux, repeater, or splitter. 3, 4 IN0+, IN0- LVDS/LVPECL Differential Input 0 5 VCC 6, 7 IN1+, IN1- LVDS/LVPECL Differential Input 1 8 NC/RSEL Logic Input. Selects differential output resistance. Set NC/RSEL to open or low when RL = 75Ω, set to high when RL = 100Ω. 9 NC 10, 11 OUT1-, OUT1+ 12 GND 13, 14 OUT0-, OUT0+ 15, 16 EN1, EN0 FUNCTION Power-Supply Input. Bypass VCC to GND with 0.1µF and 0.001µF ceramic capacitors. No Connect LVDS Differential Output 1 Ground LVDS Differential Output 0 LVCMOS/LVTTL Logic Inputs. Enables or disables the outputs. Setting EN0 or EN1 high enables the corresponding output, OUT0 or OUT1. Setting EN0 or EN1 low puts the corresponding output into high impedance (differential output resistance is also high impedance). Detailed Description The LVDS interface standard is a signaling method intended for point-to-point communication over a controlled impedance medium as defined by the ANSI TIA/EIA-644 and IEEE 1596.3 standards. LVDS uses a lower voltage swing than other common communication standards, achieving higher data rates with reduced power consumption while reducing EMI emissions and system susceptibility to noise. The MAX9152 is an 800Mbps 2 x 2 crosspoint switch designed for high-speed, low-power point-to-point and multidrop interfaces. The device accepts LVDS or differential LVPECL signals and routes them to outputs depending on the selected mode of operation. A differential input with a magnitude of 0.1V to VCC with single-ended voltage levels at or within the MAX9152's VCC and ground switches the output. A differential input with a magnitude of at least 0.15V with single-ended voltage levels at or within the MAX9152's VCC and ground is required to meet the AC specifications. In the 1:2 splitter mode, the outputs repeat the selected input. This is useful for distributing a signal or creating a copy for use in protection switching. In the repeater 6 1/2 MAX9152 OUT_+ RL/2 IN_+ VOS VOD IN_RL/2 ENABLED VID = (VIN_+) - (VIN_-) OUT_∆VOD = VOD - VOD* ∆VOS = VOS - VOS* VOD AND VOS ARE MEASURED WITH VID = +100mV. VOD* AND VOS* ARE MEASURED WITH VID = -100mV. Figure 1. Test Circuit for VOD and VOS mode, the device operates as a two-channel buffer. Repeating restores signal amplitude, allowing isolation of media segments or longer media drive. The device is a crosspoint switch where any input can be connected to any output or outputs. In 2:1 mux mode, primary and backup signals can be selected to provide a protection-switched, fault-tolerant application. _______________________________________________________________________________________ 800Mbps LVDS/LVPECL-to-LVDS 2 x 2 Crosspoint Switch MAX9152 IN0+ VID = 0 IN0IN1VID = 0 IN1+ 1.5V SEL_ tSET tHOLD OUT_+ IN0 IN1 OUT_tSWITCH EN0 = EN1 = HIGH VID = (VIN_+) − (VIN_-) Figure 2. Input to Rising Edge Select Setup, Hold, and Mux Switch Timing Diagram IN0+ VID = 0 IN0IN1VID = 0 IN1+ SEL_ 1.5V tSET tHOLD OUT_IN1 IN0 OUT_+ tSWITCH EN0 = EN1 = HIGH VID = (VIN_+) − (VIN_-) Figure 3. Input to Falling Edge Select Setup, Hold, and Mux Switch Timing Diagram Input Fail-Safe The differential inputs of the MAX9152 do not have internal fail-safe biasing. If fail-safe biasing is required, it can be implemented with external large-value resistors. IN_+ should be pulled up to VCC with 10kΩ and IN_ should be pulled down to GND with 10kΩ. The voltage-divider formed by the 10kΩ resistors and the 100Ω termination resistor (across IN_+ and IN_-) provides a slight positive differential bias and sets a high state at the device output when inputs are undriven. Output Resistance The MAX9152 has a selectable differential output resistance to reduce reflections from impedance discontinuities in the interconnect. Reflections are reduced, compared to a high-impedance output. A termination resistor at the receiver is still required and is the primary termination for the interconnect. Select the output resistance that best matches the differential characteristic impedance of the interconnect used. Select Function The SEL0 and SEL1 logic inputs allow the device to be configured as a high-speed differential crosspoint, 2:1 mux, 1:2 demux, dual repeater, or 1:2 splitter (Figure 8). See Table 1 for mode selection settings. Enable Function The EN0 and EN1 logic inputs enable and disable driver outputs OUT0 and OUT1. Setting EN0 or EN1 high enables the corresponding driver output. Setting EN0 _______________________________________________________________________________________ 7 MAX9152 800Mbps LVDS/LVPECL-to-LVDS 2 x 2 Crosspoint Switch or EN1 low puts the corresponding driver output into a high-impedance state (the differential output resistance also becomes high impedance). Table 1. Input/Output Function Table OUT_+ CL SEL0 SEL1 OUT0 OUT1 MODE L L IN0 IN0 1:2 splitter L H IN0 IN1 Repeater H L IN1 IN0 Switch H H IN1 IN1 1:2 splitter Applications Information RL/2 IN_+ Unused Differential Inputs IN_PULSE GENERATOR +1.2V Unused differential inputs should be tied to ground and VCC to prevent the high-speed input stage from switching due to noise. IN_+ should be pulled to VCC with 10kΩ and IN_- should be pulled to GND with 10kΩ. RL/2 EN_ 1/2 MAX9152 50Ω CL OUT_- Expanding the Number of LVDS Output Ports VID = (VIN_+)–(VIN_-) Devices can be cascaded to make larger switches. Total propagation delay and total jitter should be considered to determine the maximum allowable switch size. Three MAX9152s are needed to make a 2 input x 4 output crosspoint switch with two device propagation delays. Seven MAX9152s make a 2 input x 8 output crosspoint with three device delays. 3V EN_ 1.5V 1.5V tPHZ tPZH 0 VOUT_ + WHEN VID = +100mV VOH VOUT_ - WHEN VID = -100mV 50% 50% 1.2V VOUT_ + WHEN VID = -100mV VOUT_ - WHEN VID = +100mV 50% 1.2V Accepting PECL Inputs VOL The inputs accept PECL signals with the use of an attenuation circuit, as shown in Figure 9. 50% tPLZ tPZL Power-Supply Bypassing Bypass VCC to ground with high-frequency surfacemount ceramic 0.1µF and 0.001µF capacitors in paral- Figure 4. Output Active to High-Z and High-Z to Active Test Circuit and Timing Diagram SEL0 IN0+ CL OUT0+ 0 IN0- RL 1 PULSE GENERATOR CL OUT0- MAX9152 50Ω CL 50Ω 0 OUT1+ RL IN1- CL 1 OUT1- IN1+ ENABLED SEL1 Figure 5. Output Transition Time, Propagation Delay, and Output Channel-to-Channel Skew Test Circuit 8 _______________________________________________________________________________________ 800Mbps LVDS/LVPECL-to-LVDS 2 x 2 Crosspoint Switch MAX9152 VIN_VID = 0 VIN_+ VID = 0 tPHLD tPLHD IN0 OUT0 IN1 OUT1 VOUT_VOD = 0 VOD = 0 VOUT_+ 80% 50% 20% +VOD 80% VOD = 0 50% tLHT VOD = 0 20% 2 x 2 CROSSPOINT -VOD IN0 tHLT OUT0 OR OUT1 VID = (VIN_+) - (VIN_-) IN1 VOD = (VOUT_+) - (VOUT_-) tPLHD AND tPHLD ARE MEASURED FOR ANY COMBINATION OF SEL0 AND SEL1. 2:1 MUX Figure 6. Output Transition Time and Propagation Delay Timing Diagram OUT0 IN0 OR IN1 VOUT0VOD = 0 VOD = 0 VOUT0+ tCCS tCCS VOD = 0 VOD = 0 OUT1 VOUT1- 1:2 DEMUX VOUT1+ VOD = (VOUT_+) - (VOUT_-) tCCS IS MEASURED WITH SEL0 = SEL1 = HIGH OR LOW (1:2 SPLITTER MODE) OUT0 IN0 OR IN1 OUT1 Figure 7. Output Channel-to-Channel Skew 1:2 SPLITTER lel as close to the device as possible, with the smaller value capacitor closest to VCC. Differential Traces Trace characteristics affect the performance of the MAX9152. Use controlled-impedance traces. Eliminate reflections and ensure that noise couples as common mode by running the differential trace pairs close together. Reduce skew by matching the electrical length of the traces. Excessive skew can result in a degradation of magnetic field cancellation. Maintain the distance between the differential traces to avoid discontinuities in differential impedance. Avoid 90° turns and minimize the number of vias to further prevent impedance discontinuities. Cables and Connectors Transmission media should have nominal differential impedance of 75Ω or 100Ω. Use cables and connectors that have matched differential impedance to minimize impedance discontinuities. IN0 OUT0 IN1 OUT1 DUAL REPEATER Figure 8. Programmable Configurations Avoid the use of unbalanced cables such as ribbon or simple coaxial cable. Balanced cables such as twisted pair offer superior signal quality and tend to generate less EMI due to canceling effects. Balanced cables tend to pick up noise as common mode, which is rejected by the differential receiver. Board Layout For LVDS applications, a four-layer printed-circuit (PC) board that provides separate power, ground, and signal planes is recommended. _______________________________________________________________________________________ 9 MAX9152 800Mbps LVDS/LVPECL-to-LVDS 2 x 2 Crosspoint Switch Chip Information 5V 82Ω 5V TRANSISTOR COUNT: 880 PROCESS: CMOS 82Ω 50Ω 10kΩ PECL 3.3V 50Ω 1/2 MAX9152 100Ω IN_+ IN_33Ω 33Ω Figure 9. PECL to LVDS Level Conversion Network Pin Configuration TOP VIEW SEL1 1 16 EN0 SEL0 2 15 EN1 INO+ 3 14 OUT0+ INO- 4 MAX9152 13 OUT0- VCC 5 12 GND IN1+ 6 11 OUT1+ IN1- 7 10 OUT1- NC/RSEL 8 9 NC SO/TSSOP 10 ______________________________________________________________________________________ 800Mbps LVDS/LVPECL-to-LVDS 2 x 2 Crosspoint Switch TSSOP.EPS ______________________________________________________________________________________ 11 MAX9152 Package Information 800Mbps LVDS/LVPECL-to-LVDS 2 x 2 Crosspoint Switch SOICN.EPS MAX9152 Package Information (continued) Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2001 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.