MAX9205EAI+TC9G

EVALUATION KIT AVAILABLE MAX9205/MAX9207 10-Bit Bus LVDS Serializers General Description The MAX9205/MAX9207 serializers transform 10-bitwide parallel LVCMOS/LVTTL data into a serial highspeed bus low-voltage differential signaling (LVDS) data stream. The serializers typically pair with deserializers like the MAX9206/MAX9208, which receive the serial output and transform it back to 10-bit-wide parallel data. The MAX9205/MAX9207 transmit serial data at speeds up to 400Mbps and 660Mbps, respectively, over PCB traces or twisted-pair cables. Since the clock is recovered from the serial data stream, clock-to-data and data-to-data skew that would be present with a parallel bus are eliminated. The serializers require no external components and few control signals. The input data strobe edge is selected by TCLK_R/F. PWRDN is used to save power when the devices are not in use. Upon power-up, a synchronization mode is activated, which is controlled by two SYNC inputs, SYNC1 and SYNC2. The MAX9205 can lock to a 16MHz to 40MHz system clock, while the MAX9207 can lock to a 40MHz to 66MHz system clock. The serializer output is held in high impedance until the device is fully locked to the local system clock, or when the device is in powerdown mode. Both the devices operate from a single +3.3V supply, are specified for operation from -40°C to +85°C, and are available in 28-pin SSOP packages. Features o Standalone Serializer (vs. SERDES) Ideal for Unidirectional Links o Framing Bits for Deserializer Resync Allow Hot Insertion Without System Interruption o LVDS Serial Output Rated for Point-to-Point and Bus Applications o Wide Reference Clock Input Range 16MHz to 40MHz (MAX9205) 40MHz to 66MHz (MAX9207) o Low 140ps (pk-pk) Deterministic Jitter (MAX9207) o Low 34mA Supply Current (MAX9205) o 10-Bit Parallel LVCMOS/LVTTL Interface o Up to 660Mbps Payload Data Rate (MAX9207) o Programmable Active Edge on Input Latch o Pin-Compatible Upgrades to DS92LV1021 and DS92LV1023 Ordering Information MAX9205EAI+ Applications Cellular Phone Base Stations Add Drop Muxes Digital Cross-Connects TEMP RANGE PART REF CLOCK RANGE (MHz) -40°C to +85°C 28 SSOP 16 to 40 MAX9205EAI/V+ -40°C to +85°C 28 SSOP 16 to 40 -40°C to +85°C 28 SSOP 40 to 66 MAX9207EAI+ DSLAMs Network Switches and Routers Backplane Interconnect PINPACKAGE +Denotes a lead(Pb)-free/RoHS-compliant package. /V denotes an automotive qualified part. Pin Configuration and Functional Diagram appear at end of data sheet. 100Ω IN+ 100Ω OUT- INPCB OR TWISTED PAIR TCLK PLL BUS LVDS PLL SYNC 1 SYNC 2 MAX9205 MAX9207 10 OUT_ REFCLK EN PWRDN TIMING AND CONTROL OUTPUT LATCH OUT+ SERIAL-TO-PARALLEL TCLK_R/F PARALLEL-TO-SERIAL 10 IN_ INPUT LATCH Typical Application Circuit MAX9206 MAX9208 TIMING AND CONTROL CLOCK RECOVERY For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com. EN LOCK RCLK RCLK_R/F 19-2029; Rev 2; 10/12 MAX9205/MAX9207 10-Bit Bus LVDS Serializers ABSOLUTE MAXIMUM RATINGS Storage Temperature Range .............................-65°C to +150°C Junction Temperature ......................................................+150°C Operating Temperature Range ...........................-40°C to +85°C ESD Protection (Human Body Model, OUT+, OUT-) ...........±8kV Lead Temperature (soldering, 10s) .................................+300°C Soldering Temperature (reflow) .......................................+260°C AVCC, DVCC to GND..........................……………-0.3V to +4.0V IN_, SYNC1, SYNC2, EN, TCLK_R/F, TCLK, PWRDN to GND......................................-0.3V to (VCC + 0.3V) OUT+, OUT- to GND .............................................-0.3V to +4.0V Output Short-Circuit Duration.....................................Continuous Continuous Power Dissipation (TA = +70°C) 28-Pin SSOP (derate 9.5mW/°C above +70°C) ..........762mW Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. PACKAGE THERMAL CHARACTERISTICS (Note 1) SSOP Junction-to-Ambient Thermal Resistance (θJA)...............68°C/W Junction-to-Case Thermal Resistance (θJC)......................25°C/W Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial. DC ELECTRICAL CHARACTERISTICS (VAVCC = VDVCC = +3.0V to +3.6V, RL = 27Ω ±1% or 50Ω ±1%, CL = 10pF, TA = -40°C to +85°C. Typical values are at VAVCC = VDVCC = +3.3V and TA = +25°C, unless otherwise noted.) (Notes 2, 3, 4) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS LVCMOS/LVTLL LOGIC INPUTS (IN0 TO IN9, EN, SYNC1, SYNC2, TCLK, TCLK_R/F, PWRDN) High-Level Input Voltage VIH 2.0 VCC V Low-Level Input Voltage VIL GND 0.8 V -20 +20 µA Input Current IIN BUS LVDS OUTPUTS (OUT+, OUT-) VIN_ = 0V or V_VCC Differential Output Voltage VOD Figure 1 ∆VOD Figure 1 VOS Figure 1 ∆VOS Figure 1 Change in VOD Between Complementary Output States Output Offset Voltage Change in VOS Between Complementary Output States RL = 27Ω 200 286 400 mV RL = 50Ω 250 460 600 mV 1 35 mV 1.15 1.3 V 3 35 mV -13 -15 mA 0.9 Output Short-Circuit Current IOS VOUT+ or VOUT- = 0V, IN0 to IN9 = PWRDN = EN = high Output High-Impedance Current IOZ VPWRDN or VEN = 0.8V, VOUT+ or VOUT- = 0V or V_VCC -10 +10 µA Power-Off Output Current IOX V_VCC = 0V, VOUT+ or VOUT- = 0V or 3.6V -10 +10 µA ICC RL = 27_ or 50_ worst-case pattern (Figures 2, 4) POWER SUPPLY Supply Current Power-Down Supply Current 2 ICCX PWRDN = low MAX9205 MAX9207 16MHz 23 35 40MHz 34 45 40MHz 32 50 66MHz 45 60 8 mA mA Maxim Integrated MAX9205/MAX9207 10-Bit Bus LVDS Serializers AC ELECTRICAL CHARACTERISTICS (VAVCC = VDVCC = +3.0V to +3.6V, RL = 27Ω ±1% or 50Ω ±1%, CL = 10pF, TA = -40°C to +85°C. Typical values are at VAVCC = VDVCC = +3.3V and TA = +25°C, unless otherwise noted.) (Notes 3, 5) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS TRANSMIT CLOCK (TCLK) TIMING REQUIREMENTS TCLK Center Frequency fTCCF TCLK Frequency Variation TCFV TCLK Period tTCP TCLK Duty Cycle TCDC TCLK Input Transition Time tCLKT TCLK Input Jitter MAX9205 16 40 MHz MAX9207 40 66 MHz ppm -200 200 MAX9205 25 62.5 MAX9207 15.15 25 40 Figure 3 3 tJIT ns 60 % 6 ns 150 ps (RMS) SWITCHING CHARACTERISTICS RL = 27
150 300 400 RL = 50
150 350 500 RL = 27
150 300 400 RL = 50
150 350 500 Low-to-High Transition Time tLHT Figure 4 High-to-Low Transition Time tHLT Figure 4 IN_ Setup to TCLK tS Figure 5 1 ns IN_ Hold from TCLK tH Figure 5 3 ns OUTPUT High State to HighImpedance Delay tHZ Figures 6, 7 4.5 10 ns OUTPUT Low State to HighImpedance Delay tLZ Figures 6, 7 4.5 10 ns OUTPUT High Impedance to High-State Delay t ZH Figures 6, 7 4.5 10 ns OUTPUT High Impedance to Low-State Delay t ZL Figures 6, 7 4.5 10 ns SYNC Pulse Width t SPW PLL Lock Time t PL Bus LVDS Bit Width tBIT Serializer Delay t SD Maxim Integrated 6 x tTCP Figure 7 2048 x tTCP tTCP / 6 ps ns 2049 x tTCP tTCP/12 Figure 8 ps ns ns (tTCP/6) +5 ns 3 MAX9205/MAX9207 10-Bit Bus LVDS Serializers AC ELECTRICAL CHARACTERISTICS (continued) (VAVCC = VDVCC = +3.0V to +3.6V, RL = 27Ω ±1% or 50Ω ±1%, CL = 10pF, TA = -40°C to +85°C. Typical values are at VAVCC = VDVCC = +3.3V and TA = +25°C, unless otherwise noted.) (Notes 3, 5) PARAMETER SYMBOL CONDITIONS MAX9205 Deterministic Jitter (Figure 9) tDJIT MAX9207 MAX9205 Random Jitter (Figure 10) tRJIT MAX9207 MIN TYP MAX 16MHz 200 40MHz 140 40MHz 140 66MHz 140 16MHz 13 40MHz 9 40MHz 9 66MHz 6 UNITS ps (pk-pk) ps (RMS) Note 2: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground except VOD, ∆VOD, and VOS. Note 3: CL includes scope probe and test jig capacitance. Note 4: Parameters 100% tested at TA = +25°C. Limits over operating temperature range guaranteed by design and characterization. Note 5: AC parameters are guaranteed by design and characterization. Typical Operating Characteristics (VAVCC = VDVCC = +3.3V, RL = 27Ω, CL = 10pF, TA = +25°C, unless otherwise noted.) WORST-CASE PATTERN SUPPLY CURRENT vs. SUPPLY VOLTAGE WORST-CASE PATTERN SUPPLY CURRENT vs. SUPPLY VOLTAGE 30 MAX9205 toc01 MAX9205 toc01 40 20 40 30 20 TCLK = 40MHz MAX9205 TCLK = 40MHz MAX9205 10 10 3.0 3.3 SUPPLY VOLTAGE (V) 4 50 SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) 50 3.6 3.0 3.3 3.6 SUPPLY VOLTAGE (V) Maxim Integrated MAX9205/MAX9207 10-Bit Bus LVDS Serializers Pin Description PIN NAME 1, 2 SYNC 1, SYNC 2 3–12 IN0–IN9 FUNCTION LVCMOS/LVTTL Logic Inputs. The two SYNC pins are ORed. When at least one of the two pins are asserted high for at least six cycles of TCLK, the serializer initiates a transmission of 1024 SYNC patterns. If held high after 1024 SYNC patterns have been transmitted, SYNC patterns continue to be sent until the SYNC pin is asserted low. Toggling a SYNC pin after six TCLK cycles high and before 1024 SYNC patterns have been transmitted does not affect the output of the 1024 SYNC patterns. LVCMOS/LVTTL Data Inputs. Data is loaded into a 10-bit latch by the selected TCLK edge. LVCMOS/LVTTL Logic Input. High selects a TCLK rising-edge data strobe. Low selects a TCLK falling-edge data strobe. 13 TCLK_R/F 14 TCLK 15, 16 DGND Digital Circuit Ground. Connect to ground plane. 17, 26 AVCC Analog Circuit Power Supply (Includes PLL). Bypass AVCC to ground with a 0.1µF capacitor and a 0.001µF capacitor. Place the 0.001µF capacitor closest to AVCC. 18, 20, 23, 25 AGND Analog Circuit Ground. Connect to ground plane. 19 EN LVCMOS/LVTTL Reference Clock Input. The MAX9205 accepts a 16MHz to 40MHz clock. The MAX9207 accepts a 40MHz to 66MHz clock. TCLK provides a frequency reference to the PLL and strobes parallel data into the input latch. LVCMOS/LVTTL Logic Input. High enables serial data output. Low puts the bus LVDS output into high impedance. 21 OUT- Inverting Bus LVDS Differential Output 22 OUT+ Noninverting Bus LVDS Differential Output 24 PWRDN 27, 28 DVCC LVCMOS/LVTTL Logic Input. Low puts the device into power-down mode and the output into high impedance. Digital Circuit Power Supply. Bypass DVCC to ground with a 0.1µF capacitor and a 0.001µF capacitor. Place the 0.001µF capacitor closest to DVCC. Detailed Description The MAX9205/MAX9207 are 10-bit serializers designed to transmit data over balanced media that may be a standard twisted-pair cable or PCB traces at 160Mbps to 660Mbps. The interface may be double-terminated point-to-point or a heavily loaded multipoint bus. The characteristic impedance of the media and connected devices can range from 100Ω for a point-to-point interface to 54Ω for a heavily loaded multipoint bus. A double-terminated point-to-point interface uses a 100Ω-termination resistor at each end of the interface, resulting in a load of 50Ω. A heavily loaded multipoint bus requires a termination as low as 54Ω at each end of the bus, resulting in a termination load of 27Ω. The serializer requires a deserializer such as the MAX9206/MAX9208 for a complete data transmission application. Maxim Integrated A high-state start bit and a low-state stop bit, added internally, frame the 10-bit parallel input data and ensure a transition in the serial data stream. Therefore, 12 serial bits are transmitted for each 10-bit parallel input. The MAX9205 accepts a 16MHz to 40MHz reference clock, producing a serial data rate of 192Mbps (12 bits x 16MHz) to 480Mbps (12 bits x 40MHz). The MAX9207 accepts a 40MHz to 66MHz reference clock, producing 480Mbps to 792Mbps. However, since only 10 bits are from input data, the actual throughput is 10 times the TCLK frequency. To transmit data, the serializers sequence through three modes: initialization mode, synchronization mode, and data transmission mode. 5 MAX9205/MAX9207 10-Bit Bus LVDS Serializers Initialization Mode When V CC is applied, the outputs are held in high impedance and internal circuitry is disabled by on-chip power-on-reset circuitry. When the supply voltage reaches 2.35V, the PLL starts to lock to a local reference clock (16MHz to 40MHz for MAX9205 and 40MHz to 66MHz for MAX9207). The reference clock, TCLK, is provided by the system. A serializer locks within 2049 cycles of TCLK. Once locked, a serializer is ready to send data or SYNC patterns depending on the levels of SYNC 1 and SYNC 2. Synchronization Mode To rapidly synchronize with a deserializer, SYNC patterns can be sent. A SYNC pattern is six consecutive ones followed by six consecutive zeros repeating every TCLK period. When one or both SYNC inputs are asserted high for at least six cycles of TCLK, the serializer will initiate the transmission of 1024 SYNC patterns. The serializer will continue to send SYNC patterns if either of the SYNC input pins remains high. Toggling one SYNC input with the other SYNC input low before 1024 SYNC patterns are output does not interrupt the output of the 1024 SYNC patterns. Data Transmission Mode After initialization, both SYNC input pins must be set low by users or through a control signal from the deserializer before data transmission begins. Provided that SYNC inputs are low, input data at IN0–9 are clocked into the serializer by the TCLK input. Setting TCLK_R/F high selects the rising edge of TCLK for data strobe and low selects the falling edge. If either of the SYNC inputs goes high for six TCLK cycles at any time during data transmission, the data at IN0–9 are ignored and SYNC patterns are sent for at least 1024 TCLK cycles. A start bit high and a stop bit low frame the 10-bit data and function as the embedded clock edge in the serial data stream. The serial rate is the TCLK frequency times the data and appended bits. For example, if TCLK is 40MHz, the serial rate is 40 x 12 (10 + 2 bits) = 480Mbps. Since only 10 bits are from input data, the payload rate is 40 x 10 = 400Mbps. Power-Down Power-down mode is entered when the PWRDN pin is driven low. In power-down mode, the PLL of the serializer is stopped and the outputs (OUT+ and OUT-) are in high impedance, disabling drive current and also reducing supply current. When PWRDN is driven high, the serializer must reinitialize and resynchronize before data can be transferred. On power-up, in order for the MAX9205/MAX9207 to initialize correctly, PWRDN should remain below 0.7V until PCLK is stable and all power supplies are within specification. High-Impedance State The serializer output pins (OUT+ and OUT-) are held in high impedance when the supply voltage is first applied and while the PLL is locking to the local reference clock. Setting EN or PWRDN low puts the device in high impedance. After initialization, EN functions asynchronously. For example, the serializer output can be put into high impedance while SYNC patterns are being sent without affecting the internal timing of the SYNC pattern generation. However, if the serializer goes into high impedance, a deserializer loses PLL lock and needs to resynchronize before data transfer can resume. Table 1. Input /Output Function Table INPUTS OUTPUTS EN PWRDN H H H H L L X L X X L X X X SYNC 1 SYNC 2 When either or both SYNC 1 and SYNC 2 are held high for at least six TCLK cycles OUT+, OUTSynchronization Mode. SYNC patterns of six 1s and six 0s are transmitted every TCLK cycle for at least 1024 TCLK cycles. Data at IN0–9 are ignored. Data Transmission Mode. IN0–9 and 2 frame bits are transmitted every TCLK cycle. Output in high-impedance. X = Don’t care. 6 Maxim Integrated MAX9205/MAX9207 10-Bit Bus LVDS Serializers Applications Information Power-Supply Bypassing Bypass AVCC with high-frequency surface-mount ceramic 0.1µF and 0.001µF capacitors in parallel as close to the device as possible, with the smaller valued capacitor closest to AVCC. Bypass DVCC with high-frequency surface-mount ceramic 0.1µF and 0.001µF capacitors in parallel as close to the device as possible, with the smaller valued capacitor closest to DVCC. Differential Traces and Termination Output trace characteristics affect the performance of the MAX9205/MAX9207. Use controlled-impedance media and terminate at both ends of the transmission line in the media's characteristic impedance. Termination with a single resistor at the end of a pointto-point link typically provides acceptable performance. However, the MAX9205/MAX9207 output levels are specified for double-terminated point-to-point and multipoint applications. With a single 100Ω termination, the output swing is larger. TCLK RL 2 OUT+ VOD OUT- Avoid the use of unbalanced cables such as ribbon or simple coaxial cable. Balanced cables such as twisted pair offer superior signal quality and tend to generate less EMI due to canceling effects. Balanced cables tend to pick up noise as common mode, which is rejected by a differential receiver. Eliminate reflections and ensure that noise couples as common mode by running the differential traces close together. Reduce skew by matching the electrical length of the traces. Excessive skew can result in a degradation of magnetic field cancellation. The differential output signals should be routed close to each other to cancel their external magnetic field. Maintain a constant distance between the differential traces to avoid discontinuities in differential impedance. Avoid 90° turns and minimize the number of vias to further prevent impedance discontinuities. ODD IN_ VOS RL 2 EVEN IN_ TCLK_R/F = LOW Figure 2. Worst-Case ICC Test Pattern Figure 1. Output Voltage Definitions 90% 3V 90% TCLK 10% 10% tCLKT 0 tCLKT Figure 3. Input Clock Transition Time Requirement Maxim Integrated 7 MAX9205/MAX9207 10-Bit Bus LVDS Serializers 10pF OUT+ 80% 80% VDIFF = 0 RL 20% VDIFF 20% OUT10pF tLHT tHLT VDIFF = (OUT+) - (OUT-) Figure 4. Output Load and Transition Times tTCP 1.5V TCLK 1.5V tS tH 1.5V IN_ 1.5V 1.5V TIMING SHOWN FOR TCLK_R/F = LOW Figure 5. Data Input Setup and Hold Times PARASITIC PACKAGE AND TRACE CAPACITANCE 10pF OUT+ 13.5Ω +1.1V OUT- 13.5Ω EN 10pF 3V 1.5V EN 1.5V 0 tZH tHZ VOH 50% 50% 1.1V OUT± tZL tLZ 1.1V 50% 50% VOL Figure 6. High-Impedance Test Circuit and Timing 8 Maxim Integrated MAX9205/MAX9207 10-Bit Bus LVDS Serializers 2.0V PWRDN 0.8V tPL tHZ OR tLZ TCLK 1.5V tZH OR tZL OUT± ACTIVE HIGH IMPEDANCE HIGH IMPEDANCE SYNC 1 = SYNC 2 = LOW EN = HIGH TCLK_R/F = HIGH Figure 7. PLL Lock Time and PWRDN High-Impedance Delays IN IN0 - IN9 SYMBOL N + 1 IN0 - IN9 SYMBOL N tSD TCLK 1.5V TIMING SHOWN FOR TCLK_R/F = HIGH START BIT OUT0 - OUT9 SYMBOL N STOP BIT START BIT OUT0 - OUT9 SYMBOL N+1 STOP BIT OUT± TCLK_ R/F = HIGH VDIFF = 0 VDIFF = (OUT+) - (OUT-) Figure 8. Serializer Delay (OUT+) - (OUT-) WAVEFORM (OUT+) - (OUT-) WAVEFORM O DIFFERENTIAL O DIFFERENTIAL tRJIT tDJIT SUPERIMPOSED RANDOM DATA Figure 9. Definition of Deterministic Jitter (tDJIT) Maxim Integrated tRJIT "CLOCK" PATTERN (1010...) Figure 10. Definition of Random Jitter (tRJIT) 9 MAX9205/MAX9207 10-Bit Bus LVDS Serializers Topologies reduces reflections compared to a single 100Ω termination. A single 100Ω termination at the deserializer input is feasible and will make the differential signal swing larger. A serializer located at one end of a backplane bus driving multiple deserializers in a multidrop configuration is shown in Figure 12. A 54Ω resistor at the far end terminates the bus. This topology allows “broadcast” of data with a minimum of interconnect. The serializers can operate in a variety of topologies. Examples of double-terminated point-to-point, multidrop, point-to-point broadcast, and multipoint topologies are shown in Figures 11 through 14. Use 1% surface-mount termination resistors. A point-to-point connection terminated at each end in the characteristic impedance of the cable or PCB traces is shown in Figure 11. The total load seen by the serializer is 50Ω. The double termination typically SERIALIZED DATA PARALLEL DATA IN 100Ω PARALLEL DATA OUT 100Ω MAX9205 MAX9207 MAX9206 MAX9208 Figure 11. Double-Terminated Point-to-Point ASIC MAX9205 MAX9207 ASIC ASIC MAX9206 MAX9208 ASIC MAX9206 MAX9208 ASIC MAX9206 MAX9208 MAX9206 MAX9208 54Ω Figure 12. Multidrop 10 Maxim Integrated MAX9205/MAX9207 10-Bit Bus LVDS Serializers A point-to-point version of the multidrop bus is shown in Figure 13. The low-jitter MAX9150 10-port repeater is used to reproduce and transmit the serializer output over 10 double-terminated point-to-point links. Compared to the multidrop bus, more interconnect is traded for more robust hot-plug capability. The repeater eliminates nine serializers compared to 10 individual point-to-point serializer-to-deserializer connections. Since repeater jitter subtracts from the serializer-deserializer timing margin, a low-jitter repeater is essential in most high data rate applications. Multiple serializers and deserializers bused over a differential serial connection on a backplane are shown in Figure 14. The second serializer can be a backup to Board Layout For bus LVDS applications, a four-layer PCB that provides separate power, ground, and input/output signals is recommended. Separate LVTTL/LVCMOS and bus LVDS signals from each other to prevent coupling into the bus LVDS lines. ASIC ASIC ASIC MAX9206 MAX9208 MAX9205 MAX9207 MAX9150 REPEATER 100Ω the primary serializer. The typical close spacing (1in or less) of cards on a backplane reduces the characteristic impedance by as much as half the initial, unloaded value. Termination resistors that match the loaded characteristic impedance are required at each end of the bus. The total loaded seen by the serializer is 27Ω in this case. 100Ω MAX9206 MAX9208 100Ω 100Ω Figure 13. Point-to-Point Broadcast Using MAX9150 Repeater Maxim Integrated 11 MAX9205/MAX9207 10-Bit Bus LVDS Serializers ASIC ASIC MAX9205 MAX9207 MAX9205 MAX9207 ASIC ASIC MAX9206 MAX9208 ASIC MAX9206 MAX9208 MAX9206 MAX9208 54Ω 54Ω Figure 14. Multipoint Pin Configuration Functional Diagram DVCC 28 SYNC1 2 SYNC2 DVCC 27 3 IN0 AVCC 26 4 IN1 AGND 25 5 IN2 MAX9205 MAX9207 10 PLL TIMING AND CONTROL TCLK_R/F OUT+ OUT- TCLK PWRDN 24 EN PWRDN 6 IN3 AGND 23 7 IN4 OUT+ 22 8 IN5 OUT- 21 9 IN6 AGND 20 10 IN7 EN 19 11 IN8 AGND 18 12 IN9 AVCC 17 Package Information 13 TCLK_R/F DGND 16 14 TCLK DGND 15 For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. SSOP Chip Information PROCESS: CMOS 12 IN_ PARALLEL-TO-SERIAL + 1 INPUT LATCH TOP VIEW SYNC 1 SYNC 2 MAX9205 MAX9207 PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 28 SSOP A28+4 21-0056 90-0095 Maxim Integrated MAX9205/MAX9207 10-Bit Bus LVDS Serializers Revision History REVISION REVISION NUMBER DATE DESCRIPTION Initial release PAGES CHANGED 0 5/01 1 11/10 Updated Ordering Information, Absolute Maximum Ratings, and Package 1, 2, 13 — 2 10/12 Added Package Thermal Characteristics section and updated the Electrical Characteristics and the Power-Down sections 2–4, 6 Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. 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