EVALUATION KIT AVAILABLE
MAX9275/MAX9279
3.12Gbps GMSL Serializers for Coax or
STP Output Drive and Parallel Input
General Description
Benefits and Features
The audio channel supports L-PCM I2S stereo and up to
eight channels of L-PCM in TDM mode. Sample rates of
32kHz to 192kHz are supported with sample depth up to
32 bits.
● Multiple Data Rates for System Flexibility
• Up to 3.12Gbps Serial-Bit Rate
• 6.25MHz to 104MHz Pixel Clock
• 9.6kbps to 1Mbps Control Channel in UART, Mixed
UART/I2C, or I2C Mode with Clock Stretch
Capability
The MAX9275/MAX9279 are 3.12Gbps Gigabit Multimedia
Serial Link (GMSL) serializers with parallel LVCMOS
inputs and a CML serial output programmable for 50Ω
coax or 100Ω shielded twisted pair (STP) cable drive.
The MAX9279 has HDCP content protection but otherwise is the same as the MAX9275. The serializers pair
with any GMSL deserializer capable of coax input. When
programmed for STP output they are backward compatible with any GMSL deserializer. The output amplitude is
programmable 100mV to 500mV, single-ended (coax) or
100mV to 400mV differential (STP).
The embedded control channel operates at 9.6kbps to
1Mbps in UART-UART and UART-I2C modes, and up
to 1Mbps in I2C-I2C mode. Using the control channel, a
µC can program serializer, deserializer, and peripheral
device registers at any time, independent of video timing,
and manage HDCP operation (MAX9279). A GPO output
supports touch-screen controller interrupt requests from
the remote end of the link.
For use with longer cables, the serializers have programmable pre/deemphasis. Programmable spread spectrum
is available on the serial output. The serial output meets
ISO 10605 and IEC 61000-4-2 ESD standards. The core
supply is 1.7V to 1.9V and the I/O supply is 1.7V to 3.6V.
The MAX9275/MAX9279 are available in a lead-free,
56-pin, 8mm x 8mm, TQFN package with exposed pad
and 0.5mm lead pitch.
Applications
● High-Resolution Automotive Navigation
● Rear-Seat Infotainment
● Megapixel Camera Systems
● Ideal for High-Definition Video Applications
• Drives Low-Cost 50Ω Coax Cable and FAKRA
Connectors or 100Ω STP
• 104MHz High-Bandwidth Mode Supports
1920x720p/60Hz Display With 24-Bit Color
• Serializer Pre/Deemphasis Allows 15m Cable at
Full Speed
• Up to 192kHz Sample Rate And 32-Bit Sample
Depth For 7.1 Channel HD Audio
● Reduces EMI and Shielding Requirements
• Serial Output Programmable for 100mV to 500mv
Single-Ended or 100mV to 400mV Differential
• Programmable Spread Spectrum Reduces EMI
• Bypassable Input PLL for Parallel Clock Jitter
Attenuation
• Tracks Spread Spectrum on Input
• High-Immunity Mode for Maximum Control Channel Noise Rejection
● Peripheral Features for System Power-Up and
Verification
• Built-In PRBS Generator for BER Testing of the
Serial Link
• Dedicated “Up/Down” GPO for Touch-Screen
Interrupt and Other Uses
• Remote/Local Wake-Up from Sleep Mode
● Meets Rigorous Automotive and Industrial
Requirements
• -40°C to +105°C Operating Temperature
• ±8kV Contact and ±15kV Air ISO 10605 and IEC
61000-4-2 ESD Protection
Ordering Information appears at end of data sheet.
19-6751; Rev 3; 12/17
MAX9275/MAX9279
3.12Gbps GMSL Serializers for Coax or
STP Output Drive and Parallel Input
TABLE OF CONTENTS
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Benefits and Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Register Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Serial Link Signaling and Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Data-Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
High-Bandwidth Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Audio Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Audio Channel Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Reverse Control Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Control Channel and Register Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
UART Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Interfacing Command-Byte-Only I2C Devices with UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
UART Bypass Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
START and STOP Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Bit Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Slave Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Bus Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Format for Writing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Format for Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
I2C Communication with Remote Side Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
I2C Address Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
GPO/GPI Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Pre/Deemphasis Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Spread Spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Manual Programming of the Spread-Spectrum Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Serial Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
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Maxim Integrated │ 2
MAX9275/MAX9279
3.12Gbps GMSL Serializers for Coax or
STP Output Drive and Parallel Input
TABLE OF CONTENTS (continued)
Coax Splitter Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
High-Immunity Reverse Control Channel Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Configuration Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Link Startup Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Encryption Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Synchronization of Encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Repeater Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
HDCP Authentication Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
HDCP Protocol Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Example Repeater Network—Two µCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Detection and Action Upon New Device Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Notification of Start of Authentication and Enable of Encryption to Downstream Links . . . . . . . . . . . . . . . . . . . . . 46
Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Self PRBS Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Dual µC Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
PCLKIN Spread Tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Changing the Clock Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Providing a Frame Sync (Camera Applications) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Software Programming of the Device Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Configuration Blocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Compatibility with Other GMSL Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Key Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
HS/VS/DE Inversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
WS/SCK Inversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Line-Fault Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Internal Input Pulldowns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Choosing I2C/UART Pullup Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
AC-Coupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Selection of AC-Coupling Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Power-Supply Circuits and Bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Power-Supply Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Cables and Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
www.maximintegrated.com
Maxim Integrated │ 3
MAX9275/MAX9279
3.12Gbps GMSL Serializers for Coax or
STP Output Drive and Parallel Input
TABLE OF CONTENTS (continued)
Chip Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
LIST OF FIGURES
Figure 1. Serial-Output Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 2. Output Waveforms at OUT+, OUT- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 3. Single-Ended Output Template . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 4. Line Fault Detector Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 5. Worst-Case Pattern Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 6. Parallel Clock Input Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 7. I2C Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 8. Differential Output Template . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 9. Input Setup and Hold Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 10. GPI-to-GPO Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 11. Serializer Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 12. Link Startup Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 13. Power-Up Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 14. Input I2S Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 15. 24-Bit Mode Serial Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 16. 32-Bit Mode Serial Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 17. High-Bandwidth Mode Serial Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 18. Audio Channel Input Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 19. 8-Channel TDM (24-Bit Samples, Padded with Zeros) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 20. 6-Channel TDM (24-Bit Samples, No Padding) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 21. Stereo I2S (24-Bit Samples, Padded with Zeros) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 22. Stereo I2S (16-Bit Samples, No Padding) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 23. GMSL UART Protocol for Base Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 24. GMSL UART Data Format for Base Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 25. Sync Byte (0x79) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 26. ACK Byte (0xC3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 27. Format Conversion Between GMSL UART and I2C with Register Address (I2CMETHOD = 0) . . . . . . . . 32
Figure 28. Format Conversion Between GMSL UART and I2C without Register Address (I2CMETHOD = 1) . . . . . . 33
Figure 29. START and STOP Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
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Maxim Integrated │ 4
MAX9275/MAX9279
3.12Gbps GMSL Serializers for Coax or
STP Output Drive and Parallel Input
LIST OF FIGURES (continued)
Figure 30. Bit Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 31. Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 32. Slave Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 33. Format for I2C Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 34. Format for Write to Multiple Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 35. Format for I2C Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 36. 2:1 Coax Splitter Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 37. Coax Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 38. State Diagram, CDS = LOW (Video Display Application) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 39. State Diagram, CDS = HIGH (Image Sensing Application) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 40. Example Network with One Repeater and Two µCs (Tx = GMSL Serializer’s, Rx = Deserializer’s) . . . . . 50
Figure 41. Human Body Model ESD Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 42. IEC 61000-4-2 Contact Discharge ESD Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 43. ISO 10605 Contact Discharge ESD Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
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Maxim Integrated │ 5
MAX9275/MAX9279
3.12Gbps GMSL Serializers for Coax or
STP Output Drive and Parallel Input
LIST OF TABLES
Table 1. Input Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 2. Data-Rate Selection Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 3. Maximum Audio WS Frequency (kHz) for Various PCLKIN Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 4. I2C Bit-Rate Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 5. TP/COAX Drive Current (400mV Output Drive Levels) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 6. Serial Output Spread . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 7. Spread Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 8. Modulation Coefficients and Maximum SDIV Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 9. CONF[1:0] Input Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 10. CONF[3:2] Input Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 11. Reverse Control-Channel Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 12. Fast High-Immunity Mode Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 13. Startup Procedure for Video-Display Applications (CDS = Low) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 14. Startup Procedure for Image-Sensing Applications (CDS = HIGH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 15. Startup, HDCP Authentication, and Normal Operation (Deserializer is Not a Repeater)—First Part of the . .
HDCP Authentication Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 16. Link Integrity Check (Normal)—Performed Every 128 Frames After Encryption is Enabled . . . . . . . . . . . . 48
Table 17. Optional Enhanced Link Integrity Check—Performed Every 16 Frames After Encryption is Enabled . . . . . 49
Table 18. HDCP Authentication and Normal Operation (One Repeater, Two µCs)—First and Second Parts of the
.
HDCP Authentication Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 19. MAX9275/MAX9279 Feature Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 20. Line Fault Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 21. Additional Supply Current from HDCP (MAX9279 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 22. Typical Power-Supply Currents (Using Worst-Case Input Pattern) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 23. Suggested Connectors and Cables for GMSL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 24. Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 25. HDCP Register Table (MAX9279 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
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Maxim Integrated │ 6
MAX9275/MAX9279
3.12Gbps GMSL Serializers for Coax or
STP Output Drive and Parallel Input
Absolute Maximum Ratings (Note 1)
AVDD to EP...........................................................-0.5V to +1.9V
DVDD to EP..........................................................-0.5V to +1.9V
IOVDD to EP.........................................................-0.5V to +3.9V
LMN_ to EP (15mA current limit)..........................-0.5V to +3.9V
OUT+, OUT- to EP................................................-0.5V to +1.9V
All Other Pins to EP.............................-0.5V to (VIOVDD + 0.5V)
OUT+, OUT- Short Circuit to Ground or Supply........Continuous
Continuous Power Dissipation (TA = +70°C)
TQFN (derate 47.6mW/°C above +70°C)...............3809.5mW
Junction Temperature.......................................................+150°C
Storage Temperature......................................... -65°C to +150°C
Lead Temperature (soldering, 10s)..................................+300°C
Soldering Temperature (reflow)........................................+260°C
Note 1: EP connected to PCB ground.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Thermal Characteristics (Note 2)
TQFN
Junction-to-Case Thermal Resistance (θJC)..................1°C/W
Junction-to-Ambient Thermal Resistance (θJA)...........21°C/W
Note 2: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
DC Electrical Characteristics
(VAVDD = VDVDD = 1.7V to 1.9V, VIOVDD = 1.7V to 3.6V, RL = 100Ω ±1% (differential), EP connected to PCB ground (GND), TA = -40°C
to +105°C, unless otherwise noted. Typical values are at VAVDD = VDVDD = VIOVDD = 1.8V, TA = +25°C.) (Note 3)
PARAMETER
SYMBOL
CONDITIONS
MIN
(DIN_, PCLKIN, PWDN, MS/CNTL0, CDS/
CNTL3, HIM)
0.65 x
VIOVDD
SD, SCK, WS
0.7 x
VIOVDD
SINGLE-ENDED INPUTS (DIN_, PCLKIN, PWDN, MS/CNTL0, CDS/CNTL3, SD, SCK, WS, HIM)
High-Level Input Voltage
VIH1
Low-Level Input Voltage
VIL1
Input Current
IIN1
VIN = 0V to VIOVDD
TYP
MAX
UNITS
V
-20
0.35 x
VIOVDD
V
+20
µA
THREE-LEVEL LOGIC INPUTS (CONF0, CONF1, CONF2, CONF3, BWS)
High-Level Input Voltage
VIH
Low-Level Input Voltage
VIL
Mid-Level Input Current
IINM
Input Current
0.7 x
VIOVDD
(Note 4)
IIN
V
0.3 x
VIOVDD
V
-10
+10
µA
-150
+150
µA
SINGLE-ENDED OUTPUT (GPO)
High-Level Output Voltage
VOH1
IOUT = -2mA
Low-Level Output Voltage
VOL1
IOUT = 2mA
OUTPUT Short-Circuit Current
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IOS
VO = 0V
VIOVDD
- 0.2
V
0.2
VIOVDD = 3.0V to 3.6V
16
35
64
VIOVDD = 1.7V to 1.9V
3
12
21
V
mA
Maxim Integrated │ 7
MAX9275/MAX9279
3.12Gbps GMSL Serializers for Coax or
STP Output Drive and Parallel Input
DC Electrical Characteristics (continued)
(VAVDD = VDVDD = 1.7V to 1.9V, VIOVDD = 1.7V to 3.6V, RL = 100Ω ±1% (differential), EP connected to PCB ground (GND), TA = -40°C
to +105°C, unless otherwise noted. Typical values are at VAVDD = VDVDD = VIOVDD = 1.8V, TA = +25°C.) (Note 3)
PARAMETER
SYMBOL
OPEN-DRAIN INPUT/OUTPUT (RX/SDA, TX/SCL, LFLT)
High-Level Input Voltage
VIH2
Low-Level Input Voltage
VIL2
Input Current
IIN2
Low-Level Output Voltage
Input Capacitance
VOL2
CIN
CONDITIONS
MIN
TYP
MAX
0.7 x
VIOVDD
(Note 5)
IOUT = 3mA
UNITS
V
0.3 x
VIOVDD
V
µA
RX/SDA, TX/SCL
-110
+5
LFLT
-80
+5
VIOVDD = 1.7V to 1.9V
0.4
VIOVDD = 3.0V to 3.6V
0.3
Each pin (Note 6)
10
V
pF
DIFFERENTIAL SERIAL OUTPUT (OUT+, OUT-)
Differential Output Voltage
Change in VOD Between
Complimentary Output States
Output Offset Voltage
(VOUT+ + VOUT-)/2 = VOS
Change in VOS between
Complimentary Output States
Output Short-Circuit Current
VOD
DVOD
VOS
Preemphasis off (Figure 1)
300
400
3.3dB Preemphasis setting (Figure 2)
350
610
3.3dB Deemphasis setting (Figure 2)
240
425
Preemphasis off, deemphasis only
Preemphasis off
1.1
1.4
DVOS
IOS
Magnitude of Differential Output
Short Circuit Current
IOSD
Output Termination Resistance
(Internal)
RO
VOUT+ or VOUT- = 0V
500
mV
25
mV
1.56
V
25
mV
-62
mA
VOUT+ or VOUT- = 1.9V
25
VOD = 0V
25
mA
Ω
From OUT+, OUT- to VAVDD
45
54
63
Preemphasis off, high drive, Figure 3
375
500
625
3.3dB preemphasis setting, high drive,
(Figure 2)
435
765
3.3dB deemphasis setting, high drive,
(Figure 2)
300
535
VOUT+ or VOUT- = 0V
-69
SINGLE-ENDED SERIAL OUTPUT (OUT+, OUT-)
Single-Ended Output Voltage
VOUT
Output Short-Circuit Current
IOS
Output Termination Resistance
(Internal)
RO
VOUT+ or VOUT- = 1.9V
From OUT+ or OUT- to VAVDD
32
45
54
63
mV
mA
Ω
REVERSE CONTROL CHANNEL RECEIVER (OUT+, OUT-)
High Switching Threshold
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VCHR
Normal-immunity mode
27
High-immunity mode
40
mV
Maxim Integrated │ 8
MAX9275/MAX9279
3.12Gbps GMSL Serializers for Coax or
STP Output Drive and Parallel Input
DC Electrical Characteristics (continued)
(VAVDD = VDVDD = 1.7V to 1.9V, VIOVDD = 1.7V to 3.6V, RL = 100Ω ±1% (differential), EP connected to PCB ground (GND), TA = -40°C
to +105°C, unless otherwise noted. Typical values are at VAVDD = VDVDD = VIOVDD = 1.8V, TA = +25°C.) (Note 3)
PARAMETER
Low Switching Threshold
SYMBOL
VCLR
CONDITIONS
MIN
Normal-immunity mode
-27
High-immunity mode
-40
TYP
MAX
UNITS
mV
LINE FAULT DETECTION INPUT (LMN_)
Short-to-GND Threshold
VTG
Figure 4
0.3
V
Normal Threshold
VTN
Figure 4
0.57
1.07
V
Open Threshold
VTO
Figure 4
1.45
VIO +
0.06
V
Open Input Voltage
VIO
Figure 4
1.47
1.75
V
Short-to-Battery Threshold
VTE
Figure 4
2.47
V
POWER SUPPLY
fPCLKIN_ = 16.6MHz
Worst-Case Supply Current
(Figure 5, Note 7)
BWS = low
IWCS
BWS = mid
96
120
fPCLKIN_ = 33.3MHz
99
125
fPCLKIN_ = 66.6MHz
111
140
fPCLKIN_ = 104MHz
134
160
fPCLKIN_ = 36.6MHz
102
130
fPCLKIN_ = 104MHz
133
165
mA
Sleep Mode Supply Current
ICCS
Single wake-up receiver enabled
40
170
µA
Power-Down Supply Current
ICCZ
PWDN = GND
5
120
µA
Human body model, RD = 1.5kΩ,
CS = 100pF
±8
ESD PROTECTION
OUT+, OUT- (Note 8)
VESD
IEC 61000-4-2, RD =
330Ω, CS = 150pF
Contact discharge
±10
Air discharge
±12
ISO 10605, RD = 2kΩ, Contact discharge
CS = 330pF
Air discharge
All Other Pins (Note 9)
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VESD
Human body model, RD = 1.5kΩ,
CS = 100pF
kV
±10
±20
±4
kV
Maxim Integrated │ 9
MAX9275/MAX9279
3.12Gbps GMSL Serializers for Coax or
STP Output Drive and Parallel Input
AC Electrical Characteristics
(VAVDD = VDVDD = 1.7V to 1.9V, VIOVDD = 1.7V to 3.6V, RL = 100Ω ±1% (differential), EP connected to PCB ground (GND), TA = -40°C
to +105°C, unless otherwise noted. Typical values are at VAVDD = VDVDD = VIOVDD = 1.8V, TA = +25°C.) (Note 3)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
PARALLEL CLOCK INPUT (PCLKIN)
Clock Frequency
Clock Duty Cycle
Clock Transition Time
Clock Jitter
I2C/UART PORT TIMING
fPCLKIN_
DC_
tR, tF_
tJ
BWS = low, DRS = ‘1’
8.33
16.66
BWS = low, DRS = ‘0’
16.66
104
BWS = mid, DRS = ‘1’
18.33
52
BWS = mid, DRS = ‘0’
36.66
104
BWS = high, DRS = ‘1’
6.25
12.5
BWS = high, DRS = ‘0’
12.5
78
thigh/tT or tlow/tT (Figure 6), (Note 10)
35
65
%
4
ns
800
psP-P
9.6
1000
kbps
(Figure 6), (Note 10)
3.12Gbps bit rate, 300kHz sinusoidal jitter
I2C/UART Bit Rate
50
MHz
Output Rise Time
tR
30% to 70%, CL = 10pF to 100pF, 1kΩ
pullup to IOVDD
20
150
ns
Output Fall Time
tF
70% to 30%, CL = 10pF to 100pF, 1kΩ
pullup to IOVDD
20
150
ns
Low fSCL range
(I2CMSTBT = 010, I2CSLVSH = 10)
9.6
100
kHz
Mid fSCL range
(I2CMSTBT 101, I2CSLVSH = 01)
> 100
400
kHz
High fSCL range
(I2CMSTBT = 111, I2CSLVSH = 00)
> 400
1000
kHz
Low
4.0
Mid
0.6
High
0.26
Low
4.7
Mid
1.3
I2C TIMING (Figure 7)
SCL Clock Frequency
START Condition Hold Time
Low Period of SCL Clock
fSCL
tHD:STA
tLOW
fSCL range
fSCL range
High
Low
High Period of SCL Clock
Repeated START Condition
Setup Time
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tHIGH
tSU:STA
fSCL range
fSCL range
VIOVDD = 1.7V to
< 3V (Note 11)
0.6
VIOVDD = 3.0V to
3.6V
0.5
µs
µs
4.0
Mid
0.6
High
0.26
Low
4.7
Mid
0.6
High
0.26
µs
µs
Maxim Integrated │ 10
MAX9275/MAX9279
3.12Gbps GMSL Serializers for Coax or
STP Output Drive and Parallel Input
AC Electrical Characteristics (continued)
(VAVDD = VDVDD = 1.7V to 1.9V, VIOVDD = 1.7V to 3.6V, RL = 100Ω ±1% (differential), EP connected to PCB ground (GND), TA = -40°C
to +105°C, unless otherwise noted. Typical values are at VAVDD = VDVDD = VIOVDD = 1.8V, TA = +25°C.) (Note 3)
PARAMETER
Data Hold Time
Data Setup Time
Setup Time for Stop Condition
Bus Free Time
Data Valid Time (Note 12)
SYMBOL
tHD:DAT
tSU:DAT
tSU:STO
tBUF
tVD:DAT
CONDITIONS
fSCL range
(Note 10)
fSCL range
fSCL range
fSCL range
MIN
Low
0
Mid
0
High
0
Low
250
Mid
100
High
50
Low
4.0
Mid
0.6
High
0.26
Low
4.7
Mid
1.3
High
0.5
TYP
ns
µs
µs
3.45
Mid
0.9
fSCL range
VIOVDD = 1.7V to
< 3V (Note 13)
0.55
VIOVDD = 3.0V to
3.6V
0.45
Low
fSCL range
Pulse Width of Spikes
Suppressed
tSP
fSCL range
Capacitive Load Each Bus Line
CB
(Note 6)
High
µs
3.45
Mid
tVD:ACK
UNITS
µs
Low
High
Data Valid Acknowledge Time
(Note 12)
MAX
0.9
VIOVDD = 1.7V to
< 3V (Note 14)
0.55
VIOVDD = 3.0V to
3.6V
0.45
Low
50
Mid
50
High
µs
ns
50
100
pF
150
ps
SWITCHING CHARACTERISTICS (Note 10)
Differential Output Rise/Fall Time
Total Serial Output Jitter
(Differential Output)
www.maximintegrated.com
tR, tF
tTSOJ1
20% to 80%, VOD ≥ 400mV, RL = 100Ω,
serial bit rate = 3.12Gbps
3.12Gbps PRBS signal, measured at
VOD = 0V differential, preemphasis
disabled, Figure 8
90
0.25
UI
Maxim Integrated │ 11
MAX9275/MAX9279
3.12Gbps GMSL Serializers for Coax or
STP Output Drive and Parallel Input
AC Electrical Characteristics (continued)
(VAVDD = VDVDD = 1.7V to 1.9V, VIOVDD = 1.7V to 3.6V, RL = 100Ω ±1% (differential), EP connected to PCB ground (GND), TA = -40°C
to +105°C, unless otherwise noted. Typical values are at VAVDD = VDVDD = VIOVDD = 1.8V, TA = +25°C.) (Note 3)
PARAMETER
SYMBOL
CONDITIONS
Deterministic Serial Output Jitter
(Differential Output)
tDSOJ2
3.12Gbps PRBS signal, measured at
VOD = 0V differential, preemphasis disabled
(Figure 8)
MIN
TYP
MAX
UNITS
0.15
UI
Total Serial Output Jitter (Singleended Output)
tTSOJ1
3.12Gbps PRBS signal, measured at VO/2,
preemphasis disabled (Figure 3)
0.25
UI
Deterministic Serial Output Jitter
(Single-Ended Output)
tDSOJ2
3.12Gbps PRBS signal, measured at VO/2,
preemphasis disabled (Figure 3)
0.15
UI
Parallel Data Input Setup Time
tSET
(Figure 9)
2
ns
Parallel Data Input Hold Time
tHOLD
(Figure 9)
1
ns
GPI to GPO Delay
tGPIO
Deserializer GPI to serializer GPO,
(Figure 10)
Serializer Delay (Note 15)
350
Spread spectrum enabled
5440
Spread spectrum disabled
1920
µs
tSD
(Figure 11)
Link Start Time
tLOCK
(Figure 12)
3.5
ms
Power-Up Time
tPU
(Figure 13)
8
ms
WS Frequency
fWS
(See Table 3)
192
kHz
Sample Word Length
nWS
(See Table 3)
8
32
Bits
(192 x
32) x 8
kHz
I2S/TDM INPUT TIMING
8
Bits
SCK Frequency
fSCK
fSCK = fWS x nWS x (2 or 8)
(8 x 8)
x2
SCK Clock High Time
tHC
VSCK RVIH, tSCK = 1/fSCK (Note 6)
0.35 x
tSCK
ns
SCK Clock Low Time
tLC
VSCK RVIL, tSCK = 1/fSCK (Note 6)
0.35 x
tSCK
ns
SD, WS Setup Time
tSET
(Note 6) (Figure 14)
2
ns
SD, WS Hold Time
tHOLD
(Note 6) (Figure 14)
2
ns
Note 3: Limits are 100% production tested at TA = +105°C. Limits over the operating temperature range and are guaranteed by
design and characterization, unless otherwise noted.
Note 4: To provide a midlevel, leave the input open, or, if driven, put driver in high impedance. High-impedance leakage current
must be less than ±10µA.
Note 5: IIN MIN due to voltage drop across the internal pullup resistor.
Note 6: Not production tested. Guaranteed by design
Note 7: HDCP not enabled (MAX9279 only). See Table 21 for additional supply current when HDCP is enabled.
Note 8: Specified pin to ground.
Note 9: Specified pin to all supply/ground.
Note 10: Not production tested. Guaranteed by design and characterization.
Note 11: The I2C bus standard tLOW min = 0.5µs.
Note 12: I2C valid times apply only when the device is operating as a local-side device.
Note 13: The I2C bus standard tVD:DAT max = 0.45µs.
Note 14: The I2C bus standard tVD:ACK max = 0.45µs.
Note 15: Measured in serial link bit times. Bit time = 1/ (30 x fPCLKIN) for BWS = ‘0’ or open. Bit time = 1/ (40 x fPCLKIN) for
BWS = ‘1’.
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Maxim Integrated │ 12
MAX9275/MAX9279
3.12Gbps GMSL Serializers for Coax or
STP Output Drive and Parallel Input
Typical Operating Characteristics
(VAVDD = VDVDD = VIOVDD = 1.8V, TA = +25°C, unless otherwise noted.)
130
120
110
PREEMPHASIS =
0X01 TO 0X04
100
PREEMPHASIS = 0x00
15
30
45
60
75
90
105
PRBS ON, COAX
MODE, SS OFF,
HDCP OFF
150
PREEMPHASIS =
0x0B TO 0x0F
110
PREEMPHASIS =
0x01 TO 0x04
PREEMPHASIS = 0x00
5
20
35
50
65
PRBS ON,
COAX MODE,
PE OFF,
HDCP OFF
140
130
ALL SPREAD
VALUES
MAX9275 toc04
SUPPLY CURRENT
vs. PCLKIN FREQUENCY (BWS = LOW)
120
110
100
90
80
5
15 25 35 45 55 65 75 85 95 105
PCLKIN FREQUENCY (MHz)
SUPPLY CURRENT
vs. PCLKIN FREQUENCY (BWS = HIGH)
SUPPLY CURRENT
vs. PCLKIN FREQUENCY (BWS = OPEN)
PRBS ON,
COAX MODE,
PE OFF,
HDCP OFF
140
130
ALL SPREAD
VALUES
150
120
110
100
PRBS ON,
COAX MODE,
PE OFF,
HDCP OFF
140
130
ALL SPREAD
VALUES
MAX9275 toc06
PCLKIN FREQUENCY (MHz)
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
PREEMPHASIS =
0x01 TO 0x04
SUPPLY CURRENT
vs. PCLKIN FREQUENCY (BWS = HIGH)
120
90
110
PCLKIN FREQUENCY (MHz)
100
SUPPLY CURRENT (mA)
15 25 35 45 55 65 75 85 95 105
130
150
120
PCLKIN FREQUENCY (MHz)
140
90
130
90
SUPPLY CURRENT (mA)
150
PREEMPHASIS =
0x0B TO 0x0F
100
PREEMPHASIS = 0x00
5
PRBS ON, COAX
MODE, SS OFF,
HDCP OFF
140
MAX9275 toc03
90
SUPPLY CURRENT
vs. PCLKIN FREQUENCY (BWS = OPEN)
MAX9275 toc02
PREEMPHASIS =
0x0B TO 0x0F
MAX9275 toc05
SUPPLY CURRENT (mA)
140
150
SUPPLY CURRENT (mA)
PRBS ON,
COAX MODE,
SS OFF,
HDCP OFF
MAX9275 toc01
150
SUPPLY CURRENT
vs. PCLKIN FREQUENCY (BWS = LOW)
120
110
100
5
20
35
50
65
PCLKIN FREQUENCY (MHz)
www.maximintegrated.com
80
90
15
30
45
60
75
90
105
PCLKIN FREQUENCY (MHz)
Maxim Integrated │ 13
MAX9275/MAX9279
3.12Gbps GMSL Serializers for Coax or
STP Output Drive and Parallel Input
Typical Operating Characteristics (continued)
(VAVDD = VDVDD = VIOVDD = 1.8V, TA = +25°C, unless otherwise noted.)
-10
OUTPUT POWER (dBm)
fPCLKIN = 66.6MHz
0%
SPREAD
0.5%
SPREAD
-20
10
0
-30
-40
-50
-60
-70
-80
1% SPREAD
62
63
64
65
67
68
-50
-60
-80
70
-90
71
PCLKIN FREQUENCY (MHz)
2% SPREAD
1% SPREAD
4% SPREAD
31.0 31.5 32.0 32.5 33.0 33.5 34.0 34.5 35.0 35.5
PCLKIN FREQUENCY (MHz)
MAXIMUM PCLKIN FREQUENCY
vs. COAX CABLE LENGTH (BER ≤ 10-10)
MAX9275 toc09
120
PCLKIN FREQUENCY (MHz)
0.5%
SPREAD
-40
-70
69
fPCLKIN = 33.3MHz
-30
4% SPREAD
66
0%
SPREAD
-20
2% SPREAD
-90
-100
-10
OUTPUT POWER (dBm)
0
MAX9275 toc07
10
OUTPUT SPECTRUM vs. PCLKIN
FREQUENCY (VARIOUS SPREAD)
MAX9275 toc08
OUTPUT SPECTRUM vs. PCLKIN
FREQUENCY (VARIOUS SPREAD)
100
OPTIMUM PE/EQ
80
NO PE/EQ
60
NO PE, 10.7dB EQ
40
20
0
BER CAN BE AS LOW AS 10-12 FOR
CABLE LENGTHS LESS THAN 15m
0
5
10
15
20
25
CABLE LENGTH (m)
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Maxim Integrated │ 14
MAX9275/MAX9279
3.12Gbps GMSL Serializers for Coax or
STP Output Drive and Parallel Input
Pin Configuration
BWS
CONF2
CONF0
GPO/HIM
LFLT
LMN0
AVDD
OUT+
OUT-
LMN1
CONF1
TX /SCL
RX/SDA
PWDN
TOP VIEW
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
CDS/CNTL3
IOVDD 44
27
MS/CNTL0
DIN1 45
26
IOVDD
DIN2 46
25
CONF3
DIN3 47
24
WS
DIN4 48
23
SCK
22
SD
21
DIN28/CNTL2
DIN7 51
20
DIN27/CNTL1
DIN8 52
19
DIN26
DIN9 53
18
DIN25
DVDD 54
17
DIN24
16
DVDD
15
DIN23
DIN0 43
MAX9275
MAX9279
DIN5 49
DIN6 50
EP*
+
DIN10 55
DIN22
10 11 12 13 14
DIN21
9
DIN19/VS
8
DIN20/DE
DIN15
7
DIN18/HS
DIN14
6
AVDD
DIN13
5
DIN17
4
IOVDD
3
DIN16
2
PCLKIN
1
DIN12
DIN11 56
TQFN
(8mm x 8mm x 0.75mm)
*CONNECT EP TO GROUND PLANE
Pin Description
PIN
NAME
FUNCTION
1–5, 9, 43,
45–53, 55, 56
DIN[17:0]
Parallel Data Inputs with Internal Pulldown to EP. Encrypted when HDCP is enabled (MAX9279
only).
6
PCLKIN
Parallel Clock Input with Internal Pulldown to EP. Latches parallel data inputs and provides the
PLL reference clock.
7, 26, 44
IOVDD
I/O Supply Voltage. 1.8V to 3.3V logic I/O power supply. Bypass IOVDD to EP with 0.1µF and
0.001µF capacitors as close as possible to the device with the smallest value capacitor closest
to IOVDD.
8, 36
AVDD
1.8V Analog Power Supply. Bypass AVDD to EP with 0.1µF and 0.001µF capacitors as close as
possible to the device with the smaller capacitor closest to AVDD.
DIN18/HS
Parallel Data Input/Horizontal Sync with Internal Pulldown to EP. Defaults to parallel data input
on power-up.
Horizontal sync input when HDCP is enabled (MAX9279 only) or when in high-bandwidth mode
(BWS = open).
10
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Maxim Integrated │ 15
MAX9275/MAX9279
3.12Gbps GMSL Serializers for Coax or
STP Output Drive and Parallel Input
Pin Description (continued)
PIN
NAME
FUNCTION
DIN19/VS
Parallel Data Input/Vertical Sync with Internal Pulldown to EP. Defaults to parallel data input on
power-up.
Vertical sync input when HDCP is enabled (MAX9279 only) or when in high-bandwidth mode
(BWS = open).
12
DIN20/DE
Parallel Data Input/Device Enable with Internal Pulldown to EP. Defaults to parallel data input on
power-up.
Device enable input when HDCP is enabled (MAX9279 only) or when in high-bandwidth mode
(BWS = open).
13–15, 17–19
DIN[26:21]
Parallel Data Inputs with Internal Pulldown to EP. Encrypted when HDCP is enabled (MAX9279
only). DIN[26:21] used only in 32-bit and high-bandwidth modes (BWS = high or open).
16, 54
DVDD
1.8V Digital Power Supply. Bypass DVDD to EP with 0.1µF and 0.001µF capacitors as close as
possible to the device with the smaller value capacitor closest to DVDD.
DIN27/CNTL1
Parallel Data/Auxiliary Control Signal Input with Internal Pulldown to EP.
DIN27 used only in 32-bit mode (BWS = high). DIN27 not encrypted when HDCP is enabled
(MAX9279 only).
CNTL1 used only in high-bandwidth mode (BWS = open). CNTL1 not encrypted when HDCP is
enabled (MAX9279 only).
21
DIN28/CNTL2
Parallel Data/Auxiliary Control Signal Input with Internal Pulldown to EP.
DIN28 used only in 32-bit mode (BWS = high). DIN28 not encrypted when HDCP is enabled
(MAX9279 only).
CNTL2 used only in high-bandwidth mode (BWS = open). CNTL2 not encrypted when HDCP is
enabled (MAX9279 only).
22
SD
23
SCK
I2S/TDM Serial-Clock Input with Internal Pulldown to EP
24
WS
I2S/TDM Word-Select Input with Internal Pulldown to EP
25
CONF3
11
20
27
28
I2S/TDM Serial-Data Input with Internal Pulldown to EP. Disable I2S/TDM encoding to use SD as
an additional control/data input latched on the selected edge of PCLKIN. Encrypted when HDCP
is enabled.
Three-Level Configuration Input. See Table 11 for details. Use 6kΩ (max) for pullup to
IOVDD/pulldown to GND.
MS/CNTL0
Mode Select/Auxiliary Control Signal Input with Internal Pulldown to EP. Function is determined
by the MSCNTL0 register bit and defaults to MS on power-up.
MS (MSCNTL0 = 0): Set MS = low, to select base mode. Set MS = high to select the bypass
mode.
CNTL0 (MSCNTL0 = 1): Used only in high-bandwidth mode (BWS = open). CNTL0 not
encrypted when HDCP is enabled (MAX9279 only).
CDS/CNTL3
Control Direction Selection/Auxiliary Control Signal Input with Internal Pulldown to EP. Function
is determined by the CDSCNTL3 register bit and defaults to CDS on power-up.
CDS (CDSCNTL3 = 0): Control link direct selection input with internal pulldown to EP. Set CDS
= low when the control channel master µC is connected at the serializer. Set CDS = high when
the control channel master µC is connected at the deserializer.
CNTL3 (CDSCNTL3 = 1): Used only in high-bandwidth mode (BWS = open). CNTL3 not
encrypted when HDCP is enabled (MAX9279 only).
www.maximintegrated.com
Maxim Integrated │ 16
MAX9275/MAX9279
3.12Gbps GMSL Serializers for Coax or
STP Output Drive and Parallel Input
Pin Description (continued)
PIN
NAME
29
PWDN
Active-Low, Power-Down Input with Internal Pulldown to EP. Set PWDN low to enter powerdown mode to reduce power consumption.
RX/SDA
UART Receive/I2C Serial Data Input/Output with Internal 30kΩ Pullup to IOVDD. Function is
determined by the state of CONF[1:0] at power-up (Table 10). RX/SDA has an open-drain
driver and requires a pullup resistor.
RX: Input of the serializer’s UART.
SDA: Data input/output of the serializer’s I2C master/slave.
31
TX/SCL
UART Transmit/I2C Serial Clock Input/Output with Internal 30kΩ Pullup to IOVDD. Function is
determined by the state of CONF[1:0] at power-up (Table 10). TX/SCL has an open-drain driver
and requires a pullup resistor.
TX: Output of the serializer’s UART.
SCL: Clock input/output of the serializer’s I2C master/slave.
32
CONF1
Three-Level Configuration Input. See Table 10 for details. Use 6kΩ (max) for pullup to
IOVDD/pulldown to GND.
33
LMN1
Line-Fault Monitor Input 1 (see Figure 4)
34
OUT-
Inverting CML Coax/Twisted-Pair Serial Output
35
OUT+
Noninverting CML Coax/Twisted-Pair Serial Output
37
LMN0
Line-Fault Monitor Input 0 (see Figure 4)
38
LFLT
Active-Low Open-Drain Line-Fault Output. LFLT has a 60kΩ internal pullup to IOVDD. LFLT =
low indicates a line fault. LFLT is output high when PWDN = low.
39
GPO/HIM
General-Purpose Output/High-Immunity Mode Input.
Functions as HIM input with internal pulldown to EP at power-up or when resuming from
power-down mode (PWDN = low), and switches to GPO output automatically after power-up.
HIM: Default HIGHIMM bit value is latched at power-up or when resuming from power-down
mode (PWDN = low) and is active high. Connect HIM to IOVDD with a 30kΩ or less pullup
resistor to set high or leave open to set low. HIGHIMM can be programmed to a different value
after power-up. HIGHIMM in the deserializer must be set to the same value.
GPO: Output follows the state of the GPI (or INT) input on the deserializer. GPO is low after
power-up or when PWDN is low.
40
CONF0
Three-Level Configuration Input. The state of CONF0 latches at power-up or when resuming
from power-down mode (PWDN = low). See Table 10 for details. Use 6kΩ (max) for pullup to
IOVDD/pulldown to GND.
41
CONF2
Three-Level Configuration Input. The state of CONF2 latches at power-up or when resuming
from power-down mode (PWDN = low). See Table 11 for details. Use 6kΩ (max) for pullup to
IOVDD/pulldown to GND.
42
BWS
Three-Level Bus Width Select Input. Set BWS to the same level on both sides of the serial
link. Set BWS = low with 6kΩ (max) pulldown for 24 bit mode. Set BWS = 6kΩ (max) pullup to
IOVDD high for 32-bit mode. Set BWS = open for high-bandwidth mode.
—
EP
30
www.maximintegrated.com
FUNCTION
Exposed Pad. EP is internally connected to device ground. must connect EP to the PCB ground
plane through an array of vias for proper thermal and electrical performance.
Maxim Integrated │ 17
MAX9275/MAX9279
3.12Gbps GMSL Serializers for Coax or
STP Output Drive and Parallel Input
Functional Diagram
LFLT
PCLKIN
MAX9275
MAX9279
SSPLL
FILTER
PLL
CLKDIV
RGB[17:0]
DIN[26:21]
RGB[23:18]
(30-BIT OR 9b10b)
DIN18/HS
HS
HS
DIN19/VS
VS
VS
DIN20/DE
DE
DIN27/CNTL1
DIN28/CNTL2
MS/CNTL0
CDS/CNTL3
VIDEO
SYNC
FIFO
CNTL[2:1]
(9b10b)
CNTL0, CNTL3
(9b10b)
CONTROL
(9b10b)
I2S/TDM
MS, CDS
RGB
HDCP
ENCRYPT
OUT+
PARALLEL
TO
SERIAL
DE
DIN[28:27]
(30-BIT)
HDCP
KEYS
HDCP
CONTROL
CNTL[3:0]
(9b10b)
WS
OUT-
SCRAMBLE /
PARITY/
8b/10b/
9b/10b/
ENCODE
REVERSE
CONTROL
CHANNEL
HDCP
DECRYPT
FCC
SD SCK
CML TX
RX
ACB
GPO/HIM
TX /SCL
MS, CDS
CONTROL
UART/I2C
www.maximintegrated.com
LMN1
(MAX9279
ONLY)
DIN[17:0]
DOUT[28:27]
(30-BIT)
LMN0
LINE
FAULT
DETECT
RX /SDA
PWDN
BWS
CONF[3:0]
Maxim Integrated │ 18
MAX9275/MAX9279
3.12Gbps GMSL Serializers for Coax or
STP Output Drive and Parallel Input
RL/2
OUT+
VOD
VOS
OUT-
RL/2
GND
((OUT+) + (OUT-))/2
OUT-
VOS(+)
VOS(-)
VOS(-)
OUT+
DVOS = |VOS(+) - VOS(-)|
VOD(+)
VOD = 0V
VOD(-)
VOD(-)
DVOD = |VOD(+) - VOD(-)|
(OUT+) - (OUT-)
Figure 1. Serial-Output Parameters
OUT+
VOD(P)
VOS
VOD(D)
OUT-
SERIAL-BIT
TIME
Figure 2. Output Waveforms at OUT+, OUT-
OUT+
OR
OUT-
VO/2
VO
VO/2
VO
Figure 3. Single-Ended Output Template
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Maxim Integrated │ 19
MAX9275/MAX9279
3.12Gbps GMSL Serializers for Coax or
STP Output Drive and Parallel Input
1.8V
45.3kΩ*
45.3kΩ*
LMN0
GMSL
SERIALIZER
LMN1
LMN0
GMSL
SERIALIZER
4.99kΩ*
4.99kΩ*
TWISTED PAIR
OUT+
OUTPUT
LOGIC
(OUT+)
OUT-
CONNECTORS
49.9kΩ*
49.9kΩ*
1.8V
LFLT
REFERENCE
VOLTAGE
GENERATOR
45.3kΩ*
LMN0
LMN1
49.9kΩ*
GMSL
SERIALIZER
OUTPUT
LOGIC
(OUT-)
4.99kΩ*
OUT+
COAX
OUT-
49.9kΩ*
CONNECTORS
LEAVE UNUSED LINE FAULT
INPUT UNCONNECTED
*±1% TOLERANCE
Figure 4. Line Fault Detector Circuit
PCLKIN
DIN_
NOTE: PCLKIN PROGRAMMED FOR RISING LATCH EDGE.
Figure 5. Worst-Case Pattern Input
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Maxim Integrated │ 20
MAX9275/MAX9279
3.12Gbps GMSL Serializers for Coax or
STP Output Drive and Parallel Input
tT
VIH MIN
tHIGH
PCLKIN
tR
tF
VIL MAX
tLOW
Figure 6. Parallel Clock Input Requirements
START
CONDITION
(S)
PROTOCOL
BIT 7
MSB
(A7)
tLOW
tSU;STA
BIT 6
(A6)
tHIGH
BIT 0
(R/W)
ACKNOWLEDGE
(A)
STOP
CONDITION
(P)
1/fSCL
VIOVDD x 0.7
SCL
VIOVDD x 0.3
tBUF
tr
tVD;DAT
tf
tSP
VIOVDD x 0.7
SDA
VIOVDD x 0.3
tHD;STA
tSU;DAT
tHD;DAT
tVD;ACK
tSU;STO
Figure 7. I2C Timing Parameters
800mVP-P
t TSOJ1
2
t TSOJ1
2
Figure 8. Differential Output Template
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Maxim Integrated │ 21
MAX9275/MAX9279
3.12Gbps GMSL Serializers for Coax or
STP Output Drive and Parallel Input
VIH MIN
PCLKIN
VIL MAX
tSET
DIN_
tHOLD
VIH MIN
VIH MIN
VIL MAX
VIL MAX
NOTE: PCLKIN PROGRAMMED FOR RISING LATCHING EDGE.
Figure 9. Input Setup and Hold Times
VIH_MIN
DESERIALIZER
GPI
VIL_MAX
tGPIO
SERIALIZER
GPO
tGPIO
VOH_MIN
VOL_MAX
Figure 10. GPI-to-GPO Delay
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Maxim Integrated │ 22
MAX9275/MAX9279
3.12Gbps GMSL Serializers for Coax or
STP Output Drive and Parallel Input
EXPANDED TIME SCALE
DIN_
N
N+3
N+2
N+1
N+4
PCLKIN
N-1
N
OUT+/tSD
FIRST BIT
LAST BIT
Figure 11. Serializer Delay
PCLKIN
tLOCK
500µs
SERIAL LINK INACTIVE
REVERSE CONTROL CHANNEL
ENABLED
SERIAL LINK ACTIVE
CHANNEL
DISABLED
REVERSE CONTROL CHANNEL
AVAILABLE
PWDN MUST BE HIGH
Figure 12. Link Startup Time
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Maxim Integrated │ 23
MAX9275/MAX9279
3.12Gbps GMSL Serializers for Coax or
STP Output Drive and Parallel Input
PCLKIN
VIH1
PWDN
tPU
POWERED DOWN
POWERED UP,
SERIAL LINK INACTIVE
POWERED UP, SERIAL LINK ACTIVE
500µs
REVERSE CONTROL
CHANNEL DISABLED
REVERSE CONTROL
CHANNEL ENABLED
REVERSE CONTROL
CHANNEL DISABLED
REVERSE CONTROL
CHANNEL ENABLED
Figure 13. Power-Up Delay
WS
tHOLD
tSCK
tSET
tLC
SCK
tHOLD
tSET
tHC
SD
Figure 14. Input I2S Timing Parameters
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Maxim Integrated │ 24
MAX9275/MAX9279
3.12Gbps GMSL Serializers for Coax or
STP Output Drive and Parallel Input
Detailed Description
The MAX9275/MAX9279 serializers, when paired with the
MAX9276/MAX9280 deserializers, provides the full set of
operating features, but is backward compatible with the
MAX9249–MAX9270 family of Gigabit Multimedia Serial
Link (GMSL) devices, and have basic functionality when
paired with any GMSL device. The MAX9279 has HighBandwidth Digital Content Protection (HDCP) while the
MAX9275 does not.
The serializer has a maximum serial-bit rate of 3.12Gbps
for up to 15m of cable and operates up to a maximum
output clock of 104MHz in 24-bit mode and 27-bit highbandwidth mode, or 78MHz in 32-bit mode. This bit rate
and output flexibility support a wide range of displays, from
QVGA (320 x 240) to 1920 x 720 and higher with 24-bit
color, as well as megapixel image sensors. An encoded
audio channel supports L-PCM I2S stereo and up to eight
channels of L-PCM in TDM mode. Sample rates of 32kHz
to 192kHz are supported with sample depth from 8 to
32 bits. Output pre/deemphasis, combined with GMSL
deserializer equalization, extends the cable length and
enhances link reliability.
The control channel enables a µC to program the
serializer and deserializer registers and program registers
on peripherals. The control channel is also used to
perform HDCP functions (MAX9279 only). The µC can be
located at either end of the link, or when using two µCs,
at both ends. Two modes of control-channel operation
are available. Base mode uses either I2C or GMSL UART
protocol, while bypass mode uses a user-defined UART
protocol. UART protocol allows full-duplex communication,
while I2C allows half-duplex communication.
Spread spectrum is available to reduce EMI on the serial
output. The serial output complies with ISO 10605 and
IEC 61000-4-2 ESD protection standards.
Register Mapping
Registers set the operating conditions of the serializers
and are programmed using the control channel in base
mode. The MAX9275/MAX9279 holds its own device
address and the device address of the deserializer it is
paired with. Similarly, the deserializer holds its own device
address and the address of the MAX9275/MAX9279.
Whenever a device address is changed, be sure to write
the new address to both devices. The default device
address of the serializer is 0x80. Registers 0x00 and 0x01
in both devices hold the device addresses.
Table 1. Input Map
MODE
SIGNAL
INPUT PIN
24-BIT MODE
(BWS = LOW)
HIGH-BANDWIDTH
MODE (BWS = MID)
32-BIT MODE
(BWS = HIGH)
R[5:0]
DIN[5:0]
Used
Used
Used
G[5:0]
DIN[11:6]
Used
Used
Used
B[5:0]
DIN[17:12]
Used
Used
Used
HS, VS, DE
DIN18/HS, DIN19/VS, DIN20/DE
Used**
Used**
Used**
R[7:6]
DIN[22:21]
Not used
Used
Used
G[7:6]
DIN[24:23]
Not used
Used
Used
B[7:6]
DIN[26:25]
Not used
Used
Used
CNTL[2:1]
DIN[28:27]/CNTL[2:1]
Not used
Used*,**
Used**
CNTL3, CNTL0
CDS/CNTL3, MS/CNTL0
Not used
Used*,**
Not used
Used
Used
Used
Used
Used
Used
I2S/TDM
AUX SIGNAL
WS, SCK, SD
*See the High-Bandwidth Mode section for details on timing requirements.
**Not encrypted when HDCP is enabled (MAX9279 only).
www.maximintegrated.com
Maxim Integrated │ 25
MAX9275/MAX9279
3.12Gbps GMSL Serializers for Coax or
STP Output Drive and Parallel Input
Input Bit Map
3 bits contain the embedded audio channel, the embedded forward control channel, the parity bit of the serial
word (Figure 15, Figure 16).
The input bit width depends on settings of the bus width
(BWS) pin. Table 1 lists the bit map.
Serial Link Signaling and Data Format
Data-Rate Selection
Input data is scrambled and then 8b/10b coded (9b10b
in high-bandwidth mode). The deserializer recovers the
embedded serial clock, then samples, decodes, and
descrambles the data. In 24-bit mode, the first 21 bits
contain video data. In 32-bit mode, the first 29 bits contain
video data. In high-bandwidth mode, the first 24 bits contain video data, or special control signal packets. The last
High-Bandwidth Mode
The serializer use the DRS bit, and BWS input to set
the PCLKIN frequency range (Table 2). Set DRS = 1
for low data rate PCLKIN frequency range of 6.25MHz
to 16.66MHz. Set DRS = 0 for high data rate PCLKIN
frequency range of 12.5MHz to 104MHz.
The serializer uses differential CML signaling to drive twisted-pair cable and single-ended CML to drive coaxial cable
with programmable pre/deemphasis and AC-coupling.
The deserializer uses AC-coupling and programmable
channel equalization.
The serializer uses a 27-bit high-bandwidth mode to
support 24-Bit RGB at 104MHz pixel clock. Set BWS =
open in both the serializer and deserializer to use highbandwidth mode. In high-bandwidth mode, the serializer
encodes HS, VS, DE, and CNTL[3:0] to special packets.
Packets are sent by replacing a pixel before the rising
edge and after the falling edge of HS, VS, DE signals.
However, for CNTL[3:0], which is not always continuously sampled, packets always replace a pixel before
the transition of the sampled CNTL[3:0]. Keep HS, VS,
and DE low pulse widths at least 2 pixel clock cycles. By
default, CNTL[3:0] are sampled continuously when DE is
low. CNTL[3:0] are sampled only on HS/VS transitions
when DE is high . If DE triggering of encoded packets is
not desired, set the serializer’s DISDETRIG = 0 and the
CNTLTRIG bits to their desired value (register 0x15) to
change the CNTL triggering behavior. Set DETREN = 0
on the deserializer when DE is not periodic.
Table 2. Data-Rate Selection Table
DRS BIT
SETTING
BWS PIN SETTING
PCLKIN
RANGE (MHz)
0 (high
data rate)
Low (24-bit mode)
16.66 to 104
Mid (high-bandwidth mode)
36.66 to 104
High (32-bit mode)
12.5 to 78
1 (low
data rate)
Low
8.33 to 16.66
Mid
18.33 to 36.66
High
6.25 to 12.5
RGB DATA
INPUT SIGNAL
INPUT PIN
CONTROL BITS
R0
R1
B5
DIN0
DIN1
DIN17
HS
VS
I2S/TDM AUDIO
DE
DIN18/ DIN19/ DIN20/
HS
VS
DE
WS
SCK
SD
AUDIO ENCODE
SERIAL DATA
D0
D1
D17
D18
D19
UART/I2C
D20
ACB
FCC
RX/
SDA
TX/
SCL
FORWARD
CONTROL
CHANNEL BIT
PACKET
PARITY
CHECK BIT
PCB
24 BITS
MAX9279 NOTE: VS/HS MUST BE SET AT DIN[19:18] FOR HDCP FUNCTIONALITY.
ONLY DIN[17:0] AND ACB HAVE HDCP ENCRYPTION.
Figure 15. 24-Bit Mode Serial Data Format
www.maximintegrated.com
Maxim Integrated │ 26
MAX9275/MAX9279
3.12Gbps GMSL Serializers for Coax or
STP Output Drive and Parallel Input
RGB DATA
INPUT SIGNAL
INPUT PIN
CONTROL BITS
R0
R1
B5
HS
DIN0
DIN1
DIN17
VS
AUX
CONTROL
BITS
RGB DATA
DE
DIN18/ DIN19/ DIN20/
HS
VS
DE
R6
R7
G6
G7
B6
B7
DIN21
DIN22
DIN23
DIN24
DIN25
DIN26
DIN27/ DIN28/
CNTL1 CNTL2
I2S / TDM
AUDIO
WS
SCK
UART/I2C
SD
D0
D1
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
ACB
FCC
TX/
SCL
PACKET
PARITY
CHECK BIT
FORWARD
CONTROL
CHANNEL BIT
AUDIO ENCODE
SERIAL DATA
RX/
SDA
PCB
32 BITS
MAX9279 NOTE: VS/HS MUST BE SET AT DIN[19:18] FOR HDCP FUNCTIONALITY.
ONLY DIN[17:0], DIN[26:21] AND ACB HAVE HDCP ENCRYPTION.
Figure 16. 32-Bit Mode Serial Data Format
RGB DATA
INPUT SIGNAL
INPUT PIN
R0
R1
DIN0
DIN1
I2S/TDM AUDIO
RGB DATA
B5
R6
R7
G6
G7
B6
D0
D1
DIN17 DIN21 DIN22 DIN23 DIN24 DIN25 DIN26
D17
D18
D19
D20
D21
D22
27 BITS
AUX CONTROL
CONTROL BITS
B7
HS
WS
SCK
SD
AUDIO ENCODE
SERIAL DATA
UART/I2C
D23
ACB
FCC
PCB
RX/
SDA
TX/
SCL
FORWARD
PACKET
CONTROL
PARITY
CHANNEL BIT CHECK BIT
VS
DE
MS/ DIN27/ DIN28/ CDS/ DIN18/ DIN19/ DIN20/
CNTL0 CNTL1 CNTL2 CNTL3 HS
VS
DE
CONTROL SIGNAL ENCODING
SPECIAL SERIAL DATA PACKET
27 BITS
MAX9279 NOTE: VS/HS MUST BE SET AT DIN[20:18].
ONLY DIN[17:0], DIN[26:21] AND ACB HAVE HDCP ENCRYPTION.
Figure 17. High-Bandwidth Mode Serial Data Format
www.maximintegrated.com
Maxim Integrated │ 27
MAX9275/MAX9279
3.12Gbps GMSL Serializers for Coax or
STP Output Drive and Parallel Input
audio data rate and output the audio in I2S format. The
audio channel is enabled by default. When the audio
channel is disabled, the SD is treated as an auxiliary
control signal.
Audio Channel
The audio channel supports 8kHz to 192kHz audio
sampling rates and audio word lengths from 8 bits to
32 bits (2-channel I2S) or 64 to 256 bits (TDM64 to
TDM256). The audio bit clock (SCK) does not have to be
synchronized with PCLKIN. The serializer automatically
encodes audio data into a single bit stream synchronous
with PCLKIN. The deserializer decodes the audio stream
and stores audio words in a FIFO. Audio rate detection
uses an internal oscillator to continuously determine the
Since the audio data sent through the serial link is
synchronized with PCLKIN, low PCLKIN frequencies
limit the maximum audio sampling rate. Table 3 lists
the maximum audio sampling rate for various PCLKIN
frequencies. Spread-spectrum settings do not affect the
I2S/TDM data rate or WS clock frequency.
CHANNELS
Table 3. Maximum Audio WS Frequency (kHz) for Various PCLKIN Frequencies
2
4
6
8
BITS
PER
CHAN
8
16
18
20
24
32
8
16
18
20
24
32
8
16
18
20
24
32
8
16
18
20
24
32
PCLKIN FREQUENCY
(DRS = 0*)
(MHz)
12.5
+
+
185.5
174.6
152.2
123.7
+
123.7
112.0
104.2
88.6
69.9
152.2
88.6
80.2
73.3
62.5
48.3
123.7
69.9
62.5
57.1
48.3
37.1
15.0
+
+
+
+
182.7
148.4
+
148.4
134.4
125.0
106.3
83.8
182.7
106.3
93.3
88.0
75.0
57.9
148.4
83.8
75.0
68.5
57.9
44.5
16.6
+
+
+
+
+
164.3
+
164.3
148.8
138.3
117.7
92.8
+
117.7
106.6
97.3
83.0
64.1
164.3
92.8
83.0
75.8
64.1
49.3
20.0
+
+
+
+
+
+
+
+
179.2
166.7
141.8
111.8
+
141.8
128.4
117.3
100
77.2
+
111.8
100.0
91.3
77.2
59.4
25.0
+
+
+
+
+
+
+
+
+
+
177.2
139.7
+
177.2
160.5
146.6
125
96.5
+
139.7
125.0
114.2
96.5
74.2
30.0
+
+
+
+
+
+
+
+
+
+
+
167.6
+
+
+
175.9
150
115.9
+
167.6
150.0
137.0
115.9
89.1
35.0
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
175
135.2
+
+
175.0
159.9
135.2
103.9
40.0
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
154.5
+
+
+
182.7
154.5
118.8
45.0
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
173.8
+
+
+
+
173.8
133.6
50.0
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
148.4
100
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
COLOR CODING
192kHz
+Max WS rate is greater than 192kHz.
*DRS = 0 PCLKIN frequency is equal to 2x the DRS = 1 PCLKIN frequency.
www.maximintegrated.com
Maxim Integrated │ 28
MAX9275/MAX9279
3.12Gbps GMSL Serializers for Coax or
STP Output Drive and Parallel Input
Audio Channel Input
The audio channel input works with 8-channel TDM and
stereo I2S, as well as nonstandard formats. The input
format is shown in Figure 18.
FRAME
WS
The period of the WS can be 8 to 256 SCK periods. The
WS frame starts with the falling edge and can be low for
1 to 255 SCK periods. SD is one SCK period, sampled
on the rising edge. MSB/LSB order, zero padding or any
other significance assigned to the serial data does not
affect operation of the audio channel. The polarity for WS
and SCK edges is programmable.
SCK
SD
0
1
2
N
16 TO 256 BITS
Figure 19, Figure 20, Figure 21, and Figure 22 are examples of acceptable input formats.
Figure 18. Audio Channel Input Format
256 SCK
WS
SCK
SD
CH1
32 SCK
CH2
CH3
CH4
CH5
CH6
CH7
CH8
MSB 24-BIT DATA
LSB 8 BITS ZERO
Figure 19. 8-Channel TDM (24-Bit Samples, Padded with Zeros)
SCK 144
WS
SCK
SD
CH1
CH2
CH3
CH4
CH5
CH6
24 SCK
24-BIT DATA
Figure 20. 6-Channel TDM (24-Bit Samples, No Padding)
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Maxim Integrated │ 29
MAX9275/MAX9279
3.12Gbps GMSL Serializers for Coax or
STP Output Drive and Parallel Input
Reverse Control Channel
mode selection (MS) input of the device connected to the
µC. Base mode is a half-duplex control channel and the
bypass mode is a full-duplex control channel. The total
maximum forward or reverse control channel delay is 2µs
(UART) or 2 bit times (I2C) from the input of one device to
the output of the other. I2C delay is measured from a start
condition to start condition.
The serializer uses the reverse control channel to receive
I2C/UART, MS, and GPO signals from the deserializer in
the opposite direction of the video stream. The reverse
control channel and forward video data coexist on the
same serial cable forming a bidirectional link. The reverse
control channel operates independently from the forward
control channel. The reverse control channel is available
2ms after power-up. The serializer temporarily disables
the reverse control channel for 500µs after starting/
stopping the forward serial link.
Control Channel and Register Programming
The control channel is available for the µC to send and
receive control data over the serial link simultaneously
with the high-speed data. The µC controls the link from
either the serializer or the deserializer side to support
video-display or image-sensing applications. The control
channel between the µC and serializer or deserializer
runs in base mode or bypass mode according to the
UART Interface
In base mode, the µC is the host and can access the
registers of both the serializer and deserializer from either
side of the link using the GMSL UART protocol. The µC
can also program the peripherals on the remote side by
sending the UART packets to the serializer or deserializer,
with the UART packets converted to I2C by the device
on the remote side of the link. The µC communicates
with a UART peripheral in base mode (through INTTYPE
register settings), using the half-duplex default GMSL
UART protocol of the serializer/deserializer. The device
addresses of the serializer and deserializer in base mode
are programmable.
64 SCK
WS
SCK
SD
LEFT CHANNEL
RIGHT CHANNEL
32 SCK
MSB 24-BIT DATA
LSB 8 BITS ZERO
Figure 21. Stereo I2S (24-Bit Samples, Padded with Zeros)
32 SCK
WS
SCK
SD
LEFT CHANNEL
RIGHT CHANNEL
16 SCK
16-BIT DATA
Figure 22. Stereo I2S (16-Bit Samples, No Padding)
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Maxim Integrated │ 30
MAX9275/MAX9279
3.12Gbps GMSL Serializers for Coax or
STP Output Drive and Parallel Input
When the peripheral interface is I2C, the serializer/
deserializer converts UART packets to I2C that have
device addresses different from those of the serializer or
deserializer. The converted I2C bit rate is the same as the
original UART bit rate.
up to 3.5 times higher or lower than the previous bit rate.
See the Changing the Clock Frequency section for more
information on changing the control channel bit rate.
Figure 23 shows the UART protocol for writing and reading in base mode between the µC and the serializer/
deserializer.
The deserializer uses differential line coding to send
signals over the reverse channel to the serializer. The
bit rate of the control channel is 9.6kbps to 1Mbps
in both directions. The serializer and deserializer
automatically detect the control-channel bit rate in base
mode. Packet bit rate changes can be made in steps of
Figure 24 shows the UART data format. Even parity is used.
Figure 25 and Figure 26 detail the formats of the SYNC
byte (0x79) and the ACK byte (0xC3). The µC and the connected slave chip generate the SYNC byte and ACK byte,
respectively. Events such as device wake-up and GPI
WRITE DATA FORMAT
SYNC
DEV ADDR + R/W
REG ADDR
NUMBER OF BYTES
BYTE 1
BYTE N
ACK
MASTER WRITES TO SLAVE
MASTER READS FROM SLAVE
READ DATA FORMAT
SYNC
DEV ADDR + R/W
REG ADDR NUMBER OF BYTES
MASTER WRITES TO SLAVE
ACK
BYTE 1
BYTE N
MASTER READS FROM SLAVE
Figure 23. GMSL UART Protocol for Base Mode
1 UART FRAME
START
D0
D1
D2
D3
FRAME 1
D4
D5
D6
D7
PARITY
STOP
FRAME 2
STOP
FRAME 3
START
STOP
START
Figure 24. GMSL UART Data Format for Base Mode
START
D0
D1
D2
D3
D4
D5
D6
D7
1
0
0
1
1
1
1
0
Figure 25. Sync Byte (0x79)
www.maximintegrated.com
PARITY STOP
START
D0
D1
D2
D3
D4
D5
D6
D7
1
1
0
0
0
0
1
1
PARITY STOP
Figure 26. ACK Byte (0xC3)
Maxim Integrated │ 31
MAX9275/MAX9279
3.12Gbps GMSL Serializers for Coax or
STP Output Drive and Parallel Input
Interfacing Command-Byte-Only I2C Devices
with UART
generate transitions on the control channel that can be
ignored by the µC. Data written to the serializer registers
do not take effect until after the acknowledge byte is
sent. This allows the µC to verify that write commands
are received without error, even if the result of the write
command directly affects the serial link. The slave uses
the SYNC byte to synchronize with the host UART’s
data rate. If the GPI or MS inputs of the deserializer
toggle while there is control-channel communication, or
if a line fault occurs, the control-channel communication
will be corrupted. In the event of a missed or delayed
acknowledge (~1ms due to control channel timeout),
the µC should assume there was an error in the packet
transmission or response. In base mode, the µC must
keep the UART Tx/Rx lines high for no more than four bit
times between bytes in a packet. Keep the UART TX/RX
lines high for at least 16 bit times before starting to send
a new packet.
The serializers’ UART-to-I2C conversion can interface
with devices that do not require register addresses, such
as the MAX7324 GPIO expander. In this mode, the I2C
master ignores the register address byte and directly
reads/writes the subsequent data bytes (Figure 28).
Change the communication method of the I2C master
using the I2CMETHOD bit. I2CMETHOD = 1 sets
command-byte-only mode, while I2CMETHOD = 0 sets
normal mode where the first byte in the data stream is the
register address.
UART Bypass Mode
In bypass mode, the serializers ignore UART commands
from the µC and the µC communicates with the peripherals directly using its own defined UART protocol. The µC
cannot access the serializer/deserializer’s registers in this
mode. Peripherals accessed through the forward control
channel using the UART interface need to handle at least
one PCLKIN period ±10ns of jitter due to the asynchronous
sampling of the UART signal by PCLKIN. Set MS = high in
the serializer to put the control channel into bypass mode.
As shown in Figure 27, the remote-side device converts
packets going to or coming from the peripherals from
UART format to I2C format and vice versa. The remote
device removes the byte number count and adds or
receives the ACK between the data bytes of I2C. The I2C
bit rate is the same as the UART bit rate.
UART-TO-I2C CONVERSION OF WRITE PACKET (I2CMETHOD = 0)
µC
SERIALIZER/DESERIALIZER
11
SYNC FRAME
11
DEVICE ID + WR
SERIALIZER/DESERIALIZER
11
11
REGISTER ADDRESS NUMBER OF BYTES
PERIPHERAL
1
S
7
DEV ID
1 1
W A
8
REG ADDR
11
DATA 0
11
DATA N
8
DATA 0
1
A
11
ACK FRAME
1
A
8
DATA N
1 1
A P
UART-TO-I2C CONVERSION OF READ PACKET (I2CMETHOD = 0)
µC
SERIALIZER/DESERIALIZER
11
SYNC FRAME
11
DEVICE ID + RD
SERIALIZER/DESERIALIZER
11
11
REGISTER ADDRESS NUMBER OF BYTES
PERIPHERAL
1
S
7
DEV ID
1 1
W A
: MASTER TO SLAVE
8
REG ADDR
1 1
A S
: SLAVE TO MASTER
11
ACK FRAME
7
DEV ID
1 1
R A
S: START
8
DATA 0
P: STOP
1
A
11
DATA 0
8
DATA N
11
DATA N
1 1
A P
A: ACKNOWLEDGE
Figure 27. Format Conversion Between GMSL UART and I2C with Register Address (I2CMETHOD = 0)
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Maxim Integrated │ 32
MAX9275/MAX9279
3.12Gbps GMSL Serializers for Coax or
STP Output Drive and Parallel Input
I2C Interface
For applications with the µC connected to the deserializer,
set the MS pin on the deserializer. There is a 1ms wait
time between switching MS high and the bypass control
channel being active; do not send a UART command
during this time. There is no delay time when switching
to bypass mode when the µC is connected to the serializer. Although MS on either the serializer or deserializer
sets the control channel bypass mode, only the local
side device (connected to the µC) should be used to set
bypass mode. Do not switch MS while a UART command
is being sent. Do not send a logic-low value longer than
100µs to ensure proper GPO functionality. Bypass mode
accepts bit rates down to 10kbps in either direction. See
the GPO/GPI Control section for GPI functionality limitations. The control-channel data pattern should not be held
low longer than 100µs if GPI control is used.
In I2C-to-I2C mode, the serializer’s control channel
interface sends and receives data through an I2Ccompatible 2-wire interface. The interface uses a serialdata line (SDA) and a serial-clock line (SCL) to achieve
bidirectional communication between master and slave(s).
A µC master initiates all data transfers to and from the
device and generates the SCL clock that synchronizes
the data transfer. When an I2C transaction starts on the
local side device’s control channel port, the remote side
device’s control channel port becomes an I2C master
that interfaces with remote side I2C peripherals. The I2C
master must accept clock-stretching which is imposed
by the serializer (holding SCL LOW) The SDA and SCL
lines operate as both an input and an open-drain output.
Pullup resistors are required on SDA and SCL. Each
transmission consists of a START condition (Figure 7)
sent by a master, followed by the device’s 7-bit slave
address plus a R/W bit, a register address byte, one or
more data bytes, and finally a STOP condition.
UART-TO-I2C CONVERSION OF WRITE PACKET (I2CMETHOD = 1)
µC
11
SYNC FRAME
SERIALIZER/DESERIALIZER
11
11
11
DEVICE ID + WR
REGISTER ADDRESS NUMBER OF BYTES
SERIALIZER/DESERIALIZER
µC
PERIPHERAL
1
7
S DEV ID
11
DATA 0
1 1
W A
8
DATA 0
UART-TO-I2C CONVERSION OF READ PACKET (I2CMETHOD = 1)
SERIALIZER/DESERIALIZER
11
11
11
11
SYNC FRAME
DEVICE ID + RD
REGISTER ADDRESS NUMBER OF BYTES
SERIALIZER/DESERIALIZER
PERIPHERAL
MASTER TO SLAVE
11
DATA N
1
S
SLAVE TO MASTER
11
ACK FRAME
7
DEV ID
S: START
1 1
R A
8
DATA 0
P: STOP
11
ACK FRAME
1
A
8
DATA N
11
DATA 0
1
A
8
DATA N
1 1
A P
11
DATA N
1 1
A P
A: ACKNOWLEDGE
Figure 28. Format Conversion Between GMSL UART and I2C without Register Address (I2CMETHOD = 1)
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Maxim Integrated │ 33
MAX9275/MAX9279
3.12Gbps GMSL Serializers for Coax or
STP Output Drive and Parallel Input
START and STOP Conditions
Both SCL and SDA remain high when the interface is not
busy. A master signals the beginning of a transmission
with a START (S) condition by transitioning SDA from high
to low while SCL is high (see Figure 29). When the master has finished communicating with the slave, it issues
a STOP (P) condition by transitioning SDA from low to
high while SCL is high. The bus is then free for another
transmission.
Bit Transfer
One data bit is transferred during each clock pulse
(Figure 30). The data on SDA must remain stable while
SCL is high.
SDA
SCL
S
P
START
CONDITION
STOP
CONDITION
Figure 29. START and STOP Conditions
SDA
SCL
DATA LINE STABLE;
DATA VALID
CHANGE OF DATA
ALLOWED
Figure 30. Bit Transfer
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Maxim Integrated │ 34
MAX9275/MAX9279
3.12Gbps GMSL Serializers for Coax or
STP Output Drive and Parallel Input
Acknowledge
Bus Reset
The device resets the bus with the I2C START condition
for reads. When the R/W bit is set to 1, the serializers
transmit data to the master, thus the master is reading
from the device.
The acknowledge bit is a clocked 9th bit that the recipient
uses to handshake receipt of each byte of data (Figure 31).
Thus, each byte transferred effectively requires nine bits.
The master generates the 9th clock pulse, and the recipient pulls down SDA during the acknowledge clock pulse.
The SDA line is stable low during the high period of the
clock pulse. When the master is transmitting to the slave
device, the slave device generates the acknowledge bit
because the slave device is the recipient. When the slave
device is transmitting to the master, the master generates
the acknowledge bit because the master is the recipient.
The device generates an acknowledge even when the
forward control channel is not active. To prevent acknowledge generation when the forward control channel is not
active, set the I2CLOCACK bit low.
Format for Writing
Writes to the serializers comprise the transmission of the
slave address with the R/W bit set to zero, followed by at
least one byte of information. The first byte of information
is the register address or command byte. The register
address determines which register of the device is to be
written by the next byte, if received. If a STOP (P) condition is detected after the register address is received, the
device takes no further action beyond storing the register
address (Figure 33). Any bytes received after the register
address are data bytes. The first data byte goes into the
register selected by the register address, and subsequent
data bytes go into subsequent registers (Figure 34). If
multiple data bytes are transmitted before a STOP condition, these bytes are stored in subsequent registers
because the register addresses autoincrements.
Slave Address
The serializers have 7-bit long slave addresses. The bit
following a 7-bit slave address is the R/W bit, which is
low for a write command and high for a read command.
The slave address for the serializer is 10000001 for read
commands and 10000000 for write commands. See
Figure 32.
START
CONDITION
CLOCK PULSE FOR
ACKNOWLEDGE
1
SCL
2
8
9
SDA
BY
TRANSMITTER
SDA
BY
RECEIVER
S
Figure 31. Acknowledge
SDA
1
MSB
0
0
0
0
0
0
R/W
ACK
LSB
SCL
Figure 32. Slave Address
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Maxim Integrated │ 35
MAX9275/MAX9279
3.12Gbps GMSL Serializers for Coax or
STP Output Drive and Parallel Input
remote side I2C setup and hold times should be adjusted
by setting the I2CSLVSH register settings on both sides.
Format for Reading
The serializers are read using the internally stored
register address as an address pointer, the same way
the stored register address is used as an address pointer
for a write. The pointer autoincrements after each data
byte is read using the same rules as for a write. Thus, a
read is initiated by first configuring the register address
by performing a write (Figure 35). The master can now
read consecutive bytes from the device, with the first data
byte being read from the register address pointed by the
previously written register address. Once the master
sends a NACK, the device stops sending valid data.
I2C Address Translation
The serializers support I2C address translation for up to
two device addresses. Use address translation to assign
unique device addresses to peripherals with limited
I2C addresses. Source addresses (address to translate
from) are stored in registers 0x0F and 0x11. Destination
addresses (address to translate to) are stored in registers
0x10 and 0x12.
In a multilink situation where there are multiple deserializers and/or peripheral devices connected to these serializers, the deserializers support broadcast commands
to control these multiple devices. Select an unused
device address to use as a broadcast device address.
I2C Communication with Remote Side Devices
The serializers support I2C communication with a
peripheral on the remote side of the communication link
using SCL clock stretching. While multiple masters can
reside on either side of the communication link, arbitration
is not provided. The connected masters need to support
SCL clock stretching. The remote side I2C bit rate range
must be set according to the local side I2C bit rate.
Supported remote side bit rates can be found in Table 4.
Set the I2CMSTBT (register 0x13) to set the remote I2C
bit rate. If using a bit rate different from 400kbps, local and
0 = WRITE
ADDRESS = 0x80
S
1
0
0
0
0
0
0
0
Table 4. I2C Bit-Rate Ranges
REMOTE BIT RATE
RANGE
LOCAL BIT RATE
f > 50kbps
Up to 1Mbps
Any
20kbps > f > 50kbps
Up to 400kbps
Up to 110
f < 20kbps
Up to 10kbps
000
REGISTER ADDRESS = 0x00
A
0
0
0
0
0
0
I2CMSTBT
SETTING
0
REGISTER 0x00 WRITE DATA
0
A
D7
D6
D5
D4
D3
D2
D1
D0
A
P
S = START BIT
P = STOP BIT
A = ACK
D_ = DATA BIT
Figure 33. Format for I2C Write
0 = WRITE
ADDRESS = 0x80
S
1
0
0
0
0
REGISTER ADDRESS = 0x00
0
0
0
A
0
0
REGISTER 0x00 WRITE DATA
D7
D6
D5
D4
D3
D2
0
0
0
0
0
0
A
D1
D0
N
S = START BIT
P = STOP BIT
A = ACK
N = NACK
D_ = DATA BIT
REGISTER 0x01 WRITE DATA
D1
D0
A
D7
D6
D5
D4
D3
D2
P
Figure 34. Format for Write to Multiple Registers
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Maxim Integrated │ 36
MAX9275/MAX9279
3.12Gbps GMSL Serializers for Coax or
STP Output Drive and Parallel Input
0 = WRITE
ADDRESS = 0x80
S
1
0
0
0
0
REGISTER ADDRESS = 0x00
0
0
0
A
0
0
0
0
0
0
0
0
A
S = START BIT
P = STOP BIT
A = ACK
N = NACK
D_ = DATA BIT
1 = READ
ADDRESS = 0x81
REPEATED START
S
1
0
0
0
0
REGISTER 0x00 READ DATA
0
0
1
A
D7
D6
D5
D4
D3
D2
D1
D0
N
P
Figure 35. Format for I2C Read
Program all the remote-side deserializer devices to
translate the broadcast device address (source address
stored in registers 0x0F, 0x11) to the peripherals’ address
(destination address stored in registers 0x10, 0x12).
Any commands sent to the broadcast address (selected
unused address) will be sent to all deserializers and/or
peripheral devices connected to the deserializers whose
addresses match the translated broadcast address.
register 0x05 D[3:0] of the serializer. This preemphasis
function compensates the high-frequency loss of the
cable and enables reliable transmission over longer link
distances. Current drive for both TP and coax modes is
programmable. CMLLVL bits (0x05, D[5:4]) program drive
current in TP mode. CMLLVLCX (0x14,D[7:4]) program
drive current in coax mode.
GPO/GPI Control
To reduce the EMI generated by the transitions on
the serial link, the serializer output is programmable
for spread spectrum. If the deserializer paired with
the MAX9275/MAX9279 has programmable spread
spectrum, do not enable spread for both at the same time
or their interaction will cancel benefits. The deserializer
will track the serializer spread and will pass the spread
to the deserializer output. The programmable spreadspectrum amplitudes are ±0.5%, ±1%, ±1.5%, ±2%, ±3%,
and ±4% (Table 6). Some spread-spectrum amplitudes
can only be used at lower PCLKIN frequencies (Table 7).
There is no PCLKIN frequency limit for the ±0.5% spread
rate.
GPO on the serializer follows GPI transitions on the deserializer. This GPO/GPI function can be used to transmit
signals such as a frame sync in a surround-view camera
system. The GPI-to-GPO delay is 0.35ms (max). Keep
time between GPI transitions to a minimum 0.35ms. This
includes transitions from the other deserializer in coax
splitter mode. Bit D4 of register 0x06 in the deserializer
stores the GPI input state. GPO is low after power-up.
The µC can set GPO by writing to the SETGPO register
bit. Do not send a logic-low value on the deserializer RX/
SDA input (UART mode) longer than 100µs in either base
or bypass mode to ensure proper GPO/GPI functionality.
GPO/GPI commands will override and corrupt an I2C/
UART command in progress.
Pre/Deemphasis Driver
The serial line driver employs current-mode logic (CML)
signaling. The driver is differential when programmed for
twisted-pair. When programmed for coax, one side of the
CML driver is used. The line driver has programmable
pre/deemphasis which modifies the output to compensate
for cable length. There are 13 preemphasis settings as
shown in Table 5. Negative preemphasis levels are deemphasis levels in which the preemphasized swing level is
the same as normal swing, but the no-transition data is
deemphasized. Program the preemphasis levels through
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Spread Spectrum
When the spread spectrum is turned on or off the serial
link stops for several microseconds and then restarts in
order for the deserializer to lose and relock to the new
serial data stream.
The serializer includes a sawtooth divider to
control the spread modulation rate. Auto detection of the
PCLKIN operation range guarantees a spread-spectrum
modulation frequency within 20kHz to 40kHz. Additionally,
manual configuration of the sawtooth divider (SDIV: 0x03,
D[6:0]) allows the user to set a modulation frequency
according to the PCLKIN frequency. When ranges are
manually selected, program the SDIV value for a fixed
modulation frequency around 20kHz.
Maxim Integrated │ 37
MAX9275/MAX9279
3.12Gbps GMSL Serializers for Coax or
STP Output Drive and Parallel Input
Table 5. TP/COAX Drive Current (400mV Output Drive Levels)
SINGLE-ENDED VOLTAGE SWING
PREEMPHASIS
LEVEL (dB)*
PREEMP SETTING
(0x06, D[3:0])
ICML
(mA)
IPRE
(mA)
MAX (mV)
MIN (mV)
-6.0
0100
12
4
400
200
-4.1
0011
13
3
400
250
-2.5
0010
14
2
400
300
-1.2
0001
15
1
400
350
0
0000
16
0
400
400
1.1
1000
16
1
425
375
2.2
1001
16
2
450
350
3.3
1010
16
3
475
325
4.4
1011
16
4
500
300
6.0
1100
15
5
500
250
8.0
1101
14
6
500
200
10.5
1110
13
7
500
150
14.0
1111
12
8
500
100
*Negative preemphasis levels denote deemphasis.
Table 6. Serial Output Spread
SS
SPREAD (%)
000
No spread spectrum. Power-up default depends on CONF[1:0]
001
±0.5% spread spectrum. Power-up default depends on CONF[1:0]
010
±1.5% spread spectrum
011
±2% spread spectrum
100
No spread spectrum
101
±1% spread spectrum
110
±3% spread spectrum
111
±4% spread spectrum
Table 7. Spread Limitations
24-BIT OR HIGH-BANDWIDTH
MODE PCLKIN FREQUENCY
(MHz)
32-BIT MODE PCLKIN
FREQUENCY
(MHz)
SERIAL LINK BIT-RATE
(Mbps)
AVAILABLE SPREAD
RATES
< 33.3
41.66
High
> 30
Open
> 83.33
Fast high-immunity mode requires DRS = 0.
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Maxim Integrated │ 41
MAX9275/MAX9279
3.12Gbps GMSL Serializers for Coax or
STP Output Drive and Parallel Input
Link Startup Procedure
HDCP has two main phases of operation: authentication
and the link integrity check. The µC starts authentication by writing to the START_AUTHENTICATION bit in
the GMSL serializer. The GMSL serializer generates a
64-bit random number. The host µC first reads the 64-bit
random number from the GMSL serializer and writes it
to the deserializer. The µC then reads the GMSL serializer public key selection vector (AKSV) and writes it to
the deserializer. The µC then reads the deserializer KSV
(BKSV) and writes it to the GMSL serializer. The µC
begins checking BKSV against the revocation list. Using
the cipher, the GMSL serializer and deserializer calculate
a 16-bit response value, R0 and R0’, respectively. The
GMSL amendment for HDCP reduces the 100ms minimum wait time allowed for the receiver to generate R0’
(specified in HDCP rev 1.3) to 128 pixel clock cycles in
the GMSL amendment.
Table 13 lists the start-up procedure for display applications (CDS = Low). Table 14 lists the startup procedure
for image-sensing applications (CDS = High). The control
channel is available after the video link or the configuration link is established. If the deserializer powers up after
the serializer, the control channel becomes unavailable
for 2ms after power-up.
High-Bandwidth Digital Content
Protection (HDCP)
Note: The explanation of HDCP operation in this data
sheet is provided as a guide for general understanding.
Implementation of HDCP in a product must meet the
requirements given in the HDCP System v1.3 Amendment
for GMSL, which is available from DCP.
Table 13. Startup Procedure for Video-Display Applications (CDS = Low)
NO.
µC
SERIALIZER
DESERIALIZER
(AUTOSTART ENABLED)
(AUTOSTART DISABLED)
µC connected to serializer
Set all configuration inputs.
Set CONF[3:2] for autostart.
If any configuration inputs are
available on one end of the
link but not the other, always
connect that configuration
input low.
Set all configuration inputs.
Set CONF[3:2] to disable
autostart. If any configuration
inputs are available on one
end of the link but not the
other, always connect that
configuration input low.
Set all configuration
inputs. If any
configuration inputs are
available on one end of
the link but not the other,
always connects that
configuration input low.
1
Powers up
Powers up and loads default
settings. Establishes video
link when valid PCLK
available.
Powers up and loads default
settings
Powers up and loads
default settings. Locks
to video link signal if
available.
2
Enables serial link by setting
SEREN = 1 or configuration
link by setting SEREN = 0
and CLINKEN = 1 (if valid
PCLK not available) and gets
an acknowledge. Waits for
link to be establish (~3ms).
Establishes configuration or
video link
Locks to configuration or
video link signal
3
Writes configuration bits in
the serializer/ deserializer
and gets an acknowledge.
—
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Configuration changed from default settings
Configuration changed
from default settings
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MAX9275/MAX9279
3.12Gbps GMSL Serializers for Coax or
STP Output Drive and Parallel Input
Table 13. Startup Procedure for Video-Display Applications (CDS = Low) (continued)
NO.
SERIALIZER
µC
(AUTOSTART ENABLED)
DESERIALIZER
(AUTOSTART DISABLED)
4
If not already enabled,
sets SEREN = 1, gets an
acknowledge and waits for
video link to be established
(~3ms)
Establishes video link when valid PCLK available (if not
already enabled)
Locks to video link signal
(if not already locked)
5
Begin sending video data to
input
Video data serialized and sent across serial link.
Video data received and
deserialized
SEREN BIT
AUTOS
SETTING POWER-UP VALUE
LOW
1
HIGH
0
POWER-DOWN
OR POWER-OFF
CLINKEN = 0 OR
SEREN = 1
CLINKEN = 0 OR
SEREN = 1
PWDN = HIGH,
POWER-ON
POWER-ON
IDLE
AUTOS = LOW
CLINKEN = 1
CONFIG
LINK STARTING
CONFIG LINK
UNLOCKED
CONFIG LINK
OPERATING
CONFIG LINK
PROGRAM
REGISTERS
LOCKED
PWDN = LOW OR
POWER-OFF
ALL STATES
PWDN = HIGH
POWER-ON,
AUTOS = LOW
SEREN = 1,
PCLKIN RUNNING
VIDEO
LINK LOCKING
SEREN = 0,
NO PCLKIN
SEREN = 0, OR
NO PCLKIN
VIDEO LINK
LOCKED
PRBSEN = 0
VIDEO LINK
OPERATING
PRBSEN = 1
VIDEO LINK
PRBS TEST
VIDEO LINK
UNLOCKED
Figure 38. State Diagram, CDS = LOW (Video Display Application)
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Maxim Integrated │ 43
MAX9275/MAX9279
3.12Gbps GMSL Serializers for Coax or
STP Output Drive and Parallel Input
Table 14. Startup Procedure for Image-Sensing Applications (CDS = HIGH)
NO.
SERIALIZER
µC
DESERIALIZER
(AUTOSTART ENABLED)
(AUTOSTART DISABLED)
µC connected to deserializer
Set all configuration
inputs. Set CONF[3:2] for
autostart.
Set all configuration inputs.
Set CONF[3:2] to disable
autostart.
Set all configuration
inputs
1
Powers up
Powers up and loads
default settings.
Establishes video link
when valid PCLK available
Powers up and loads
default settings. Goes to
sleep after 8ms.
Powers up and loads
default settings.
Locks to video link
signal if available.
2
Writes deserializer configuration bits
and gets an acknowledge.
—
3
Wakes up the serializer by sending
dummy packet, and then writing
SLEEP = 0 within 8ms. May not get
an acknowledge (or gets a dummy
acknowledge) if not locked.
—
4
Writes serializer configuration bits.
May not get an acknowledge (or gets a
dummy acknowledge) if not locked.
Configuration changed from default settings
5
If not already enabled, sets SEREN =
1, gets an acknowledge and waits for
serial link to be established (~3ms)
Establishes video link when valid PCLK available (if not
already enabled)
Locks to video link
signal (if not already
locked)
6
Begin sending video data to input
Video data serialized and sent across serial link
Video data received
and deserialized
—
AUTOS
SETTING
LOW
HIGH
Wakes up
POWER-UP VALUE
SEREN
SLEEP
1
0
0
1
SLEEP
SLEEP = 1
FOR > 8ms
REVERSE LINK
Configuration
changed from default
settings
—
—
—
CLINKEN = 0 OR
SEREN = 1
CLINKEN = 0 OR
SEREN = 1
WAKE-UP
SLEEP = 0,
POWER-ON
IDLE
SEREN = 0
CLINKEN = 1
CONFIG
LINK STARTED
WAKE-UP SIGNAL
PWDN = HIGH,
POWER-ON,
AUTOS = HIGH
SLEEP = 1
ALL STATES
PWDN = LOW OR
POWER-OFF
POWER-DOWN
OR
POWER-OFF
SLEEP = 0,
SLEEP = 1
PWDN = HIGH,
POWER-ON
AUTOS = LOW
SEREN = 1,
PCLKIN RUNNING
CONFIG LINK
LOCKED
CONFIG LINK
OPERATING
PROGRAM
REGISTERS
SEREN = 0 OR
NO PCLKIN
SEREN = 0 OR
NO PCLKIN
VIDEO
LINK LOCKING
CONFIG LINK
UNLOCKED
VIDEO LINK
LOCKED
VIDEO LINK
OPERATING
PRBSEN = 0
PRBSEN = 1
VIDEO LINK
PRBS TEST
VIDEO LINK
UNLOCKED
Figure 39. State Diagram, CDS = HIGH (Image Sensing Application)
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Maxim Integrated │ 44
MAX9275/MAX9279
There are two response-value comparison modes: internal
comparison and µC comparison. Set EN_INT_COMP = 1
to select internal comparison mode. Set EN_INT_COMP
= 0 to select µC comparison mode. In internal comparison mode, the µC reads the deserializer response R0’
and writes it to the GMSL serializer. The GMSL serializer
compares R0’ to its internally generated response value
R0, and sets R0_RI_MATCHED. In µC comparison mode,
the µC reads and compares the R0/R0’ values from the
GMSL serializer/deserializer.
During response-value generation and comparison, the
host µC checks for a valid BKSV (having 20 1s and 20
0s is also reported in BKSV_INVALID) and checks BKSV
against the revocation list. If BKSV is not on the list and
the response values match, the host authenticates the
link. If the response values do not match, the µC resamples the response values (as described in HDCP rev 1.3,
Appendix C). If resampling fails, the µC restarts authentication by setting the RESET_HDCP bit in the GMSL
serializer. If BKSV appears on the revocation list, the host
cannot transmit data that requires protection. The host
knows when the link is authenticated and decides when
to output data requiring protection. The µC performs a link
integrity check every 128 frames or every 2s ±0.5s. The
GMSL serializer/deserializer generate response values
every 128 frames. These values are compared internally
(internal comparison mode) or can be compared in the
host µC.
In addition, the GMSL serializer/deserializer provide
response values for the enhanced link verification.
Enhanced link verification is an optional method of link
verification for faster detection of loss-of-synchronization.
For this option, the GMSL serializer and deserializer
generate 8-bit enhanced link-verification response values
(PJ and PJ’) every 16 frames. The host must detect three
consecutive PJ/PJ’ mismatches before resampling.
Encryption Enable
The GMSL link transfers either encrypted or
nonencrypted data. To encrypt data, the host µC sets
the encryption enable (ENCRYPTION_ENABLE) bit in
both the GMSL serializer and deserializer. The µC must
set ENCRYPTION_ENABLE in the same VSYNC cycle
in both the GMSL serializer and deserializer (no internal
VSYNC falling edges between the two writes). The same
timing applies when clearing ENCRYPTION_ENABLE to
disable encryption.
Note:
ENCRYPTION_ENABLE
enables/disables
encryption on the GMSL irrespective of the content.
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3.12Gbps GMSL Serializers for Coax or
STP Output Drive and Parallel Input
To comply with HDCP, the µC must not allow content
requiring encryption to cross the GMSL unencrypted.
The µC must complete the authentication process before
enabling encryption. In addition, encryption must be
disabled before starting a new authentication session.
Synchronization of Encryption
The video vertical sync (VSYNC) synchronizes the start
of encryption. Once encryption has started, the GMSL
generates a new encryption key for each frame and each
line, with the internal falling edge of VSYNC and HSYNC.
Rekeying is transparent to data and does not disrupt the
encryption of video or audio data.
Repeater Support
The GMSL serializer/deserializer include features to build
an HDCP repeater. An HDCP repeater receives and
decrypts HDCP content and then encrypts and transmits
on one or more downstream links. A repeater can also use
decrypted HDCP content (e.g., to display on a screen).
To support HDCP repeater-authentication protocol, the
deserializer has a REPEATER register bit. This register
bit must be set to 1 by a µC (most likely on the repeater
module). Both the GMSL serializer and deserializer use
SHA-1 hash-value calculation over the assembled KSV
lists. HDCP GMSL links support a maximum of 15 receivers (total number including the ones in repeater modules).
If the total number of downstream receivers exceeds 14,
the µC must set the MAX_DEVS_EXCEEDED register bit
when it assembles the KSV list.
HDCP Authentication Procedures
The GMSL serializer generates a 64-bit random number exceeding the HDCP requirement. The GMSL
serializer/deserializer internal one-time programmable
(OTP) memories contain a unique HDCP keyset programmed at the factory. The host µC initiates and controls
the HDCP authentication procedure. The GMSL serializer
and deserializer generate HDCP authentication response
values for the verification of authentication. Use the
following procedures to authenticate the HDCP GMSL
encryption (refer to the HDCP 1.3 Amendment for GMSL
for details). The µC must perform link integrity checks
while encryption is enabled (see Table 16). Any event that
indicates that the deserializer has lost link synchronization
should retrigger authentication. The µC must first write 1
to the RESET_HDCP bit in the GMSL serializer before
starting a new authentication attempt.
Maxim Integrated │ 45
MAX9275/MAX9279
3.12Gbps GMSL Serializers for Coax or
STP Output Drive and Parallel Input
HDCP Protocol Summary
for an authentication request from the upstream transmitter/repeaters.
Table 15, Table 16, and Table 17 list the summaries of the
HDCP protocol. These tables serve as an implementation
guide only. Meet the requirements in the GMSL amendment for HDCP to be in full compliance.
Example Repeater Network—Two µCs
The example shown in Figure 40 has one repeater and two
µCs. Table 18 summarizes the authentication operation.
Detection and Action Upon New Device
Connection
When a new device is connected to the system, the
device must be authenticated and the device’s KSV
checked against the revocation list. The downstream
µCs can set the NEW_DEV_CONN bit of the upstream
receiver and invoke an interrupt to notify upstream µCs.
Notification of Start of Authentication and
Enable of Encryption to Downstream Links
HDCP repeaters do not immediately begin authentication
upon startup or detection of a new device, but instead wait
Use the following procedure to notify downstream links of
the start of a new authentication request:
1) Host µC begins authentication with the HDCP repeater’s input receiver.
2) When AKSV is written to HDCP repeater’s input
receiver, its AUTH_STARTED bit is automatically set
and its GPIO1 goes high (if GPIO1_FUNCTION is set
to high).
3) HDCP repeater’s µC waits for a low-to-high transition
on HDCP repeater input receiver’s AUTH_STARTED
bit and/or GPIO1 (if configured) and starts authentication downstream.
4) HDCP repeater’s µC resets the AUTH_STARTED bit.
Set GPIO0_FUNCTION to high to have GPIO0 follow the
ENCRYPTION_ENABLE bit of the receiver. The repeater
µC can use this function for notification when encryption
is enabled/disabled by an upstream µC.
Table 15. Startup, HDCP Authentication, and Normal Operation (Deserializer is Not a
Repeater)—First Part of the HDCP Authentication Protocol
NO.
µC
HDCP GMSL SERIALIZER
Powers up waiting for HDCP
authentication.
1
Initial state after power-up.
2
Makes sure that A/V data not requiring
protection (low-value content) is available at
the GMSL serializer inputs (such as blue or
informative screen). Alternatively, uses the
FORCE_VIDEO and FORCE_AUDIO bits of
the GMSL serializer to mask A/V data at the
input of the GMSL serializer. Starts the link by
writing SEREN = H or link starts automatically
if AUTOS is low.
—
3
—
Starts serialization and transmits
low-value content A/V data.
HDCP GMSL DESERIALIZER
Powers up waiting for HDCP
authentication.
—
Locks to incoming data stream and
outputs low-value content A/V data.
4
Reads the locked bit of the deserializer and
makes sure the link is established.
5
Optionally writes a random-number seed to
the GMSL serializer.
Combines seed with internally
generated random number. If
no seed provided, only internal
random number is used.
—
6
If HDCP encryption is required, starts
authentication by writing 1 to the
START_AUTHENTICATION bit of the GMSL
serializer.
Generates (stores) AN, and
resets the
START_AUTHENTICATION bit
to 0.
—
www.maximintegrated.com
—
—
Maxim Integrated │ 46
MAX9275/MAX9279
3.12Gbps GMSL Serializers for Coax or
STP Output Drive and Parallel Input
Table 15. Startup, HDCP Authentication, and Normal Operation (Deserializer is Not a
Repeater)—First Part of the HDCP Authentication Protocol (continued)
NO.
µC
7
Reads AN and AKSV from the GMSL serializer
and writes to the deserializer.
8
Reads the BKSV and REPEATER bit from the
deserializer and writes to the GMSL serializer.
9
Reads the INVALID_BKSV bit of the GMSL
serializer and continues with authentication
if it is 0. Authentication can be restarted if it
fails (set RESET_HDCP = 1 before restarting
authentication).
—
—
10
Reads R0’ from the deserializer and reads
R0 from the GMSL serializer. If they match,
continues with authentication; otherwise,
retries up to two more times (optionally, GMSL
serializer comparison can be used to detect if
R0/R0’ match). Authentication can be restarted
if it fails (set RESET_HDCP = 1 before
restarting authentication).
—
—
11
Waits for the VSYNC falling edge (internal to
the GMSL serializer) and then sets the
ENCRYPTION_ENABLE bit to 1 in the
deserializer and GMSL serializer (if the µC is
not able to monitor VSYNC, it can utilize the
VSYNC_DET bit in the GMSL serializer).
12
Checks that BKSV is not in the Key
Revocation list and continues if it is not.
Authentication can be restarted if it fails.
Note: Revocation list check can start after
BKSV is read in step 8.
13
Starts transmission of A/V content that needs
protection.
www.maximintegrated.com
HDCP GMSL SERIALIZER
—
Generates R0, triggered by the
µC’s write of BKSV.
Encryption enabled after the
next VSYNC falling edge.
—
Performs HDCP encryption on
high-value content A/V data.
HDCP GMSL DESERIALIZER
Generates R0’ triggered by the µC’s
write of AKSV.
—
Decryption enabled after the next
VSYNC falling edge.
—
Performs HDCP decryption on highvalue content A/V data.
Maxim Integrated │ 47
MAX9275/MAX9279
3.12Gbps GMSL Serializers for Coax or
STP Output Drive and Parallel Input
Table 16. Link Integrity Check (Normal)—Performed Every 128 Frames After Encryption
is Enabled
NO.
µC
HDCP GMSL SERIALIZER
HDCP GMSL DESERIALIZER
1
—
Generates Ri and updates the
RI register every 128 VSYNC
cycles.
Generates Ri’ and updates the RI’
register every 128 VSYNC cycles.
2
—
Continues to encrypt and
transmit A/V data.
Continues to receive, decrypt, and
output A/V data.
3
Every 128 video frames (VSYNC cycles) or
every 2s.
—
—
4
Reads RI from the GMSL serializer.
—
—
5
Reads RI’ from the deserializer.
—
—
6
Reads RI again from the GMSL serializer and
makes sure it is stable (matches the previous
RI that it has read from the GMSL serializer). If
RI is not stable, go back to step 5.
—
—
7
If RI matches RI’, the link integrity check is
successful; go back to step 3.
—
—
8
If RI does not match RI’, the link integrity
check fails. After the detection of failure of
link integrity check, the µC makes sure that
A/V data not requiring protection (low-value
content) is available at the GMSL serializer
inputs (such as blue or informative screen).
Alternatively, the FORCE_VIDEO and
FORCE_AUDIO bits of the GMSL serializer
can be used to mask A/V data input of the
GMSL serializer.
—
—
9
Writes 0 to the ENCRYPTION_ENABLE bit of
the GMSL serializer and deserializer.
Disables encryption and
transmits low-value content A/V
data.
Disables decryption and outputs lowvalue content A/V data.
10
Restarts authentication by writing 1 to the
RESET_HDCP bit followed by writing 1 to the
START_AUTHENTICATION bit in the GMSL
serializer.
—
—
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Maxim Integrated │ 48
MAX9275/MAX9279
3.12Gbps GMSL Serializers for Coax or
STP Output Drive and Parallel Input
Table 17. Optional Enhanced Link Integrity Check—Performed Every 16 Frames After
Encryption is Enabled
NO.
µC
HDCP GMSL SERIALIZER
HDCP GMSL DESERIALIZER
1
—
Generates Pj and updates the
PJ register every 16 VSYNC
cycles.
Generates Pj’ and updates the PJ’
register every 16 VSYNC cycles.
2
—
Continues to encrypt and
transmit A/V data.
Continues to receive, decrypt, and
output A/V data.
3
Every 16 video frames, reads PJ from the
GMSL serializer and PJ’ from the deserializer.
—
—
4
If PJ matches PJ’, the enhanced link integrity
check is successful; go back to step 3.
—
—
5
If there is a mismatch, retry up to two more
times from step 3. Enhanced link integrity
check fails after 3 mismatches. After the
detection of failure of enhanced link integrity
check, the µC makes sure that A/V data not
requiring protection (low-value content) is
available at the GMSL serializer inputs (such
as blue or informative screen). Alternatively,
the FORCE_VIDEO and FORCE_AUDIO bits
of the GMSL serializer can be used to mask
A/V data input of the GMSL serializer.
—
—
6
Writes 0 to the ENCRYPTION_ENABLE bit of
the GMSL serializer and deserializer.
Disables encryption and
transmits low-value content A/V
data.
Disables decryption and outputs lowvalue content A/V data.
7
Restarts authentication by writing 1 to the
RESET_HDCP bit followed by writing 1 to the
START_AUTHENTICATION bit in the GMSL
serializer.
—
—
www.maximintegrated.com
Maxim Integrated │ 49
MAX9275/MAX9279
3.12Gbps GMSL Serializers for Coax or
STP Output Drive and Parallel Input
BD-DRIVE
TX_B1
DISPLAY 1
REPEATER
RX_R1
TX_R1
RX_D1
VIDEO
ROUTING
µC_B
DISPLAY 2
MEMORY
WITH SRM
RX_R2
µC_R
TX_R2
RX_D2
VIDEO CONNECTION
CONTROL CONNECTION 1 (µC_B IN BD-DRIVE IS MASTER)
CONTROL CONNECTION 2 (µC_R IN REPEATER IS MASTER)
Figure 40. Example Network with One Repeater and Two µCs (Tx = GMSL Serializer’s, Rx = Deserializer’s)
Table 18. HDCP Authentication and Normal Operation (One Repeater, Two µCs)—First
and Second Parts of the HDCP Authentication Protocol
NO.
1
µC_B
Initial state after power-up.
2
www.maximintegrated.com
—
µC_R
Initial state after power-up.
Writes REPEATER = 1 in
RX_R1. Retries until proper
acknowledge frame received.
Note: This step must be
completed before the first part
of authentication is started
between TX_B1 and RX_R1 by
the µC_B (step 7). For example,
to satisfy this requirement,
RX_R1 can be held at powerdown until µC_R is ready to
write the REPEATER bit, or
µC_B can poll µC_R before
starting authentication.
HDCP GMSL
SERIALIZER
(TX_B1, TX_R1,
TX_R2)
HDCP GMSL
DESERIALIZER
(RX_R1, RX_D1,
RX_D2)
TX_B1 CDS = 0
TX_R1 CDS = 0
TX_R2 CDS = 0
RX_R1 CDS = 1
RX_D1 CDS = 0
RX_D2 CDS = 0
All: Power-up waiting for
HDCP authentication.
All: Power-up waiting for
HDCP authentication.
—
—
Maxim Integrated │ 50
MAX9275/MAX9279
3.12Gbps GMSL Serializers for Coax or
STP Output Drive and Parallel Input
Table 18. HDCP Authentication and Normal Operation (One Repeater, Two µCs)—First
and Second Parts of the HDCP Authentication Protocol (continued)
NO.
3
µC_B
Makes sure that A/V data
not requiring protection (lowvalue content) is available at
the TX_B1 inputs (such as
blue or informative screen).
Alternatively, the FORCE_
VIDEO and FORCE_AUDIO
bits of TX_B1 can be used to
mask A/V data input of TX_B1.
Starts the link between TX_B1
and RX_R1 by writing SEREN
= H to TX_B1, or link starts
automatically if AUTOS is low.
4
—
µC_R
—
Starts all downstream links
by writing SEREN = H to
TX_R1, TX_R2, or links start
automatically if AUTOS of
transmitters are low.
HDCP GMSL
SERIALIZER
(TX_B1, TX_R1,
TX_R2)
HDCP GMSL
DESERIALIZER
(RX_R1, RX_D1,
RX_D2)
TX_B1 CDS = 0
TX_R1 CDS = 0
TX_R2 CDS = 0
RX_R1 CDS = 1
RX_D1 CDS = 0
RX_D2 CDS = 0
TX_B1: Starts
serialization and
transmits low-value
content A/V data.
RX_R1: Locks to
incoming data stream
and outputs low-value
content A/V data.
TX_R1, TX_R2: Starts
serialization and
transmits low-value
content A/V data.
RX_D1, RX_D2: Locks
to incoming data stream
and outputs low-value
content A/V data.
Reads the locked bit of RX_R1
and makes sure the link
between TX_B1 and RX_R1 is
established.
Reads the locked bit of RX_D1
and makes sure the link
between TX_R1 and RX_D1 is
established. Reads the locked
bit of RX_D2 and makes sure
the link between TX_R2 and
RX_D2 is established.
—
—
6
Optionally, writes a random
number seed to TX_B1.
Writes 1 to the GPIO_0_
FUNCTION and GPIO_1_
FUNCTION bits in RX_R1 to
change GPIO functionality used
for HDCP purpose. Optionally,
writes a random-number seed to
TX_R1 and TX_R2.
—
—
7
Starts and completes the
first part of the authentication
protocol between TX_B1, RX_R1
(see steps 6–10 in Table 15).
5
www.maximintegrated.com
—
TX_B1: According
to commands from
µC_B, generates AN,
computes R0.
RX_R1: According to
commands from µC_B,
computes R0’.
Maxim Integrated │ 51
MAX9275/MAX9279
3.12Gbps GMSL Serializers for Coax or
STP Output Drive and Parallel Input
Table 18. HDCP Authentication and Normal Operation (One Repeater, Two µCs)—First
and Second Parts of the HDCP Authentication Protocol (continued)
NO.
µC_B
µC_R
8
—
When GPIO_1 = 1 is detected,
starts and completes the first part
of the authentication protocol
between the (TX_R1, RX_D1)
and (TX_R2, RX_D2) links (see
steps 6–10 in Table 15.
9
Waits for the VSYNC falling
edge and then enables
encryption on the (TX_B1,
RX_R1) link. Full authentication
is not complete yet so it makes
sure A/V content that needs
protection is not transmitted.
Since REPEATER = 1 was read
from RX_R1, the second part of
authentication is required.
—
10
—
Blocks control channel
from µC_B side by setting
REVCCEN = FWDCCEN = 0
in RX_R1. Retries until proper
acknowledge frame received.
11
12
When GPIO_0 = 1 is detected,
enables encryption on the
(TX_R1, RX_D1) and (TX_R2,
RX_D2) links.
Waits for some time to allow
µC_R to make the KSV list
ready in RX_R1. Then polls
(reads) the KSV_LIST_READY
bit of RX_R1 regularly until
proper acknowledge frame is
received and bit is read as 1.
13
www.maximintegrated.com
Writes BKSVs of RX_D1 and
RX_D2 to the KSV list in RX_
R1. Then, calculates and writes
the BINFO register of RX_R1.
Writes 1 to the KSV_LIST_
READY bit of RX_R1 and then
unblocks the control channel
from the µC_B side by setting
REVCCEN = FWDCCEN = 1 in
RX_R1.
HDCP GMSL
SERIALIZER
(TX_B1, TX_R1,
TX_R2)
HDCP GMSL
DESERIALIZER
(RX_R1, RX_D1,
RX_D2)
TX_B1 CDS = 0
TX_R1 CDS = 0
TX_R2 CDS = 0
RX_R1 CDS = 1
RX_D1 CDS = 0
RX_D2 CDS = 0
TX_R1, TX_R2:
According to commands
from µC_R, generates
AN, computes R0.
RX_D1, RX_D2:
According to commands
from µC_R, computes
R0’.
TX_B1: Encryption
enabled after next
VSYNC falling edge.
RX_R1: Decryption
enabled after next
VSYNC falling edge.
TX_R1, TX_R2:
Encryption enabled
after next VSYNC
falling edge.
RX_D1, RX_D2:
Decryption enabled
after next VSYNC
falling edge.
—
RX_R1: Control
channel from serializer
side (TX_B1) is blocked
after FWDCCEN =
REVCCEN = 0 is
written.
—
RX_R1: Triggered by
µC_R’s write of BINFO,
calculates hash value
(V’) on the KSV list,
BINFO and the secretvalue M0’.
—
RX_R1: Control channel
from the serializer side
(TX_B1) is unblocked
after FWDCCEN =
REVCCEN = 1 is
written.
Maxim Integrated │ 52
MAX9275/MAX9279
3.12Gbps GMSL Serializers for Coax or
STP Output Drive and Parallel Input
Table 18. HDCP Authentication and Normal Operation (One Repeater, Two µCs)—First
and Second Parts of the HDCP Authentication Protocol (continued)
NO.
µC_B
µC_R
HDCP GMSL
SERIALIZER
(TX_B1, TX_R1,
TX_R2)
HDCP GMSL
DESERIALIZER
(RX_R1, RX_D1,
RX_D2)
TX_B1 CDS = 0
TX_R1 CDS = 0
TX_R2 CDS = 0
RX_R1 CDS = 1
RX_D1 CDS = 0
RX_D2 CDS = 0
—
14
Reads the KSV list and BINFO
from RX_R1 and writes them
to TX_B1. If any of the MAX_
DEVS_EXCEEDED or MAX_
CASCADE_EXCEEDED bits
is 1, then authentication fails.
Note: BINFO must be written
after the KSV list.
—
TX_B1: Triggered by
µC_B’s write of BINFO,
calculates hash value
(V) on the KSV list,
BINFO and the secretvalue M0.
15
Reads V from TX_B1 and V’
from RX_R1. If they match,
continues with authentication;
otherwise, retries up to two
more times.
—
—
—
16
Searches for each KSV in the
KSV list and BKSV of RX_R1 in
the Key Revocation list.
—
—
—
17
If keys are not revoked,
the second part of the
authentication protocol is
completed.
—
—
—
18
Starts transmission of A/V
content that needs protection.
—
www.maximintegrated.com
All: Perform HDCP
encryption on highvalue A/V data.
All: Perform HDCP
decryption on highvalue A/V data.
Maxim Integrated │ 53
MAX9275/MAX9279
Applications Information
Self PRBS Test
The serializers include a PRBS pattern generator which
works with bit-error verification in the deserializer. To
run the PRBS test, disable encryption (if used), set
DISHSFILT, DISVSFILT, and DISDEFILT to ‘1’, to disable
glitch filter in the deserializer. Then, set PRBSEN = 1
(0x04, D5) in the serializer and then in the deserializer.
To exit the PRBS test, set PRBSEN = 0 (0x04, D5) in the
deserializer and then in the serializer.
Dual µC Control
Usually systems have one microcontroller to run the
control channel, located on the serializer side for display
applications or on the deserializer side for image-sensing
applications. However, a µC can reside on each side
simultaneously, and trade off running the control channel.
In this case, each µC can communicate with the serializer
and deserializer and any peripheral devices.
Contention will occur if both µCs attempt to use the
control channel at the same time. It is up to the user
to prevent this contention by implementing a higher
level protocol. In addition, the control channel does not
provide arbitration between I2C masters on both sides of
the link. An acknowledge frame is not generated when
communication fails due to contention. If communication
across the serial link is not required, the µCs can disable
the forward and reverse control channel using the
FWDCCEN and REVCCEN bits (0x04, D[1:0]) in the
serializer/deserializer. Communication across the serial
link is stopped and contention between µCs cannot occur.
As an example of dual µC use in an image-sensing
application, the serializer can be in sleep mode and
waiting for wake-up by µC on the deserializer side. After
wake-up, the serializer-side µC assumes master control
of the serializer’s registers.
Jitter-Filtering PLL
In some applications, the clock input (PCLKIN) includes
noise, which reduces link reliability. The clock input has a
programmable narrowband jitter-filter PLL that attenuates
frequencies higher than 100kHz (typical). Enable the
jitter-filter by setting DISJITFILT = 0 (0x05, D6).
PCLKIN Spread Tracking
The serializers can operate with a spread PCLKIN signal.
When using a spread PCLKIN, disable the jitter-filter by
setting DISJITFILT = 1 (0x05, D6). Do not exceed the
spread limitation shown in Table 8. In addition, turn off
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3.12Gbps GMSL Serializers for Coax or
STP Output Drive and Parallel Input
spread spectrum in the serializer and deserializer. The
serializer and deserializer track the spread on PCLKIN.
Changing the Clock Frequency
It is recommended that the serial link be enabled after
the video clock (fPCLKIN) and the control-channel
clock (fUART/fI2C) are stable. When changing the clock
frequency, stop the video clock for 5µs, apply the clock
at the new frequency, then restart the serial link or toggle
SEREN. On-the-fly changes in clock frequency are
possible if the new frequency is immediately stable and
without glitches. The reverse control channel remains
unavailable for 500μs after serial link start or stop. When
using the UART interface, limit on-the-fly changes in
fUART to factors of less than 3.5 at a time to ensure
that the device recognizes the UART sync pattern. For
example, when lowering the UART frequency from 1Mbps
to 100kbps, first send data at 333kbps then at 100kbps for
reduction ratios of 3 and 3.333, respectively.
Providing a Frame Sync (Camera
Applications)
The GPI/GPO provide a simple solution for camera
applications that require a Frame Sync signal from the
ECU (e.g., surround view systems). Connect the ECU
Frame Sync signal to the GPI input, and connect GPO
output to the camera Frame Sync input. GPI/GPO has
a typical delay of 275µs. Skew between multiple GPI/
GPO channels is typically 115µs. If a lower skew signal
is required, connect the camera’s frame sync input one of
the deserializer’s GPIOs and use an I2C broadcast write
command to change the GPIO output state. This has a
maximum skew of 0.5µs, + 1 I2C bit time.
Software Programming of the Device
Addresses
The serializers and deserializers have programmable
device addresses. This allows multiple GMSL devices,
along with I2C peripherals, to coexist on the same control
channel. The serializer device address is in register 0x00
of each device, while the deserializer device address is in
register 0x01 of each device. To change a device address,
first write to the device whose address changes (register
0x00 of the serializer for serializer device address change,
or register 0x01 of the deserializer for deserializer device
address change). Then write the same address into the
corresponding register on the other device (register 0x00
of the deserializer for serializer device address change,
or register 0x01 of the serializer for deserializer device
address change).
Maxim Integrated │ 54
MAX9275/MAX9279
3.12Gbps GMSL Serializers for Coax or
STP Output Drive and Parallel Input
3-Level Configuration Inputs
CONF[3:0] and BWS are 3-level inputs that control the
serial interface configuration and power-up defaults.
Connect 3-level inputs through a pullup resistor to IOVDD
to set a high level, a pulldown resistor to GND to set a low
level, or open to set a mid level. For digital control, use
three-state logic to drive the 3-level logic input.
Configuration Blocking
The serializers can block changes to registers. Set
CFGBLOCK to make registers 0x00 to registers 0x1F as
read only. Once set, the registers remain blocked until the
supplies are removed or until PWDN is low.
Compatibility with Other GMSL Devices
The serializers are designed to pair with the MAX9276–
MAX9282 deserializers but interoperates with any GMSL
serializers. See the Table 19 for operating limitations
Key Memory
Each device has a unique HDCP key set that is stored
in secure nonvolatile memory (NVM). The HDCP key set
consists of forty 56-bit private keys and one 40-bit public
key. The NVM is qualified for automotive applications.
HS/VS/DE Inversion
The serializer uses an active-high HS, VS, and DE
for encoding and HDCP encryption. Set INVHSYNC,
INVVSYNC, and INVDE in the serializer (registers 0x0D,
0x0E) to invert active-low input signals for use with the
GMSL devices. Set INVHSYNC, INVVSYNC, and INVDE
in the deserializer (register 0x0E) to output active-low
signals for use with downstream devices.
WS/SCK Inversion
The serializer uses standard polarities for I2S. Set
INVWS, INVSCK in the serializer (register 0x1B) to invert
opposite polarity signals for use with the GMSL devices.
Set INVWS, INVSCK in the deserializer (register 0x1D) to
output reverse-polarity signals for downstream use.
Line-Fault Detection
The line-fault detector in the serializer monitors for line
failures such as short to ground, short to battery, and
open link for system fault diagnosis. Figure 4 shows the
required external resistor connections. LFLT = low when
a line fault is detected and LFLT goes high when the line
returns to normal. The line-fault type is stored in 0x08
D[3:0] of the serializer. Filter LFLT with the µC to reduce
the detector’s susceptibility to short ground shifts. The
fault detector threshold voltages are referenced to the
serializer ground. Additional passive components set
the DC level of the cable (Figure 4). If the serializer and
GMSL deserializer grounds are different, the link DC voltage during normal operation can vary and cross one of
the fault-detection thresholds.
For the fault-detection circuit, select the resistor’s power
rating to handle a short to the battery. In coax mode,
leave the unused line fault inputs unconnected. To detect
the short-together case, refer to Application Note 4709:
MAX9259 GMSL Line-Fault Detection.
Table 20 lists the mapping for line-fault types.
Table 19. MAX9275/MAX9279 Feature Compatibility
MAX9275/MAX9279 FEATURE
GMSL DESERIALIZER
HDCP (MAX9279 only)
If feature not supported in deserializer, must not be turned on in the MAX9279
High-bandwidth mode
If feature not supported in deserializer, must only use 24-bit and 32-bit modes
I2C to I2C
If feature not supported in deserializer, must use UART to I2C or UART to UART
Coax
If feature not supported in deserializer, must connect unused serial input through 200nF and
50Ω in series to VDD and set the reverse control channel amplitude to 100mV.
High-immunity control channel
If feature not supported in deserializer, must use the legacy reverse control channel mode
TDM encoding
If feature not supported in deserializer, must use I2S encoding (with 50% WS duty cycle), if
supported
I2S encoding
If feature not supported in deserializer must disable I2S in the MAX9275/MAX9279
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Maxim Integrated │ 55
MAX9275/MAX9279
3.12Gbps GMSL Serializers for Coax or
STP Output Drive and Parallel Input
Internal Input Pulldowns
The control and configuration inputs (except 3-level
inputs) include a pulldown resistor to GND. External pulldown resistors are not needed.
Choosing I2C/UART Pullup Resistors
I2C and UART open-drain lines require a pullup resistor
to provide a logic-high level. There are tradeoffs between
power dissipation and speed, and a compromise may
be required when choosing pullup resistor values. Every
device connected to the bus introduces some capacitance
even when the device is not in operation. I2C specifies
300ns rise times (30% to 70%) for fast mode, which
is defined for data rates up to 400kbps (see the I2C
specifications in the AC Electrical Characteristics table
for details). To meet the fast-mode rise-time requirement,
choose the pullup resistors so that rise time tR = 0.85
x RPULLUP x CBUS < 300ns. The waveforms are not
recognized if the transition time becomes too slow. The
device supports I2C/UART rates up to 1Mbps.
AC-Coupling
AC-coupling isolates the receiver from DC voltages up
to the voltage rating of the capacitor. Capacitors at the
serializer output and at the deserializer input are needed
for proper link operation and to provide protection if either
end of the cable is shorted to a battery. AC-coupling
blocks low-frequency ground shifts and low-frequency
common-mode noise.
Selection of AC-Coupling Capacitors
Voltage droop and the digital sum variation (DSV) of
transmitted symbols cause signal transitions to start from
different voltage levels. Because the transition time is fixed,
starting the signal transition from different voltage levels
causes timing jitter. The time constant for an AC-coupled
link needs to be chosen to reduce droop and jitter to an
acceptable level. The RC network for an AC-coupled link
consists of the CML/coax receiver termination resistor
(RTR), the CML/coax driver termination resistor (RTD),
and the series AC-coupling capacitors (C). The RC
time constant for four equal-value series capacitors
is (C x (RTD + RTR))/4. RTD and RTR are required to
match the transmission line impedance (usually 100Ω
differential, 50Ω single ended). This leaves the capacitor
selection to change the system time constant. Use at
0.22µF (using legacy reverse control channel), 47nF
(using high-immunity reverse control channel), or larger
high-frequency surface-mount ceramic capacitors, with
sufficient voltage rating to withstand a short to battery, to
pass the lower speed reverse control-channel signal. Use
capacitors with a case size less than 3.2mm x 1.6mm to
have lower parasitic effects to the high-speed signal.
Power-Supply Circuits and Bypassing
The serializers use an AVDD and DVDD of 1.7V to 1.9V.
All single-ended inputs and outputs except for the serial
output derive power from an IOVDD of 1.7V to 3.6V,
which scale with IOVDD. Proper voltage-supply bypassing is essential for high-frequency circuit stability.
Table 20. Line Fault Mapping
REGISTER ADDRESS
BITS
D[3:2]
NAME
LFNEG
0X08
D[1:0]
www.maximintegrated.com
LFPOS
VALUE
LINE FAULT TYPE
00
Negative cable wire shorted to supply voltage
01
Negative cable wire shorted to ground
10
Normal operation
11
Negative cable wire disconnected
00
Positive cable wire shorted to supply voltage
01
Positive cable wire shorted to ground
10
Normal operation
11
Positive cable wire disconnected
Maxim Integrated │ 56
MAX9275/MAX9279
3.12Gbps GMSL Serializers for Coax or
STP Output Drive and Parallel Input
Power-Supply Table
Power-supply currents shown in the DC Electrical
Characteristics table is the sum of the currents from
AVDD, DVDD, and IOVDD. Typical currents from the
individual power supplies are shown in Table 22. HDCP
operation (MAX9279 only) draws additional current. This
is shown in Table 21.
Cables and Connectors
Interconnect for CML typically has a differential impedance of 100Ω. Use cables and connectors that have
matched differential impedance to minimize impedance
discontinuities. Coax cables typically have a characteristic
impedance of 50Ω (contact the factory for 75Ω operation).
Table 23 lists the suggested cables and connectors used
in the GMSL link.
Board Layout
Separate LVCMOS logic signals and CML/coax highspeed signals to prevent crosstalk. Use a four-layer PCB
with separate layers for power, ground, CML/coax, and
LVCMOS logic signals. Layout PCB traces close to each
other for a 100Ω differential characteristic impedance for
STP. The trace dimensions depend on the type of trace
used (microstrip or stripline). Note that two 50Ω PCB
traces do not have 100Ω differential impedance when
brought close together—the impedance goes down when
the traces are brought closer. Use a 50Ω trace for the
single-ended output when driving coax.
Route the PCB traces for differential CML channel in parallel to maintain the differential characteristic impedance.
Avoid vias. Keep PCB traces that make up a differential
pair equal length to avoid skew within the differential pair.
Table 21. Additional Supply Current from HDCP (MAX9279 Only)
PCLK (MHz)
MAXHDCP CURRENT (mA)
16.6
12
33.3
15
36.6
15
66.6
20
104
26
Table 22. Typical Power-Supply Currents (Using Worst-Case Input Pattern)
PCLK
(MHz)
AVDD
(mA)
DVDD
(mA)
IOVDD
(mA)
33
91
20
0.1
104
99.5
26.5
0.4
Table 23. Suggested Connectors and Cables for GMSL
VENDOR
CONNECTOR
CABLE
TYPE
Rosenberger
59S2AX-400A5-Y
Dacar 302
Coax
Rosenberger
D4S10A-40ML5-Z
Dacar 535-2
STP
Nissei
GT11L-2S
F-2WME AWG28
STP
JAE
MX38-FF
A-BW-Lxxxxx
STP
www.maximintegrated.com
Maxim Integrated │ 57
MAX9275/MAX9279
3.12Gbps GMSL Serializers for Coax or
STP Output Drive and Parallel Input
ESD Protection
ESD tolerance is rated for Human Body Model, IEC
61000-4-2, and ISO 10605. The ISO 10605 and IEC
61000-4-2 standards specify ESD tolerance for electronic
systems. The serial link inputs are rated for ISO 10605
ESD protection and IEC 61000-4-2 ESD protection. All
pins are tested for the Human Body Model. The Human
Body Model discharge components are CS = 100pF and
RD = 1.5kΩ (Figure 41). The IEC 61000-4-2 discharge
components are CS = 150pF and RD = 330Ω (Figure 42).
The ISO 10605 discharge components are CS = 330pF
and RD = 2kΩ (Figure 43).
1MΩ
HIGHVOLTAGE
DC
SOURCE
CHARGE-CURRENTLIMIT RESISTOR
CS
100pF
HIGHVOLTAGE
DC
SOURCE
CHARGE-CURRENTLIMIT RESISTOR
CS
150pF
STORAGE
CAPACITOR
DEVICE
UNDER
TEST
RD
2kΩ
DISCHARGE
RESISTANCE
STORAGE
CAPACITOR
DISCHARGE
RESISTANCE
Figure 42. IEC 61000-4-2 Contact Discharge ESD Test Circuit
RD
1.5kΩ
Figure 41. Human Body Model ESD Test Circuit
www.maximintegrated.com
RD
330Ω
DEVICE
UNDER
TEST
HIGHVOLTAGE
DC
SOURCE
CHARGE-CURRENTLIMIT RESISTOR
CS
330pF
DISCHARGE
RESISTANCE
STORAGE
CAPACITOR
DEVICE
UNDER
TEST
Figure 43. ISO 10605 Contact Discharge ESD Test Circuit
Maxim Integrated │ 58
MAX9275/MAX9279
3.12Gbps GMSL Serializers for Coax or
STP Output Drive and Parallel Input
Table 24. Register Table
REGISTER
ADDRESS
0x00
0x01
BITS
NAME
VALUE
D[7:1]
SERID
XXXXXXX
D0
CFGBLOCK
D[7:1]
D0
D[7:5]
Normal operation
1
Registers 0x00 to 0x1F are read only
DESID
XXXXXXX
Deserializer device address address
—
0
0x02
D4
D[3:2]
D[1:0]
D[7:6]
AUDIOEN
PRNG
SRNG
www.maximintegrated.com
0
1001000
Reserved
0
No spread spectrum. (Power-up default values
depend on values of CONF[1:0] at power-up).
001
±0.5% spread spectrum (Power-up default values
depend on values of CONF[1:0] at power-up).
010
±1.5% spread spectrum
011
±2% spread spectrum
100
No spread spectrum
101
±1% spread spectrum
110
±3% spread spectrum
111
±4% spread spectrum
0
Disable I2S/TDM channel
1
Enable I2S/TDM channel
00
12.5MHz to 25MHz pixel clock
01
25MHz to 50MHz pixel clock
10
50MHz to 104MHz pixel clock
000, 001
1
11
11
Automatically detect the pixel clock range
00
0.5 to 1Gbps serial bit rate
01
1 to 2Gbps serial bit rate
10
2 to 3.12Gbps serial bit rate
11
Automatically detect serial bit rate
00
Calibrate spread modulation rate only once after
locking
01
Calibrate spread modulation rate every 2ms after
locking
10
Calibrate spread modulation rate every 16ms after
locking
11
Calibrate spread modulation rate every 256ms after
locking
000000
SDIV
1000000
000
AUTOFM
0x03
D[5:0]
Serializer device address
0
SS
DEFAULT
VALUE
FUNCTION
XXXXXX
11
00
Auto calibrate sawtooth divider
Manual SDIV setting. See the Manual Programming
of Spread-Spectrum Divider section.
000000
Maxim Integrated │ 59
MAX9275/MAX9279
3.12Gbps GMSL Serializers for Coax or
STP Output Drive and Parallel Input
Table 24. Register Table (continued)
REGISTER
ADDRESS
BITS
D7
0x04
NAME
CLINKEN
D5
PRBSEN
D4
D[3:2]
FUNCTION
0
Disable serial link. (Power-up default values depend
on values of CONF[3:2] at power-up). Reverse
control channel communication remains unavailable
for 500µs after the serializer starts/stops the serial link
1
Enable serial link. Power-up default values depend
on values of CONF[3:2] at power-up). Reverse
control channel communication remains unavailable
for 500µs after the serializer starts/stops the serial link
0
Disable configuration link
1
Enable configuration link
0
Disable PRBS test
1
Enable PRBS test
0
Normal mode. (Power-up default value depends on
CDS/CNTL3 and CONF[3:2] pin values at power-up).
1
Activate sleep mode. (Power-up default value
depends on CDS/CNTL3 and CONF[3:2] pin values at
power-up)
00
Base mode uses I2C interface when I2CSEL = 0,
CDS = 1
01
Base mode uses UART interface when I2CSEL = 0,
CDS = 1
SEREN
D6
SLEEP
INTTYPE
10, 11
D1
D0
www.maximintegrated.com
DEFAULT
VALUE
VALUE
Disable reverse control channel from deserializer
(receiving)
1
Enable reverse control channel from deserializer
(receiving)
0
Disable forward control channel to deserializer
(sending)
1
Enable forward control channel to deserializer
(sending)
FWDCCEN
0
0
0, 1
00
Local control channel disabled
0
REVCCEN
0, 1
1
1
Maxim Integrated │ 60
MAX9275/MAX9279
3.12Gbps GMSL Serializers for Coax or
STP Output Drive and Parallel Input
Table 24. Register Table (continued)
REGISTER
ADDRESS
BITS
D7
D6
D[5:4]
NAME
DISJITFILT
CMLLVL
PREEMP
DEFAULT
VALUE
FUNCTION
0
I2C conversion sends the register address when
converting UART to I2C
1
Disable sending of I2C register address when
converting UART to I2C (command-byte-only mode)
0
Enable jitter filter
1
Disable jitter filter
00
100mV CML twisted pair output level (see Table 6).
01
200mV CML twisted pair output level
10
300mV CML twisted pair output level
11
400mV CML twisted pair output level
I2CMETHOD
0x05
D[3:0]
VALUE
0000
Preemphasis off
0001
-1.2dB preemphasis
0010
-2.5dB preemphasis
0011
-4.1dB preemphasis
0100
-6.0dB preemphasis
0101
Do not use
0110
Do not use
0111
Do not use
1000
1.1dB preemphasis
1001
2.2dB preemphasis
1010
3.3dB preemphasis
1011
4.4dB preemphasis
1100
6.0dB preemphasis
1101
8.0dB preemphasis
1110
10.5dB preemphasis
1111
14.0dB preemphasis
0
1
11
0000
0x06
D[7:0]
—
01000000
Reserved
01000000
0x07
D[7:0]
—
00100010
Reserved
00100010
D[7:4]
—
0000
Reserved
0000
(Read only)
D[3:2]
LFNEG
0x08
D[1:0]
LFPOS
00
Negative cable wire shorted to supply voltage
01
Negative cable wire shorted to ground
10
Normal operation
11
Negative cable wire disconnected
00
Positive cable wire shorted to supply voltage
01
Positive cable wire shorted to ground
10
Normal operation
11
Positive cable wire disconnected
10
(Read only)
10
(Read only)
0x09
D[7:0]
—
XXXXXXXX
Reserved
(Read only)
0x0A
D[7:0]
—
XXXXXXXX
Reserved
(Read only)
0x0B
D[7:0]
—
XXXXXXXX
Reserved
(Read only)
www.maximintegrated.com
Maxim Integrated │ 61
MAX9275/MAX9279
3.12Gbps GMSL Serializers for Coax or
STP Output Drive and Parallel Input
Table 24. Register Table (continued)
REGISTER
ADDRESS
BITS
NAME
VALUE
0x0C
D[7:0]
—
00100000
0x0D
0x0E
0x0F
0x10
0x11
0x12
D7
SETGPO
D6
INVVSYNC
D5
INVHSYNC
D[4:0]
—
D7
INVDE
Reserved
0
Set GPO to output low
1
Set GPO to output high
0
Do not invert VSYNC input
1
Invert VSYNC input
0
Do not invert HSYNC input
1
Invert HSYNC input
01111
Do not invert DE input
1
Invert DE input
—
0000010
D[7:1]
I2CSRCA
XXXXXXX
D0
—
0
D[7:1]
I2CDSTA
XXXXXXX
D0
—
0
00100000
0
0
0
Reserved
0
D[6:0]
DEFAULT
VALUE
FUNCTION
01111
0
Reserved
0000010
I2C address translator source A
0000000
Reserved
0
I2C address translator destination A
0000000
Reserved
0
I2C address translator source B
D[7:1]
I2CSRCB
XXXXXXX
D0
—
0
D[7:1]
I2CDSTB
XXXXXXX
D0
—
0
Reserved
0
Acknowledge not generated when forward channel is
not available
1
I2C to I2C-slave generates local acknowledge when
forward channel is not available
00
352ns/117ns I2C setup/hold time
01
469ns/234ns I2C setup/hold time
10
938ns/352ns I2C setup/hold time
11
1046ns/469ns I2C setup/hold time
D7
D[6:5]
I2CLOCACK
I2CSLVSH
0x13
D[4:2]
D[1:0]
www.maximintegrated.com
I2CMSTBT
I2CSLVTO
0000000
Reserved
0
I2C address translator destination B
000
8.47kbps (typ) I2C to I2C-Master bit rate setting
001
28.3kbps (typ) I2C to I2C-Master bit rate setting
010
84.7kbps (typ) I2C to I2C-Master bit rate setting
011
105kbps (typ) I2C to I2C-Master bit rate setting
100
173kbps (typ) I2C to I2C-Master bit rate setting
101
339kbps (typ) I2C to I2C-Master bit rate setting
110
533kbps (typ) I2C to I2C-Master bit rate setting
111
837kbps (typ) I2C to I2C-Master bit rate setting
00
64µs (typ) I2C to I2C-Slave remote timeout
01
256µs (typ) I2C to I2C-Slave remote timeout
10
1024µs (typ) I2C to I2C-Slave remote timeout
11
No I2C to I2C-Slave remote timeout
0000000
0
1
01
101
10
Maxim Integrated │ 62
MAX9275/MAX9279
3.12Gbps GMSL Serializers for Coax or
STP Output Drive and Parallel Input
Table 24. Register Table (continued)
REGISTER
ADDRESS
BITS
D[7:4]
NAME
CMLLVLCX
0x14
D[3:1]
D0
D7
D[6:5]
—
DISRWAKE
D3
0x16
DEFAULT
VALUE
FUNCTION
0000
Do not use
0001
50mV CML coax output level
0010
100mV CML coax output level
0011
150mV CML coax output level
0100
200mV CML coax output level
0101
250mV CML coax output level
0110
300mV CML coax output level
0111
350mV CML coax output level
1000
400mV CML coax output level
1001
450mV CML coax output level
1010
500mV CML coax output level
1011
Do not use
11XX
Do not use
000
Reserved
1010
000
0
Enable wake-up receiver (enable remote wakeup
1
Disable wake-up receiver (disable remote wakeup)
0
Enable DE trigger of Encoded packets in highbandwidth mode
1
Disable DE trigger of Encoded packets in highbandwidth mode
00
No trigger of encoded CNTL packets in highbandwidth mode
01
Always trigger encoded CNTL packets in highbandwidth mode
10
Trigger encoded CNTL packets in high-bandwidth
mode when DE is low
11
Trigger encoded CNTL packets in high-bandwidth
mode when HS is low
0
Disable reverse channel from positive input with coax
cable
1
Enable reverse channel from positive input with coax
cable
0
Disable reverse channel from negative input with coax
cable
1
Enable reverse channel from negative input with coax
cable
DISDETRIG
CNTLTRIG
0x15
D4
VALUE
ENREVP
ENREVN
0
0
10
1
0
D[2:0]
—
010
Reserved
010
D[7:0]
—
XXXXXXXX
Reserved
XXXXXXXX
www.maximintegrated.com
Maxim Integrated │ 63
MAX9275/MAX9279
3.12Gbps GMSL Serializers for Coax or
STP Output Drive and Parallel Input
Table 24. Register Table (continued)
REGISTER
ADDRESS
0x17
BITS
D7
NAME
VALUE
DEFAULT
VALUE
FUNCTION
0
Set reverse channel to legacy mode. (power-up
default value depends on GPO/HIM pin value at
power-up)
1
Set reverse channel to high immunity mode (powerup default value depends on GPO/HIM pin value at
power-up)
HIGHIMM
0, 1
D[6:0]
—
0011111
Reserved
0011111
0x18
D[7:0]
—
XXXXXXXX
Reserved
(Read only)
0x19
D[7:0]
—
01001010
Reserved
01001010
D7
D6
0x1B
0x1E
0x1F
1
High-immunity reverse channel mode uses 1Mbps bit
rate
0
Reserved
0
MS/CNTL0 functions as MS input
1
MS/CNTL0 functions as CNTL0 input
0
CDS/CNTL3 functions as CDS input
1
CDS/CNTL3 functions as CNTL3 input
REVFAST
—
D5
MSCNTL0
D4
CDSCNTL3
D[3:1]
—
0x1A
D0
0
High-immunity reverse channel mode uses 500kbps
bit rate
000
D7
INVSCK
D6
INVWS
D[5:0]
—
D[7:0]
ID
D[7:5]
—
D4
CAPS
D[3:0]
REVISION
0
0
0
Reserved
000
0
256µs reverse-channel arbitration time out duration
(coax splitter mode only)
1
4ms reverse-channel arbitration time out duration
(coax splitter mode only)
0
Do not invert SCK input
1
Invert SCK input
0
Do not invert WS input
1
Invert WS input
REVARBTO
010000
Reserved
00100001
Device is a MAX9275 (0x21)
00100101
Device is a MAX9279 (0x25)
000
Reserved
0
Not HDCP capable (MAX9275)
1
HDCP capable (MAX9279)
XXXX
Device revision
0
0
0
0
010000
00100X01
(Read only)
000
(Read only)
(Read only)
(Read only)
*X = Don’t care
www.maximintegrated.com
Maxim Integrated │ 64
MAX9275/MAX9279
3.12Gbps GMSL Serializers for Coax or
STP Output Drive and Parallel Input
Table 25. HDCP Register Table (MAX9279 only)
REGISTER
ADDRESS
SIZE
(Bytes)
NAME
READ/
WRITE
0x80 to
0x84
5
BKSV
Read/write
HDCP receiver KSV
Read/write
RI (read only) of the transmitter when EN_INT_
COMP = 0
RI’ (read/write) of the receiver when EN_INT_
COMP = 1
0xFFFF
0xFF
0x85 to
0x86
2
RI/RI’
FUNCTION
DEFAULT VALUE
(hex)
0x0000000000
0x87
1
PJ/PJ’
Read/write
PJ (read only) of the transmitter when EN_INT_
COMP = 0
PJ’ (read/write) of the receiver when EN_INT_
COMP = 1
0x88 to
0x8F
8
AN
Read only
Session random number
(Read only)
0x90 to
0x94
5
AKSV
Read only
HDCP transmitter KSV
(Read only)
D7 = PD_HDCP
1 = Power-down HDCP circuits
0 = HDCP circuits normal
D6 = EN_INT_COMP
1 = Internal comparison mode
0 = µC comparison mode
D5 = FORCE_AUDIO
1 = Force audio data to 0
0 = Normal operation
D4 = FORCE_VIDEO
1 = Force video data DFORCE value
0 = Normal operation
0x95
1
ACTRL
Read/write
D3 = RESET_HDCP
1 = Reset HDCP circuits. Automatically set to 0
upon completion
0 = Normal operation
0x00
D2 = START_AUTHENTICATION
1 = Start authentication. Automatically set to 0
once authentication starts
0 = Normal operation
D1 = VSYNC_DET
1 = Internal falling edge on VSYNC detected
0 = No falling edge detected
D0 = ENCRYPTION_ENABLE
1 = Enable encryption
0 = Disable encryption
www.maximintegrated.com
Maxim Integrated │ 65
MAX9275/MAX9279
3.12Gbps GMSL Serializers for Coax or
STP Output Drive and Parallel Input
Table 25. HDCP Register Table (MAX9279 only) (continued)
REGISTER
ADDRESS
SIZE
(BYTES)
NAME
READ/
WRITE
FUNCTION
DEFAULT VALUE
(hex)
D[7:4] = Reserved
D3 = V_MATCHED
1 = V matches V’ (when EN_INT_COMP = 1)
0 = V does not match V’ or EN_INT_COMP = 0
0x96
1
ASTATUS
Read only
D2 = PJ_MATCHED
1 = PJ matches PJ’ (when EN_INT_COMP = 1)
0 = PJ does not match PJ’ or EN_INT_COMP = 0
D1 = R0_RI_MATCHED
1 = RI matches RI’ (when EN_INT_COMP = 1)
0 = RI does not match RI’ or EN_INT_COMP = 0
0x00
(Read only)
D0 = BKSV_INVALID
1 = BKSV is not valid
0 = BKSV is valid
D[7:1] = RESERVED
D0 = REPEATER
1 = Set to one if device is a repeater
0 = Set to zero if device is not a repeater
0x97
1
BCAPS
Read/write
0x98 to
0x9C
5
ASEED
Read/write
Internal random number generator optional seed
value
Read/write
Forced video data transmitted when
FORCE_VIDEO = 1.
R[7:0] = DFORCE[7:0]
G[7:0] = DFORCE[15:8]
B[7:0] = DFORCE[23:16]
0x000000
Read/write
H0 part of SHA-1 hash value.
V (read only) of the transmitter when
EN_INT_COMP = 0
V’ (read/write) of the receiver when
EN_INT_COMP = 1
0x00000000
Read/write
H1 part of SHA-1 hash value.
V (read only) of the transmitter when
EN_INT_COMP = 0
V’ (read/write) of the receiver when
EN_INT_COMP = 1
0x00000000
Read/write
H2 part of SHA-1 hash value.
V (read only) of the transmitter when
EN_INT_COMP = 0
V’ (read/write) of the receiver when
EN_INT_COMP = 1
0x00000000
0x9D to
0x9F
0xA0 to
0xA3
0xA4 to
0xA7
0xA8 to
0xAB
3
4
4
4
www.maximintegrated.com
DFORCE
V.H0,
V’.H0
V.H1,
V’.H1
V.H2,
V’.H2
0x00
0x0000000000
Maxim Integrated │ 66
MAX9275/MAX9279
3.12Gbps GMSL Serializers for Coax or
STP Output Drive and Parallel Input
Table 25. HDCP Register Table (MAX9279 only) (continued)
REGISTER
ADDRESS
0xAC to
0xAF
0xB0 to
0xB3
SIZE
(BYTES)
4
4
NAME
V.H3,
V’.H3
V.H4,
V’.H4
READ/
WRITE
FUNCTION
DEFAULT VALUE
(hex)
Read/write
H3 part of SHA-1 hash value.
V (read only) of the transmitter when
EN_INT_COMP = 0
V’ (read/write) of the receiver when
EN_INT_COMP = 1
0x00000000
Read/write
H4 part of SHA-1 hash value.
V (read only) of the transmitter when
EN_INT_COMP = 0
V’ (read/write) of the receiver when
EN_INT_COMP = 1
0x00000000
D[15:12] = Reserved
0xB4 to
0xB5
D11 = MAX_CASCADE_EXCEEDED
1 = Set to one if more than 7 cascaded devices
attached
0 = Set to zero if 7 or fewer cascaded devices
attached
2
BINFO
Read/write
D[10:8] = DEPTH
Depth of cascaded devices
0x0000
D7 = MAX_DEVS_EXCEEDED
1 = Set to one if more than 14 devices attached
0 = Set to zero if 14 or fewer devices attached
D[6:0] = DEVICE_COUNT
Number of devices attached
0xB6
1
GPMEM
Read/write
General-purpose memory byte
0xB7 to
0xB9
3
-
Read only
Reserved
0xBA to
0xFF
70
KSV_LIST
Read/write
List of KSVs downstream repeaters and receivers
(maximum of 14 devices)
www.maximintegrated.com
0x00
0x000000
All Zero
Maxim Integrated │ 67
MAX9275/MAX9279
3.12Gbps GMSL Serializers for Coax or
STP Output Drive and Parallel Input
Typical Application Circuit
PCLK
45.3kΩ
CDS /CNTL3
GPU
45.3kΩ
INTOUT/ADD2
LMN0
MAX9275
MAX9279
DISPLAY
CNTL3/ADD1
LMN1
ECU
PCLK
RGBHV
PCLKOUT
DOUT(26:0)
I2CSEL
CNTL0/ADD0
PCLKIN
DIN(26:0)
RGB
4.99kΩ
MAX9276
MAX9280
4.99kΩ
TO PERIPHERALS
GPI
UART
TX
RX
RX/SDA
TX/SCL
LFLT
LFLT
RX/SDA
OUT+
IN+
OUT-
IN-
49.9kΩ
CONF3
WS
WS
AUDIO SCK
SD
TX/SCL
MAX9850
49.9kΩ
CONF2
SCK
CONF0
SD
CONF1
SCL
SDA
LOCK
CX / TP
WS
SCK
SD
WS
SCK
SD
MCLK
NOTE: NOT ALL PULLUP/PULLDOWN RESISTORS ARE SHOWN. SEE PIN DESCRIPTION FOR DETAILS.
VIDEO-DISPLAY APPLICATION
Ordering Information
PART
MAX9275GTN+
TEMP RANGE
Chip Information
PINPACKAGE
HDCP
-40°C to +105°C 56 TQFN-EP*
NO
MAX9275GTN/V+ -40°C to +105°C 56 TQFN-EP*
NO
MAX9279GTN+
-40°C to +105°C 56 TQFN-EP*
YES**
MAX9279GTN/V+ -40°C to +105°C 56 TQFN-EP*
YES**
+Denotes a lead(Pb)-free/RoHS-compliant package.
/V denotes an automotive qualified product.
*EP = Exposed pad.
**HDCP parts require registration with Digital Content
Protection, LLC..
www.maximintegrated.com
PROCESS: CMOS
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
56 TQFN-EP
T5688+2
21-0135
90-0046
Maxim Integrated │ 68
MAX9275/MAX9279
3.12Gbps GMSL Serializers for Coax or
STP Output Drive and Parallel Input
Revision History
REVISION
NUMBER
REVISION
DATE
PAGES
CHANGED
DESCRIPTION
0
8/13
Initial release
—
1
7/15
Removed future product designations from Ordering Information
71
2
10/17
Fixed typos, clarified feature descriptions, removed old/unnecessary content (including
Table 1)
3
12/17
Added a new Note 12 in the AC Electrical Characteristics table and renumbered the
remaining three notes; replaced Figure 7
2, 16–18, 20,
23, 25–29, 31,
33–36, 39, 40,
41–60, 62–71
11, 12, 21
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
© 2017 Maxim Integrated Products, Inc. │ 69
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