19-2543; Rev 0; 7/02
Dual 1:5 Differential Clock Drivers with LVPECL
Inputs and LVDS Outputs
Features
The MAX9317/MAX9317A/MAX9317B/MAX9317C lowskew, dual 1-to-5 differential drivers are designed for
clock and data distribution. The differential input is
reproduced at five LVDS outputs with a low output-tooutput skew of 5ps.
The MAX9317/MAX9317A are designed for low-voltage
operation from a 2.375V to 2.625V power supply for use
in 2.5V systems. The MAX9317B/MAX9317C operate
from a 3.0V to 3.6V power supply for use in 3.3V systems. The MAX9317A/MAX9317C feature 50Ω input termination resistors to reduce component count.
The MAX9317 family is available in 32-pin 7mm ✕ 7mm
TQFP and space-saving 5mm ✕ 5mm QFN packages
and operate across the extended temperature range of
-40°C to +85°C. The MAX9317A is pin compatible with
ON Semiconductor’s MC100EP210S.
♦ Guaranteed 1.0GHz Operating Frequency
♦ 145ps (max) Part-to-Part Skew
♦ 5ps Output-to-Output Skew
♦ 330ps Propagation Delay from CLK_ to Q_
♦ 2.375V to 2.625V Operation (MAX9317/MAX9317A)
♦ 3.0V to 3.6V Operation (MAX9317B/MAX9317C)
♦ ESD Protection: ±2kV (Human Body Model)
♦ Internal 50Ω Input Termination Resistors
(MAX9317A/MAX9317C)
Ordering Information
Applications
PART
Precision Clock Distribution
Low-Jitter Data Repeaters
TEMP RANGE
PINPACKAGE
MAX9317ETJ*
-40°C to +85°C 32 Thin QFN
MAX9317ECJ
-40°C to +85°C 32 TQFP
MAX9317AETJ* -40°C to +85°C 32 Thin QFN
MAX9317AECJ -40°C to +85°C 32 TQFP
MAX9317BETJ* -40°C to +85°C 32 Thin QFN
MAX9317BECJ -40°C to +85°C 32 TQFP
MAX9317CETJ* -40°C to +85°C 32 Thin QFN
MAX9317CECJ -40°C to +85°C 32 TQFP
*Future product—contact factory for availability.
Data and Clock Drivers and Buffers
Central-Office Backplane Clock Distribution
DSLAM Backplanes
Base Stations
ATE
Pin Configurations appear at end of data sheet.
NOMINAL
SUPPLY
VOLTAGE
(V)
2.5
2.5
2.5
2.5
3.3
3.3
3.3
3.3
VCC
VTA
QA2
QA1
QA1
QA0
QA2
26
27
28
29
9, 16
25, 32
30
31
QA0
Functional Diagram
MAX9317
MAX9317A
MAX9317B
MAX9317C
2
RIN
50Ω
RIN
50Ω
24
23
CLKA
CLKA
CLKB
CLKB
3
22
4
21
6
20
7
19
18
RIN
50Ω
QA3
QA4
QA4
QB0
QB0
QB1
QB1
5
15
QB2
14
QB2
13
QB3
QB3
QB4
QB4
MAX9317A/MAX9317C ONLY.
12
1, 8
10
GND
17
11
VTB
RIN
50Ω
QA3
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX9317/MAX9317A/MAX9317B/MAX9317C
General Description
MAX9317/MAX9317A/MAX9317B/MAX9317C
Dual 1:5 Differential Clock Drivers with LVPECL
Inputs and LVDS Outputs
ABSOLUTE MAXIMUM RATINGS
VCC to GND ...........................................................-0.3V to +4.1V
Input Pins to GND.......................................-0.3V to (VCC + 0.3V)
Differential Input Voltage .............VCC or 3.0V, whichever is less
Continuous Output Current .................................................28mA
Surge Output Current..........................................................50mA
Continuous Power Dissipation (TA = +70°C)
32-Pin, 7mm ✕ 7mm TQFP
(derate 20.7mW/°C above +70°C) .................................1.65W
32-Pin 5mm ✕ 5mm QFN
(derate 21.3mW/°C above +70°C) ...................................1.7W
Junction-to-Ambient Thermal Resistance in Still Air
32-Pin, 7mm ✕ 7mm TQFP......................................+48.4°C/W
32-Pin, 5mm ✕ 5mm QFN ..........................................+47°C/W
Junction-to-Case Thermal Resistance
32-Pin, 7mm ✕ 7mm TQFP.........................................+12°C/W
32-Pin, 5mm ✕ 5mm QFN ............................................+2°C/W
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
ESD Protection
Human Body Model (CLK_, CLK_, Q_, Q_, VT_) .............±2kV
Soldering Temperature (10s) ...........................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = 2.375V to 2.625V (MAX9317/MAX9317A), VCC = 3.0V to 3.6V (MAX9317B/MAX9317C), all outputs loaded 100Ω ±1%
between Q_ and Q_, unless otherwise noted. Typical values are at V CC = 2.5V (MAX9317/MAX9317A), V CC = 3.3V
(MAX9317B/MAX9317C), VIHD = VCC - 1.0V, VILD = VCC - 1.5V, unless otherwise noted.) (Notes 1, 2, and 3)
PARAMETER
SYMBOL
CONDITIONS
-40°C
MIN
TYP
+25°C
MAX
MIN
TYP
+85°C
MAX
MIN
TYP
MAX
UNITS
INPUTS (CLK_, CLK_)
Differential Input
High Voltage
VIHD
Figure 1
1.2
VCC
1.2
VCC
1.2
VCC
V
Differential Input
Low Voltage
VILD
Figure 1
0
VCC
- 0.1
0
VCC
- 0.1
0
VCC
- 0.1
V
MAX9317/
MAX9317A
0.1
VCC
0.1
VCC
0.1
VCC
VID
VIHD VILD
MAX9317B/
MAX9317C
0.1
3.0
0.1
3.0
0.1
3.0
CLK_, or CLK_ =
VIHD or VILD,
MAX9317/MAX9317B
-60
+60
-60
+60
-60
+60
µA
RIN
MAX9317A/MAX9317C,
Figure 2 (Note 4)
43
57
43
57
43
57
Ω
Output High
Voltage
VOH
Figure 1
1.6
V
Output Low
Voltage
VOL
Figure 1
Differential Input
Voltage
Input Current
Input Termination
Resistance
IIH, IIL
V
50
50
50
OUTPUTS (Q_, Q_)
2
1.6
0.9
1.6
0.9
0.9
_______________________________________________________________________________________
V
Dual 1:5 Differential Clock Drivers with LVPECL
Inputs and LVDS Outputs
(VCC = 2.375V to 2.625V (MAX9317/MAX9317A), VCC = 3.0V to 3.6V (MAX9317B/MAX9317C), all outputs loaded 100Ω ±1%
between Q_ and Q_, unless otherwise noted. Typical values are at V CC = 2.5V (MAX9317/MAX9317A), V CC = 3.3V
(MAX9317B/MAX9317C), VIHD = VCC - 1.0V, VILD = VCC - 1.5V, unless otherwise noted.) (Notes 1, 2, and 3)
PARAMETER
SYMBOL
Differential
Output Voltage
VOD
Change in VOD
Between
Complementary
Output States
∆VOD
Output Offset
Voltage
VOS
Change in VOS
Between
Complementary
Output States
∆VOS
Output ShortCircuit Current
IOSC
CONDITIONS
Figure 1
-40°C
+25°C
+85°C
UNITS
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
250
350
450
250
350
450
250
350
450
mV
7
50
6
50
6
50
mV
1.125 1.25 1.375 1.125 1.25 1.375 1.125 1.25 1.375
25
25
25
Q_ shorted to Q_
12
12
12
Q_ or Q_ shorted to
GND
28
28
28
V
mV
mA
POWER SUPPLY
Power-Supply
Current (Note 5)
ICC
MAX9317/9317A
69
107
75
107
80
107
MAX9317B/9317C
75
107
81
107
86
107
mA
AC ELECTRICAL CHARACTERISTICS
(VCC = 2.375V to 2.625V (MAX9317/MAX9317A) or VCC = 3.0V to 3.6V (MAX9317B/MAX9317C), all outputs loaded with 100Ω ±1%,
between Q_ and Q_, fIN ≤ 1.0GHz, input transition time = 125ps (20% to 80%), VIHD - VILD = 0.15V to VCC, unless otherwise noted.
Typical values are at VCC = 2.5V (MAX9317/MAX9317A), VCC = 3.3V (MAX9317B/MAX9317C), fIN = 1.0GHz, VIHD = VCC - 1.0V,
VILD = VCC - 1.5V, unless otherwise noted.) (Notes 1 and 4)
PARAMETER
Propagation
Delay CLK_,
CLK_ to Q_, Q_
SYMBOL
CONDITIONS
tPHL
tPLH
Figure 1
Output-to-Output
Skew
tSKEW1
(Note 6)
Part-to-Part Skew
tSKEW2
(Note 7)
Added Random
Jitter
Added
Deterministic Jitter
Operating
Frequency
-40°C
+25°C
+85°C
UNITS
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
250
310
600
250
330
600
250
335
600
ps
9
55
5
45
4
25
ps
145
ps
145
145
tRJ
fIN = 1.0GHz, clock
pattern (Note 8)
0.8
2.0
0.8
2.0
0.8
2.0
ps(RMS)
tDJ
fIN = 1.0GHz, 223 - 1
PRBS pattern (Note 8)
80
105
80
105
80
105
ps(P-P)
fMAX
VOD ≥ 250mV
1.0
1.0
1.0
GHz
_______________________________________________________________________________________
3
MAX9317/MAX9317A/MAX9317B/MAX9317C
DC ELECTRICAL CHARACTERISTICS (continued)
AC ELECTRICAL CHARACTERISTICS (continued)
(VCC = 2.375V to 2.625V (MAX9317/MAX9317A) or VCC = 3.0V to 3.6V (MAX9317B/MAX9317C), all outputs loaded with 100Ω ±1%,
between Q_ and Q_, fIN ≤ 1.0GHz, input transition time = 125ps (20% to 80%), VIHD - VILD = 0.15V to VCC, unless otherwise noted.
Typical values are at VCC = 2.5V (MAX9317/MAX9317A), VCC = 3.3V (MAX9317B/MAX9317C), fIN = 1.0GHz, VIHD = VCC - 1.0V,
VILD = VCC - 1.5V, unless otherwise noted.) (Notes 1 and 4)
PARAMETER
SYMBOL
Differential
Output Rise/Fall
Time
-40°C
CONDITIONS
tR/tF
20% to 80%, Figure 1
+25°C
+85°C
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
140
200
300
140
205
300
140
205
300
UNITS
ps
Note 1: Measurements are made with the device in thermal equilibrium.
Note 2: Current into a pin is defined as positive. Current out of a pin is defined as negative.
Note 3: DC parameters are production tested at +25°C. DC limits are guaranteed by design and characterization over the full operating temperature range.
Note 4: Guaranteed by design and characterization, and are not production tested. Limits are set to ±6 sigma.
Note 5: All outputs loaded with 100Ω differential, all inputs biased differential high or low except VT_.
Note 6: Measured between outputs of the same device at the signal crossing points for a same-edge transition.
Note 7: Measured between outputs on different devices for identical transitions and VCC levels.
Note 8: Device jitter added to the input signal.
Typical Operating Characteristics
(MAX9317, VCC = 2.5V, all outputs loaded with 100Ω ±1%, between Q_ and Q_, fIN = 1.0GHz, input transition time = 125ps (20% to
80%), VIHD = VCC - 1.0V, VILD = VCC - 1.5V, unless otherwise noted.)
OUTPUT AMPLITUDE (VOH - VOL)
vs. CLK_ FREQUENCY
OUTPUT AMPLITUDE (mV)
80
75
70
300
200
100
65
0
-15
10
35
TEMPERATURE (°C)
60
85
0.5
1.0
1.5
CLK_ FREQUENCY (GHz)
RISE TIME
190
2.0
-40
-15
330
tPLH
320
tPHL
324.0
CLK-TO-Q PROPAGATION DELAY (ps)
335
10
35
TEMPERATURE (°C)
323.5
tPHL
323.0
tPLH
322.5
322.0
310
-40
4
200
CLK-TO-Q PROPAGATION DELAY vs. HIGH
VOLTAGE OF DIFFERENTIAL INPUT (VIHD)
MAX9317 toc04
CLK-TO-Q PROPAGATION DELAY (ps)
340
315
FALL TIME
210
180
0
CLK-TO-Q PROPAGATION DELAY
vs. TEMPERATURE
325
220
MAX9317 toc05
-40
230
MAX9317 toc03
85
400
MAX9317 toc02
INPUTS OPEN, OUTPUTS TERMINATED
WITH 100Ω DIFFERENTIAL
MAX9317 toc01
90
OUTPUT RISE/FALL TIME
vs. TEMPERATURE
OUTPUT RISE/FALL TIME (ps)
SUPPLY CURRENT vs. TEMPERATURE
SUPPLY CURRENT (mA)
MAX9317/MAX9317A/MAX9317B/MAX9317C
Dual 1:5 Differential Clock Drivers with LVPECL
Inputs and LVDS Outputs
-15
10
35
TEMPERATURE (°C)
60
85
1.2
1.5
1.8
2.1
2.4
HIGH VOLTAGE OF DIFFERENTIAL INPUT (V)
_______________________________________________________________________________________
60
85
Dual 1:5 Differential Clock Drivers with LVPECL
Inputs and LVDS Outputs
NAME
PIN
1, 8
MAX9317
MAX9317B
GND
MAX9317A
MAX9317C
GND
N.C.
—
FUNCTION
Ground
No Connection. Connect this pin to ground or leave floating.
3
CLKA
CLKA
CLKA Input Termination Voltage. This pin is connected to CLKA and CLKA through 50Ω
termination resistors. Connect this pin to VCC - 2V for an LVPECL input signal on CLKA or
leave floating for an LVDS input signal.
Noninverting Differential Clock Input A
4
CLKA
CLKA
Inverting Differential Clock Input A
N.C.
—
2
5
—
VTA
No Connection. Connect this pin to ground or leave floating.
CLKB Input Termination Voltage. This pin is connected to CLKB and CLKB through 50Ω
termination resistors. Connect this pin to VCC - 2V for an LVPECL input signal on CLKB or
leave floating for an LVDS input signal.
Noninverting Differential Clock Input B
—
VTB
6
CLKB
CLKB
7
CLKB
CLKB
9, 16,
25, 32
VCC
VCC
10
QB4
QB4
Inverting Differential Clock Input B
Positive Supply Voltage. Bypass each VCC pin to ground with 0.1µF and 0.01µF ceramic
capacitors. Place the capacitors as close to the device as possible with the 0.01µF
capacitor closest to the device.
CLKB Inverting Differential Output 4. Terminate with 100Ω to QB4.
11
QB4
QB4
CLKB Noninverting Differential Output 4. Terminate with 100Ω to QB4.
12
QB3
QB3
CLKB Inverting Differential Output 3. Terminate with 100Ω to QB3.
13
QB3
QB3
CLKB Noninverting Differential Output 3. Terminate with 100Ω to QB3.
14
QB2
QB2
CLKB Inverting Differential Output 2. Terminate with 100Ω to QB2.
15
QB2
QB2
CLKB Noninverting Differential Output 2. Terminate with 100Ω to QB2.
17
QB1
QB1
CLKB Inverting Differential Output 1. Terminate with 100Ω to QB1.
18
QB1
QB1
CLKB Noninverting Differential Output 1. Terminate with 100Ω to QB1.
19
QB0
QB0
CLKB Inverting Differential Output 0. Terminate with 100Ω to QB0.
20
QB0
QB0
CLKB Noninverting Differential Output 0. Terminate with 100Ω to QB0.
21
QA4
QA4
CLKA Inverting Differential Output 4. Terminate with 100Ω to QA4.
22
QA4
QA4
CLKA Noninverting Differential Output 4. Terminate with 100Ω to QA4.
23
QA3
QA3
CLKA Inverting Differential Output 3. Terminate with 100Ω to QA3.
24
QA3
QA3
CLKA Noninverting Differential Output 3. Terminate with 100Ω to QA3.
26
QA2
QA2
CLKA Inverting Differential Output 2. Terminate with 100Ω to QA2.
27
QA2
QA2
CLKA Noninverting Differential Output 2. Terminate with 100Ω to QA2.
28
QA1
QA1
CLKA Inverting Differential Output 1. Terminate with 100Ω to QA1.
29
QA1
QA1
CLKA Noninverting Differential Output 1. Terminate with 100Ω to QA1.
30
QA0
QA0
CLKA Inverting Differential Output 0. Terminate with 100Ω to QA0.
31
QA0
QA0
—
EP
EP
CLKA Noninverting Differential Output 0. Terminate with 100Ω to QA0.
Exposed Pad. QFN package only. Internally connected to ground.
_______________________________________________________________________________________
5
MAX9317/MAX9317A/MAX9317B/MAX9317C
Pin Description
MAX9317/MAX9317A/MAX9317B/MAX9317C
Dual 1:5 Differential Clock Drivers with LVPECL
Inputs and LVDS Outputs
VIHD
CLK
VIHD - VILD
CLK
VILD
tPLH
tPHL
VOH
Q_
VOD
VOL
Q_
80%
Q_ - Q_
80%
DIFFERENTIAL
OUTPUT
WAVEFORM
0V
(DIFFERENTIAL)
20%
20%
tR
tF
Figure 1. MAX9317 Timing Diagram
Detailed Description
The MAX9317 family of low-skew, 1-to-5 dual differential drivers are designed for clock or data distribution.
Two independent 1-to-5 splitters accept a differential
input signal and reproduce it on five separate differential LVDS outputs. The output drivers are guaranteed to
operate at frequencies up to 1.0GHz with the LVDS output levels conforming to the EIA/TIA-644 standard.
The MAX9317/MAX9317A operate from a 2.375V to
2.625V power supply for use in 2.5V systems. The
MAX9317B/MAX9317C operate from a 3.0V to 3.6V
supply for 3.3V systems.
CLK_
CLK_
6
RIN
50Ω
VT_
VCC 2.0V
MAX9317A
MAX9317C
(a) MAX9317A/MAX9317C CONFIGURED FOR LVPECL INPUT SIGNALS.
Differential LVPECL and LVDS Input
The MAX9317 family has two input differential pairs:
CLKA and CLKA, and CLKB and CLKB. Each differential input pair can be configured or terminated independently. The inputs are designed to be driven by either
LVPECL or LVDS signals with a maximum differential
voltage of VCC or 3.0V, whichever is less.
The MAX9317A/MAX9317C reduce external component
count by having the input 50Ω termination resistors on
chip. Configure the MAX9317A/MAX9317C to receive
LVPECL signals by connecting VT_ to VCC - 2V (Figure
2(a)). Leaving the V T_ input floating configures the
RIN
50Ω
LVPECL
DRIVER
CLK_
RIN
50Ω
VT_
RIN
50Ω
LVDS
DRIVER
CLK_
MAX9317A
MAX9317C
(b) MAX9317A/MAX9317C CONFIGURED FOR LVDS INPUT SIGNALS.
Figure 2. MAX9317A/MAX9317C Input Terminations
_______________________________________________________________________________________
Dual 1:5 Differential Clock Drivers with LVPECL
Inputs and LVDS Outputs
The LVDS input signal must adhere to the specifications
given in the Electrical Characteristics table. Note that the
signal must be at least 1.2V to be a valid logic HIGH.
Applications Information
Output Termination
Terminate the outputs with 100Ω across each differential pair (Q_ to Q_). Ensure that output currents do not
exceed the current limits as specified in the Absolute
Maximum Ratings table. Under all operating conditions,
observe the device’s total thermal limits.
Power-Supply Bypassing
Bypass each VCC pin to ground with high-frequency surface-mount ceramic 0.1µF and 0.01µF capacitors in parallel and as close to the device as possible, with the
0.01µF capacitor closest to the device. Use multiple parallel vias to minimize parasitic inductance and reduce
power-supply bounce with high-current transients.
Circuit Board Traces
Circuit board trace layout is very important to maintain
the signal integrity of high-speed differential signals. Use
50Ω traces for CLK_, CLK_, Q_, and Q_. Maintaining
integrity is accomplished in part by reducing signal
reflections and skew, and increasing common-mode
noise immunity by keeping the differential traces close
together.
Signal reflections are caused by discontinuities in the
50Ω characteristic impedance of the traces. Avoid discontinuities by maintaining the distance between differential traces, and not using sharp corners or vias.
Maintaining distance between the traces also increases
common-mode noise immunity. Reducing signal skew
is accomplished by matching the electrical length of
the differential traces.
Chip Information
TRANSISTOR COUNT: 1119
PROCESS: Bipolar
25
VCC
26
QA2
VCC
27
QA2
QA2
28
QA1
QA2
29
QA1
QA1
30
QA0
QA1
31
QA0
QA0
32
TOP VIEW
VCC
QA0
TOP VIEW
VCC
Pin Configurations
32
31
30
29
28
27
26
25
GND
1
24 QA3
GND
1
24 QA3
N.C. (VTA)
2
23 QA3
N.C. (VTA)
2
23 QA3
CLKA
3
22 QA4
CLKA
3
22 QA4
CLKA
4
21 QA4
CLKA
4
N.C. (VTB)
5
20 QB0
N.C. (VTB)
5
CLKB
6
19 QB0
CLKB
6
CLKB
7
18 QB1
CLKB
7
GND
8
17 QB1
GND
8
21 QA4
**EXPOSED PADDLE
18 QB1
20 QB0
19 QB0
10
11
12
13
14
15
16
9
10
11
12
13
14
15
16
QB3
QB3
QB2
QB2
VCC
VCC
QB4
QB4
QB3
QB3
QB2
QB2
VCC
17 QB1
QB4
VCC
9
MAX9317
MAX9317A
MAX9317B
MAX9317C
QB4
MAX9317
MAX9317A
MAX9317B
MAX9317C
TQFP (7mm x 7mm)
( ) MAX9317A/MAX9317C.
QFN-EP**
**EXPOSED PADDLE AND CORNER PINS ARE CONNECTED TO VEE.
_______________________________________________________________________________________
7
MAX9317/MAX9317A/MAX9317B/MAX9317C
respective input with a differential 100Ω termination to
receive LVDS signals (Figure 2(b)).
The MAX9317/MAX9317B accept LVPECL if the inputs
are externally terminated with 50Ω resistors from CLKA
and CLKA or CLKB and CLKB to VCC - 2V. Alternatively,
if the inputs are differentially terminated with 100Ω, they
accept an LVDS input signal.
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
D2
0.15 C A
D
b
CL
0.10 M C A B
D2/2
D/2
PIN # 1
I.D.
QFN THIN 5x5x0.8 .EPS
MAX9317/MAX9317A/MAX9317B/MAX9317C
Dual 1:5 Differential Clock Drivers with LVPECL
Inputs and LVDS Outputs
k
0.15 C B
PIN # 1 I.D.
0.35x45
E/2
E2/2
CL
(NE-1) X e
E
E2
k
L
DETAIL A
e
(ND-1) X e
CL
CL
L
L
e
e
0.10 C
A
C
0.08 C
A1 A3
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE
16, 20, 28, 32L, QFN THIN, 5x5x0.8 mm
APPROVAL
8
DOCUMENT CONTROL NO.
REV.
21-0140
C
_______________________________________________________________________________________
1
2
Dual 1:5 Differential Clock Drivers with LVPECL
Inputs and LVDS Outputs
COMMON DIMENSIONS
EXPOSED PAD VARIATIONS
NOTES:
1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.
3. N IS THE TOTAL NUMBER OF TERMINALS.
4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1
SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE
ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE.
5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm
FROM TERMINAL TIP.
6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.
7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.
8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
9. DRAWING CONFORMS TO JEDEC MO220.
10. WARPAGE SHALL NOT EXCEED 0.10 mm.
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE
16, 20, 28, 32L, QFN THIN, 5x5x0.8 mm
APPROVAL
DOCUMENT CONTROL NO.
REV.
21-0140
C
2
2
_______________________________________________________________________________________
9
MAX9317/MAX9317A/MAX9317B/MAX9317C
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
32L/48L,TQFP.EPS
MAX9317/MAX9317A/MAX9317B/MAX9317C
Dual 1:5 Differential Clock Drivers with LVPECL
Inputs and LVDS Outputs
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
10 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2002 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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